Name:_________________ Roll No:__________

Lab: Computer Architecture (6th Semester)

LAB # 2
Introduction to Gate level & Dataflow Modelling
through implementation of 4 bit Ripple Carry at gate level and its
simulation using Xilinx ISE tools.

Procedure:
1. Launch the Xilinx ISE 7.1 software as follows:

Start >> Programs >> Xilinx ISE 7.1 >> Project Navigator

2. Start a new project as follows:

File >> New Project

3. Give the project name as : Ripple_Carry

4. Select the top level module type as : HDL

5. Click Next.

6. In the next window of ‘Select Device and Design Flow for the Project’:

Select the simulator as : ISE simulator

In the Device Family option,

Select Spartan3
In the Device option
Select xc3s200
In the Package option
Select ft256
In the Speed Grade option
Select -5
In the Top Level Module Type option
Select HDL
In the Synthesis Tool option
Select XST(VHDL/Verilog)
In the Simulator option
Select ISE Simulator
In the Generated Simulation Language option
Select Verilog

Then, select Next.

8. In the next window of ‘Create a new source’:

Simply click Next. We shall not use this option for the time
being.
9. In the next window of ‘Add Existing Sources’:
Simply click Next. We shall not use this option for the time
being.
10. In the next window, click Finish.
11. Select Project >> New Source
12. In the ‘New Source’ window:
Select ‘Verilog module’ out of different options available in the
left hand column.
Give the file name as: Any appropriate (e.g. Half_adder )
13. In the next window of ‘Define Verilog Source’:
Simply click Next. We shall not use this option for the time
being.
14. In the next window, click Finish.

15. Use the following Verilog Code:

Codes of following are available & Present in a notepad file. Just copy
from there and paste.

module half_adder(sum , carry, in1, in2);

output sum;
output carry;
 input in1;
input in2;

xor x1(sum, in1, in2);

and a1(carry, in1, in2);

endmodule

16. Repeat step 11,12,13 & 14 but save now file name as Full_adder.

17. Use the following Verilog Code:

module Full_adder(sum,cout,in1, in2, cin);

input in1,in2,cin;
output sum,cout;

wire t_sum,t_c1,t_c2;

half_adder blk1(t_sum,t_c1,in1,in2);
half_adder blk2(sum,t_c2,t_sum,cin);
or blk3 (cout,t_c1,t_c2);

endmodule .

18. Repeat Step 17 with file name as ripple_Carry. And use the following code.

module ripple_Carry(sum, carry_out, a, b, carry_in);

output [3:0] sum;

output carry_out;
input [3:0] a,b;
input carry_in;

wire c1, c2, c3;

 Full_adder fa0(sum[0], c1, a[0], b[0], carry_in);
Full_adder fa1(sum[1], c2, a[1], b[1], c1);
Full_adder fa2(sum[2], c3, a[2], b[2], c2);
Full_adder fa3(sum[3], carry_out, a[3], b[3], c3);

endmodule

Points to Ponder:
• Synthesis the ripple_Carry.

• See the test bench waveform.

Make a new Project and implement the following code:

// MUX 2 to1
module mux2x1(a, b, s, out);
input a, b, s;
output out;

assign out = (a & ~s) | (b & s);

endmodule
//

// MUX 4 to 1
module mux4x1(a, b, c, d, s0, s1, out);
input a, b, c, d, s0, s1;
output out;
wire w1, w2;

mux2x1 m1(a, b, s0, w1);

mux2x1 m2(c, d, s0, w2);
mux2x1 m3(w1, w2, s1, out);

endmodule

//
// MUX 8 to 1
module mux8x1(a, b, c, d, e, f, g, h, s0, s1, s2, out);
input a, b, c, d, e, f, g , h, s0, s1, s2;
output out;
wire w1, w2;

mux4x1 m1(a, b, c, d, s0, s1, w1);

mux4x1 m2(e, f, g, h, s0, s1, w2);
mux2x1 m3(w1, w2, s2, out);
endmodule
//

//MUX 16 to 1

module mux16x1(a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p, s0, s1, s2, s3, out);

input a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p, s0, s1, s2, s3;
output out;
wire w1, w2;

mux8x1 m1(a, b, c, d, e, f, g, h, s0, s1, s2, w1);

mux8x1 m2(i, j, k, l, m, n, o, p, s0, s1, s2, w2);
mux2x1 m3(w1, w2, s3, out);

endmodule
//

ASSIGNMENT (To do in today lab session):

Implement a barrel shifter using MUX 16 to1

Table representing barrel shifting function:

Signal I/O Number of Bits
Data ; Input 4
type Input 2
amount Input 2
out Output 4
Where
Type 00 indicates left Shift
Type 01 indicates right Shift
Type 10 indicates left Rotate
Type 11 indicates right Rotate
And
module barrel_shifter(data, type, amount, out);

input [3:0] data;

input [1:0] type;
input [1:0] amount;
output [3:0] out;

// Write the code

endmodule
Amount decides number of bits shifted/rotated.
Hint:
1) For Shift left operation (type 00) and amount of amount 01 (shift left by one
bit ) apply:

MUX NO Apply on pin number 2

1 data[2]
2 data[1]
3 data[0]
4 1’b0

• Pins start from 1 to 16

2) For left rotate operation (type 10) and amount of amount 11 (rotate right
by three bit ) apply:

MUX NO Apply on pin number 13

1 data[0]
2 data[3]
3 data[2]
4 data[1]