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CAP 208
SUBMITTED TO-
Anjlee Mam
SUBMITTED BY-
SACHIN RAJ
B34
D3901
Part-A
Ans-
Ans-
Isolated I/O
Difference
Ans-
[5] Address Reg <- Address Reg +1; WC(Word Counter) <-
WC - 1
Output
[3] Buffer <- One byte; Output Device <- W, for all
disassembled bytes
Q4. Why does DMA have priority over CPU when both request a
memory transfer?
Ans-
The CPU can wait to fetch instructions and data from memory
without any damage occurring except loss of time. DMA usually
transfers data from a device that cannot be stopped since
information continues to flow so loss of data may occur.
During DMA transfer, the CPU is idle and has no control of the
memory buses. A DMA controller takes over the buses to manage
the transfer directly between the I/O device and memory.
Ans-
Memory Organisation
Hard Drive
RAM
CPU
MMU
RAM Chip-
ROM Chip-
Q6 Discuss Associative memory, Cache memory and Virtual memory?
Ans-
Associative memory
Hardware Organisation
Cache memory
Locality of Reference
Temporal Locality
Spatial Locality
Cache