Professional Documents
Culture Documents
ELEC 100
M. Raja [2010]
Performance of a device and/or circuit
The speed of operation of a device is dependent on mobility µ of the charge
carriers and inversely dependent on the square of the channel length L (or
minimum feature size m)
Speed
L2
When designing a transistor or circuit, the designer needs to define the different
dimensions of the device i.e. channel width, channel length and contacts etc in
terms of the ‘minimum feature’ size m
This makes the design independent of the actual dimensions. For example if the
device has W = 10µm and L = 3µm then if for a given technology m = 0.5µm,
then W and L are given as 20 m and 6 m respectively
Minimum feature size is the smallest dimension a designer can select for a
given technology
Circuits design, simulation & layout formation
Circuits are designed using standard software packages such as Cadence
or Mentor Graphics
Within the libraries of the software there exist standard circuits which a
designer can use
Circuit designer can input values for parameters of the devices or circuits
and carry out a simulation
Once the circuit design is selected, layouts for the masks can be produced
L
R Rsquare where Rsquare
W t
Where is the resistivity of the material, L is the length, W is the width and t
is the thickness of the resistor
Circuit designers are normally given the sheet resistance, and produce the
designs for the load by changing the value of W and L only
m
L
t
If the resistor is divided into square of equal length and width given by the
minimum feature size then the resistance can be expressed as,
L n m
R Rsquare Rsquare n Rsquares
W m
A m B
B
Design and layout of ‘active’ loads
Due to large areas of implanted resistors on silicon wafer, active (transistor)
loads are normally preferred
contact
W
or via
The aspect ratio (W/L) of the load can be determined using the device constant
of the transistor depending the mode of operation
n m
A mask is needed to define the polysilicon stripe for the gate. Other regions
apart from the strip will be etched off after the patterning process
Fabrication and layouts for a n-MOSFET
After patterning and etching the polysilicon in other region, the gate strip is
defined as below:
L= m
W=s m
For small devices, the width of this stripe is equal to m and normally defines
the channel length L of the transistor. And the length at which the strips
overlaps the active region is the width W of the transistor given as a multiple of
m, as shown in diagram above where s is a whole number
Fabrication and layouts for a n-MOSFET
The silicon dioxide is etched off and
removed from the source and drain
regions
a
a
The contacts must have a minimum alignment error a from the gate or the
edge of the implant
A contact to the gate must be made away from the device and must be made
on the widened part of the stripe so that this contact holes is square with sides
equal to the m and a distance equal to the maximum alignment error from the
edge of the poly gate
Fabrication and layouts for a n-MOSFET
Aluminium is evaporated to cover the whole
area and is then patterned into the shape of
the conductor patterns across the chip. The
aluminium makes contact to the source and
drain down the contact holes
The width of the aluminium stripes must cover the contact holes with allowance
on either side of an amount equal to the minimum alignment accuracy a
Note the oxide on top of the gate isolates from the aluminium contact
Example of single inverter layout
This layout is an example of a
inverter consisting an n-MOS
driver with an n-MOS saturated
load
All the dimensions of the devices are expressed in terms of the minimum
feature size m hence independent of actual dimensions
Coursework
Design layouts for the 2-stage inverter
VDD
shown in Figure 1
RL
Both inverters consists of n-MOST C
Vo’
drivers A and B Vout
implanted resistor RL
The aspect ratio of the load C however is different. Note the resistance of C
needs to be larger than A so that the output voltage Vo’ is low (>VT of B).
Select a practical value of Vo’ (< VT of driver B)
Coursework
VDD
Channel length L can be assumed to
be equal to minimum feature size m RL
C
logic 0
Vin = VDD (logic 1) = 5V, VT of the n- Vo’ logic 1
Vout
MOSTs = 0.3 V, βo = 1.8 10-4 AV-2
A B
on off
Select a practical value for W and Vo’. Vin
logic 1
For each inverter, the resistance of the load should be greater than the driver
so as to obtain a low voltage for logic 0
Include all your calculations and reasons for the assumptions made
Include all the design layouts (for each of the masks and the overall layout)
in scaled graph paper and label the regions indicating the values of the
minimum features sizes chosen
Recommended Texts
K. Martin, Digital Integrated Circuit Design, Pub. Oxford ISBN0-19512584