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Integrated Electronics & Design

ELEC 100

Simple circuits – design issues & layout formations

M. Raja [2010]
Performance of a device and/or circuit
 The speed of operation of a device is dependent on mobility µ of the charge
carriers and inversely dependent on the square of the channel length L (or
minimum feature size m)

Speed
L2

 When designing a transistor or circuit, the designer needs to define the different
dimensions of the device i.e. channel width, channel length and contacts etc in
terms of the ‘minimum feature’ size m

 This makes the design independent of the actual dimensions. For example if the
device has W = 10µm and L = 3µm then if for a given technology m = 0.5µm,
then W and L are given as 20 m and 6 m respectively

 Minimum feature size is the smallest dimension a designer can select for a
given technology
Circuits design, simulation & layout formation
 Circuits are designed using standard software packages such as Cadence
or Mentor Graphics

 Within the libraries of the software there exist standard circuits which a
designer can use

 Circuit designer can input values for parameters of the devices or circuits
and carry out a simulation

 Once the circuit design is selected, layouts for the masks can be produced

 Note masks are normally required during photolithography process to define


specific region where particular processes need to be carried out (see
lecture on fabrications)
Design of the load resistor
 In digital circuits, resistors are used as loads but not common due to the large
areas

 The resistance can be defined in terms of ‘sheet resistance’ Rsquare ( /square)


as:

L
R Rsquare where Rsquare
W t

 Where is the resistivity of the material, L is the length, W is the width and t
is the thickness of the resistor

 Circuit designers are normally given the sheet resistance, and produce the
designs for the load by changing the value of W and L only

 Note: Do not confuse W and L for a resistor with those of a transistor


Design of the load resistor
 The dimensions of the resistor i.e. W, L and t can represented in terms of the
minimum feature size m as indicated in the diagram below:

m
L
t

 If the resistor is divided into square of equal length and width given by the
minimum feature size then the resistance can be expressed as,

L n m
R Rsquare Rsquare n Rsquares
W m

 n is number (whole number) of squares. The sheet resistance is normally fixed


value depending on the implantation process e.g. Rsquare= 200 /square
Layout formation of the load resistor
 Normally the resistor implanted load takes a large area on silicon. To minimise
the space the resistor is normally laid in a ’serpentine’ pattern
 For example, if you need a load resistor of 2.6k and given Rsquare= 200 /sq
then you would require 13 squares. And to minimise the area, the squares are
arranged in a serpentine pattern rather than a straight line shown below

A m B

B
Design and layout of ‘active’ loads
 Due to large areas of implanted resistors on silicon wafer, active (transistor)
loads are normally preferred

 As discussed previously, the different active loads include saturated, unsaturated


and depletion modes

 The layout of an active load can be represented as shown below, with


dimensions W and L represented in terms m. W can be assumed to be equal to
m and L factor of n m

contact
W
or via

 The aspect ratio (W/L) of the load can be determined using the device constant
of the transistor depending the mode of operation

 Contact regions are included at the ends, also expressed in terms of m


Layout formation for a n-MOSFET
 The layouts for the n-MOSFET can be appreciated by following the fabrication
process

 The four masks that need to be defined are:


 device area
masks indicating the shape of the design
 gate strip corresponding to the material to be etched away
 contacts
indicates the shape of the design corresponding
 metal pattern to the metal to be left behind after etching

 Recall the fabrication processes for n- MOSFET


Fabrication and layouts for a n-MOSFET
 A polished doped (e.g. p-type) silicon
slice is oxidised to form a thick field
oxide for layering

 The next stage involved defining the


‘active region’ where the transistor is to
be defined
 To open up this region, a mask is required to define the active region or device
area. The mask or layout can be represented by a square (on left) whose size
must be equal to a multiple of the minimum feature size m
n m

n m

Top view of device area Cross-section view


Fabrication and layouts for a n-MOSFET
 The wafer is re-oxidised to form a thin
gate oxide

 Polysilicon (for gate contact) is then


deposited and covers the whole wafer

 A mask is needed to define the polysilicon stripe for the gate. Other regions
apart from the strip will be etched off after the patterning process
Fabrication and layouts for a n-MOSFET
 After patterning and etching the polysilicon in other region, the gate strip is
defined as below:

L= m

W=s m

 For small devices, the width of this stripe is equal to m and normally defines
the channel length L of the transistor. And the length at which the strips
overlaps the active region is the width W of the transistor given as a multiple of
m, as shown in diagram above where s is a whole number
Fabrication and layouts for a n-MOSFET
 The silicon dioxide is etched off and
removed from the source and drain
regions

 Ion implantation process is carried out


to define or doped the source and
drain contacts. The polysilicon gate is
also doped in the same process and
makes it more conducting

 A thick layer of silicon dioxide is


deposited on the surface
Fabrication and layouts for a n-MOSFET
 Contacts or via holes need to be opened through the silicon dioxide. Each
of these holes must have a dimension equal to m or a multiple of it

a
a

 The contacts must have a minimum alignment error a from the gate or the
edge of the implant

 A contact to the gate must be made away from the device and must be made
on the widened part of the stripe so that this contact holes is square with sides
equal to the m and a distance equal to the maximum alignment error from the
edge of the poly gate
Fabrication and layouts for a n-MOSFET
 Aluminium is evaporated to cover the whole
area and is then patterned into the shape of
the conductor patterns across the chip. The
aluminium makes contact to the source and
drain down the contact holes

 The width of the aluminium stripes must cover the contact holes with allowance
on either side of an amount equal to the minimum alignment accuracy a

 Note the oxide on top of the gate isolates from the aluminium contact
Example of single inverter layout
 This layout is an example of a
inverter consisting an n-MOS
driver with an n-MOS saturated
load

 In circuits, addition layers are


included for the VDD and GND
lines. The width of these lines
are normally equal to m

 The designs need to be


arranged in such a way so as
to minimize the total area of
the silicon used

 All the dimensions of the devices are expressed in terms of the minimum
feature size m hence independent of actual dimensions
Coursework
 Design layouts for the 2-stage inverter
VDD
shown in Figure 1
RL
 Both inverters consists of n-MOST C

Vo’
drivers A and B Vout

 For 1st inverter the load C is a saturated B


A
n-MOST whilst load of 2nd inverter is an Vin

implanted resistor RL

 The aspect ratios (W/L) of both drivers


Figure 1
can be assumed to be the same

 The aspect ratio of the load C however is different. Note the resistance of C
needs to be larger than A so that the output voltage Vo’ is low (>VT of B).
Select a practical value of Vo’ (< VT of driver B)
Coursework
VDD
 Channel length L can be assumed to
be equal to minimum feature size m RL
C
logic 0
 Vin = VDD (logic 1) = 5V, VT of the n- Vo’ logic 1
Vout
MOSTs = 0.3 V, βo = 1.8 10-4 AV-2
A B
on off
 Select a practical value for W and Vo’. Vin
logic 1

The resistance of the load C and RL


can be assumed to be the same
Figure 1

 For each inverter, the resistance of the load should be greater than the driver
so as to obtain a low voltage for logic 0

 Use equivalent circuits or potential dividers to determine the resistance values


Report
 Give a brief description of the operation of the circuit in figure 1

 Include all your calculations and reasons for the assumptions made

 Include all the design layouts (for each of the masks and the overall layout)
in scaled graph paper and label the regions indicating the values of the
minimum features sizes chosen

 Use different shading to indicate the different regions

 Deadline for submission of the report is 21st April 2010

 Recommended Texts
K. Martin, Digital Integrated Circuit Design, Pub. Oxford ISBN0-19512584

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