LOW VOLTAGE SWING CIRCUITS FOR LOW DISSIPATION BUSSES
Gian Carlo Cardarilli1, Marcello Salmeri2, Adelio Salsano3, Osvaldo Simonelli4
Department of Electronic Engineering, University of Roma “Tor Vergata”
Via della Ricerca Scientifica - I-00133 Roma - Italy
1
cardarilli@utovrm.it, 2 salmeri@eln.utovrm.it, 3 salsano@eln.utovrm.it, 4 simonelli@utovrm.it
ABSTRACT
Power reduction is one of the most important issues of
the modern VLSI design. Many analysis show that larger
quantity of power is dissipated for the communication,
both inside that outside of the chip. Different
methodologies have been proposed to reduce such power
dissipation. In this paper we consider the approach based
on the reduction of the voltage. In literature this approach
is based on interface circuits that make use of
sophisticated technology. Moreover the proposed circuits
and quite complex. Our efforts are devoted to develop a
solution based on quite simple interface circuits
implemented in conventional CMOS technology. In this
paper we will review the interface circuits already are
proposed by the authors [10] will discuss the measurement
results of a testing chip. Starting from the drawbacks
highlighted by these measurements we propose a new
circuits based on a new technique of voltage swing
reduction and we present a preliminary simulation.
1. INTRODUCTION
The growing demand of portable equipment and the
growing complexity of the VLSI circuits makes the power
reduction one of the most important design issue for
future architectures and therefore in the optimization
process new design tools add the power issue constraint to
the classically considered area and speed [1]: power
saving is paid at the price of area increase and/or speed
decrease.
As it is well known, in the CMOS technology the
major contribute to power consumption is given by the
charge of parasitic capacitance. Consequently, most of the
power is dissipated in the interconnections characterized
by a large capacitances. For these reasons, the internal and
the external busses are the more critical point in the circuit
for the power consumption. In fact they consist of long
interconnection lines with large fan-out. Paper [2] shows
that these busses dissipate up to 50% of the total power of
the VLSI circuit.
Different approaches have been proposed in order to
limit the power consumption in the bus. These methods
are based on two basic techniques: the first one reduces
the power by reducing the swing of bus signals [3-5],
while the second one reduces the consumption by
implementing a charge-recycling procedure [6].
A complete evaluation of these solutions involves a
comparison of the resulting architectures in terms of
power reduction, technology constraints and hardware
complexity. For example, while charge-recycling
techniques are very efficient in terms of power saving,
they seem quite complex in terms of circuit
implementation.
In our work we use an approach based on voltage
swing reduction. This approach requires additional
circuitry consisting in a driver and a receiver for each line
of the bus.
Different solutions have been proposed in literature
for the implementation of circuits based on reduced
voltage swing. The main drawbacks are related to the
circuit complexity and to the need of special technology.
Instead, our efforts are devoted to develop a solution
based on quite simple interface circuits implemented in
conventional CMOS technology. In the following section
we will review the interface circuits already proposed by
the authors [10] and will discuss the measurement results
on a testing chip. These measures show a good power
reduction (more than 80%) but point out some drawbacks
of the driver. In particular the bus voltage is greatly
dependent on the capacitive load. Starting from these
drawbacks we propose a new circuit based on a new
technique of voltage swing reduction which is simulated.
2. THE NEW BUS ARCHITECTURE
The architecture consists in a two rail bus, with a
driver for each original line which transforms the 0’s and
1’s respectively in low swing differential signal on either
output line. The differential low swing output signal is
transformed in a full swing (0 to Vdd) signal by a receiver
realized with a sense amplifier as in [4]. The block
structure is shown in Fig. 1 and the theoretical power
saving with respect to the dissipation is given by
P1 − P 2 Vdd - 2 ⋅ Vs
≅
P1 Vdd
where P1 and P2 are the powers dissipated on the
standard and low power busses, Vs and Vdd are the low
swing voltage on the bus and supply voltages.
As can be easily verified, the power saving could
reach a theoretical value of 88% for Vs = 300 mV and td
Vdd = 5 V.
DRIVERS RECEIVERS
CLK
DATA_IN (1) BUS_LINE (1) OUT (1)
Cw
DATA_IN (1) 1 1 OUT (1)
BUS_LINE (1)

DATA_IN (2) BUS_LINE (2) OUT (2) Fig. 3. Schematic of drivers and receiver.
DATA_IN (2) 2 2 OUT (2)
BUS_LINE (2)
The data bit driver is realized with two similar circuits
having complementary input and output signals (IN1, IN2
and INP, INN).
DATA_IN (N) BUS_LINE (N) OUT (N) The single driver circuit consists of an inverter with
DATA_IN (N) N
BUS_LINE (N) N OUT (N) the pull-up transistor (MP1) connected to Vdd by means of
another pMOS (MP2) which controls the current flow
Fig. 1. Bus architecture scheme [10]. from the supply. The control of the current flow from the
supply to the bus is realized by controlling the state of
This architecture is similar to the ones proposed in [3, pMOS MP2 when the pMOS MP1 is on. We can drive the
4] but, as will be shown in the next section, our solution bus with different voltage swings changing the time td
uses a conventional technology and less complexity corresponding to MP1 and MP2 both on.
hardware for the driver. The receiver consists of a current-controlled latch
sense-amplifier. While the clock is high, the sense
3. THE EXPERIMENTAL CHIP amplifier outputs are predischarged. When the clock
varies from 1 to 0, the sense amplifier is activated and it
In Fig. 2 the layout of an experimental chip is shown. captures the differential value between the two rail bus
It is realized using a conventional CMOS 0.7 µm ES2 inputs. The full swing outputs can drive the following
technology. conventional digital circuit.

4. THE MEASUREMENTS
Receiver In order to verify the simulation results presented in
[10] and the reliability of the proposed architecture, a set
of measurements have been realized. The scheme of the
experimental setup is shown in Fig. 4.
BUS

Drivers
Fig. 2. Photo of the experimental chip.

The chip includes two drivers which control the

voltage swing on the internal bus. This bus consists of two
1500 µm long wires. Another line is added, which is
driven with full swing voltage to permit the measurement
of cross-talk interference on the adjacent two low-voltage
wires. The couple of drivers and receiver is shown in
Fig.3. Fig. 4. Scheme of the experimental setup.

Each measurement was done twice, with and without a

full swing signal on the line close to the differential wire.
Considering this coupled line at the minimum allowed
distance from the bus, we obtained that it’s possible to
reduce the voltage swing to 300 mV before errors would doesn’t affect the performance of the circuit because it can
occur during transmission. increase the charged bus line to a higher voltage value.

CK Receiver INN

INP

Fig. 6. Signals on the bus.

CK Drivers The entity of power reduction can be inferred from

Fig. 7 which shows the measurements of the supply
Fig. 5a. Receiver and driver clock signals. current for different values of the voltage on the bus. In
Fig. 7a we can see the spikes of current produced by the
driver and receiver switching.

IN2

Driver Receiver

IN1
Fig. 5b. Driver input signals.

INN Fig. 7a. Supply current with bus swing of 300 mV.

INP

Fig. 5c. Bus signals.

OUTP
Fig. 7b. Supply current with bus swing of 5 V.

OUTN The power dissipated with this low voltage swing bus,
calculated as the integral of the supply voltage and
current, is reduced of about 80%.

5. THE NEW DRIVER

Fig. 5d. Receiver output signals.
The power used for off-chip driving is very
Fig. 5, acquired from a digital oscilloscope with a base dominating and becomes more dominating with scaling
[2]. Up to 70% of the power may be due to off-chip
time at 2 µs/div, shows the signals on all the chain of the
driving and in order to reduce the global power, it is
transmission system. The output from the receiver (shown
necessary to reduce the power used for off-chip driving.
in Fig. 5d) can drive correctly an external SR flip-flop.
This can be done by several choices: using a more
Fig.6 shows the measurements of the signals on the
advanced off-chip technology (Multi Chip Module), using
bus with a low bit rate in order to easily acquire the supply
single chip solution or reducing the off chip swing.
current signal. Here it is possible to see the effect of the
One of the main drawback of the above circuit [10]
receiver clock on the bus due to the capacitance coupling
concerns on the dependence of the output voltage swing
the bus line and the receiver clock line. This behavior
on the bus capacitance. In order to obtain a voltage bus
swing independent from the load we propose the new
driver shown in Fig. 8.
In this circuit, when the input signal (IN) go down, the
current flows from the supply to the bus until the output
voltage reaches the voltage (VREF - Vtn) where VREF is the
voltage on the gate of nMOS MN2 and Vtn is its threshold
voltage. In order to have a reference voltage without any
static power dissipation it was realized using a couple of
transistors nMOS and pMOS, the pMOS connect to Vss
and nMOS connect to Vdd.
Fig. 8. New driver circuit.
Fig. 9 shows the bus and the reference voltages
obtained by simulating the driver with different loads (100
fF, 1 pF and 10 pF). It could be highlighted two
advantages. The first one is the very short rise time of the
bus signal because of the very low bus voltage level. The
second one concerns the low sensitivity of this level from
the capacitive load because the output voltage doesn’t rise
over (VREF - Vtn).
CLOAD
100f
OUT 1p
10p
REF
Fig. 9. Voltage swing on the bus with different load.
6. CONCLUSIONS
This paper proposes a new low-swing architecture for
VLSI busses which greatly reduces power dissipation on
long lines without the need of non-conventional
technology or high complexity hardware.
The experimental results confirm the validity of the
architecture showing a power saving of more than 80%
with respect to a conventional circuits. The simulation
results of the new proposed driver promises moreover a
very low sensibility for different loads.
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