Octal, 14-Bit, 50 MSPS,

Serial LVDS, 1.8 V ADC

AD9252
FEATURES FUNCTIONAL BLOCK DIAGRAM
AVDD PDWN DRVDD DRGND
8 analog-to-digital converters (ADCs) integrated into 1 package
93.5 mW ADC power per channel at 50 MSPS AD9252 14
SNR = 73 dB (to Nyquist) VIN + A SERIAL D+A
ADC LVDS D–A
ENOB = 12 bits VIN – A

SFDR = 84 dBc (to Nyquist) 14

VIN + B SERIAL D+B
ADC
Excellent linearity VIN – B LVDS D–B

DNL = ±0.4 LSB (typical); INL = ±1.5 LSB (typical) 14

VIN + C SERIAL D+C
Serial LVDS (ANSI-644, default) VIN – C
ADC
LVDS D–C
Low power, reduced signal option (similar to IEEE 1596.3) 14
VIN + D SERIAL D+D
Data and frame clock outputs VIN – D
ADC LVDS D–D
325 MHz, full-power analog bandwidth 14
2 V p-p input voltage range VIN + E SERIAL D+E
ADC LVDS D–E
VIN – E
1.8 V supply operation
14
Serial port control VIN + F
ADC
SERIAL D+F
VIN – F LVDS D–F
Full-chip and individual-channel power-down modes
14
Flexible bit orientation VIN + G SERIAL D+G
ADC D–G
Built-in and custom digital test pattern generation VIN – G LVDS

Programmable clock and data alignment VIN + H

14
D+H
SERIAL
Programmable output resolution ADC LVDS D–H
VIN – H
Standby mode
VREF
SENSE FCO+
APPLICATIONS 0.5V FCO–
DATA RATE
Medical imaging and nondestructive ultrasound REFT REF MULTIPLIER
REFB SELECT SERIAL PORT DCO+
Portable ultrasound and digital beam-forming systems INTERFACE DCO–

Quadrature radio receivers

06296-001
RBIAS AGND CSB SDIO/ SCLK/ CLK+ CLK–
Diversity radio receivers ODM DTP
Tape drives Figure 1.
Optical networking
Test equipment The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
GENERAL DESCRIPTION clock and data alignment and programmable digital test pattern
The AD9252 is an octal, 14-bit, 50 MSPS ADC with an on-chip generation. The available digital test patterns include built-in
sample-and-hold circuit designed for low cost, low power, small size, deterministic and pseudorandom patterns, along with custom user-
and ease of use. Operating at a conversion rate of up to 50 MSPS, defined test patterns entered via the serial port interface (SPI).
it is optimized for outstanding dynamic performance and low The AD9252 is available in an RoHS compliant, 64-lead LFCSP. It is
power in applications where a small package size is critical. specified over the industrial temperature range of −40°C to +85°C.
The ADC requires a single 1.8 V power supply and LVPECL-/ PRODUCT HIGHLIGHTS
CMOS-/LVDS-compatible sample rate clock for full performance
1. Small Footprint. Eight ADCs are contained in a small package.
operation. No external reference or driver components are
2. Low Power of 93.5 mW per Channel at 50 MSPS.
required for many applications.
3. Ease of Use. A data clock output (DCO) operates up to
The ADC automatically multiplies the sample rate clock for 350 MHz and supports double data rate (DDR) operation.
the appropriate LVDS serial data rate. A data clock (DCO) 4. User Flexibility. SPI control offers a wide range of flexible
for capturing data on the output and a frame clock (FCO) for features to meet specific system requirements.
signaling a new output byte are provided. Individual channel 5. Pin-Compatible Family. This includes the AD9212 (10-bit)
power-down is supported and typically consumes less than and AD9222 (12-bit).
2 mW when all channels are disabled.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com
Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2006–2010 Analog Devices, Inc. All rights reserved.
AD9252
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Specifications.......................................................................... 4
Digital Specifications ................................................................... 5
Switching Specifications .............................................................. 6
Timing Diagrams.......................................................................... 7
Absolute Maximum Ratings............................................................ 9
Thermal Impedance ..................................................................... 9
ESD Caution .................................................................................. 9
Pin Configuration and Function Descriptions ........................... 10
Equivalent Circuits ......................................................................... 12
Typical Performance Characteristics ........................................... 14
Theory of Operation ...................................................................... 17
Analog Input Considerations.................................................... 17
REVISION HISTORY
4/10—Rev. C to Rev. D
Changes to Address 16 in Table 16............................................... 31
Updated Outline Dimensions ....................................................... 52
Changes to Ordering Guide .......................................................... 52
12/09—Rev. B to Rev. C
Updated Outline Dimensions ....................................................... 52
Changes to Ordering Guide .......................................................... 52
7/09—Rev. A to Rev. B
Changes to Figure 5 ........................................................................ 10
Changes to Figure 38 and Figure 39 ............................................. 18
Changes to Figure 51 and Figure 52 ............................................. 25
Updated Outline Dimensions ....................................................... 52
12/07—Rev. 0 to Rev. A
Changes to Features.......................................................................... 1
Changes to Crosstalk Parameter..................................................... 3
Changes to Figure 2 to Figure 4 ...................................................... 7
Changes to Table 9 Endnote .......................................................... 23
Changes to Digital Outputs and Timing Section ....................... 24
Added Table 10 ............................................................................... 24
Changes to Table 11 and Table 12 ................................................ 24
Rev. D | Page 2 of 52
Clock Input Considerations ...................................................... 19
Serial Port Interface (SPI) .............................................................. 27
Hardware Interface..................................................................... 27
Memory Map .................................................................................. 29
Reading the Memory Map Table .............................................. 29
Reserved Locations .................................................................... 29
Default Values ............................................................................. 29
Logic Levels ................................................................................. 29
Applications Information .............................................................. 32
Design Guidelines ...................................................................... 32
Evaluation Board ............................................................................ 33
Power Supplies ............................................................................ 33
Input Signals................................................................................ 33
Output Signals ............................................................................ 33
Default Operation and Jumper Selection Settings ................. 34
Alternative Analog Input Drive Configuration...................... 35
Outline Dimensions ....................................................................... 52
Ordering Guide .......................................................................... 52
Changes to RBIAS Pin Section ..................................................... 25
Deleted Figure 51 to Figure 52...................................................... 25
Moved Figure 53 ............................................................................. 25
Changes to Serial Port Interface (SPI) Section ........................... 27
Changes to Table 15 ....................................................................... 28
Changes to Reading the Memory Map Table Section ............... 29
Added Applications Information and
Design Guidelines Sections ...................................................... 32
Changes to Input Signals Section ................................................. 33
Changes to Output Signals Section .............................................. 33
Changes to Figure 60...................................................................... 33
Changes to Default Operation and Jumper Selection
Settings Section .......................................................................... 34
Changes to Alternative Analog Input Drive
Configuration Section............................................................... 35
Added Figure 62 and Figure 63 .................................................... 35
Changes to Figure 68...................................................................... 42
Changes to Table 17 ....................................................................... 48
Updated Outline Dimensions ....................................................... 52
Changes to Ordering Guide .......................................................... 52
10/06—Revision 0: Initial Version
 AD9252

SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 1.
AD9252-50
Parameter 1 Temperature Min Typ Max Unit
RESOLUTION 14 Bits
ACCURACY
No Missing Codes Full Guaranteed
Offset Error Full ±1 ±8 mV
Offset Matching Full ±3 ±8 mV
Gain Error Full ±1.5 ±2.5 % FS
Gain Matching Full ±0.3 ±0.7 % FS
Differential Nonlinearity (DNL) Full ±0.4 ±1 LSB
Integral Nonlinearity (INL) Full ±1.5 ±4 LSB
TEMPERATURE DRIFT
Offset Error Full ±2 ppm/°C
Gain Error Full ±17 ppm/°C
Reference Voltage (1 V Mode) Full ±21 ppm/°C
REFERENCE
Output Voltage Error (VREF = 1 V) Full ±2 ±30 mV
Load Regulation @ 1.0 mA (VREF = 1 V) Full 3 mV
Input Resistance Full 6 kΩ
ANALOG INPUTS
Differential Input Voltage Range (VREF = 1 V) Full 2 V p-p
Common-Mode Voltage Full AVDD/2 V
Differential Input Capacitance Full 7 pF
Analog Bandwidth, Full Power Full 325 MHz
POWER SUPPLY
AVDD Full 1.7 1.8 1.9 V
DRVDD Full 1.7 1.8 1.9 V
IAVDD Full 360 373.4 mA
IDRVDD Full 55.5 58 mA
Total Power Dissipation (Including Output Drivers) Full 748 773 mW
Power-Down Dissipation Full 2 11 mW
Standby Dissipation 2 Full 89 mW
CROSSTALK
AIN = −0.5 dBFS Full −90 dB
Overrange 3 Full −90 dB
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2
Can be controlled via the SPI.
3
Overrange condition is specific with 6 dB of the full-scale input range.

Rev. D | Page 3 of 52
AD9252
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 2.
AD9252-50
Parameter 1 Temperature Min Typ Max Unit
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 2.4 MHz Full 73.2 dB
fIN = 19.7 MHz Full 71 73 dB
fIN = 35 MHz Full 72.7 dB
fIN = 70 MHz Full 71 dB
SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)
fIN = 2.4 MHz Full 72.5 dB
fIN = 19.7 MHz Full 70.2 72.2 dB
fIN = 35 MHz Full 72 dB
fIN = 70 MHz Full 70.5 dB
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.4 MHz Full 11.87 Bits
fIN = 19.7 MHz Full 11.5 11.84 Bits
fIN = 35 MHz Full 11.79 Bits
fIN = 70 MHz Full 11.5 Bits
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 2.4 MHz Full 85 dBc
fIN = 19.7 MHz Full 73 84 dBc
fIN = 35 MHz Full 83 dBc
fIN = 70 MHz Full 79 dBc
WORST HARMONIC (SECOND OR THIRD)
fIN = 2.4 MHz Full −85 dBc
fIN = 19.7 MHz Full −84 −73 dBc
fIN = 35 MHz Full −83 dBc
fIN = 70 MHz Full −79 dBc
WORST OTHER (EXCLUDING SECOND OR THIRD)
fIN = 2.4 MHz Full −90 dBc
fIN = 19.7 MHz Full −90 −80 dBc
fIN = 35 MHz Full −90 dBc
fIN = 70 MHz Full −89 dBc
TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1 AND AIN2 = −7.0 dBFS
fIN1 = 15 MHz, fIN2 = 16 MHz 25°C 80.0 dBc
fIN1 = 70 MHz, fIN2 = 71 MHz 25°C 80.0 dBc
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

Rev. D | Page 4 of 52
 AD9252
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 3.
AD9252-50
Parameter 1 Temperature Min Typ Max Unit
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance CMOS/LVDS/LVPECL
Differential Input Voltage 2 Full 250 mV p-p
Input Common-Mode Voltage Full 1.2 V
Input Resistance (Differential) 25°C 20 kΩ
Input Capacitance 25°C 1.5 pF
LOGIC INPUTS (PDWN, SCLK/DTP)
Logic 1 Voltage Full 1.2 3.6 V
Logic 0 Voltage Full 0.3 V
Input Resistance 25°C 30 kΩ
Input Capacitance 25°C 0.5 pF
LOGIC INPUT (CSB)
Logic 1 Voltage Full 1.2 3.6 V
Logic 0 Voltage Full 0.3 V
Input Resistance 25°C 70 kΩ
Input Capacitance 25°C 0.5 pF
LOGIC INPUT (SDIO/ODM)
Logic 1 Voltage Full 1.2 DRVDD + 0.3 V
Logic 0 Voltage Full 0 0.3 V
Input Resistance 25°C 30 kΩ
Input Capacitance 25°C 2 pF
LOGIC OUTPUT (SDIO/ODM)3
Logic 1 Voltage (IOH = 800 μA) Full 1.79 V
Logic 0 Voltage (IOL = 50 μA) Full 0.05 V
DIGITAL OUTPUTS (D + x, D − x), (ANSI-644)
Logic Compliance LVDS
Differential Output Voltage (VOD) Full 247 454 mV
Output Offset Voltage (VOS) Full 1.125 1.375 V
Output Coding (Default) Offset binary
DIGITAL OUTPUTS (D + x, D − x),
(LOW POWER, REDUCED SIGNAL OPTION)
Logic Compliance LVDS
Differential Output Voltage (VOD) Full 150 250 mV
Output Offset Voltage (VOS) Full 1.10 1.30 V
Output Coding (Default) Offset binary
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2
This is specified for LVDS and LVPECL only.
3
This is specified for 13 SDIO pins sharing the same connection.

Rev. D | Page 5 of 52
AD9252
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 4.
AD9252-50
Parameter 1 Temp Min Typ Max Unit
CLOCK 2
Maximum Clock Rate Full 50 MSPS
Minimum Clock Rate Full 10 MSPS
Clock Pulse Width High (tEH) Full 10.0 ns
Clock Pulse Width Low (tEL) Full 10.0 ns
OUTPUT PARAMETERS2, 3
Propagation Delay (tPD) Full 1.5 2.3 3.1 ns
Rise Time (tR) (20% to 80%) Full 300 ps
Fall Time (tF) (20% to 80%) Full 300 ps
FCO Propagation Delay (tFCO) Full 1.5 2.3 3.1 ns
DCO Propagation Delay (tCPD) 4 Full tFCO + (tSAMPLE/28) ns
DCO to Data Delay (tDATA)4 Full (tSAMPLE/28) − 300 (tSAMPLE/28) (tSAMPLE/28) + 300 ps
DCO to FCO Delay (tFRAME)4 Full (tSAMPLE/28) − 300 (tSAMPLE/28) (tSAMPLE/28) + 300 ps
Data-to-Data Skew (tDATA-MAX − tDATA-MIN) Full ±50 ±200 ps
Wake-Up Time (Standby) 25°C 600 ns
Wake-Up Time (Power-Down) 25°C 375 μs
Pipeline Latency Full 8 CLK cycles
APERTURE
Aperture Delay (tA) 25°C 750 ps
Aperture Uncertainty (Jitter) 25°C <1 ps rms
Out-of-Range Recovery Time 25°C 1 CLK cycles
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2
Can be adjusted via the SPI.
3
Measurements were made using a part soldered to FR-4 material.
4
tSAMPLE/28 is based on the number of bits divided by 2 because the delays are based on half duty cycles.

Rev. D | Page 6 of 52
 AD9252
TIMING DIAGRAMS
N–1

VIN ± x

tA
N

tEH tEL
CLK–

CLK+

tCPD
DCO–

DCO+

tFCO tFRAME
FCO–

FCO+

tPD tDATA
D–x
MSB D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB D12

06296-002
N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–8 N–8
D+x

Figure 2. 14-Bit Data Serial Stream (Default), MSB First

N–1

VIN ± x tA

tEH tEL
CLK–

CLK+

tCPD
DCO–

DCO+

tFCO tFRAME
FCO–

FCO+

tPD tDATA
D–x
MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB D10
N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–8 N–8
06296-003

D+x

Figure 3. 12-Bit Data Serial Stream, MSB First

Rev. D | Page 7 of 52
AD9252
N–1

VIN ± x

tA

tEH tEL
CLK–

CLK+

tCPD
DCO–

DCO+

tFCO tFRAME
FCO–

FCO+

tPD tDATA
D–x
LSB D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 LSB D0

06296-004
N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–9 N–8 N–8
D+x

Figure 4. 14-Bit Data Serial Stream, LSB First

Rev. D | Page 8 of 52
 AD9252

ABSOLUTE MAXIMUM RATINGS

THERMAL IMPEDANCE
Table 5.
With Table 6.
Parameter Respect To Rating Air Flow Velocity (m/s) θJA1 θJB θJC Unit
ELECTRICAL 0.0 17.7 °C/W
AVDD AGND −0.3 V to +2.0 V 1.0 15.5 8.7 0.6 °C/W
DRVDD DRGND −0.3 V to +2.0 V 2.5 13.9 °C/W
AGND DRGND −0.3 V to +0.3 V
1
AVDD DRVDD −2.0 V to +2.0 V θJA for a 4-layer PCB with solid ground plane (simulated). Exposed pad
soldered to PCB.
Digital Outputs DRGND −0.3 V to +2.0 V
(D + x, D − x, DCO+,
DCO−, FCO+, FCO−) ESD CAUTION
CLK+, CLK− AGND −0.3 V to +3.9 V
VIN + x, VIN − x AGND −0.3 V to +2.0 V
SDIO/ODM AGND −0.3 V to +2.0 V
PDWN, SCLK/DTP, CSB AGND −0.3 V to +3.9 V
REFT, REFB, RBIAS AGND −0.3 V to +2.0 V
VREF, SENSE AGND −0.3 V to +2.0 V
ENVIRONMENTAL
Operating Temperature −40°C to +85°C
Range (Ambient)
Storage Temperature −65°C to +150°C
Range (Ambient)
Maximum Junction 150°C
Temperature
Lead Temperature 300°C
(Soldering, 10 sec)
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Rev. D | Page 9 of 52
AD9252

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VIN + D

VIN + C
VIN – D

VIN – C
VIN + E
VIN – E
VIN + F
VIN – F

SENSE
RBIAS
AVDD

AVDD

AVDD
REFB
VREF
REFT
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PIN 1
AVDD 1 INDICATOR 48 AVDD
VIN + G 2 47 VIN + B
VIN – G 3 46 VIN – B
AVDD 4 EXPOSED PADDLE, PIN 0 45 AVDD
VIN – H 5 (BOTTOM OF PACKAGE) 44 VIN – A
VIN + H 6 43 VIN + A
AVDD 7 AD9252 42 AVDD
AVDD 8 41 PDWN
TOP VIEW
CLK– 9 40 CSB
(Not to Scale)
CLK+ 10 39 SDIO/ODM
AVDD 11 38 SCLK/DTP
AVDD 12 37 AVDD
DRGND 13 36 DRGND
DRVDD 14 35 DRVDD
D–H 15 34 D+A
D+H 16 33 D–A
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
D+F
D+G

D+E

FCO–
FCO+

D+D

D+C

D+B
D–E
D–F

D–D

D–C

D–B
D–G

DCO+
DCO–

06296-005
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND
Figure 5. 64-Lead LFCSP Pin Configuration, Top View

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description
0 AGND Analog Ground (Exposed Paddle)
1, 4, 7, 8, 11, AVDD 1.8 V Analog Supply
12, 37, 42, 45,
48, 51, 59, 62
13, 36 DRGND Digital Output Driver Ground
14, 35 DRVDD 1.8 V Digital Output Driver Supply
2 VIN + G ADC G Analog Input True
3 VIN − G ADC G Analog Input Complement
5 VIN − H ADC H Analog Input Complement
6 VIN + H ADC H Analog Input True
9 CLK− Input Clock Complement
10 CLK+ Input Clock True
15 D−H ADC H Digital Output Complement
16 D+H ADC H Digital Output True
17 D−G ADC G Digital Output Complement
18 D+G ADC G Digital Output True
19 D−F ADC F Digital Output Complement
20 D+F ADC F Digital Output True
21 D−E ADC E Digital Output Complement
22 D+E ADC E Digital Output True
23 DCO− Data Clock Digital Output Complement
24 DCO+ Data Clock Digital Output True
25 FCO− Frame Clock Digital Output Complement
26 FCO+ Frame Clock Digital Output True
27 D−D ADC D Digital Output Complement
28 D+D ADC D Digital Output True
29 D−C ADC C Digital Output Complement
30 D+C ADC C Digital Output True
31 D−B ADC B Digital Output Complement

Rev. D | Page 10 of 52
 AD9252
Pin No. Mnemonic Description
32 D+B ADC B Digital Output True
33 D−A ADC A Digital Output Complement
34 D+A ADC A Digital Output True
38 SCLK/DTP Serial Clock/Digital Test Pattern
39 SDIO/ODM Serial Data Input-Output/Output Driver Mode
40 CSB Chip Select Bar
41 PDWN Power-Down
43 VIN + A ADC A Analog Input True
44 VIN − A ADC A Analog Input Complement
46 VIN − B ADC B Analog Input Complement
47 VIN + B ADC B Analog Input True
49 VIN + C ADC C Analog Input True
50 VIN − C ADC C Analog Input Complement
52 VIN − D ADC D Analog Input Complement
53 VIN + D ADC D Analog Input True
54 RBIAS External Resistor to Set the Internal ADC Core Bias Current
55 SENSE Reference Mode Selection
56 VREF Voltage Reference Input/Output
57 REFB Negative Differential Reference
58 REFT Positive Differential Reference
60 VIN + E ADC E Analog Input True
61 VIN − E ADC E Analog Input Complement
63 VIN − F ADC F Analog Input Complement
64 VIN + F ADC F Analog Input True

Rev. D | Page 11 of 52
AD9252

EQUIVALENT CIRCUITS
DRVDD

V V

VIN ± x D–x D+x

V V

06296-006

06296-009
DRGND

Figure 6. Equivalent Analog Input Circuit Figure 9. Equivalent Digital Output Circuit

10Ω
CLK+

10kΩ

1.25V

10kΩ
1kΩ
10Ω SCLK/DTP OR PDWN
CLK– 30kΩ
06296-007

06296-010
Figure 7. Equivalent Clock Input Circuit Figure 10. Equivalent SCLK/DTP or PDWN Input Circuit

100Ω
RBIAS

350Ω
SDIO/ODM

30kΩ
06296-011
06296-008

Figure 8. Equivalent SDIO/ODM Input Circuit Figure 11. Equivalent RBIAS Circuit

Rev. D | Page 12 of 52
 AD9252
AVDD

70kΩ
1kΩ
CSB

VREF

06296-012

06296-014
6kΩ

Figure 12. Equivalent CSB Input Circuit Figure 14. Equivalent VREF Circuit

1kΩ
SENSE
06296-013

Figure 13. Equivalent SENSE Circuit

Rev. D | Page 13 of 52
AD9252

TYPICAL PERFORMANCE CHARACTERISTICS

0 0
AIN = –0.5dBFS AIN = –0.5dBFS
SNR = 73.71dB SNR = 71.16dB
ENOB = 11.95 BITS ENOB = 11.53 BITS
–20 SFDR = 85.86dBc –20 SFDR = 72.92dBc

AMPLITUDE (dBFS)
AMPLITUDE (dBFS)

–40 –40

–60 –60

–80 –80

–100 –100

–120 –120

06296-051
06296-048
0 5 10 15 20 25 0 5 10 15 20 25
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 15. Single-Tone 32k FFT with fIN = 2.3 MHz, fSAMPLE = 50 MSPS Figure 18. Single-Tone 32k FFT with fIN = 120 MHz, fSAMPLE = 50 MSPS

0 90
AIN = –0.5dBFS
SNR = 72.98dB SFDR
ENOB = 11.83 BITS
–20 SFDR = 83.8dBc 85
AMPLITUDE (dBFS)

–40 80
SNR/SFDR (dB)

–60 75 SNR

–80 70

–100 65

–120 60
06296-049

06296-039
0 5 10 15 20 25 10 15 20 25 30 35 40 45 50
FREQUENCY (MHz) ENCODE RATE (MSPS)

Figure 16. Single-Tone 32k FFT with fIN = 35 MHz, fSAMPLE = 50 MSPS Figure 19. SNR/SFDR vs. fSAMPLE, fIN = 10.3 MHz, AD9252-50

0 90
AIN = –0.5dBFS
SNR = 72.36dB
ENOB = 11.73 BITS
–20 SFDR = 86.21dBc 85
SFDR
AMPLITUDE (dBFS)

–40 80
SNR/SFDR (dB)

–60 75
SNR

–80 70

–100 65

–120 60
06296-050

06296-040

0 5 10 15 20 25 10 15 20 25 30 35 40 45 50
FREQUENCY (MHz) ENCODE RATE (MSPS)

Figure 17. Single-Tone 32k FFT with fIN = 70 MHz, fSAMPLE = 50 MSPS Figure 20. SNR/SFDR vs. fSAMPLE, fIN = 19.7 MHz, AD9252-50

Rev. D | Page 14 of 52
 AD9252
90 0
AIN1 AND AIN2 = –7dBFS
SFDR = 83.64dB
80 IMD2 = 95.57dBc
–20 IMD3 = 84.26dBc
SFDR
70

AMPLITUDE (dBFS)
–40
SNR/SFDR (dB)

60

50 –60
80dB REFERENCE
40
SNR –80
30

–100
20

06296-041

06296-044
10 –120
–60 –50 –40 –30 –20 –10 0 0 5 10 15 20 25
ANALOG INPUT LEVEL (dBFS) FREQUENCY (MHz)

Figure 21. SNR/SFDR vs. Analog Input Level, fIN = 10.3 MHz, fSAMPLE = 50 MSPS Figure 24. Two-Tone 32k FFT with fIN1 = 70 MHz and
fIN2 = 71 MHz, fSAMPLE = 50 MSPS

90 90

80
85
SFDR SFDR
70
80
SNR/SFDR (dB)

60
SNR/SFDR (dB)

50 75
SNR
80dB REFERENCE
40
SNR 70

30

65
20
06296-042

10 60

06296-045
–60 –50 –40 –30 –20 –10 0 1 10 100 1000
ANALOG INPUT LEVEL (dBFS) ANALOG INPUT FREQUENCY (MHz)

Figure 22. SNR/SFDR vs. Analog Input Level, fIN = 19.7 MHz, fSAMPLE = 50 MSPS Figure 25. SNR/SFDR vs. fIN, fSAMPLE = 50 MSPS

0 90
AIN1 AND AIN2 = –7dBFS
SFDR = 86.27dB
IMD2 = 97.82dBc
–20 IMD3 = 86.13dBc 85
SFDR
AMPLITUDE (dBFS)

–40 80
SINAD/SFDR (dB)

–60 75
SINAD

–80 70

–100 65
06296-046

–120 60
06296-043

0 5 10 15 20 25 –40 –20 0 20 40 60 80
FREQUENCY (MHz) TEMPERATURE (°C)

Figure 23. Two-Tone 32k FFT with fIN1 = 15 MHz and Figure 26. SINAD/SFDR vs. Temperature, fIN = 19.7 MHz, fSAMPLE = 50 MSPS
fIN2 = 16 MHz, fSAMPLE = 50 MSPS

Rev. D | Page 15 of 52
AD9252
2.0 1.8
1.047LSB rms
1.5 1.6

1.4

NUMBER OF HITS (Millions)

1.0
1.2
0.5
INL (LSB)

1.0
0
0.8
–0.5
0.6

–1.0
0.4

–1.5 0.2

–2.0 0

06296-054
06296-053
0 2000 4000 6000 8000 10000 12000 14000 16000 N–3 N–2 N–1 N N+1 N+2 N+3
CODE CODE

Figure 27. INL, fIN = 2.3 MHz, fSAMPLE = 50 MSPS Figure 30. Input-Referred Noise Histogram, fSAMPLE = 50 MSPS

1.0 0
NPR = 62.5dB
0.8 NOTCH = 18.0MHz
NOTCH WIDTH = 2.3MHz
–20
0.6

0.4
AMPLITUDE (dBFS)

–40
0.2
DNL (LSB)

0 –60

–0.2
–80
–0.4

–0.6
–100
–0.8

–1.0 –120

06296-038
06296-052

0 2000 4000 6000 8000 10000 12000 14000 16000 0 5 10 15 20 25

CODE FREQUENCY (MHz)

Figure 28. DNL, fIN = 2.3 MHz, fSAMPLE = 50 MSPS Figure 31. Noise Power Ratio (NPR), fSAMPLE = 50 MSPS

–30 0

–1
–35 –3dB BANDWIDTH = 325MHz
–2
–40
–3
AMPLITUDE (dBFS)

–45 –4
CMRR (dB)

–5
–50
–6
–55 –7

–8
–60
–9
–65
–10

–70 –11
06296-037
06296-055

0 5 10 15 20 25 30 35 40 0 50 100 150 200 250 300 350 400 450 500

FREQUENCY (MHz) FREQUENCY (MHz)

Figure 29. CMRR vs. Frequency, fSAMPLE = 50 MSPS Figure 32. Full-Power Bandwidth vs. Frequency, fSAMPLE = 50 MSPS

Rev. D | Page 16 of 52
 AD9252

THEORY OF OPERATION
The AD9252 architecture consists of a pipelined ADC divided
into three sections: a 4-bit first stage followed by eight 1.5-bit
stages and a 3-bit flash. Each stage provides sufficient overlap
to correct for flash errors in the preceding stage. The quantized
outputs from each stage are combined into a final 14-bit result
in the digital correction logic. The pipelined architecture permits
the first stage to operate with a new input sample while the
remaining stages operate with preceding samples. Sampling
occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor DAC
and an interstage residue amplifier (for example, a multiplying
digital-to-analog converter (MDAC)). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
The output staging block aligns the data, corrects errors, and
passes the data to the output buffers. The data is then serialized
and aligned to the frame and data clocks.
ANALOG INPUT CONSIDERATIONS
front end at high IF frequencies. Either a shunt capacitor or two
single-ended capacitors can be placed on the inputs to provide a
matching passive network. This ultimately creates a low-pass
filter at the input to limit unwanted broadband noise. See the
AN-742 Application Note, Frequency Domain Response of
Switched-Capacitor ADCs; the AN-827 Application Note, A
Resonant Approach to Interfacing Amplifiers to Switched-Capacitor
ADCs; and the Analog Dialogue article “Transformer-Coupled
Front-End for Wideband A/D Converters” (Volume 39, April
2005) for more information. In general, the precise values
depend on the application.
The analog inputs of the AD9252 are not internally dc-biased.
Therefore, in ac-coupled applications, the user must provide
this bias externally. Setting the device so that VCM = AVDD/2 is
recommended for optimum performance, but the device can
function over a wider range with reasonable performance, as
shown in Figure 34 and Figure 35.
90
SFDR (dBc)
85
80
SNR/SFDR (dB)

The analog input to the AD9252 is a differential switched-

capacitor circuit designed for processing differential input signals. 75

This circuit can support a wide common-mode range while SNR (dB)
maintaining excellent performance. An input common-mode 70

voltage of midsupply minimizes signal-dependent errors and

provides optimum performance. 65

60

06296-056
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
H ANALOG INPUT COMMON-MODE VOLTAGE (V)

CPAR Figure 34. SNR/SFDR vs. Common-Mode Voltage,

H fIN = 2.3 MHz, fSAMPLE = 50 MSPS
VIN + x
CSAMPLE
90
S S
S S
CSAMPLE 85
VIN – x SFDR (dBc)
H
CPAR
80
SNR/SFDR (dB)
06296-017

75
Figure 33. Switched-Capacitor Input Circuit SNR (dB)

The clock signal alternately switches the input circuit between 70

sample mode and hold mode (see Figure 33). When the input
circuit is switched into sample mode, the signal source must be 65

capable of charging the sample capacitors and settling within

one-half of a clock cycle. A small resistor in series with each 60
06296-057

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

input can help reduce the peak transient current injected from ANALOG INPUT COMMON-MODE VOLTAGE (V)
the output stage of the driving source. In addition, low-Q inductors
Figure 35. SNR/SFDR vs. Common-Mode Voltage,
or ferrite beads can be placed on each leg of the input to reduce fIN = 35 MHz, fSAMPLE = 50 MSPS
high differential capacitance at the analog inputs and therefore
achieve the maximum bandwidth of the ADC. Such use of low-Q
inductors or ferrite beads is required when driving the converter

Rev. D | Page 17 of 52
AD9252
ADT1-1WT
For best dynamic performance, the source impedances driving 1:1 Z RATIO C
R
VIN + x and VIN − x should be matched such that common-mode VIN + x

settling errors are symmetrical. These errors are reduced by the 2V p-p
ADC
49.9Ω CDIFF1 AD9252
common-mode rejection of the ADC. An internal reference buffer R
AVDD VIN – x AGND
creates the positive and negative reference voltages, REFT and C
1kΩ
REFB, respectively, that define the span of the ADC core. The
output common mode of the reference buffer is set to midsupply, 1kΩ

and the REFT and REFB voltages and span are defined as 0.1μF

06296-018
1C IS OPTIONAL.
DIFF
REFT = 1/2 (AVDD + VREF)
REFB = 1/2 (AVDD − VREF) Figure 36. Differential Transformer-Coupled Configuration
for Baseband Applications
Span = 2 × (REFT − REFB) = 2 × VREF
2V p-p ADT1-1WT
16nH 0.1μF 1:1 Z RATIO 16nH 33Ω
It can be seen from these equations that the REFT and REFB VIN+ x
voltages are symmetrical about the midsupply voltage and, by 65Ω
499Ω 2.2pF 1kΩ ADC
16nH
AD9252
definition, the input span is twice the value of the VREF voltage. 33Ω
VIN– x

Maximum SNR performance is achieved by setting the ADC to AVDD

1kΩ
the largest span in a differential configuration. In the case of the
AD9252, the largest input span available is 2 V p-p.

06296-019
1kΩ 0.1μF

Differential Input Configurations

Figure 37. Differential Transformer-Coupled Configuration for IF Applications
There are several ways to drive the AD9252 either actively or
passively; however, optimum performance is achieved by driving
Single-Ended Input Configuration
the analog input differentially. For example, using the AD8334 A single-ended input may provide adequate performance in cost-
differential driver to drive the AD9252 provides excellent perfor- sensitive applications. In this configuration, SFDR and distortion
mance and a flexible interface to the ADC (see Figure 39) for performance degrade due to the large input common-mode swing.
baseband applications. This configuration is commonly used If the application requires a single-ended input configuration,
for medical ultrasound systems. ensure that the source impedances on each input are well matched
in order to achieve the best possible performance. A full-scale input
For applications where SNR is a key parameter, differential
of 2 V p-p can still be applied to the ADC’s VIN + x pin while the
transformer coupling is the recommended input configuration
VIN − x pin is terminated. Figure 38 details a typical single-
(see Figure 36 and Figure 37), because the noise performance of
ended input configuration.
most amplifiers is not adequate to achieve the true performance
AVDD
of the AD9252.
C
Regardless of the configuration, the value of the shunt capacitor, 1kΩ R
VIN + x
C, is dependent on the input frequency and may need to be 2V p-p 49.9Ω 0.1µF 1kΩ
reduced or removed. CDIFF1 ADC
AVDD AD9252
1kΩ 25Ω R
VIN – x
0.1µF 1kΩ C

06296-020
1C IS OPTIONAL.
DIFF

Figure 38. Single-Ended Input Configuration

0.1μF

LOP VIP

187Ω 0.1μF R
0.1μF 120nH INH VOH
VIN + x
1V p-p
AD8334 1.0kΩ
22pF
LNA VGA 374Ω C
ADC
AD9252
1.0kΩ
R
0.1μF LMD VIN – x
VOL 187Ω 0.1μF
AVDD
LON VIN 0.1μF 10μF
1kΩ
06296-021

18nF 274Ω 0.1μF 1kΩ

Figure 39. Differential Input Configuration Using the AD8334

Rev. D | Page 18 of 52
 AD9252
CLOCK INPUT CONSIDERATIONS In some applications, it is acceptable to drive the sample clock
For optimum performance, the AD9252 sample clock inputs inputs with a single-ended CMOS signal. In such applications,
(CLK+ and CLK−) should be clocked with a differential signal. CLK+ should be driven directly from a CMOS gate, and the
This signal is typically ac-coupled into the CLK+ and CLK− pins CLK− pin should be bypassed to ground with a 0.1 μF capacitor
via a transformer or capacitors. These pins are biased internally in parallel with a 39 kΩ resistor (see Figure 43). Although the
and require no additional biasing. CLK+ input circuit supply is AVDD (1.8 V), this input is
designed to withstand input voltages of up to 3.3 V, making the
Figure 40 shows the preferred method for clocking the AD9252. selection of the drive logic voltage very flexible.
The low jitter clock source is converted from single-ended to
AD9510/AD9511/
differential using an RF transformer. The back-to-back Schottky AD9512/AD9513/
AD9514/AD9515
diodes across the secondary transformer limit clock excursions 0.1µF
CLK+ CLK
into the AD9252 to approximately 0.8 V p-p differential. This OPTIONAL
0.1µF
50Ω1 100Ω
helps prevent the large voltage swings of the clock from feeding CMOS DRIVER CLK+

through to other portions of the AD9252, and it preserves the ADC

CLK AD9252
fast rise and fall times of the signal, which are critical to low 0.1µF
CLK–
jitter performance. 0.1µF 39kΩ

06296-025
150Ω RESISTOR IS OPTIONAL.
Mini-Circuits®
ADT1-1WT, 1:1Z Figure 43. Single-Ended 1.8 V CMOS Sample Clock
0.1µF 0.1µF
XFMR
CLK+ CLK+ AD9510/AD9511/
50Ω 100Ω ADC AD9512/AD9513/
0.1µF AD9252 AD9514/AD9515
0.1µF
CLK–
CLK+ CLK
SCHOTTKY OPTIONAL 0.1µF
06296-022

0.1µF 50Ω1 100Ω

DIODES:
CMOS DRIVER CLK+
HSM2812
ADC
Figure 40. Transformer-Coupled Differential Clock CLK AD9252
0.1µF 0.1µF
Another option is to ac-couple a differential PECL signal to the CLK–

06296-026
sample clock input pins as shown in Figure 41. The AD9510/ 150Ω RESISTOR IS OPTIONAL.
AD9511/AD9512/AD9513/AD9514/AD9515 family of clock Figure 44. Single-Ended 3.3 V CMOS Sample Clock
drivers offers excellent jitter performance.
AD9510/AD9511/
Clock Duty Cycle Considerations
AD9512/AD9513/
AD9514/AD9515 Typical high speed ADCs use both clock edges to generate a
0.1µF 0.1µF variety of internal timing signals. As a result, these ADCs may
CLK+ CLK CLK+
be sensitive to the clock duty cycle. Commonly, a 5% tolerance is
100Ω ADC
0.1µF
PECL DRIVER AD9252 required on the clock duty cycle to maintain dynamic performance
0.1µF
CLK– CLK CLK– characteristics. The AD9252 contains a duty cycle stabilizer (DCS)
50Ω1 50Ω1 240Ω 240Ω
that retimes the nonsampling edge, providing an internal clock
06296-023

150Ω RESISTORS ARE

signal with a nominal 50% duty cycle. This allows a wide range
OPTIONAL.
of clock input duty cycles without affecting the performance of
Figure 41. Differential PECL Sample Clock
the AD9252. When the DCS is on, noise and distortion perfor-
AD9510/AD9511/
AD9512/AD9513/ mance are nearly flat for a wide range of duty cycles. However,
AD9514/AD9515
0.1µF 0.1µF
some applications may require the DCS function to be off. If so,
CLK+ CLK CLK+ keep in mind that the dynamic range performance can be affected
100Ω ADC when operated in this mode. See the Memory Map section for
LVDS DRIVER AD9252
0.1µF 0.1µF
CLK– CLK–
more details on using this feature.
CLK
50Ω1 50Ω1 The duty cycle stabilizer uses a delay-locked loop (DLL) to
06296-024

create the nonsampling edge. As a result, any changes to the

150Ω RESISTORS ARE OPTIONAL.
sampling frequency require approximately eight clock cycles
Figure 42. Differential LVDS Sample Clock
to allow the DLL to acquire and lock to the new rate.

Rev. D | Page 19 of 52
AD9252
Clock Jitter Considerations Power Dissipation and Power-Down Mode
High speed, high resolution ADCs are sensitive to the quality of the As shown in Figure 46, the power dissipated by the AD9252 is
clock input. The degradation in SNR at a given input frequency proportional to its sample rate. The digital power dissipation
(fA) due only to aperture jitter (tJ) can be calculated by does not vary much because it is determined primarily by the
SNR Degradation = 20 × log 10(1/2 × π × fA × tJ) DRVDD supply and bias current of the LVDS output drivers.
0.40 0.80
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input 0.35
0.75
signal, and ADC aperture jitter specifications. IF undersampling 0.30
applications are particularly sensitive to jitter (see Figure 45). AVDD CURRENT
0.70
0.25

CURRENT (A)

POWER (W)
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9252. 0.20
TOTAL POWER
0.65

Power supplies for clock drivers should be separated from the

0.15
ADC output driver supplies to avoid modulating the clock signal 0.60

with digital noise. Low jitter crystal-controlled oscillators make 0.10

the best clock sources. If the clock is generated from another DRVDD CURRENT 0.55
0.05
type of source (by gating, dividing, or other methods), it should
be retimed by the original clock at the last step. 0 0.50

06296-062
10 15 20 25 30 35 40 45 50
Refer to the AN-501 Application Note and the AN-756 ENCODE (MSPS)

Application Note for more in-depth information about jitter Figure 46. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, fSAMPLE = 50 MSPS
performance as it relates to ADCs.
130
RMS CLOCK JITTER REQUIREMENT
120

110

100 16 BITS

90 14 BITS
SNR (dB)

80
12 BITS
70
10 BITS
60
0.125ps
8 BITS
50 0.25ps
0.5ps
40 1.0ps
2.0ps
30
06296-015

1 10 100 1000
ANALOG INPUT FREQUENCY (MHz)

Figure 45. Ideal SNR vs. Input Frequency and Jitter

Rev. D | Page 20 of 52

By asserting the PDWN pin high, the AD9252 is placed into
power-down mode. In this state, the ADC typically dissipates
11 mW. During power-down, the LVDS output drivers are placed
into a high impedance state. The AD9252 returns to normal
operating mode when the PDWN pin is pulled low. This pin is
both 1.8 V and 3.3 V tolerant.
In power-down mode, low power dissipation is achieved by
shutting down the reference, reference buffer, PLL, and biasing
networks. The decoupling capacitors on REFT and REFB are
discharged when entering power-down mode and must be
recharged when returning to normal operation. As a result, the
wake-up time is related to the time spent in the power-down
mode: shorter cycles result in proportionally shorter wake-up
times. With the recommended 0.1 μF and 4.7 μF decoupling
capacitors on REFT and REFB, approximately 1 sec is required
to fully discharge the reference buffer decoupling capacitors and
approximately 375 μs is required to restore full operation.
There are several other power-down options available when
using the SPI. The user can individually power down each
channel or put the entire device into standby mode. The latter
option allows the user to keep the internal PLL powered when
fast wake-up times (~600 ns) are required. See the Memory
Map section for more details on using these features.
Digital Outputs and Timing
The AD9252 differential outputs conform to the ANSI-644 LVDS
standard by default upon power-up. This can be changed to a low
power, reduced signal option (similar to the IEEE 1596.3 standard)
via the SDIO/ODM pin or the SPI. This LVDS standard can further
reduce the overall power dissipation of the device by approximately
36 mW. See the SDIO/ODM Pin section or Table 16 in the
Memory Map section for more information. The LVDS driver
current is derived on chip and sets the output current at each
output equal to a nominal 3.5 mA. A 100 Ω differential termination
resistor placed at the LVDS receiver inputs results in a nominal
350 mV swing at the receiver.
The AD9252 LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs for superior switching
performance in noisy environments. Single point-to-point net
topologies are recommended with a 100 Ω termination resistor
placed as close to the receiver as possible. If there is no far-end
receiver termination or there is poor differential trace routing,
timing errors may result. To avoid such timing errors, it is
Rev. D | Page 21 of 52
AD9252
recommended that the trace length be no longer than 24 inches
and that the differential output traces be kept close together and
at equal lengths. An example of the FCO and data stream when
the AD9252 is used with traces of proper length and position is
shown in Figure 47.
06296-027
CH1 500mV/DIV = FCO 5.0ns/DIV
CH2 500mV/DIV = DCO
CH3 500mV/DIV = DATA
Figure 47. LVDS Output Timing Example in ANSI-644 Mode (Default)
An example of the LVDS output using the ANSI-644 standard
(default) data eye and a time interval error (TIE) jitter histogram
with trace lengths less than 24 inches on standard FR-4 material
is shown in Figure 48. Figure 49 shows an example of the trace
length exceeding 24 inches on standard FR-4 material. Notice
that the TIE jitter histogram reflects the decrease of the data eye
opening as the edge deviates from the ideal position. It is the user’s
responsibility to determine if the waveforms meet the timing
budget of the design when the trace lengths exceed 24 inches.
Additional SPI options allow the user to further increase the
internal termination (increasing the current) of all eight outputs
in order to drive longer trace lengths (see Figure 50). Even though
this produces sharper rise and fall times on the data edges and
is less prone to bit errors, the power dissipation of the DRVDD
supply increases when this option is used. In addition, notice in
Figure 50 that the histogram has improved.
In cases that require increased driver strength to the DCO± and
FCO± outputs because of load mismatch, Register 0x15 allows
the user to increase the drive strength by 2×. To do this, first
set the appropriate bit in Register 0x05. Note that this feature
cannot be used with Bit 4 and Bit 5 in Register 0x15. Bit 4 and
Bit 5 take precedence over this feature. See the Memory Map
section for more details.
AD9252
500 EYE: ALL BITS ULS: 12071/12071 400 EYE: ALL BITS ULS: 12072/12072
400
300
EYE DIAGRAM VOLTAGE (mV)

EYE DIAGRAM VOLTAGE (mV)

300
200
200
100
100

0 0

–100
–100
–200
–200
–300
–300
–400

–500 –400

–1.5ns –1.0ns –0.5ns 0ns 0.5ns 1.0ns 1.5ns –1.5ns –1.0ns –0.5ns 0ns 0.5ns 1.0ns 1.5ns

90 80

80 70
TIE JITTER HISTOGRAM (Hits)

TIE JITTER HISTOGRAM (Hits)

70
60
60
50
50
40
40
30
30
20
20

10 10
06296-030

06296-029
0 0
–150ps –100ps –50ps 0ps 50ps 100ps 150ps –150ps –100ps –50ps 0ps 50ps 100ps 150ps

Figure 48. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Figure 50. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω
Less Than 24 Inches on Standard FR-4 Termination On and Trace Lengths Greater Than 24 Inches on Standard FR-4

500
The format of the output data is offset binary by default. An
EYE: ALL BITS ULS: 12067/12067
400
example of the output coding format can be found in Table 8.
To change the output data format to twos complement, see the
EYE DIAGRAM VOLTAGE (mV)

300

200
Memory Map section.
100
Table 8. Digital Output Coding
0
(VIN + x) − (VIN − x), Digital Output Offset Binary
–100
Code Input Span = 2 V p-p (V) (D13 ... D0)
–200
16383 +1.00 11 1111 1111 1111
–300
8192 0.00 10 0000 0000 0000
–400
8191 −0.000122 01 1111 1111 1111
–500
0 −1.00 00 0000 0000 0000
–1.5ns –1.0ns –0.5ns 0ns 0.5ns 1.0ns 1.5ns

100 Data from each ADC is serialized and provided on a separate

90 channel. The data rate for each serial stream is equal to 14 bits
80
times the sample clock rate, with a maximum of 700 Mbps
TIE JITTER HISTOGRAM (Hits)

70
(14 bits × 50 MSPS = 700 Mbps). The lowest typical conversion
rate is 10 MSPS. However, if lower sample rates are required for
60
a specific application, the PLL can be set up via the SPI to allow
50
encode rates as low as 5 MSPS. See the Memory Map section for
40
information about enabling this feature.
30

20

10
06296-028

0
–200ps –100ps 0ps 100ps 200ps

Figure 49. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Greater Than 24 Inches on Standard FR-4

Rev. D | Page 22 of 52

Two output clocks are provided to assist in capturing data from
the AD9252. The DCO is used to clock the output data and is
equal to seven times the sample clock (CLK) rate. Data is clocked
out of the AD9252 and must be captured on the rising and
AD9252
falling edges of the DCO that supports double data rate (DDR)
capturing. The FCO is used to signal the start of a new output
byte and is equal to the sample clock rate. See the timing
diagram shown in Figure 2 for more information.

Table 9. Flexible Output Test Modes

Subject
Output Test to Data
Mode Bit Format
Sequence Pattern Name Digital Output Word 1 Digital Output Word 2 Select
0000 Off (default) N/A N/A N/A
0001 Midscale short 1000 0000 (8-bit) Same Yes
10 0000 0000 (10-bit)
1000 0000 0000 (12-bit)
10 0000 0000 0000 (14-bit)
0010 +Full-scale short 1111 1111 (8-bit) Same Yes
11 1111 1111 (10-bit)
1111 1111 1111 (12-bit)
11 1111 1111 1111 (14-bit)
0011 −Full-scale short 0000 0000 (8-bit) Same Yes
00 0000 0000 (10-bit)
0000 0000 0000 (12-bit)
00 0000 0000 0000 (14-bit)
0100 Checkerboard 1010 1010 (8-bit) 0101 0101 (8-bit) No
10 1010 1010 (10-bit) 01 0101 0101 (10-bit)
1010 1010 1010 (12-bit) 0101 0101 0101 (12-bit)
10 1010 1010 1010 (14-bit) 01 0101 0101 0101 (14-bit)
0101 PN sequence long 1 N/A N/A Yes
0110 PN sequence short1 N/A N/A Yes
0111 One-/zero-word toggle 1111 1111 (8-bit) 0000 0000 (8-bit) No
11 1111 1111 (10-bit) 00 0000 0000 (10-bit)
1111 1111 1111 (12-bit) 0000 0000 0000 (12-bit)
11 1111 1111 1111 (14-bit) 00 0000 0000 0000 (14-bit)
1000 User input Register 0x19 and Register 0x1A Register 0x1B and Register 0x1C No
1001 1-/0-bit toggle 1010 1010 (8-bit) N/A No
10 1010 1010 (10-bit)
1010 1010 1010 (12-bit)
10 1010 1010 1010 (14-bit)
1010 1× sync 0000 1111 (8-bit) N/A No
00 0001 1111 (10-bit)
0000 0011 1111 (12-bit)
00 0000 0111 1111 (14-bit)
1011 One bit high 1000 0000 (8-bit) N/A No
10 0000 0000 (10-bit)
1000 0000 0000 (12-bit)
10 0000 0000 0000 (14-bit)
1100 Mixed frequency 1010 0011 (8-bit) N/A No
10 0110 0011 (10-bit)
1010 0011 0011 (12-bit)
10 1000 0110 0111 (14-bit)
1
All test mode options except PN sequence short and PN sequence long can support 8- to 14-bit word lengths in order to verify data capture to the receiver.

Rev. D | Page 23 of 52
AD9252
When the SPI is used, the DCO phase can be adjusted in 60° SDIO/ODM Pin
increments relative to the data edge. This enables the user to The SDIO/ODM pin is for use in applications that do not require
refine system timing margins if required. The default DCO+ SPI mode operation. This pin can enable a low power, reduced
and DCO− timing, as shown in Figure 2, is 90° relative to the signal option (similar to the IEEE 1596.3 reduced range link
output data edge. output standard) if it and the CSB pin are tied to AVDD during
An 8-, 10-, and 12-bit serial stream can also be initiated from device power-up. This option should only be used when the
the SPI. This allows the user to implement different serial stream digital output trace lengths are less than 2 inches from the LVDS
to test the device’s compatibility with lower and higher resolution receiver. When this option is used, the FCO, DCO, and outputs
systems. When changing the resolution to an 8-, 10-, or 12-bit function normally, but the LVDS signal swing of all channels is
serial stream, the data stream is shortened. See Figure 3 for a reduced from 350 mV p-p to 200 mV p-p, allowing the user to
12-bit example. further reduce the power on the DRVDD supply.
When the SPI is used, the data outputs can be inverted from For applications where this pin is not used, it should be tied low.
their nominal state. This is not to be confused with inverting In this case, the device pin can be left open, and the 30 kΩ internal
the serial stream to an LSB-first mode. In default mode, as pull-down resistor pulls this pin low. This pin is only 1.8 V tolerant.
shown in Figure 2, the MSB is first in the data output serial If applications require this pin to be driven from a 3.3 V logic level,
stream. However, this can be inverted so that the LSB is first in insert a 1 kΩ resistor in series with this pin to limit the current.
the data output serial stream (see Figure 4).
Table 11. Output Driver Mode Pin Settings
There are 12 digital output test pattern options available that Resulting Resulting
can be initiated through the SPI. This feature is useful when Selected ODM ODM Voltage Output Standard FCO and DCO
validating receiver capture and timing. Refer to Table 9 for the Normal AGND ANSI-644 ANSI-644
output bit sequencing options available. Some test patterns have Operation (10 kΩ pull- (default) (default)
down resistor)
two serial sequential words and can be alternated in various ODM AVDD Low power, Low power,
ways, depending on the test pattern chosen. Note that some reduced signal reduced signal
patterns do not adhere to the data format select option. In option option
addition, customer user-defined test patterns can be assigned in
the 0x19, 0x1A, 0x1B, and 0x1C register addresses. All test mode SCLK/DTP Pin
options except PN sequence short and PN sequence long can The SCLK/DTP pin is for use in applications that do not require
support 8- to 14-bit word lengths in order to verify data capture SPI mode operation. This pin can enable a single digital test pattern
to the receiver. if it and the CSB pin are held high during device power-up. When
The PN sequence short pattern produces a pseudorandom bit the SCLK/DTP is tied to AVDD, the ADC channel outputs shift
sequence that repeats itself every 29 − 1 or 511 bits. A description out the following pattern: 10 0000 0000 0000. The FCO and DCO
of the PN sequence and how it is generated can be found in function normally while all channels shift out the repeatable test
Section 5.1 of the ITU-T 0.150 (05/96) standard. The only pattern. This pattern allows the user to perform timing alignment
difference is that the starting value must be a specific value adjustments among the FCO, DCO, and output data. For normal
instead of all 1s (see Table 10 for the initial values). operation, this pin should be tied to AGND through a 10 kΩ
The PN sequence long pattern produces a pseudorandom bit resistor. This pin is both 1.8 V and 3.3 V tolerant.
sequence that repeats itself every 223 − 1 or 8,388,607 bits. A Table 12. Digital Test Pattern Pin Settings
description of the PN sequence and how it is generated can be Resulting Resulting
found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The Selected DTP DTP Voltage D + x and D − x FCO and DCO
only differences are that the starting value must be a specific Normal AGND Normal Normal operation
value instead of all 1s (see Table 10 for the initial values) and the Operation (10 kΩ pull- operation
down resistor)
AD9252 inverts the bit stream with relation to the ITU standard.
DTP AVDD 10 0000 0000 Normal operation
0000
Table 10. PN Sequence
Initial First Three Output Samples
Sequence Value (MSB First) Additional and custom test patterns can also be observed when
PN Sequence Short 0x0df 0x37e4, 0x3533, 0x0063 commanded from the SPI port. Consult the Memory Map section
PN Sequence Long 0x26e028 0x191f, 0x35c2, 0x2359 for information about the options available.

Rev. D | Page 24 of 52
 AD9252
CSB Pin VIN + x
The CSB pin should be tied to AVDD for applications that do VIN – x
REFT
not require SPI mode operation. By tying CSB high, all SCLK
0.1µF
and SDIO information is ignored. This pin is both 1.8 V and ADC +
0.1µF 4.7µF
CORE
3.3 V tolerant.
REFB
RBIAS Pin 0.1µF
VREF
To set the internal core bias current of the ADC, place a resistor
1µF 0.1µF
that is nominally equal to 10.0 kΩ between the RBIAS pin and SELECT
0.5V

ground. The resistor current is derived on chip and sets the LOGIC
SENSE
AVDD current of the ADC to a nominal 360 mA at 50 MSPS.
Therefore, it is imperative that at least a 1% tolerance on this
resistor be used to achieve consistent performance.

06296-031
Voltage Reference
A stable, accurate 0.5 V voltage reference is built into the Figure 51. Internal Reference Configuration
AD9252. This is gained up internally by a factor of 2, setting
VREF to 1.0 V, which results in a full-scale differential input VIN + x

span of 2 V p-p. VREF is set internally by default; however, the VIN – x

REFT
VREF pin can be driven externally with a 1.0 V reference to
0.1µF
improve accuracy. ADC +
0.1µF 4.7µF
CORE
When applying the decoupling capacitors to the VREF, REFT, EXTERNAL REFB
REFERENCE
and REFB pins, use ceramic low-ESR capacitors. These capacitors 0.1µF
VREF
should be close to the ADC pins and on the same layer of the
1µF1 0.1µF1 0.5V
PCB as the AD9252. The recommended capacitor values and SELECT
AVDD
configurations for the AD9252 reference pin are shown in LOGIC

Figure 51. SENSE

Table 13. Reference Settings

Resulting
Selected SENSE Resulting Differential

06296-032
Mode Voltage VREF (V) Span (V p-p) 1OPTIONAL.

External AVDD N/A 2 × external Figure 52. External Reference Operation

Reference reference
5
Internal, AGND to 0.2 V 1.0 2.0
2 V p-p FSR 0

Internal Reference Operation –5

VREF ERROR (%)

A comparator within the AD9252 detects the potential at the –10

SENSE pin and configures the reference. If SENSE is grounded,
the reference amplifier switch is connected to the internal –15

resistor divider (see Figure 51), setting VREF to 1 V.

–20
The REFT and REFB pins establish their input span of the ADC
core from the reference configuration. The analog input full- –25
06296-061

scale range of the ADC equals twice the voltage at the reference
–30
pin for either an internal or an external reference configuration. 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
CURRENT LOAD (mA)
If the reference of the AD9252 is used to drive multiple
Figure 53. VREF Accuracy vs. Load
converters to improve gain matching, the loading of the refer-
ence by the other converters must be considered. Figure 53
depicts how the internal reference voltage is affected by loading.

Rev. D | Page 25 of 52
AD9252
0.02
External Reference Operation
0
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac- –0.02

teristics. Figure 54 shows the typical drift characteristics of the –0.04

VREF ERROR (%)

internal reference in 1 V mode. –0.06

When the SENSE pin is tied to AVDD, the internal reference is –0.08

disabled, allowing the use of an external reference. The external –0.10

reference is loaded with an equivalent 6 kΩ load. An internal –0.12
reference buffer generates the positive and negative full-scale
–0.14
references, REFT and REFB, for the ADC core. Therefore, the
–0.16
external reference must be limited to a nominal voltage of 1.0 V.
–0.18

06296-060
–40 –20 0 20 40 60 80
TEMPERATURE (°C)

Figure 54. Typical VREF Drift

Rev. D | Page 26 of 52

SERIAL PORT INTERFACE (SPI)
The AD9252 serial port interface allows the user to configure
the converter for specific functions or operations through a
structured register space provided inside the ADC. This may
provide the user with additional flexibility and customization,
depending on the application. Addresses are accessed via the
serial port and can be written to or read from via the port. Memory
is organized into bytes that can be further divided into fields, as
documented in the Memory Map section. Detailed operational
information can be found in the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
Three pins define the SPI: the SCLK, SDIO, and CSB pins (see
Table 14). The SCLK pin is used to synchronize the read and
write data presented to the ADC. The SDIO pin is a dual-
purpose pin that allows data to be sent to and read from the
internal ADC memory map registers. The CSB pin is an active
low control that enables or disables the read and write cycles.
Table 14. Serial Port Pins
Pin Function
SCLK Serial Clock. The serial shift clock input, which is used to
synchronize serial interface reads and writes.
SDIO Serial Data Input/Output. A dual-purpose pin that typically
serves as an input or output, depending on the instruction
sent and the relative position in the timing frame.
CSB Chip Select Bar (Active Low). This control gates the read
and write cycles.
The falling edge of the CSB in conjunction with the rising edge
of the SCLK determines the start of the framing sequence. During
an instruction phase, a 16-bit instruction is transmitted, followed
by one or more data bytes, which is determined by Bit Field W0
and Bit Field W1. An example of the serial timing and its
definitions can be found in Figure 56 and Table 15.
During normal operation, CSB is used to signal to the device
that SPI commands are to be received and processed. When
CSB is brought low, the device processes SCLK and SDIO to
execute instructions. Normally, CSB remains low until the
communication cycle is complete. However, if connected to a
slow device, CSB can be brought high between bytes, allowing
older microcontrollers enough time to transfer data into shift
registers. CSB can be stalled when transferring one, two, or
three bytes of data.
When W0 and W1 are set to 11, the device enters streaming
mode and continues to process data, either reading or writing,
until CSB is taken high to end the communication cycle. This
allows complete memory transfers without requiring additional
instructions.
Rev. D | Page 27 of 52
AD9252
Regardless of the mode, if CSB is taken high in the middle of a
byte transfer, the SPI state machine is reset and the device waits
for a new instruction.
In addition to the operation modes, the SPI port configuration
influences how the AD9252 operates. For applications that do
not require a control port, the CSB line can be tied and held high.
This places the remainder of the SPI pins into their secondary
modes, as defined in the SDIO/ODM Pin and SCLK/DTP Pin
sections. CSB can also be tied low to enable 2-wire mode. When
CSB is tied low, SCLK and SDIO are the only pins required for
communication. Although the device is synchronized during
power-up, the user should ensure that the serial port remains
synchronized with the CSB line when using this mode. When
operating in 2-wire mode, it is recommended that a 1-, 2-, or 3-
byte transfer be used exclusively. Without an active CSB line,
streaming mode can be entered but not exited.
In addition to word length, the instruction phase determines if
the serial frame is a read or write operation, allowing the serial
port to be used to both program the chip and read the contents
of the on-chip memory. If the instruction is a readback operation,
performing a readback causes the SDIO pin to change from an
input to an output at the appropriate point in the serial frame.
Data can be sent in MSB- or LSB-first mode. MSB-first mode
is the default at power-up and can be changed by adjusting the
configuration register. For more information about this and
other features, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.
HARDWARE INTERFACE
The pins described in Table 14 constitute the physical interface
between the user’s programming device and the serial port of
the AD9252. The SCLK and CSB pins function as inputs when
using the SPI. The SDIO pin is bidirectional, functioning as an
input during write phases and as an output during readback.
If multiple SDIO pins share a common connection, care should be
taken to ensure that proper VOH levels are met. Assuming the same
load for each AD9252, Figure 55 shows the number of SDIO pins
that can be connected together and the resulting VOH level.
This interface is flexible enough to be controlled by either serial
PROMs or PIC mirocontrollers, providing the user with an
alternative method, other than a full SPI controller, to program
the ADC (see the AN-812 Application Note).
If the user chooses not to use the SPI, these dual-function pins
serve their secondary functions when the CSB is strapped to
AVDD during device power-up. See the Theory of Operation
section for details on which pin-strappable functions are
supported on the SPI pins.
AD9252
1.800
1.795
1.790
1.785
1.780
1.775
1.770

VOH (V)
1.765
1.760
1.755
1.750
1.745
1.740
1.735
1.730
1.725
1.720
1.715

06296-059
0 10 20 30 40 50 60 70 80 90 100
NUMBER OF SDIO PINS CONNECTED TOGETHER

Figure 55. SDIO Pin Loading

tDS tHI tCLK tH

tS tDH tLO
CSB

SCLK DON’T CARE DON’T CARE

SDIO DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE

06296-033
Figure 56. Serial Timing Details

Table 15. Serial Timing Definitions

Parameter Timing (Minimum, ns) Description
tDS 5 Setup time between the data and the rising edge of SCLK
tDH 2 Hold time between the data and the rising edge of SCLK
tCLK 40 Period of the clock
tS 5 Setup time between CSB and SCLK
tH 2 Hold time between CSB and SCLK
tHI 16 Minimum period that SCLK should be in a logic high state
tLO 16 Minimum period that SCLK should be in a logic low state
tEN_SDIO 10 Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge (not shown in Figure 56)
tDIS_SDIO 10 Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK
rising edge (not shown in Figure 56)

Rev. D | Page 28 of 52
 AD9252

MEMORY MAP
READING THE MEMORY MAP TABLE RESERVED LOCATIONS
Each row in the memory map register table (Table 16) has eight Undefined memory locations should not be written to except
address locations. The memory map is divided into three sections: when writing the default values suggested in this data sheet.
the chip configuration register map (Address 0x00 to Address 0x02), Addresses that have values marked as 0 should be considered
the device index and transfer register map (Address 0x04, reserved and have 0 written to their registers during power-up.
Address 0x05, and Address 0xFF), and the ADC functions register DEFAULT VALUES
map (Address 0x08 to Address 0x22).
When the AD9252 comes out of a reset, critical registers are
The leftmost column of the memory map indicates the register preloaded with default values. These values are indicated in
address number; the default value is shown in the second right- Table 16, where an X refers to an undefined feature.
most column. The Bit 7 column is the start of the default
LOGIC LEVELS
hexadecimal value given. For example, Address 0x09, the clock
register, has a default value of 0x01, meaning Bit 7 = 0, Bit 6 = 0, An explanation of various registers follows: “bit is set” is
Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or synonymous with “bit is set to Logic 1” or “writing Logic 1 for
0000 0001 in binary. This setting is the default for the duty cycle the bit.” Similarly, “clear a bit” is synonymous with “bit is set to
stabilizer in the on condition. By writing 0 to Bit 0 of this address Logic 0” or “writing Logic 0 for the bit.”
followed by writing 0x01 in Register 0xFF (transfer bit), the duty
cycle stabilizer turns off. It is important to follow each writing
sequence with a transfer bit to update the SPI registers. All
registers, except Register 0x00, Register 0x04, Register 0x05, and
Register 0xFF, are buffered with a master-slave latch and require
writing to the transfer bit. For more information on this and
other functions, consult the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.

Rev. D | Page 29 of 52
AD9252
Table 16. Memory Map Register 1
Default
Addr. (MSB) (LSB) Value Notes/
(Hex) Parameter Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Hex) Comments
Chip Configuration Registers
00 chip_port_config 0 LSB first Soft 1 1 Soft LSB first 0 0x18 The nibbles
1 = on reset reset 1 = on should be
0 = off 1 = on 1 = on 0 = off mirrored so
(default) 0 = off 0 = off (default) that LSB- or
(default) (default) MSB-first mode
is set correctly
regardless of
shift mode.
01 chip_id 8-bit Chip ID Bits [7:0] Read Default is unique
(AD9252 = 0x09), (default) only chip ID, different
for each device.
This is a read-
only register.
02 chip_grade X Child ID [6:4] X X X X Read Child ID used to
(identify device variants of Chip ID) only differentiate
011 = 50 MSPS graded devices.
Device Index and Transfer Registers
04 device_index_2 X X X X Data Data Data Data 0x0F Bits are set to
Channel Channel Channel Channel determine which
H G F E on-chip device
1 = on 1 = on 1 = on 1 = on receives the next
(default) (default) (default) (default) write command.
0 = off 0 = off 0 = off 0 = off
05 device_index_1 X X Clock Clock Data Data Data Data 0x0F Bits are set to
Channel Channel Channel Channel Channel Channel determine which
DCO FCO D C B A on-chip device
1 = on 1 = on 1 = on 1 = on 1 = on 1 = on receives the next
0 = off 0 = off (default) (default) (default) (default) write command.
(default) (default) 0 = off 0 = off 0 = off 0 = off
FF device_update X X X X X X X SW 0x00 Synchronously
transfer transfers data
1 = on from the master
0 = off shift register to
(default) the slave.
ADC Functions Registers
08 modes X X X X X Internal power-down mode 0x00 Determines
000 = chip run (default) various generic
001 = full power-down modes of chip
010 = standby operation.
011 = reset
09 clock X X X X X X X Duty 0x01 Turns the
cycle internal duty
stabilizer cycle stabilizer
1 = on on and off.
(default)
0 = off
0D test_io User test mode Reset PN Reset Output test mode—see Table 9 in the 0x00 When this register
00 = off (default) long gen PN short Digital Outputs and Timing section is set, the test
01 = on, single alternate 1 = on gen 0000 = off (default) data is placed on
10 = on, single once 0 = off 1 = on 0001 = midscale short the output pins
11 = on, alternate once (default) 0 = off 0010 = +FS short in place of
(default) 0011 = −FS short normal data.
0100 = checkerboard output
0101 = PN 23 sequence
0110 = PN 9 sequence
0111 = one-/zero-word toggle
1000 = user input
1001 = 1-/0-bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency
(format determined by output_mode)

Rev. D | Page 30 of 52
 AD9252
Default
Addr. (MSB) (LSB) Value Notes/
(Hex) Parameter Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (Hex) Comments
14 output_mode X 0 = LVDS X X X Output 00 = offset binary 0x00 Configures the
ANSI-644 invert (default) outputs and the
(default) 1 = on 01 = twos complement format of the data.
1 = LVDS 0 = off
low power, (default)
(IEEE 1596.3
similar)
15 output_adjust X X Output driver X X X DCO and 0x00 Determines
termination FCO LVDS or other
00 = none (default) 2× drive output properties.
01 = 200 Ω strength Primarily func-
10 = 100 Ω 1 = on tions to set the
11 = 100 Ω 0 = off LVDS span and
(default) common-mode
levels in place of
an external
resistor.
16 output_phase X X X X 0011 = output clock phase adjust 0x03 On devices that
(0000 through 1010) utilize global
0000 = 0° relative to data edge clock divide,
0001 = 60° relative to data edge this register
0010 = 120° relative to data edge determines
0011 = 180° relative to data edge (default) which phase
0101 = 300° relative to data edge of the divider
0110 = 360° relative to data edge output is used
1000 = 480° relative to data edge to supply the
1001 = 540° relative to data edge output clock.
1010 = 600° relative to data edge Internal latching
1011 to 1111 = 660° relative to data edge is unaffected.
19 user_patt1_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined
pattern, 1 LSB.
1A user_patt1_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined
pattern, 1 MSB.
1B user_patt2_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined
pattern, 2 LSB.
1C user_patt2_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined
pattern, 2 MSB.
21 serial_control LSB first X X X <10 000 = 14 bits (default, normal bit 0x00 Serial stream
1 = on MSPS, stream) control. Default
0 = off low 001 = 8 bits causes MSB first
(default) encode 010 = 10 bits and the native
rate 011 = 12 bits bit stream
mode 100 = 14 bits (global).
1 = on
0 = off
(default)
22 serial_ch_stat X X X X X X Channel Channel 0x00 Used to power
output power- down individual
reset down sections of a
1 = on 1 = on converter (local).
0 = off 0 = off
(default) (default)

1
X = an undefined feature.

Rev. D | Page 31 of 52
AD9252
APPLICATIONS INFORMATION
DESIGN GUIDELINES
Before starting design and layout of the AD9252 as a system, it
is recommended that the designer become familiar with these
guidelines, which discuss the special circuit connections and
layout requirements needed for certain pins.
Power and Ground Recommendations
When connecting power to the AD9252, it is recommended
that two separate 1.8 V supplies be used: one for analog (AVDD)
and one for digital (DRVDD). If only one supply is available, it
should be routed to the AVDD first and then tapped off and
isolated with a ferrite bead or a filter choke preceded by
decoupling capacitors for the DRVDD. The user can employ
several different decoupling capacitors to cover both high and
low frequencies. These capacitors should be located close to the
point of entry at the PC board level and close to the parts with
minimal trace lengths.
A single PC board ground plane should be sufficient when
using the AD9252. With proper decoupling and smart parti-
tioning of the PC board’s analog, digital, and clock sections,
optimum performance can be easily achieved.
Rev. D | Page 32 of 52
Exposed Paddle Thermal Heat Slug Recommendations
It is required that the exposed paddle on the underside of the
ADC be connected to analog ground (AGND) to achieve the
best electrical and thermal performance of the AD9252. An
exposed continuous copper plane on the PCB should mate to
the AD9252 exposed paddle, Pin 0. The copper plane should
have several vias to achieve the lowest possible resistive thermal
path for heat dissipation to flow through the bottom of the PCB.
These vias should be solder-filled or plugged.
To maximize the coverage and adhesion between the ADC and
PCB, partition the continuous copper plane by overlaying a
silkscreen on the PCB into several uniform sections. This provides
multiple tie points between the ADC and PCB during the
reflow process, whereas using one continuous plane with no
partitions guarantees only one tie point. See Figure 57 for a PCB
layout example. For detailed information on packaging and the
PCB layout of chip scale packages, see the AN-772 Application
Note, A Design and Manufacturing Guide for the Lead Frame
Chip Scale Package (LFCSP).
SILKSCREEN PARTITION
PIN 1 INDICATOR
06296-034
Figure 57. Typical PCB Layout
 AD9252

EVALUATION BOARD
The AD9252 evaluation board provides all the support cir- each section. At least one 1.8 V supply is needed for AVDD_DUT
cuitry required to operate the ADC in its various modes and and DRVDD_DUT; however, it is recommended that separate
configurations. The converter can be driven differentially by using supplies be used for both analog and digital signals and that each
a transformer (default) or an AD8334 driver. The ADC can also be supply have a current capability of 1 A. To operate the evaluation
driven in a single-ended fashion. Separate power pins are provided board using the VGA option, a separate 5.0 V analog supply
to isolate the DUT from the drive circuitry of the AD8334. Each (AVDD_5 V) is needed. To operate the evaluation board using
input configuration can be selected by changing the connections the SPI and alternate clock options, a separate 3.3 V analog supply
of various jumpers (see Figure 62 to Figure 66). Figure 58 shows (AVDD_3.3 V) is needed in addition to the other supplies.
the typical bench characterization setup used to evaluate the
INPUT SIGNALS
ac performance of the AD9252. It is critical that the signal sources
used for the analog input and clock have very low phase noise When connecting the clock and analog sources to the
(<1 ps rms jitter) to realize the optimum performance of the evaluation board, use clean signal generators with low phase
converter. Proper filtering of the analog input signal to remove noise, such as Rohde & Schwarz SMA or HP8644 signal generators
harmonics and lower the integrated or broadband noise at the or the equivalent, as well as a 1 m, shielded, RG-58, 50 Ω coaxial
input is also necessary to achieve the specified noise performance. cable. Enter the desired frequency and amplitude from the ADC
specifications tables. Typically, most Analog Devices, Inc., evalu-
See Figure 62 to Figure 72 for the complete schematics and ation boards can accept approximately 2.8 V p-p or 13 dBm
layout diagrams demonstrating the routing and grounding sine wave input for the clock. When connecting the analog
techniques that should be applied at the system level. input source, it is recommended to use a multipole, narrow-band,
POWER SUPPLIES band-pass filter with 50 Ω terminations. Good choices of such
This evaluation board has a wall-mountable switching power band-pass filters are available from TTE, Allen Avionics, and
supply that provides a 6 V, 2 A maximum output. Connect the K&L Microwave, Inc. The filter should be connected directly to
supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz to the evaluation board if possible.
63 Hz. The other end of the supply is a 2.1 mm inner diameter OUTPUT SIGNALS
jack that connects to the PCB at P701. Once on the PC board, The default setup uses the Analog Devices HSC-ADC-FPGA-8Z
the 6 V supply is fused and conditioned before connecting to high speed deserialization board to deserialize the digital output
three low dropout linear regulators that supply the proper bias data and convert it to parallel CMOS. These two channels interface
to each of the various sections on the board. directly with the Analog Devices standard dual-channel FIFO
When operating the evaluation board in a nondefault condition, data capture board (HSC-ADC-EVALB-DCZ). Two of the eight
L701 to L704 can be removed to disconnect the switching channels can then be evaluated at the same time. For more
power supply. This enables the user to bias each section of the information on the channel settings and their optional settings,
board individually. Use P702 to connect a different supply for visit www.analog.com/FIFO.

WALL OUTLET
100V AC TO 240V AC
47Hz TO 63Hz
6V DC
2A MAX
5.0V 1.8V 1.8V 3.3V 3.3V 1.5V 3.3V
– + – + – + – + – + – + – +
SWITCHING
POWER
SUPPLY
1.5V_FPGA

GND

VCC
GND

GND

GND

GND

GND

GND
3.3V_D
AVDD_5V

AVDD_3.3V
AVDD_DUT

DRVDD_DUT

PC
RUNNING
ROHDE & SCHWARZ, ADC
SMA, HSC-ADC_FPGA-8Z HSC-ADC-EVALB-DCZ ANALYZER
BAND-PASS XFMR HIGH SPEED FIFO DATA AND SPI
2V p-p SIGNAL
FILTER INPUT DESERIALIZATION CAPTURE USER
SYNTHESIZER
CH A TO CH H BOARD 2-CH BOARD SOFTWARE
ROHDE & SCHWARZ,
AD9252 14-BIT USB
EVALUATION BOARD 14-BIT
SMA, CLK SERIAL PARALLEL CONNECTION
06296-035

2V p-p SIGNAL LVDS CMOS

SYNTHESIZER SPI SPI SPI SPI

Figure 58. Evaluation Board Connection

Rev. D | Page 33 of 52
AD9252
DEFAULT OPERATION AND JUMPER SELECTION
SETTINGS
The following is a list of the default and optional settings or
modes allowed on the AD9252 Rev. A evaluation board.
• Power: Connect the switching power supply that is
provided with the evaluation kit between a rated 100 V ac
to 240 V ac wall outlet at 47 Hz to 63 Hz and P701.
• AIN: The evaluation board is set up for a transformer-
coupled analog input with an optimum 50 Ω impedance
match of 150 MHz of bandwidth (see Figure 59). For more
bandwidth response, the differential capacitor across the
analog inputs can be changed or removed. The common
mode of the analog inputs is developed from the center
tap of the transformer or AVDD_DUT/2.
0
–1
–2 –3dB CUTOFF = 186MHz
–3
–4
AMPLITUDE (dBFS)
–5
–6
–7
–8
–9
–10
–11
–12
–13
–14
0 50 100 150 200 250 300 350 400
FREQUENCY (MHz)
Figure 59. Evaluation Board Full-Power Bandwidth
• VREF: VREF is set to 1.0 V by tying the SENSE pin to
ground, R317. This causes the ADC to operate in 2.0 V p-p
full-scale range. A separate external reference option using
the ADR510 or ADR520 is also included on the evaluation
board. Populate R312 and R313, and remove C307. Proper
use of the VREF options is noted in the Voltage Reference
section.
• RBIAS: RBIAS has a default setting of 10 kΩ (R301) to
ground and is used to set the ADC core bias current.
• Clock: The default clock input circuitry is derived from a
simple transformer-coupled circuit using a high bandwidth
1:1 impedance ratio transformer (T401) that adds a very
low amount of jitter to the clock path. The clock input is
50 Ω terminated and ac-coupled to handle single-ended
sine wave types of inputs. The transformer converts the
single-ended input to a differential signal that is clipped
before entering the ADC clock inputs.
A differential LVPECL clock can also be used to clock the
ADC input using the AD9515 (U401). Populate R406 and
R407 with 0 Ω resistors, and remove R215 and R216 to
disconnect the default clock path inputs. In addition, populate
C205 and C206 with a 0.1 μF capacitor, and remove C409 and
C410 to disconnect the default clock path outputs. The
AD9515 has many pin-strappable options that are set to a
default mode of operation. Consult the AD9515 data sheet
for more information about these and other options.
In addition, an on-board oscillator is available on the OSC401
and can act as the primary clock source. The setup is quick
and involves installing R403 with a 0 Ω resistor and setting
the enable jumper (J401) to the on position. If the user wishes
to employ a different oscillator, two oscillator footprint options
are available (OSC401) to check the ADC performance.
• PDWN: To enable the power-down feature, short J301 to
the on position (AVDD) for the PDWN pin.
• SCLK/DTP: To enable the digital test pattern on the digital
outputs of the ADC, use J304. If J304 is tied to AVDD during
device power-up, Test Pattern 10 0000 0000 0000 is enabled.
See the SCLK/DTP Pin section for details.
• SDIO/ODM: To enable the low power, reduced signal option
(similar to the IEEE 1595.3 reduced range link LVDS output
standard), use J303. If J303 is tied to AVDD during device
power-up, it enables the LVDS outputs in a low power,
reduced signal option from the default ANSI-644 standard.
06296-036
450 500 This option changes the signal swing from 350 mV p-p to
200 mV p-p, reducing the power of the DRVDD supply. See
the SDIO/ODM Pin section for more details.
• CSB: To enable processing of the SPI information on the
SDIO and SCLK pins, tie J302 low in the always enable
mode. To ignore the SDIO and SCLK information, tie J302
to AVDD.
• Non-SPI Mode: For users who wish to operate the DUT
without using the SPI, simply remove Jumpers J302, J303,
and J304. This disconnects the CSB, SCLK/DTP, and
SDIO/ODM pins from the control bus, allowing the DUT
to operate in its simplest mode. Each of these pins has
internal termination and will float to its respective level.
• D + x, D − x: If an alternative data capture method to the
setup shown in Figure 62 is used, optional receiver
terminations, R318 and R320 to R328, can be installed next
to the high speed backplane connector.
Rev. D | Page 34 of 52

ALTERNATIVE ANALOG INPUT DRIVE
CONFIGURATION
The following is a brief description of the alternative analog
input drive configuration using the AD8334 dual VGA. If this
drive option is in use, some components may need to be populated,
in which case all the necessary components are listed in Table 17.
For more details on the AD8334 dual VGA, including how it works
and its optional pin settings, consult the AD8334 data sheet.
To configure the analog input to drive the VGA instead of the
default transformer option, the following components need to
be removed and/or changed.
• Remove R102, R115, R128, R141, R161, R162, R163, R164,
R202, R208, R218, R225, R234, R241, R252, R259, T101,
AD9252
In this example, a 16 MHz, two-pole low-pass filter was applied
to the AD8334 outputs. The following components need to be
removed and/or changed:
• Remove L507, L508, L511, L512, L515, L516, L519, L520,
L607, L608, L611, L612, L615, L616, L619, and L620 on the
AD8334 analog outputs.
• Populate L507, L508, L511, L512, L515, L516, L519, L520,
L607, L608, L611, L612, L615, L616, L619, and L620 with
680 nH inductors.
• Populate C543, C547, C551, C555, C643, C647, C651, and
C655 with a 68 pF capacitor.
680nH

06296-083
68pF
680nH
T102, T103, T104, T201, T202, T203, and T204 in the
default analog input path. Figure 60. Example Filter Configured for16 MHz, Two-Pole Low-Pass Filter

• Populate R101, R114, R127, R140, R201, R217, R233, and 0

fSAMPLE = 50MSPS
R251 with 0 Ω resistors in the analog input path. AIN = 3.5MHz
–20 AD8334 = MAX GAIN SETTING
• Populate R152, R153, R154, R155, R156, R157, R158, R159,
R215, R216, R229, R230, R247, R248, R263, R264, C103,

AMPLITUDE (dBFS)
–40
C105, C110, C112, C117, C119, C124, C126, C203, C205,
C210, C212, C217, C219, C224, and C226 with 10 kΩ –60
resistors to provide an input common-mode level to the
ADC analog inputs. –80

• Populate R105, R113, R118, R124, R131, R137, R151, R160,

–100
R205, R213, R221, R222, R237, R238, R255, and R256 with
0 Ω resistors in the ADC analog input path to connect the
–120

06296-084
VGA outputs. 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0
FREQUENCY (MHz)
• Remove R515, R520, R527, R532, R615, R620, R627, and
Figure 61. AD9252 FFT Example Results Using
R632 on the AD8334 analog outputs. 16 MHz, Two-Pole Low-Pass Filter Applied to the AD8334 Outputs
(Analog Input Signal = −1.03 dBFS, SNR = 60.2 dBc, SFDR = 66.23 dBc)
• Remove R512, R524, R612, and R624 to set the AD8334
mode and AD8334 HILO pin low. Some applications may
require this to be different. Consult the AD8334 data sheet
for more information on these functions.
In this configuration, L505 to L520 and L605 to L620 are populated
with 0 Ω resistors to allow signal connection and use of a filter if
additional requirements are necessary.

Rev. D | Page 35 of 52
 AD9252

AVDD_DUT
AVDD_DUT
DNP P106
P102 DNP
VGA Input
R152 VGA Input
Connection Ain R105 Ain R131
DNP Connection R154
INH1 0Ω−DNP 0Ω−DNP
INH3 DNP
R104 C101
CH_A FB102 R108 C115
R130 CH_C FB108 R134
0Ω 0.1µF T101 10Ω 33Ω 0.1µF
1 6 0Ω T103 10Ω 33Ω
VIN_A 1 6
R101 VIN_C
Channel A R106 R127
0Ω−DNP 2 5 Channel C R132
CM1 CM1 DNP 0Ω−DNP 2 5
P101 C102 R161 C104 R109 CM3 CM3 DNP
499Ω 1kΩ P105 R163 C117 C118
0.1µF 3 4 R110 2.2pF DNP R135
Ain R107 C103 3 4 499Ω 2.2pF 1kΩ
FB101 R113 33Ω Ain R133
DNP DNP FB107
10Ω CH_A VIN_A R137 DNP
R102 0Ω−DNP FB103 10Ω C116 CH_C VIN_C
R103 CM1 0.1µF FB109
64.9Ω 10Ω R128 R129 0Ω−DNP R136
0Ω C105 10Ω
64.9Ω 0Ω CM3 33Ω C119
DNP R156
1 DNP R158
E101 DNP 1
E103 DNP
C106
DNP AVDD_DUT C120
AVDD_DUT DNP
R138
R111 AVDD_DUT 1kΩ R139
1kΩ C121 AVDD_DUT
C107 1kΩ 0.1µF
R112 0.1µF
1kΩ

VGA Input AVDD_DUT VGA Input AVDD_DUT

Connection Connection
INH2 INH4

R153 R155
R118 DNP R151 DNP
R114 0Ω−DNP R140
Channel B 0Ω−DNP Channel D 0Ω−DNP
0Ω−DNP C122
P103 FB104 C108 CH_B FB105 R121 FB110 CH_D FB111 R146
P107 0.1µF
10Ω 0.1µF 10Ω 33Ω 10Ω T104 10Ω 33Ω
Ain 1 T102 6 1 6
VIN_B Ain VIN_D

Rev. D | Page 36 of 52
DNP R119 DNP R144
2 5 R162 2 5
P104 CM2 CM2 DNP R123 P108 CM4 CM4 DNP R164 R148
R115 C109 499Ω C111 R141 C124 C125
0.1µF 1kΩ 499Ω 1kΩ
64.9Ω 3 4 R122 2.2pF 64.9Ω 3 4 DNP 2.2pF
Ain R120 C110 Ain R145
R124 33Ω R160
R116 DNP DNP R143 DNP
0Ω CH_B VIN_B C123 CH_D VIN_D
0Ω−DNP FB106 0Ω FB112
0.1µF CM4 0Ω−DNP R147
R117 10Ω R142 10Ω
CM2 33Ω
C112 0Ω C126
0Ω R157 1 R159
DNP E104 DNP
1 DNP DNP
E102 C127
AVDD_DUT DNP
C113 R149
AVDD_DUT DNP 1kΩ
C128
R125 AVDD_DUT R150 AVDD_DUT
1kΩ 0.1µF
1KΩ C114

Figure 62. Evaluation Board Schematic, DUT Analog Inputs

R126 0.1µF
1kΩ
06296-072

DNP: DO NOT POPULATE.

 AVDD_DUT AVDD_DUT
DNP
VGA Input P202 VGA Input DNP
Connection R205 Connection P206 R248
Ain R216 R237
INH5 C201 0Ω−DNP INH7 Ain 0Ω−DNP DNP
R204 CH_E FB202 R209 DNP C215
0.1µF R236 CH_G FB208 R242
0Ω 10Ω 33Ω 0.1µF
Channel E 1 T201 6 0Ω T203 10Ω 33Ω
VIN_E 1 6
R201 R233 VIN_G
2 5 R206 C203 Channel G R239
P201 0Ω−DNP CM5 CM5 DNP R208 C204 R214 0Ω−DNP 2 5
P205 CM7 CM7 DNP R241 C217 C218 R246
3 4 499Ω R210 2.2pF 1kΩ 1kΩ
Ain R207 DNP 3 4 499Ω DNP 2.2pF
FB201 33Ω Ain R240
DNP FB207 R238 DNP
10Ω C202 CH_E VIN_E
R202 R203 R213 FB203 10Ω C216 CH_G VIN_G
0.1µF CM5 10Ω R234 R235 0.1µF FB209
64.9Ω 0Ω 0Ω−DNP C205 0Ω−DNP R245
64.9kΩ 0Ω CM7 10Ω 33Ω C219
1 DNP R215 R247
1 DNP
E201 DNP E203 DNP
C206
DNP AVDD_DUT C220
AVDD_DUT DNP
R211 AVDD_DUT R249 C221
C207 1kΩ AVDD_DUT
1kΩ
R212 R250 0.1µF
0.1µF 1kΩ
1kΩ

VGA Input AVDD_DUT VGA Input

Connection AVDD_DUT
Connection
INH6 INH8

Channel F R221 R230 R255 R264

R217 DNP Channel H R251 DNP
0Ω−DNP C208 0Ω−DNP C222 0Ω−DNP
FB204 FB205 R226 0Ω−DNP FB210 FB211 R260
P203 0.1µF CH_F
33Ω P207 0.1µF CH_H
10Ω 10Ω 10Ω 10Ω 33Ω
Ain 1 T202 6 Ain 1 T204 6
VIN_F VIN_H
R257

Rev. D | Page 37 of 52
DNP 2 5 R223 DNP 2 5
R220 CM6 CM6 R225 R228 R254 CM8 CM8 DNP
R218 P204 0Ω DNP C210 C211 R252 P208 0Ω R259 C224 C225 R262
64.9Ω 3 4 499Ω 2.2pF 1kΩ 64.9Ω 3 4 499Ω DNP 2.2pF 1kΩ
R224 DNP Ain
Ain R222 R258
DNP R256 DNP
C209 CH_F VIN_F C223 CH_H VIN_H
0.1µF 0Ω−DNP FB206 0.1µF 0Ω−DNP FB212
R219 R227 R253 R261
10Ω 33Ω C212 10Ω 33Ω
0Ω CM6 R229 0Ω 1 CM8 C226 R263
1 DNP DNP E204 DNP DNP
E202 C227
R231 AVDD_DUT DNP
C213
AVDD_DUT R265 C228
DNP
1kΩ 1kΩ
C214 AVDD_DUT AVDD_DUT
R266 0.1µF
R232 1kΩ
1kΩ 0.1µF
06296-073

Figure 63. Evaluation Board Schematic, DUT Analog Inputs (Continued)

DNP: DO NOT POPULATE.
AD9252
 C301
0.1µF Reference
Decoupling

C303 C304
4.7µF 0.1µF
AD9252

C302
0.1µF

R301
10kΩ

AVDD_DUT
AVDD_DUT

VIN_E
VIN_E

VIN_F
VIN_F
Digital Outputs
P301

VIN_D
VIN_D
GNDCD10
60

AVDD_DUT
VIN_C

VIN_C
DCO

VSENSE_DUT
DCO

VREF_DUT
40 C10 D10 50
GNDCD9 R318
59
FCO D9 FCO DNP
39 C9 49
GNDCD8 R320

0
58

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
CHA D8 CHA DNP
38 C8 48
GNDCD7 R321
57
AVDD_DUT CHB CHB DNP

REFT
VREF

REFB

SLUG
AVDD
AVDD
AVDD

VIN+F
VIN−F
VIN−E
VIN+E
37

VIN+D
VIN−D
VIN−C
VIN+C

RBIAS
1 48 C7 GNDCD6 D7 47 R322

SENSE
AVDD_DUT AVDD AVDD AVDD_DUT
56 R318,R320−R328
CHC D6 CHC DNP
2 47 36 C6 46
Optional Output
VIN_G VIN+G VIN+B VIN_B GNDCD5 R323 Terminations
55
3 46 CHD D5 CHD DNP
VIN_G VIN−G VIN−B VIN_B 35 C5 45
GNDCD4 R324

DNP
R303 R304

R302
54
4 45 100kΩ DNP DNP
AVDD_DUT AVDD AVDD AVDD_DUT CHE 34 C4 44 CHE
GNDCD3 D4 R325
53
5 44 DNP
VIN_H VIN−H VIN−A VIN_A CHF 33 43 CHF
C3 GNDCD2 D3 R326
J301
6 43 1 3 52
VIN_H VIN+H VIN+A VIN_A PDWN ENABLE DNP
CHG 32 C2 42 CHG

2
GNDCD1 D2 R327
7 42 51
AVDD_DUT AVDD AVDD AVDD_DUT DNP
CSB_DUT CHH C1 41 CHH
J302 31 D1
1 GNDAB10 R328
8 AD9252BCPZ-50 41 3 ALWAYS ENABLE SPI
AVDD_DUT AVDD PDWN 30
B10 DNP

2
10 A10 20
9 40 GNDAB9
CLK CLK− CSB 29
R319 SDIO_ODM B9
10 U301 39 J303 9 A9 19
1 GNDAB8
CLK CLK+ SDIO/ODM 3 ODM Enable 28
1kΩ B8

2
11 38 8 A8 18
AVDD_DUT AVDD SCLK/DTP GNDAB7
27
SCLK_DTP B7
12 37 J304 7 A7 17
AVDD_DUT AVDD AVDD AVDD_DUT 1 3 GNDAB6
DTP Enable
26

2
13 36 B6
GND DRGND DRGND GND 6 A6 16
GNDAB5
25
14 35 B5

Rev. D | Page 38 of 52
DRVDD_DUT DRVDD DRVDD DRVDD_DUT SCLK_CHB 5 A5 15
SCLK_CHA
GNDAB4
15 34 24
CHH D−H D+A CHA SDI_CHB B4

R305
R306
SDI_CHA

10kΩ
R307
4 A4 14

100kΩ
100kΩ
GNDAB3
16 33 23
CHH D+H D−A CHA B3 CSB1_CHA
CSB3_CHB 3 A3 13
GNDAB2
22

DCO−
DCO+
FCO−
FCO+

D−G
D+G
D−D
D+D
D−C
D+C

D−E
D+E
D−B
D+B

D−F
D+F
CSB4_CHB B2 CSB2_CHA
2 A2 12
GNDAB1

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
21
SDO_CHB B1 SDO_CHA
1 A1 11

CHF
CHF
NC

CHE
CHE
CHB
CHB

FCO
FCO
CHD
CHD
CHC
CHC

CHG
CHG
DCO
DCO

Figure 64. Evaluation Board Schematic, DUT, VREF, and Digital Output Interface
AVDD_DUT

OPTIONAL
EXT REF
Reference Circuitry
R309 Vref Select VSENSE_DUT
4.99kΩ VREF_DUT
U302 R311 R314
DNP DNP
ADR510ARTZ VREF = 0.5V
TRIM/NC 1.0V VOUT

R315

GND
R312 DNP VREF = External
DNP
C306
AVDD_DUT

C305 R310 0.1µF C307 R31

R308 0.1µF 1µF DNP VREF = 0.5V(1 + R219/R220)
10kΩ
470kΩ
CW

R313 R317
DNP 0Ω VREF = 1V

Remove C214 when

06296-074

DNP: DO NOT POPULATE. using external Vref

 AVDD_3.3V

OPTIONAL CLOCK DRIVE CIRCUIT

R401
C401 10kΩ
0.1µF
AVDD_3.3V

3
ENABLE OSC401 R414 AVDD_3.3V
AVDD_3.3V 4.12kΩ
Optional Clock 2
J401 R408 R409 R410 DNP
Oscillator
DNP DNP 10kΩ
OSC401 DISABLE OSC401 0.1µF
C405
14 1
VCC OE OPT_CLK
1 U401 CLK

32
1
31
33
12 3 R424 R425
VCC OE DNP

VS
R406 2 GND_PAD 23 R422 LVPECL OUTPUT AVDD_3.3V
0Ω 0Ω

GND
R402 100Ω 0.1µF AD9515 Pin−strap settings

RSET
10 5 0Ω CLK OUT0
OUT GND 10kΩ R411 C406 DNP
DNP 49.9Ω 3 22
8 7 DNP CLKB AD9515BCPZ OUT0B CLK S0
OUT GND R427
R426 R436 R437
OPT_CLK
R420 R421 AVDD_3.3V AVDD_3.3V
CRYSTAL_3 SIGNAL=AVDD_3.3V;4,17,20,21,24,26,29,30 0Ω 0Ω 0Ω 0Ω
Encode 5 19 240Ω 240Ω DNP DNP
R403 R407 SYNCB OUT1
Input 0Ω SIGNAL=DNC;27,28
0Ω R412 R413 18 S1 S6
DNP OPT_CLK R429
DNP DNP 10kΩ OUT1B R428 R438 R439
P401
AVDD_3.3V AVDD_3.3V

VREF
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
0Ω 0Ω 0Ω 0Ω
DNP DNP

6
7
8
9
Enc C407

10
11
12
13
14
15
16
25
C402 R423 0.1µF
100Ω LVDS OUTPUT S2 S7
0.1µF DNP
R404 R430 R431 R440 R441
49.9Ω 1
E401 AVDD_3.3V AVDD_3.3V
0Ω 0Ω 0Ω 0Ω
Clock Circuit S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 C408 DNP DNP
0.1µF R446
R417
OPT_CLK CLK DNP DNP S3 S8
DNP 0Ω
R415 T401 R432 R433 R442 R443
P402 0.1µF AVDD_3.3V

3
AVDD_3.3V
3 4 CR401 C409 0Ω 0Ω 0Ω 0Ω
Enc 0Ω DNP DNP
C403 2 5 HSMS-2812-TR1G CLIP SINE OUT (DEFAULT)
R416
S4 S9

2
1
0.1µF C410
R405 R434 R435 R444 R445

Rev. D | Page 39 of 52
0Ω 1 6 0.1µF
0Ω
C411 R418 AVDD_3.3V AVDD_3.3V
0Ω 0Ω 0Ω 0Ω
0.1µF 0Ω CLK DNP DNP

S5 S10

AVDD_3.3V

Figure 65. Evaluation Board Schematic, Clock Circuitry

C 41 2 C413 C 4 14 C 415 C416 C417 C 4 18
0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF

DNP: DO NOT POPULATE.

06296-075
AD9252
 AD9252

Populate L505−L520 with 0Ω

resistors or design your own filter.
EXT VG Power Down Enable
(0−1V=Disable Power)
JP501 CH_D CH_D CH_C CH_C CH_B CH_B CH_A CH_A
1 2 DNP AVDD_5V
10kΩ
C507 C508 R506
1000pF 0.1µF
R517 R522 R529 R534

GND
Rclamp Pin DNP DNP DNP DNP

VG12
HILO Pin=LO=+/− 50mV
HILO Pin=H=+/− 75mV

External
10kΩ
R505
R501
10kΩ

VG12
10µF
C510

CW
C543 C547 C551 C555
DNP DNP DNP DNP

Variable Gain Drive

L507 L508 L511 L512 L515 L516 L519 L520
0Ω 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω
R502

C509
0.1µF

AVDD_5V
39kΩ

C502
0.018µF
R503
274Ω
C505
0.1µF
C542 C546 C550 C554

(0−1.0V DC)
DNP DNP DNP DNP
L505 L506 L509 L510 L513 L514 L517 L518

C501
0.1µF

Variable Gain Circuit

0Ω 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω
C506
INH4

10kΩ
R504

AVDD_5V
R516 R521 R528 R533

VG12

AVDD_5V
0.1µF DNP DNP DNP DNP

L501
120nH
C503
22pF
10µF
C512
C504
0.1µF
U501

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
C540 C541 C544 C545 C548 C549 C552 C553
0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF

0.1µF
C511

VIP1
VIN1

INH1
EN12
EN34

LON1
LOP1
VPS1

LMD1
VCM1
VCM2

COM2
COM1
R515 R527 R532

GAIN12

COM1X
CLMP12
R520

C513
374Ω 374Ω 374Ω

0.1µF
374Ω

R513
187Ω
1 48 R514 R518 R519 R525 R526 R530 R531
INH3 INH2 COM12
187Ω 187Ω 187Ω 187Ω 187Ω 187Ω 187Ω
2 47

L502
LMD2 VOH1
AVDD_5V

120nH
C537
0.1µF 3 46

C515
COM2X VOL1

0.018µF

C514
22pF
R507
274Ω
4 45
LON2 VPS12 AVDD_5V
C518 5 44
R524

LOP2 VOL2
10kΩ

C538 0.1µF
0.1µF 6 43
VIP2 VOH2
7 42
VIN2 COM12
8 41
AVDD_5V VPS2 MODE
R523
10kΩ

AD8334ACPZ-REEL
9 40
AVDD_5V VPS3 NC MODE Pin
Positive Gain Slope = 0−1.0V
10 39 Negitive Gain Slope = 2.25−5.0V
VIN3 COM34
11 38
VIP3 VOH3
0.1µF
C522 C523 12 37
LOP3 VOL3

Rev. D | Page 40 of 52
0.1µF
13 36
LON3 VPS34 AVDD_5V
14 35
COM3X VOL4

R508
274Ω

C521
15 34

0.018µF
LMD3 VOH4
C524
0.1µF 16 33
INH3 COM34

L503
120nH
INH2
CLMP34

COM4X
GAIN34

COM3
COM4
VCM4
VCM3

LON4
VPS4

LOP4

INH4
LMD4
HILO

VIP4
VIN4
NC

C519
0.1µF
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

C520
22pF
EXT VG
10µF
C533

JP502
1 2
C529

C528 0.1µF
VG34

Figure 66. Evaluation Board Schematic, Optional DUT Analog Input Drive
0.1µF

GND

VG34
C534
0.1µF

AVDD_5V

External
R535

VG34
10kΩ

L504
AVDD_5V

120nH
INH1
10µF
C535

CW
C530

Variable Gain Drive

0.1µF
R509
274Ω

C527

C525
0.1µF
0.018µF
R536
R512
10kΩ

C526
39kΩ

22pF
Rclamp Pin
0.1µF
C536

HILO Pin=LO=+/− 50mV

C531 HILO Pin=H=+/− 75mV

(0−1.0V DC)
1000pF DNP
C532 10kΩ
0.1µF R510

Variable Gain Circuit

R511
10kΩ

AVDD_5V
DNP: DO NOT POPULATE.
06296-076
 MODE Pin
Populate L605−L620 with 0Ω
Positive Gain Slope = 0−1.0V
EXT VG Power Down Enable Negative Gain Slope = 2.25−5.0V resistors or design your own filter.
(0−1V=Disable Power)
JP601 CH_H CH_H CH_G CH_G CH_F CH_F CH_E CH_E
1 2 AVDD_5V
C607 DNP
1000pF C608 10kΩ
0.1µF R606
R617 R622 R629 R636

GND
DNP DNP DNP DNP

VG56
Rclamp Pin
HILO Pin=LO=+/− 50mV
HILO Pin=H=+/− 75mV

External
R605
R601

10kΩ
10kΩ

10µF

VG56
C610

CW
C643 C647 C651 C655
DNP DNP DNP DNP

Variable Gain Drive

L607 L608 L611 L612 L615 L616 L619 L620
0Ω 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω

C609
0.1µF
R602

AVDD_5V
39kΩ

C602
0.018µF
R603
274Ω
C605
0.1µF
C642 C646 C650 C654

(0−1.0V DC)
DNP DNP DNP DNP

C601
0.1µF
L605 L606 L609 L610 L613 L614 L617 L618

Variable Gain Circuit

C606 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω
INH8

AVDD_5V
R604

AVDD_5V
R616 R621 R628 R633

VG56
0.1µF DNP DNP DNP DNP

L601
120nH
C603
22pF
10µF
C612
C604
0.1µF

10kΩ
U601

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
C640 C641 C644 C645 C648 C649 C652 C653
0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF

C611
0.1µF

VIN1

VIP1

INH1
EN12
EN34

LON1
LOP1
VPS1

LMD1
VCM1
VCM2

COM2
COM1
R620 R627 R632

COM1X
GAIN12
CLMP12
R615

C613
0.1µF
374Ω 374Ω 374Ω
374Ω
R613
187Ω
1 48 R618 R619 R625 R626 R630 R631
INH7 INH2 COM12 R614
187Ω 187Ω 187Ω 187Ω 187Ω 187Ω 187Ω
2 47
LMD2 VOH1 AVDD_5V

L602
C616

120nH
0.1µF 3 46
COM2X VOL1

C615
0.018µF

C614
22pF
R607
274Ω
4 45
LON2 VPS12 AVDD_5V R624
C618 5 44 10kΩ
LOP2 VOL2
C617 0.1µF
0.1µF 6 43
VIP2 VOH2
7 42
VIN2 COM12
R623
8 41
AVDD_5V VPS2 MODE 10kΩ
AD8334ACPZ-REEL
9 40
AVDD_5V VPS3 NC
10 39
VIN3 COM34
11 38
VIP3 VOH3
0.1µF
C622 C623 12 37
LOP3 VOL3

Rev. D | Page 41 of 52
0.1µF
13 36
LON3 VPS34 AVDD_5V
14 35
COM3X VOL4

R608
274Ω

C621
15 34

0.018µF
LMD3 VOH4
C624
0.1µF 16 33
INH3 COM34

L603
120nH
INH6
CLMP34

COM4X
GAIN34

COM3
COM4
VCM4
VCM3

LON4
LOP4
VPS4

LMD4
HILO

INH4
VIP4
VIN4
NC

C619
0.1µF
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

C620
22pF
EXT VG
JP602
1 2
C629
10µF
C633

VG78

C628 0.1µF
0.1µF

GND
AVDD_5V

VG78

External
R634
C634
0.1µF

10kΩ

VG78
120nH
L604
AVDD_5V

Figure 67. Evaluation Board Schematic, Optional DUT Analog Input Drive (Continued)
INH5

CW
C630
0.1µF

Variable Gain Drive

R609
274Ω

C627

C625
0.1µF
10µF
C635

0.018µF

R635
R612
10kΩ

C626
39kΩ
22pF
Rclamp Pin
HILO Pin=LO=+/− 50mV
HILO Pin=H=+/− 75mV
DNP

(0−1.0V DC)
C631 C632 10kΩ
C636
0.1µF

1000pF 0.1µF R610

10kΩ
R611

Variable Gain Circuit

AVDD_5V
DNP: DO NOT POPULATE.
06296-077
AD9252
 AD9252

SPI CIRCUITRY FROM FIFO

Power Supply Input

+5V = PROGRAMMING = AVDD_5V 6V, 2A max
+3.3V = NORMAL OPERATION = AVDD_3.3V
REMOVE WHEN USING OR PROGRAMMING PIC (U402)
D702

CSB1_CHA
SCLK_CHA
SDI_CHA
SDO_CHA
AVDD_3.3V AVDD_5V F701 FER701
PWR_IN
1 2
P701 NANOSMDC110F-2
J701 4 3 SK33-TP
1 3 1
C704

R708
R709

2
R706
R707
AVDD_3.3V 10µF D701
C701
S2A-TP
CR702

GREEN

2
3
7.5V POWER

0Ω
0Ω
0Ω
0Ω
0.1µF U701
R710 CON005
1 8 R703 2.5MM JACK
VDD VSS 1kΩ
0Ω−DNP R716
R701 2 GP5 261Ω
4.7kΩ GP0 7
S701 R704
3 GP4 GP1 6
1 3
4 GP2 5 0Ω−DNP
2 4 MCLR/GP3
PIC12F629-I/SNG R705
0Ω−DNP Optional Power
RESET/ RE R702 Input
PROGRAM 261Ω
P702 L703
DNP 10µH
SDIO_ODM 1 3.3V_AVDD
P1 AVDD_3.3V +3.3V
2 C710
P2 C709
5V_AVDD 10µF 0.1µF

CR701
3
P3

OPTIONAL GREEN
NC7WZ07P6X_NL R712
AVDD_DUT 4
1kΩ R713 P4
1kΩ 5 DUT_AVDD
1 A1 Y1 6 P5 L701
E701 6 10µH
1 2 5 P6 AVDD_5V +5.0V
GND VCC AVDD_DUT
7 DUT_DRVDD
R711 3 A2 Y2 4 P7
10kΩ C705 C706
8 10µF 0.1µF
P8

GP0
GP1

MCLR/GP3
PICVCC
U702

9
7
5
3
1
C702

0.1µF
PIC PROGRAMMING HEADER ISP J702 L702
10µH

8
6
4
2

10
AVDD_DUT +1.8V
NC7WZ16P6X_NL C707
Decoupling Capacitors 10µF C708
0.1µF
1 A1 Y1 6
SCLK_DTP

Rev. D | Page 42 of 52
GP0
GP1
2 GND VCC 5 AVDD_DUT AVDD_5V

PICVCC
3 A2 Y2 4 C724 C725 C726 L704
CSB_DUT C723 C727

MCLR/GP3
10µH
0.1µF 0.1µF 0.1µF 0.1µF 0.1µF
DRVDD_DUT+1.8V
U703 C712
R715 C711

0.1µF
C703
R714 10µF 0.1µF
10kΩ 10kΩ

AVDD_DUT

C730 C731 C732 C733 C734 C735

0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF
AVDD_5V
U707 U705
L705 L707 C749 C750 C751 C752 C753
PWR_IN ADP3339AKCZ−1.8-RL 10µH PWR_IN ADP3339AKCZ−3.3-RL 10µH 0.1µF 0.1µF 0.1µF
3 2 3 2 0.1µF 0.1µF
IN OUT DUT_AVDD IN OUT 3.3V_AVDD
4 4
OUT OUT AVDD_DUT
C714 C715 C719 C720

GND

GND
1µF 1µF 1µF 1µF C744 C745 C746 C747 C748

1
1 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF

Figure 68. Evaluation Board Schematic, Power Supply Inputs and SPI Interface Circuitry
U704 L706 U706 L708
PWR_IN ADP3339AKCZ−1.8-RL 10µH PWR_IN ADP3339AKCZ−5-RL7 10µH AVDD_3.3V
3 2 3 2 DRVDD_DUT
IN OUT DUT_DRVDD IN OUT 5V_AVDD
OUT 4 4
OUT C742 C743
C740 C741
C716 C717 C721 C722 0.1µF 0.1µF 0.1µF 0.1µF
GND

GND
1µF 1µF 1µF 1µF
1

DNP: DO NOT POPULATE.

06296-078
 AD9252

06296-079
Figure 69. Evaluation Board Layout, Primary Side

Rev. D | Page 43 of 52
AD9252

06296-080
Figure 70. Evaluation Board Layout, Ground Plane

Rev. D | Page 44 of 52
 AD9252

06296-081
Figure 71. Evaluation Board Layout, Power Plane

Rev. D | Page 45 of 52
AD9252

06296-082
Figure 72. Evaluation Board Layout, Secondary Side (Mirrored Image)

Rev. D | Page 46 of 52
 AD9252
Table 17. Evaluation Board Bill of Materials (BOM) 1
Qty
per Reference Manufacturer
Item Board Designator Device Package Value Manufacturer Part Number
1 1 AD9252LFCSP_REVA PCB PCB PCB
2 118 C101, C102, C107, Capacitor 402 0.1 μF, ceramic, X5R, Murata GRM155R71C104KA88D
C108, C109, C114, 10 V, 10% tol
C115, C116, C121,
C122, C123, C128,
C201, C202, C207,
C208, C209, C214,
C215, C216, C221,
C222, C223, C228,
C301, C302, C304,
C305, C306, C401,
C402, C403, C409,
C410, C411, C412,
C413, C414, C415,
C416, C417, C418,
C501, C504, C505,
C506, C508, C509,
C511, C513, C518,
C519, C522, C523,
C524, C525, C528,
C529, C530, C532,
C534, C536, C537,
C538, C601, C604,
C605, C606, C608,
C609, C611, C613,
C616, C617, C618,
C619, C622, C623,
C624, C625, C628,
C629, C630, C632,
C634, C636, C701,
C702, C703, C706,
C708, C710, C712,
C723, C724, C725,
C726, C727, C730,
C731, C732, C733,
C734, C735, C740,
C741, C742, C743,
C744, C745, C746,
C747, C748, C749,
C750, C751, C752,
C753
3 8 C104, C111, C118, Capacitor 402 2.2 pF, ceramic, COG, Murata GRM1555C1H2R20CZ01D
C125, C204, C211, 0.25 pF tol, 50 V
C218, C225
4 8 C510, C512, C533, Capacitor 805 10 μF, 6.3 V ±10%, Murata GRM219R60J106KE19D
C535, C610, C612, ceramic, X5R
C633, C635
5 1 C303 Capacitor 603 4.7 μF, ceramic, X5R, Murata GRM188R60J475KE19D
6.3 V, 10% tol
6 4 C507, C531, C607, Capacitor 402 1000 pF, ceramic, X7R, Murata GRM155R71H102KA01D
C631 25 V, 10% tol
7 8 C502, C515, C521, Capacitor 402 0.018 μF, ceramic, X7R, AVX 0402YC183KAT2A
C527, C602, C615, 16 V, 10% tol
C621, C627

Rev. D | Page 47 of 52
AD9252
Qty
per Reference Manufacturer
Item Board Designator Device Package Value Manufacturer Part Number
8 8 C503, C514, C520, Capacitor 402 22 pF, ceramic, NPO, Murata GRM1555C1H220JZ01D
C526, C603, C614, 5% tol, 50 V
C620, C626
9 1 C704 Capacitor 1206 10 μF, tantalum, ROHM Co., Ltd. TCA1C106M8R
16 V, 20% tol
10 9 C307, C714, C715, Capacitor 603 1 μF, ceramic, X5R, Murata GRM188R61C105KA93D
C716, C717, C719, 6.3 V, 10% tol
C720, C721, C722
11 16 C540, C541, C544, Capacitor 805 0.1 μF, ceramic, X7R, Murata GRM21BR71H104KA01L
C545, C548, C549, 50 V, 10% tol
C552, C553, C640,
C641, C644, C645,
C648, C649, C652,
C653
12 4 C705, C707, C709, Capacitor 603 10 μF, ceramic, X5R, Murata GRM188R60J106ME47D
C711 6.3 V, 20% tol
13 1 CR401 Diode SOT-23 30 V, 20 mA, dual Avago HSMS-2812-TR1G
Schottky Technologies
14 2 CR701, CR702 LED 603 Green, 4 V, 5 m candela Panasonic LNJ314G8TRA
15 1 D702 Diode DO- 3 A, 30 V, SMC Micro SK33-TP
214AB Commercial Co.
16 1 D701 Diode DO- 5 A, 50 V, SMC Micro S2A-TP
214AA Commercial Co.
17 1 F701 Fuse 1210 6.0 V, 2.2 A trip-current Tyco/Raychem NANOSMDC110F-2
resettable fuse
18 1 FER701 Choke coil 2020 10 μH, 5 A, 50 V, 190 Ω Murata DLW5BSN191SQ2L
@ 100 MHz
19 24 FB101, FB102, Ferrite bead 603 10 Ω, test frequency Murata BLM18BA100SN1D
FB103, FB104, 100 MHz, 25% tol,
FB105, FB106, 500 mA
FB107, FB108,
FB109, FB110,
FB111, FB112,
FB201, FB202,
FB203, FB204,
FB205, FB206,
FB207, FB208,
FB209, FB210,
FB211, FB212
20 4 JP501, JP502, Connector 2-pin 100 mil header jumper, Samtec TSW-102-07-G-S
JP601, JP602 2-pin
21 6 J301, J302, J303, Connector 3-pin 100 mil header jumper, Samtec TSW-103-07-G-S
J304, J401, J701 3-pin
23 1 J702 Connector 10-pin 100 mil header, male, Samtec TSW-105-08-G-D
2 × 5 double row
straight
24 8 L701, L702, L703, Ferrite bead 1210 10 μH, bead core 3.2 × Murata BLM31PG500SN1L
L704, L705, L706, 2.5 × 1.6 SMD, 2 A
L707, L708
25 8 L501, L502, L503, Inductor 402 120 nH, test freq Murata LQG15HNR12J02D
L504, L601, L602, 100 MHz, 5% tol,
L603, L604 150 mA

Rev. D | Page 48 of 52
 AD9252
Qty
per Reference Manufacturer
Item Board Designator Device Package Value Manufacturer Part Number
26 32 L505, L506, L507, Resistor 805 0 Ω, 1/8 W, 5% tol NIC NRC04Z0TRF
L508, L509, L510, Components
L511, L512, L513, Corp.
L514, L515, L516,
L517, L518, L519,
L520, L605, L606,
L607, L608, L609,
L610, L611, L612,
L613, L614, L615,
L616, L617, L618,
L619, L620
27 1 OSC401 Oscillator SMT Clock oscillator, Valpey Fisher VFAC3-BHL-50MHz
50.00 MHz, 3.3 V,
±5% duty cycle
28 9 P101, P103, P105, Connector SMA Side-mount SMA for Johnson 142-0701-851
P107, P201, P203, 0.063" board thickness Components
P205, P207, P401
29 1 P301 Connector HEADER 1469169-1, right angle Tyco 6469169-1
2-pair, 25 mm, header
assembly
30 1 P701 Connector 0.1", RAPC722, power Switchcraft RAPC722X
PCMT supply connector
31 21 R301, R307, R401, Resistor 402 10 kΩ, 1/16 W, 5% tol NIC NRC04J103TRF
R402, R410, R413, Components
R504, R505, R511, Corp.
R512, R523, R524,
R604, R605, R611,
R612, R623, R624,
R711, R714, R715
32 18 R103, R117, R129, Resistor 402 0 Ω, 1/16 W, 5% tol NIC NRC04Z0TRF
R142, R203, R219, Components
R235, R253, R317, Corp.
R405, R415, R416,
R417, R418, R706,
R707, R708, R709
33 8 R102, R115, R128, Resistor 402 64.9 Ω, 1/16 W, 1% tol NIC NRC04F64R9TRF
R141, R202, R218, Components
R234, R252 Corp.
34 8 R104, R116, R130, Resistor 603 0 Ω, 1/10 W, 5% tol NIC NRC06Z0TRF
R143, R204, R220, Components
R236, R254 Corp.
35 28 R109, R111, R112, Resistor 402 1 kΩ, 1/16 W, 1% tol NIC NRC04F1001TRF
R123, R125, R126, Components
R135, R138, R139, Corp.
R148, R149, R150,
R211, R212, R214,
R228, R231, R232,
R246, R249, R250,
R262, R265, R266,
R319, R710, R712,
R713
36 16 R108, R110, R121, Resistor 402 33 Ω, 1/16 W, 5% tol NIC NRC04J330TRF
R122, R134, R136, Components
R146, R147, R209, Corp.
R210, R226, R227,
R242, R245, R260,
R261

Rev. D | Page 49 of 52
AD9252
Qty
per Reference Manufacturer
Item Board Designator Device Package Value Manufacturer Part Number
37 8 R161, R162, R163, Resistor 402 499 Ω, 1/16 W, 1% tol NIC NRC04F4990TRF
R164, R208, R225, Components
R241, R259 Corp.
38 3 R303, R305, R306 Resistor 402 100 kΩ, 1/16 W, 1% tol NIC NRC04F1003TRF
Components
Corp.
39 1 R414 Resistor 402 4.12 kΩ, 1/16W, 1% tol NIC NRC04F4121TRF
Components
Corp.
40 1 R404 Resistor 402 49.9 Ω, 1/16 W, 0.5% tol Susumu RR0510R-49R9-D
41 1 R309 Resistor 402 4.99 kΩ, 1/16 W, 5% tol NIC NRC04F4991TRF
Components
Corp.
42 5 R310, R501, R535, Potentiometer 3-lead 10 kΩ, Cermet trimmer Copal CT94EW103
R601, R634 potentiometer, 18-turn Electronics
top adjust, 10%, 1/2 W Corp.
43 1 R308 Resistor 402 470 kΩ, 1/16 W, 5% tol NIC NRC04J474TRF
Components
Corp.
44 4 R502, R536, R602, Resistor 402 39 kΩ, 1/16 W, 5% tol NIC NRC04J393TRF
R635 Components
Corp.
45 16 R513, R514, R518, Resistor 402 187 Ω, 1/16 W, 1% tol NIC NRC04F1870TRF
R519, R525, R526, Components
R530, R531, R613, Corp.
R614, R618, R619,
R625, R626, R630,
R631
46 8 R515, R520, R527, Resistor 402 374 Ω, 1/16 W, 1% tol NIC NRC04F3740TRF
R532, R615, R620, Components
R627, R632 Corp.
47 8 R503, R507, R508, Resistor 402 274 Ω, 1/16 W, 1% tol NIC NRC04F2740TRF
R509, R603, R607, Components
R608, R609 Corp.
48 11 R425, R427, R429, Resistor 201 0 Ω, 1/20 W, 5% tol NIC NRC02Z0TRF
R431, R433, R435, Components
R436, R439, R441, Corp.
R443, R445
49 1 R701 Resistor 402 4.7 kΩ, 1/16 W, 1% tol NIC NRC04J472TRF
Components
Corp.
50 1 R702 Resistor 402 261 Ω, 1/16 W, 1% tol NIC NRC04F2610TRF
Components
Corp.
51 1 R716 Resistor 603 261 Ω, 1/16 W, 1% tol NIC NRC06F261OTRF
Components
Corp.
52 2 R420, R421 Resistor 402 240 Ω, 1/16 W, 5% tol NIC NRC04J241TRF
Components
Corp.
53 2 R422, R423 Resistor 402 100 Ω, 1/16 W, 1% tol NIC NRC04F1000TRF
Components
Corp.
54 1 S701 Switch SMD Light Touch, Panasonic EVQPLDA15
100 GE, 5 mm

Rev. D | Page 50 of 52
 AD9252
Qty
per Reference Manufacturer
Item Board Designator Device Package Value Manufacturer Part Number
55 9 T101, T102, T103, Transformer CD542 ADT1-1WT+, Mini-Circuits ADT1-1WT+
T104, T201, T202, 1:1 impedance ratio
T203, T204, T401 transformer
56 2 U704, U707 IC SOT-223 ADP3339AKC-1.8-RL, Analog Devices ADP3339AKCZ-1.8-RL
1.5 A, 1.8 V LDO
regulator
57 2 U501, U601 IC CP-64-3 AD8334ACPZ-REEL, Analog Devices AD8334ACPZ-REEL
ultralow noise
precision dual VGA
58 1 U706 IC SOT-223 ADP3339AKC-5-RL7 Analog Devices ADP3339AKCZ-5-RL7
59 1 U705 IC SOT-223 ADP3339AKC-3.3-RL Analog Devices ADP3339AKCZ-3.3-RL
60 1 U301 IC CP-64-3 AD9252BCPZ-50, octal, Analog Devices AD9252BCPZ-50
14-bit, 50 MSPS serial
LVDS 1.8 V ADC
61 1 U302 IC SOT-23 ADR510ARTZ, 1.0 V, Analog Devices ADR510ARTZ
precision low noise
shunt voltage
reference
62 1 U401 IC LFCSP AD9515BCPZ, 1.6 GHz Analog Devices AD9515BCPZ
CP-32-2 clock distribution IC
63 1 U702 IC SC70, NC7WZ07P6X_NL, Fairchild NC7WZ07P6X_NL
MAA06A UHS dual buffer
64 1 U703 IC SC70, NC7WZ16P6X_NL, Fairchild NC7WZ16P6X_NL
MAA06A UHS dual buffer
65 1 U701 IC 8-SOIC Flash prog Microchip PIC12F629-I/SNG
mem 1k × 14,
RAM size 64 × 8,
20 MHz speed, PIC12F
controller series
1
This BOM is RoHS compliant.

Rev. D | Page 51 of 52
AD9252

OUTLINE DIMENSIONS
9.00 0.60 MAX
BSC SQ 0.60
MAX PIN 1
49 64 1 INDICATOR
48
PIN 1
INDICATOR

0.50 EXPOSED PAD 7.55

8.75 BSC (BOTTOM VIEW)
BSC SQ 7.50 SQ
7.45

0.50
33 16
0.40
32 17
0.30
0.22 MIN
TOP VIEW
7.50
REF
12° MAX 0.80 MAX
1.00
0.65 TYP FOR PROPER CONNECTION OF
0.85
0.05 MAX THE EXPOSED PAD, REFER TO
0.80 THE PIN CONFIGURATION AND
0.02 NOM
FUNCTION DESCRIPTIONS
SEATING 0.30 SECTION OF THIS DATA SHEET.
PLANE 0.20 REF
0.23

02-23-2010-B
0.18

COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4

Figure 73. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
(CP-64-6)
Dimensions shown in millimeters

ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD9252ABCPZ-50 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-64-6
AD9252ABCPZRL7-50 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Tape and Reel CP-64-6
AD9252-50EBZ Evaluation Board
1
Z = RoHS Compliant Part.

©2006–2010 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D06296-0-4/10(D)

Rev. D | Page 52 of 52