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High-side current-sensing switched-mode

regulator provides constant-current LED drive
Bradley Albing, Philips Medical Systems Inc, Cleveland, OH
any suitable circuits exist for erence diode. A voltage of 3.3V appear-

M driving LEDs in constant-current

mode and from low-voltage
sources. For example, references 1, 2, and
3 show circuits that use switched-mode-
regulator ICs and low-voltage sources to
supply LED current. To produce a con-
stant-current output using the circuit in
Reference 2, you configure the regulator
IC as a boost-mode switcher and use a re-
sistor to sense the load current flowing in
the LED string’s low side, or negative-re-
turn leg. The sense resistor produces a
proportional voltage that’s applied to the
LT1300’s Sense input through a 2.5V ref-
ing at the LT1300’s feedback-input ter-
minal, Pin 4, indicates that the circuit’s
output is within regulation.
In applications that require a series
string of LEDs to operate with its low side
connected to ground, current sensing
must take place in the string’s high side.
You can use either a rail-to-rail op amp
and a handful of passive components or
a dedicated current-sensing IC, such as
Maxim’s MAX4073T, to accomplish
high-side sensing. However, adding a
current-sensing IC increases circuit cost.
To complicate matters, in this applica-
High-side current-sensing
switched-mode regulator provides
constant-current LED drive ..........................95
Microcontroller’s DAC provides
code analysis ..................................................96
Two gates and a microprocessor
form digital PLL ..............................................98
Simple sine synthesizer generates
19-kHz pilot tone for FM baseband
signal ..............................................................100
Publish your Design Idea in EDN. See the
What’s Up section at www.edn.com.

9V

LED
D3

R1 + C1 LED
10k 120
F L1 D4
22
H
LED
5 D1
I-LIM VCC 6 R4 D5
1N5817
15
3 IC1 7 1
SHDN SW LED
LT1300
8 4 C2 + D6
P-GND SENSE R2 Q1
10
F 100k 2N4402 R5
1 2 1k LED
GND SEL
D7
2
D2 LED
1N5248 D8
C3 18V
R3
1
F LED
9V RETURN 1k
D9
3
LED
D10

S1
ON/OFF
Figure 1

A single switched-mode-regulator IC drives a series-connected string of LEDs in constant-current mode.

www.edn.com April 14, 2005 | edn 95

design
ideas
tion, only three conductors are available
to connect a remotely mounted LED
string, D3 through D10, and on/off switch
S1 to the regulator circuitry.
In this Design Idea, an LT1300, IC1,
boosts 9V to drive the LED string, which
presents a total forward-voltage drop of
approximately 12V (Figure 1). Resistor R4
serves as a current-sense resistor. At a cur-
rent of approximately 40 mA, transistor
Q1 conducts and forces current through
R3, developing sufficient voltage drop to
produce the requisite 3.3V at Sense Pin 4
of IC1, bringing its output current into
regulation. Zener diode D2 limits the reg-
ulator’s output voltage in case the LED
string or connector opens. Switch S1 turns
on the circuit by grounding IC1’s Pin 3.왏
References
1. LT1300 data sheet, Linear Technol-
ogy Corp.
2. Application Note 59, Linear Tech-
nology Corp.
3. Caldwell, Steve, “1.5V battery pow-
ers white-LED driver,” EDN, Sept 30,
2004, pg 96.

Microcontroller’s DAC provides code analysis

Dave Bordui, Cypress Semiconductor, Heathrow, FL
inding out where your microcon-

F troller’s firmware spends most of its

time can be a tedious task when you
use a conventional in-circuit emulator
VARIOUS
FIRMWARE
SUBROUTINES,
STATES, OR
and breakpoint techniques. Other such VARIABLES
tasks include discovering why a state ma- 8-BIT
chine doesn’t work as you intended and INTERNAL I/O DRIVER I/O PIN
SUBROUTINE, STATE, DAC
where your code goes during real-time
VARIABLE, ERROR,
operation or during an error condition. DEBUG VALUES
Classic debugging methods can also be-
come cumbersome when you attempt to
observe error states or debug a program- CHARACTERISTIC
flow problem. Fortunately, a technique OPERATING
WAVEFORM
that takes advantage of a feature that
many microcontrollers now include of-
fers a simple debugging aid that allows ERROR
CONDITION
designers to easily monitor these and OR STATE
other operations.
The technique uses the DAC in mi-
crocontrollers such as Cypress Mi- Figure 1 OSCILLOSCOPE
crosystems’s PSoC (programmable-
system-on-chip) family (Figure 1). These
devices provide a microcontroller core Put an unused internal DAC to work as a code analyzer and see where a microcontroller’s routines
and an array of mixed-signal building go wrong.
blocks that includes true DACs that can
deliver fixed dc levels. Other types of of the microcontroller’s unused analog portion of the firmware is executing sim-
DACs that deliver pulse-width-modulat- output pins. Then, you write the state ply by measuring the DAC’s dc output
ed outputs are unsuitable for this appli- constant to the DAC whenever the voltage at a given time.
cation. To use this technique, you create firmware enters a particular location. If You can define state constants to
firmware “state constants” that represent you use an 8-bit DAC, you can also mon- highlight certain conditions. For exam-
operating states of your design. If your itor the value of any 8-bit variable. Next, ple, by reserving all state constants’ val-
code structure comprises a state machine you connect an oscilloscope’s vertical in- ues greater than 127 for error states, you
or contains a large “switch/case” state- put to the DAC’s output pin and observe can set the oscilloscope’s horizontal
ment, then you have already defined its output voltage, which the instrument sweep generator to trigger at a level that
these constants. Otherwise, you can eas- displays as a characteristic waveform that indicates an error. As a precaution, make
ily add the constants as needed. represents the firmware’s operation. If sure that the microcontroller’s DAC op-
Once you define the constants, you en- your oscilloscope includes measurement erates within its allowable update-rate
able a DAC and configure it to drive one cursors, you can easily determine which range.왏
96 edn | April 14, 2005 www.edn.com
design
ideas
Two gates and a microprocessor form digital PLL
Kenneth Martin, TareTronics Inc, Corinth, MS
ou can use Microchip’s low-cost IC3 5V

Y PIC16F818 microprocessor and a

pair of gates to construct a digital
PLL that can clean noisy digital signals 1
CLKOUT 15
PIC16F818

RA6
VDD 14
VDD

over a range of 4 to 40 kHz. Featuring f1 12 3 PHASE-GATED CLOCK 12 C1

11 2 RB8
13 IC2 0.1
F
programmable lock range, phase differ- CD4071B VSS 5
ential, and loop gain, the digital-PLL en- IC1 PHASE OR fIN 13 RB7
CD4077B
gine and lock detector can extract clock fOUT
fOUT 2
and data information from noisy, short- RA3

range radio signals (Figure 1). When you

LOCK INDICATOR 18
construct it using a QFN-packaged mi- LOCK RA1

croprocessor and discrete single-gate R 1

1k OPTIONAL
logic devices, the circuit occupies a pc- NOTES:
LED1 PINOUTS ARE FOR A PIC16F818 DIP.
board area that’s approximately as large ILLUMINATED OPTIONAL IC2 IS A CD4071B OR FUNCTIONALLY EQUIVALENT
as an aspirin. WHEN SINGLE-OR GATE.
LOCKED
Figure 2 is analogous to a first- IC3 IS A CD4077B OR FUNCTIONALLY EQUIVALENT
Figure 1 SINGLE-XNOR GATE.
order analog PLL (Reference 1). CONNECT PIN 14 TO VDD AND PIN 7 TO GROUND
With its associated period register, Timer ON IC1 AND IC2.
GROUND ALL UNUSED GATE INPUTS.
2 functions as a DCO (digitally con-
trolled oscillator). When Timer 2’s count This microcomputer-based digital-PLL circuit locks to signals over a 4- to 40-kHz range and
matches the byte in its period register, the requires a minimal number of components.
timer generates an interrupt. The micro-
processor then computes a byte of infor- four, or eight. During each of the output able count changes in the direction nec-
mation that writes to the period register frequency’s half-periods, Timer 1 accu- essary to achieve and maintain phase lock
to set the duration of the next half-peri- mulates (integrates) the prescaled pulses. between the input and the output fre-
od. In addition, the interrupt toggles an The interrupt-service-routine software quency. As an example, assume that the
I/O port’s output to produce square-wave for Timer 2 closes the loop and deter- input frequency is 10 kHz; the maximum
signal-output frequency, which drives mines the digital PLL’s key parameters. clock-frequency cycle count for each out-
one input of the external XNOR (exclu- This routine comprises 19 instructions put-frequency half-period, N0, is 110; the
sive-nor) gate, IC1. The external input that execute in about 10
sec when IC3’s division factor for the clock-frequency
signal’s input frequency drives the XNOR internal clock oscillator runs at 8 MHz. count that represents the phase of the
gate’s remaining input to produce an out- After each Timer 2 interrupt, the inter- output frequency, K, is two; and the out-
put signal, which represents the phase rupt-service routine toggles the output put frequency is phase-locked to the in-
difference, between the output and the frequency, checks for phase lock, and put frequency. The half-period of 10 kHz
input frequency. This XNOR-based then divides the output of Timer 1 by is 50
sec, or 100 counts, when the clock
phase detector provides good perform- two, making K equal to one, two, four, frequency is 2 MHz. Substituting these
ance with noisy digital input signals. eight, or 16. The routine subtracts the re- values in Equation 1 and solving for the
The phase difference signal’s duty cy- sulting value from N0 and writes the dif- variable phase count yields a value of 20,
cle remains linear over a 0 to 180 range ference to Timer 2’s period register, which corresponds to a phase of 0.1, or
of two same-frequency signals. Applying which sets the length of the output fre- 36. Thus, with these parameters, the dig-
the phase detector’s output along with quency’s next half-period. Although ital PLL’s output frequency locks to the
clock-signal clock frequency to OR gate some interrupt-service-routine opera- input frequency with a phase difference
IC2 produces an output burst of 2-MHz tions slightly modify the result, this count of 36.
clock pulses during each half-period in- is typically as follows: If the input frequency decreases, its
terval of output frequency. The burst’s half-period lengthens, and the variable
length and the number of clock pulses it (1) phase count becomes smaller. According
contains depend directly on the duty cy- to Equation 1, after the division factor di-
cle or phase interval of the output fre- For phase lock, the output-frequency vides the variable phase count and you
quency relative to the input frequency. half-period must equal the input-fre- subtract it from the maximum half-pe-
The circuit applies phase-difference quency half-period. The computed vari- riod clock-frequency count, the half-pe-
pulses from IC2 to the internal prescaler able half-period count adjusts the out- riod of the output frequency increases,
associated with IC3’s Timer 1, which di- put’s frequency and phase. If the input lowering the output frequency and driv-
vides them by a preset factor of one, two, frequency is within lock range, the vari- ing it toward a new match with the input
98 edn | April 14, 2005 www.edn.com
design
ideas
frequency. If the input frequency in-
creases, the reverse occurs. fCLK
Equation 2 defines the digital PLL’s
operation in phase-lock frequency, and PRESCALE
INPUT 8-BIT
design-selected system parameters: fIN
+
TIMER 1L
ONE, TWO,
(COUNTER
FOUR,
MODE)
OR EIGHT
(2)

+2
ⳮ
34ⱕN0ⱕ255; Ktwo, four, Figure 2 N0


+
eight, or 16; and 0ⱕⱕ0.5,where MAXIMUM fOUT
HALF-PERIOD
f is the frequency, fCLK is the clock fre- PERIOD
quency, N0 is the maximum clock-fre-
quency cycle count for each output-fre- PERIOD REGISTER
quency half-period,  is the phase of the FOR TIMER 2
output frequency relative to the input fOUT 8-BIT fCLK
frequency, and K is the division factor for TIMER 2
the clock-frequency cycle count that rep-
resents the output phase of the output An XNOR-gate phase detector provides good performance with noisy signals, and a microprocessor
frequency relative to the input frequency. handles signal processing.
Adding a constant value of 2.5 to the out-
put frequency’s period count compen- a center frequency of 9266 Hz, a mini- You can adapt the digital PLL’s basic
sates for interrupt-service-routine oper- mum frequency of 8989 Hz, and a lock design to a variety of applications by
ations that slightly affect the timing. The range of 555 Hz. modifying the software and extending
calculated value of phase-lock frequency Resolution of the DCO using Timer 2 the interrupt-service routine. For exam-
is accurate to within 1.5% over most establishes the time jitter of the output ple, stopping updates to Timer 2’s peri-
of the PLL’s usable range. Because the frequency relative to the input frequency. od register puts the PLL in “coast” mode.
PLL comprises only digital circuits and Depending on the integer count written Other expansion possibilities include im-
software, operation with any combina- to its period register, Timer 2 produces plementing more sophisticated lock-de-
tion of parameters is repeatable. discrete frequencies for output frequen- tection circuitry to determine whether
You can manipulate Equation 2 to cy. When the input frequency falls be- the input frequency falls within a certain
solve for any variable in terms of the re- tween discrete output frequencies that frequency range and making dynamic
maining four. To calculate the upper and two adjacent counts produce, the PLL adjustments of the values of N0 and K for
lower limits of the lock range, set  at 0.5 switches between the counts to produce better performance. You can download
and 0, respectively. To calculate the digi- an averaged but jittery output-frequency Listing 1, which is the assembly-language
tal PLL’s “center frequency,” set  at 0.25, signal at the same frequency as the input source code, as well as the hex program-
which corresponds to a 90 phase angle. frequency. Using a relatively large value of ming file for IC3, from the online version
In the previous example, maximum fre- N0 reduces jitter, whereas a smaller value of this Design Idea at www.edn.com.왏
quency is 13,408 Hz, center frequency is increases jitter. To improve resolution and
11,204 Hz, and minimum frequency is reduce jitter, you can increase the clock Reference
8989 Hz. The lock range is 13,408 to frequency to 5 MHz by configuring the 1. Gardner, Floyd M, Phaselock Tech-
8989, or 4419 Hz. Increasing K to 16 microprocessor’s on-chip oscillator to use niques, Second Edition, Wiley-Inter-
yields a maximum frequency of 9544 Hz an external 20-MHz crystal. science, 1979, ISBN 0-471-04294-3.

Simple sine synthesizer generates

19-kHz pilot tone for FM baseband signal
Carlos Bernal and Diego Puyal, Departamento Ingeniería Electrónica y Comunicaciones,
Universidad de Zaragoza, Zaragoza, Spain
multiplex signal comprises base- munications Authorization) channels comprises a baseband signal, and the

A band information transmitted on a

stereo analog FM-broadcast system,
plus one or more SCA (Subsidiary Com-
(Figure 1). This Design Idea presents a
low-cost method of generating the basic
19-kHz pilot tone. The 19-kHz pilot tone
LR and L R signals consist of DSBSC
(double-sideband-suppressed-carrier)
modulation centered at 38 kHz. For a re-
100 edn | April 14, 2005 www.edn.com
design
ideas
ceiver to correctly demodulate the sig-
nal, the transmitted pilot tone and L R PILOT TONE

signal must synchronize at their respec- SCA SERVICES

tive zero crossings. In addition, any dis-
tortion in the pilot tone produces har- L+R SCA1 SCA2
LⳮR LⳮR
monics that can interfere with adjacent (LSB) (USB)

sections of the signal. 15 19 23 38 53 75 99

The low-distortion, 19-kHz pilot-tone MODULATION
generator comprises a resistive voltage (kHz)
divider, R1 through R11, con-
Figure 1
nected between the VCC and A typical FM-broadcast signal contains a complex spectrum.
VCC supply rails (Figure 2). The resis-
tors’ values are weighted to provide N8 a zero-order hold circuit, producing an of hex inverter IC1 serve as a crystal os-
approximate sampled values of a sine N times Nyquist oversampled sine wave cillator and buffer.
wave and are relatively low to present of frequency fSIN, plus several attenuated You can expand the basic circuit by du-
“stiff,” low-impedance sources to eight- alias frequencies centered at: fALIAS plicating the resistor network, multi-
channel analog multiplexer IC1. An m
(2
N
fSINE), where m1, 2, 3. For plexer, and up/down counter. An exter-
up/down counter, IC2, drives IC1 and most applications, a simple passive RC nal audio source drives the resistor
takes advantage of a sine wave’s inherent filter at the multiplexer’s output ade- network’s upper and lower ends with L
symmetry to enhance the resolution and quately removes the alias frequencies. Bi- and R audio signals that have undergone
reduce the distortion of the 19-kHz pi- nary counter IC3 generates a 608-kHz lowpass-filtering to eliminate compo-
lot sine wave. clock signal plus a 19-kHz up/down con- nents with frequencies greater than 15
In effect, analog multiplexer IC1 acts as trol signal for counter IC2, and sections kHz. A 1.216-MHz signal clocks the sec-
ond up/down counter and
VCC
a 38-kHz up/down control
R1 R 2
IC1
R R
signal derived from higher
MC14051 14 15
10 10
13
X0 X
3 7.5k 6.8k PILOT-TONE frequency taps on counter
OUTPUT
14
X1
C C
1 P
10k C
IC2. The added circuitry
R 15 1 2 3
3 X2
20 12 X3
1 nF 1 nF 1 nF generates the baseband
1
5
X4 LR channel, and the L R
X5
R
2
X6
modulation in synchro-
4 4
36 X7 nism with the 19-kHz pilot
6
INH tone because all clock puls-
R 11
es originate from a com-
5 A
47 10
B mon counter. To produce
9 NOTES:
C
RESISTOR TOLERANCE IS 1%. the composite multiplex
R
ⳮV CC
7
VEE
USE 100-nF, CERAMIC-BYPASS CAPACITORS
ON V PINS OF ALL ICs.
CC
signal, the outputs of both
6
51
IC2
GROUND UNUSED INPUTS ON IC .
4 analog multiplexers sum in
4 6
12
P0 MC14516 Q0
P1 Q1
11 an external network.
13 14
3 P2
P3
Q2
2 Using the specified com-
Q3
R
47
7
1
PE COUT
7 5 IC
HEF4069
3 6 ponents, the circuit gener-
5
10
CIN
U/D
ates a 19-kHz pilot tone
15
9
CLK
RST
with harmonics 60 dB be-
R
36
8
low the fundamental and
synchronous with the max-
imums of the suppressed
R
20
9

IC IC
38-kHz carrier. The same
1 4A 2 3 4B 4 1 3
Q0
HEF4069 HEF4069
VCC
CLK
2 EN IC 5A Q1
4 B NODE circuit structure produces
HEF4520 Q2 5
R R
R 13
7
R Q3 6 LR- and L R-channel
10 11
R 330
10 10
22M
12
generation without chang-
9 11
10
CLK Q0
12 ing components’ values. Po-
ⳮV EN IC 5B Q1 C NODE
CC HEF4520 Q2 13 tentiometer P1 allows a
15 R 14
X 1 Q3
4.86 MHz 9010 fine phase adjust-
Figure 2 ment to correct distortion
and to resynchronize at zero
The pilot-tone-generator circuit uses low-cost CMOS-logic circuits plus an analog multiplexer. crossing.왏

102 edn | April 14, 2005 www.edn.com