If Digital Radio Based On Blackfin Processor

IF Digital Radio Based on Bla
kn
Pro essor
GEOFFREY CHAUVEAU
Master's Degree Proje t
Sto kholm, Sweden
XR-EE-SB 2006:008
IF Digital Radio Based on Blackn Processor
Master thesis report
6th March 2006
Georey Chauveau
Acknowledgements
This Master thesis work has been carried out during between September 2005 and February 2006 in the
Radio Program of Siemens VDO in Rambouillet.
First of all, I would like to thank my supervisor at Siemens VDO, Cyrille Potereau, for allowing me to do
this project and introducing me to the world of car radios. His help and advice were very useful during the
project. I would like also to thank my advisor at KTH, David Hammarwall, for his review work. Finally I
would like to extend my thanks everyone at Siemens VDO involved during this project, especially all members
of the Hardware group for their support and for making my time in this company most enjoyable.
Rambouillet, February 2006

Abstract
Over the last fteen years, digital signal processing has taken a growing part in radio systems with the rapid
advances in IC technlogy. Previously dedicated to the sound processing part, digital techniques are now used
directly on modulated signals with high carrier frequencies and allow the replacement of analog hardware parts
by a single chip with higher performance, exibility and reliability, and reduced size and cost. The mixing and
demodulation parts are indeed completely performed by software now.
In this project, the design of a software AM/FM radio receiver with a Blackn DSP is studied. The rst
step is to study the feasibility of such a radio receiver with a development board. The second step is to build
a complete radio receiver on a dedicated board using the components and the DSP tting the best to this
application. The structure adopted is a superheterodyne receiver with two stages allowing a low sampling
frequency of the modulated signal. The performance of this receiver is then measured and compared with a
standard radio receiver and possible improvements are suggested.
i
ii
Contents
Introduction 1
1 Development board 3
1.1 Hardware components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1.1 The Blackn BF533 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1.2 The development board: EZ-KIT Lite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Purpose of this board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1.3 The A/D converter : AD7655 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection with the Blackn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1.4 Serial ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1.5 Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1.6 Audio codec AD1836 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Software part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2.1 Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SPORT conguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
DMA conguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2.2 Data processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Choosing clocks and data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Mixing the input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Designing lters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Demodulation and audio ltering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Moving data to the audio codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.3 First results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.3.1 Talkthrough test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.3.2 Demodulation test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.3.3 FM demodulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.3.4 AM demodulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2 Dedicated board 21
2.1 Hardware components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.1.1 Aim of this board and general layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.1.2 BF532 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.1.3 AD converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.1.4 Dierential ADC Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.1.5 Parallel port interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.1.6 Tuner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.1.7 Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
iii
2.1.8 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.1.9 Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.1.10 External memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SD-RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.1.11 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.1.12 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.1.13 Electrical schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2 Software part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.2.1 Data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
PPI conguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DMA transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.2.2 Signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Bandpass ltering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Mixing and lowpass ltering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Demodulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Audio ltering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.2.3 Data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
SPORT conguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
DMA conguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.3 Radio measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.3.1 SNR and THD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.3.2 Frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.4 Source of problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.4.1 Clock alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.4.2 Clock shape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.4.3 Range and saturation of components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.5 Possible improvements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.5.1 Hardware improvements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.5.2 Software improvements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Conclusion 43
A Source code 45
A.1 Main . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
A.2 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
A.2.1 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
A.2.2 Communication ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
A.2.3 Header le . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
A.3 Handling of interruptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
A.4 Data processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
B Theoretical results 57
B.1 Radio signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
B.1.1 Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
B.1.2 AM and FM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
AM modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
FM modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
B.2 Equivalent lowpass of the baseband signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
B.3 Demodulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
B.3.1 1st method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
B.3.2 2nd method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
B.3.3 Digital case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
B.3.4 Lowpass lters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
B.3.5 Extracting the audio signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
AM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
FM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
C Master thesis proposal 63

C.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
C.2 Problem denition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
C.2.1 Hardware part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
C.2.2 Software part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
C.2.3 Possible additional developments and improvements (depending on the time left) . . . . . 64
C.3 Research Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
C.4 Expected Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
C.5 Time Plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
References 65
v
Introduction
Siemens VDO Automotive (SV) Rambouillet is specialized in development and production of car radios and
multimedia systems for car manufacturers (GM, Renault, PSA, BMW ...). The study takes place inside the
"radio program" group which develops platforms (generic hardware and software which are then customized for
each customer) and more especially in the hardware key component group which is in charge of the development
and validation of radio components (microcontroller, DSP, power amplier, etc ...).
The latest generation of car radios uses a new kind of technology to perform the radio reception called
"IF digital". Previously, the FM/AM de-modulation was performed inside the tuner module with analog
components, and an analog signal, which was nearly the audio signal, was delivered to the DSP for nal
processing. With the latest generation of radio, the tuner module is only a front end doing the HF reception
and delivers a not demodulated signal called Intermediate Frequency (IF) to the DSP. This IF is digitalized and
then ltered and demodulated in the DSP. Only a few IC suppliers are providing specic DSP's and software
for car radio with integrated mixers and lters. Siemens VDO Automotive is interested in getting the full
knowledge of this system (hardware and software) in order to make its own improvement and to increase its
number of possible IC suppliers.
The aim of this master thesis is thus to design a complete digital superheterodyne (with frequency transposi-
tion) radio receiver whose main part is a Blackn DSP. The prototype has to use a tuner made by SV providing
an intermediate frequency (IF), a modulated signal at a xed carrier frequency, from an external radio signal.
The design of the receiver is separeted into two parts: a rst prototype on a development board and then a
complete radio receiver on a dedicated board.
1
IF Digital Radio Based on Blackn Processor
2
Chapter 1
Development board
The rst part of the study is focused on the design of a prototype using a development board. The main
task is to make a "proof of concept" and test the functionality of the Blackn DSP in a radio conguration.
An interface between the development board and an external A/D converter has to be built.
The rst section of this part focuses on the description of the hardware components chosen to design the
radio, their specications and the connection between them. The second section deals with the design of the
software that commands all the hardware components and performs the signal processing. The third section
deals with preliminary results.
1.1 Hardware components

1.1.1 The Blackn BF533
The central part of this digital radio is a Blackn DSP, the BF533, produced by Analog Devices. Its low
price, high speed (core clock up to 600 MHz and up to 1200 MMAC per second) and low power consumption
(less than 300mW) make it a good choice for an embedded product. Moreover, designed specically for audio
and video processing, it is provided with many communication features (SPI, PPI, SPORT, UART...) and a
exible DMA structure. Finally, the fact that it is easy to read and write assembler for Blackn simplies the
development on this processor. See [6] for detailed specications.
1.1.2 The development board: EZ-KIT Lite

Purpose of this board
A development board made by Analog Devices is used to speed up the design of the digital radio. This
will save the time needed to choose and assemble all the components needed on a card. Besides, this card is
provided with a software development environment.
Components
Here are all the useful features of the development board for the design of a digital radio.
• Blackn BF533SKBC600 DSP
• 32 Mb of SDRAM
• 2 Mb of Flash memory
• an AD1836 audio codec with input and output connectors
• general purpose LED and push buttons
• USB connectivity
3
IF Digital Radio Based on Blackn Processor CHAPTER 1. DEVELOPMENT BOARD
• Three 90-pin connectors providing PPI, SPI, EBIU Timers0-2, UART, Programmable Flags, SPORT0,
and SPORT1 expansion interfaces for analyzing and interfacing
• Evaluation suite of Visual DSP ++
A complete list of features and all schematics of the EZ-KIT Lite are available on the web site of Analog
Devices (see [7] and [4])
1.1.3 The A/D converter : AD7655

Since the A/D converter of the audio codec has a sampling frequency of 48 kHz, an external one is needed
to sample the IF without aliasing. The AD7655 A/D converter is chosen for this purpose.
Properties
This component is a cheap 4 input channels 16 bit A/D converter with serial and parallel outputs that can
provide up to 1 million samples per second, according to its reference data sheet [1].
Connection with the Blackn

On the development board, the parallel port is already connected to the video circuitry and therefore not
available. The only port left is the Serial Port 1 and thus the serial data format is used.
Limitations
The input signal must be in the range 0-5V (a 2.5 V DC signal must be added to a zero-mean input) and
after some tests, the sample frequency can not exceed 385 kHz. Over this frequency, the delay between the
sampling and the transmission of the data bits is too high, and data bits were not sent entirely and interrupted
by a new sampling. No obvious fact could explain such a delay, probably because there was a weakness in the
particular chip mounted on the board.
1.1.4 Serial ports

The Blackn has two serial ports: SPORT0 and SPORT1. SPORT0 is connected to the audio codec and
SPORT1 is used to receive data from the A/D converter.
Three signals are used with serial ports (see Figure 1.1):
Frame synchronization signal This signal is used to state the beginning of a data word or the beginning of
the transmission of data words.
Serial data clock signal This signal is a clock synchronized with the transmission of a data bit.
Data signal This signal transmits the data bits one by one at each serial clock pulse.
1.1.5 Connection diagram

To control the sampling frequency, the Timer 1 of the Blackn processor is programmed at the desired
frequency and connected to the "Conversion Start" pin of the A/D converter. The data output pin is connected
on the primary side of SPORT1 (DR1PRI). The serial data clock is generated by the A/D converter and
connected to the RSCLK1 pin of the Blackn. The frame synchronization clock is also generated by the
converter and connected to the RFS1 pin.
To limit the number of supplies, the 2.5 V reference was done with a voltage divider (two 4kΩ resistors) and
an operational amplier.
The input signal is ltered with a highpass lter to remove any DC-component and shifted with a voltage
divider to have a mean value of 2.5 V. A high speed operational amplier (AD8021) protects the input of the
A/D converter by limiting the input voltage within the range 0-5V. Only the input A is used here, the other
4
1.1. HARDWARE COMPONENTS
Figure 1.1: Serial port signals (from Hardware Reference Manual, chapter 12 [3])
inputs are reserved for future improvements and connected to ground. Therefore, the transmitted data word
will be a 32 bit word beginning with 16 zeros (the input B data) and nishing with the 16 bits of input A.
See Figure 1.2 for the complete connection diagram and the AD7655 data sheet [1] for more explanations
about the connection of the converter. Photos of the complete prototype are shown in Figures 1.3 and 1.4.
1.1.6 Audio codec AD1836

The audio codec AD1836 is the audio codec embedded on the EZ-KIT Lite development board. It works at
a sampling frequency of 48 kHz or 96 kHz and can deal with four input and six output channels.
This codec is connected to the Blackn processor by two means:
• the SPI port to send conguration values to the codec
• the SPORT0 port to send and receive data
5
Figure 1.2: Connection diagram of the A/D converter
6
Figure 1.3: AD converter and its external connection
7
Figure 1.4: Complete prototype
8
1.2. SOFTWARE PART
1.2 Software part

Once the A/D converter and the serial port of the Blackn connected to each other, the latter must be
activated and congured with a software. Moreover, data from the serial port are stored in the memory using
Direct Memory Access (DMA) to relieve the processor and DMA must be activated and congured too. The
second part of the software deals with the processing of the data.
1.2.1 Data transfer

Principle
Each bit of data from the A/D converter is stored in a shift register (RX1 shift primary register for the
primary side of the receive part of the serial port 1). Once the 32 bit are stored, the whole word in sent to the
register RX HOLD which puts it into the RX register, a 16 bit FIFO register (each 32 bit word is divided in
two parts). This FIFO register is connected to a data bus that allows DMA transfers. After the completion of
the DMA transfer, an interrupt is generated and the data are processed (see Figure 1.5). The interrupt could
have been generated by the serial port after the input of every word in the FIFO register, but this gives less
exibility by dealing with only one word transfers and using the Peripheral Access Bus driven by the core.
Figure 1.5: Principle of data transmission
SPORT conguration
The receive conguration of the serial port 1 of the Blackn is set by two 32-bit registers: SPORT1_RCR1
and SPORT1_RCR2. The following conguration has been chosen to match the conguration of the A/D
9
converter and the format of its output data:
External CLK The data clock is produced by the A/D converter and is external from the point of view of
the Blackn (corresponding to EXT/INT=LOW on the converter).
External Frame sync The synchronization signal is produced by the A/D converter.
Active Low RFS The synchronization signal is active when its value is low (INVSYNC=HIGH on the con-
verter).
Late frame syncs The rst bit of the receive data word is sampled in the same serial clock cycle that the
frame sync is asserted.
Receive Frame Sync Required A frame sync signal is needed before each data word (not before the rst
data word only). This gives better control on the data in case of a missing bit.
Sampling edge for data and frame syncs Sample data and external frame sync with rising edge of RSCLK.
MSB rst The most signicant bit is sent rst, the least signicant is sent last.
32-bit data The data word contains the 16 bits of the signal B of the converter followed by the 16 bits of the
signal A.
Secondary side disabled Only one data channel is needed here.

Stereo frame sync disabled This is used for stereo audio codec and changes the frame synchronization signal
into a left/right signal.
Refer to chapter 12 of Hardware Reference Manual [3] for a complete description of the conguration of the
serial ports.
The serial port SPORT0 used by the audio codec uses primary and secondary sides, 24-bit words and stereo
frame syncs.
DMA conguration
To use DMA transfers for reception, several parameters must be set:
DMA link The DMA peripheral map must be congured to link one DMA channel to SPORT1. Here, the
DMA3 channel is used.
Start address This gives the address in the memory where data will be stored. This address is not set directly:
a table with the right size just needs to be allocated at the beginning of the software and the register
DMA3_START_ADDR points to this table.
Inner loop count This species the number of data to read in. In autobuer mode, when the DMA counter
exceeds this number, the Current Address Register" of the DMA points to the start address again. Here,
only one word is transferred, the value of DMA3_X_COUNT is 1.
Inner loop address increment This increment is the stride that is applied to the Current Address Reg-
ister after transferring each element. SPORT1 transfers 32-bit words, hence the value of the register
DMA3_X_MODIFY is 4 (4 bytes).
Autobuer mode DMA is performed in a continuous way. After the completion of a DMA transfer, all
parameters are reloaded and a new transfer begins.
DMA direction Set to "Write" to specify that this transfer is a write operation.
Transfer word size 32 bits
Data interrupt Set to on to allow completion of work unit to generate a data interrupt.
Refer to chapter 9 of Hardware Reference Manual [3] for a complete description of DMA conguration on
the Blackn.
10
1.2. SOFTWARE PART
Clocks
Core and system clocks The default values of the core clock and system clock are respectively 270 MHz
and 54 MHz. These values, common for applications with low power consumption, are unfortunately too low
to perform signal processing at high rate and thus have to be raised up to their maximum: 600 MHz for the
core clock (limited by the Blackn) and 133 MHz (limited by the SD RAM ). These two clocks are generated
with frequency multipliers and dividers (see Figure 1.6) from a crystal at 27 MHz (an internal oscillator circuit
creates the input clock at 27 MHz). This input frequency can be divided by 2 according to the value of the
variable DF (0 or 1) and is then multiplied by MSEL (1 ≤ MSEL ≤ 64), using an on-chip PLL. This VCO
frequency is afterwards divided by the value of CSEL (1, 2, 4 or 8) to generate the core clock CCLK, and by
the value of SSEL (1 ≤ SSEL ≤ 15) to generate the system clock SCLK. The values of MSEL, CSEL and SSEL
are modied in the registers PLL_DIV and PLL_CTL.
Figure 1.6: Generation of core and system clocks (from Hardware Reference Manual, chapter 8 [3])
Clocks for components using serial ports The A/D converter and the audio codec are used as master
components: they produce their own serial clocks to transmit data on the serial ports of the Blackn. However,
the signal that allows the A/D converter to start a conversion must be external. To have control on the sampling
frequency of this converter, the convert signal is generated by a timer of the Blackn.
To congure this timer, several parameters must be set: its period (a multiple of the system clock period),
its width and its direction (output). The fact that the timer period is a multiple of the system clock adds some
constraints on the choice of the clock parameters, if a particular sampling frequency is sought. Refer to chapter
15 of Hardware Reference Manual [3] for explanations about the conguration of the timers.
All the clocks involved in the data transfer are plotted in Figure 1.7. The lower part refers to the A/D
converter and the upper part to the audio codec. The CONV signal is generated by the timer 1 of the Blackn,
the RSCLK, RDATA and RSYNC by the A/D converter and the TDATA, TSYNC and TSCLK by the audio
codec. The signal that clocks the audio codec is an external oscillator at 12.288 MHz.
1.2.2 Data processing

Principle
What the software does is summarized in Figure 1.8. For AM demodulation, the phase extraction followed
by a derivative is replaced by the extraction of the modulus of the signal. See section B in the Appendix for
theoretical explanations.
11
Figure 1.7: Clock and data signals
Figure 1.8: Principle of demodulation (FM)
Choosing clocks and data format

To simplify the design of the software, an external generator is used to produce a modulated signal with a
carrier frequency of 80 kHz.
The core clocks and system clocks are set to 567 MHz and 113.4 MHz respectively, by choosing DF=0,
MSEL=21, CSEL=1 and SSEL=5. The corresponding conguration register values are 0x0005 for PLL_DIV
and 0x2a00 for PLL_CTL.
The sampling frequency is set to 360 kHz (0x0000013b in TIMER1_PERIOD).
The Blackn is specically designed to deal with xed point numbers: it supports 8-, 16-, 32-, and 40-bit
xed-point data in hardware. Floating point numbers are available but the support of these ones is done in
software and is therefore slower. Moreover, the native formats for the Blackn processor family are a signed
fractional 1.M format and an unsigned fractional 0.N format, where N is the number of bits in the data word
and M = N − 1: a lot of built-in functions are already done to deal with data in these formats at high speed
9
(up to 1.2 10 multiply and accumulate (MAC) operations per second on 16 bit fractional numbers).
Since the data from A/D converter gives a 32-bit word formed with two 16-bit signals, the fract16 format
is used (1 sign bit and 15 data bits in 2-complement). The only operation to perform on input data is to take
the last 16 bits and subtract 0x7f (0.5 in unsigned format) to have a signed value. Note that it is compulsory
to have signed values to use the built-in lter functions (see section 1.2.2).
12
1.2. SOFTWARE PART
Mixing the input signal

The rst step of the demodulation is to multiply the input signal with e−j2πfc t , with t = k/fs the sampled
time. To avoid the use of trigonometric functions (a lot of calculations), a table with all the needed data is
fc
used. The factor e−j2π fs k is indeed periodic with a period T = fs .lcm(1/fc , 1/fs ) ( T = 9 for fs = 360 kHz
−j2π ffsc k
and fc = 80 kHz). Therefore only the 9 rst values of the factor e are computed with Matlab, rounded
to 16 bit precision and stored in a text le which is loaded by the software.
To store the result of this multiplication, the structure complex_fract16, formed with two fract16 numbers,
is used. This structure has built-in functions to execute every operation on complex numbers.
Designing lters
The output of the mixer passes through a lowpass lter to extract only the low frequencies and remove
the image frequencies. To keep the same time delay for all frequencies a linear phase lter is necessary (see
section B.3.4). Therefore, a FIR lter is used.
With Matlab, a FIR lter with 64 coecients and a cut-o frequency of 10kHz is built (see Figure 1.9).
Figure 1.9: Lowpass lter for the IQ signal
The coecients of the lter are then rounded to 16 bit precision are stored in a text le. The built-in
function cr_fr16 performs the ltering on a complex number.
Demodulation and audio ltering

The IQ signal is then demodulated. For a FM modulated signal, the product of the last sample and the
complex conjugate of its predecessor is computed, and the phase of this result is calculated (using atan2_fr16
function). For an AM modulated signal, the modulus of the IQ signal is computed. See appendix B for more
explanations about the demodulation of the signal.
The resulting signal is often noisy, and a lter is used to remove frequencies over 15kHz (see the lter in
Figure 1.10).
13
Figure 1.10: Lowpass lter for the audio signal
Moving data to the audio codec

The audio signal is then scaled on 24 bits, which is basically a shift of 8 bits on the left and stored into a
transmit variable that is read at a frequency of 48 kHz by the audio codec (using DMA transfer and SPORT0).
14
1.3. FIRST RESULTS
1.3 First results

Several steps were necessary to test components and build a working software.
1.3.1 Talkthrough test

A low frequency input signal is sampled by the A/D converter and observed at the audio output. The
purpose of this experiment is to test the communication between the A/D converter and the Blackn and is
very useful to congure the serial port, the DMA, the audio codec and the converter.
In Figure 1.11, the input signal seems deteriorated by the sampling (big peaks due to some oating wires in
the circuit) but the output signal is correct.
Figure 1.11: Talkthrough test
1.3.2 Demodulation test

A FM modulated signal is generated with Matlab and stored in a text le. The demodulation is performed
in parallel with Matlab and the DSP to test the operations of signal processing such as multiplications and
ltering. The intermediate and output signals are checked thanks to a feature of Visual DSP ++ that can plot
tables of values. A comparison between the Matlab simulation and the computation of the DSP is shown in
Figures 1.12, 1.13 and 1.14.
15
Figure 1.12: Output of the mixer before and after ltering (real part): Matlab (left) and DSP (right)
Figure 1.13: Output of the mixer before and after ltering (imaginary part): Matlab (left) and DSP (right)
Figure 1.14: Audio output of the mixer: Matlab (left) and DSP (right)
16
1.3. FIRST RESULTS
1.3.3 FM demodulation
This is a combination between the last two tests: a modulated signal with a carrier frequency of 80 kHz
is sampled at 360 kHz and demodulated. This signal has frequency bandwidth of 3 kHz and carries a 400 Hz
signal. To improve the results, the rst part of the input data words (normally sixteen bits at zero) is used
to remove a part of the noise of the input signal (the cyclic noise created by the AD converter is the same for
every sample and can be removed by subtraction).
The rst values of every signal are stored in memory for verication. See Figure 1.15, 1.16, 1.17, 1.18 and
1.19 for plots of all intermediate signals from the DSP.
The signal on the audio output is represented in Figures 1.20 (without ltering) and 1.21 (ltered).
Figure 1.15: I signals: real part of the output of the mixer before and after ltering
Figure 1.16: Q signals: imaginary part of the output of the mixer before and after ltering
17
Figure 1.17: IQ signals
Figure 1.18: Output signal
Figure 1.19: Filtered output signal
18
1.3. FIRST RESULTS
Figure 1.20: FM demodulation without ltering (fc =80 kHz, fs =360 kHz, f0 =500 Hz)
Figure 1.21: FM demodulation with ltering (fc =80 kHz, fs =360 kHz, f0 =500 Hz)
19
1.3.4 AM demodulation
From a FM radio, it is easy to build a AM radio: only the demodulation part is changed and replaced by a
calculation of the modulus of the IQ signal (see Figure 1.22).
Figure 1.22: AM demodulation with ltering (fc =80 kHz, fs =360 kHz, f0 =500 Hz)
20
Chapter 2
Dedicated board
2.1 Hardware components
This part deals with a description of the components chosen for the dedicated board.
2.1.1 Aim of this board and general layout

The next step of development is to build a dedicated board whose sole purpose is to receive a RF signal from
an antenna and demodulate it with a single circuit. Moreover, the EZ-KIT does not provide an easy access to
its parallel peripheral interface (used by the video circuit) that must be used to reach high working frequencies.
It will therefore be possible to use this communication port by building a dedicated board.
Figure 2.1: Components of the board
As shown on Figure 2.1, a tuner provides an IF signal with a carrier frequency of 10.7 MHz from a RF signal
with a carrier frequency around 100 MHz (FM). Several components are compulsory to build this radio receiver:
a tuner, a mixer (to work at a low carrier frequency), an AD converter to sample the modulated signal, a DSP
to demodulate the sampled signal and an audio DA converter to produce sound.
21
IF Digital Radio Based on Blackn Processor CHAPTER 2. DEDICATED BOARD
2.1.2 BF532
A Blackn BF532 is used for this board for convenience, since the BF533 is only available in a BGA package
(very dicult to solder and to debug). The main dierences between these two DSP are the maximum core clock
frequency (400 MHz instead of 600 MHz) and the amount of internal memory (32 kbytes less of instruction
SRAM and 32 kbytes less of data SRAM). However, the BF532 oers the same connectivity as the BF533
(same number of serial and parallel interfaces). Tests done on the demonstration board showed that this
memory capacity and this clock frequency were enough for a radio application.
2.1.3 AD converter
The AD converter used on this board is a ADS8402I [14] from Texas Instruments. This converter provides
a 16 bit parallel interface and a sampling frequency up to 1.25 MHz. Moreover, it accepts a dierential input
with an input voltage range between −Vref and Vref (Vref is an external voltage reference, here 2.7 V). This chip
is supplied with an analog voltage 5 V and a digital voltage 3.3 V. The sampling frequency is controlled by a
timer (Timer 0) of the DSP. In order to use only one timer, the Timer 0 pin of the DSP is connected to both the
conversion pin of the AD converter and the PPI_CLK pin of the DSP. At every falling edge of a clock signal,
a new conversion begins while the previous sample is read.
2.1.4 Dierential ADC Driver

Since the AD converter has a dierential input, an operational amplier with a dierential output is required
to create two signals S + and S − from the single-ended output S of the mixer (S + − S − = S ). The value of the
+ −
common mode voltage (S + S ) is xed by an external voltage (here 1.35 V) to meet the specications of the
AD converter. The component chosen for this task is an AD8138 from Analog Devices (see schematics 2.7 and
datasheet [2]).
2.1.5 Parallel port interface

The parallel port interface provided by the DSP is used to transfer data from the AD converter to the DSP.
The parallel interface uses at least two kinds of signals:
Data signals Up to 16 data signals are used to convey each data bit.
Clock signals This signal is a clock synchronized with all the data signals.
Frame synchronization signals These three signals can be used to distinguish dierent groups of data words
(these are often used to transfer video but are not needed here).
2.1.6 Tuner
The tuner (made by Siemens VDO) is a front-end converting a RF signal to an IF signal with a carrier
frequency of 10.4 MHz. This tuner is driven by an external oscillator of 100 kHz and the frequency selection is
2
commanded by the DSP or by an external command (with I C instructions).
2.1.7 Mixer
Due to hardware limitations, the IF signal can not be directly sampled and a frequency transposition of
the IF is required. The mixer is a RF2713 chip used to shift the spectrum of the IF to a carrier frequency of
300 kHz. This frequency is chosen to work at a sampling frequency of 1200 kHz. The output of the mixer is
not directly the baseband signal to avoid problems with DC components. The mixer is driven by an external
oscillator of frequency 20.8 MHz (twice 10.4 MHz) (see schematics 2.6 and datasheet of the RF2713[13]). The
output of the mixer has two frequency components: one useful component centered at 10.7 − 10.4 = 0.3 MHz
and one image component centered at 10.7 + 10.4 = 21.1 MHz . A lowpass lter is therefore necessary after the
mixer to keep only the low frequency.
22
2.1.8 Oscillators
The board needs three oscillator circuits:
• a 18 MHz circuit to drive the Blackn
• a 20.8 MHz circuit to drive the mixer
• a 100 kHz circuit to drive the tuner
These circuits use quartz crystals and logical gates (inverters, counters, etc) to create oscillations (the 18 MHz
oscillation circuit is embedded inside the DSP, only the quartz is external). Basically, an inverter is connected
in parallel with the quartz to create oscillations and a counter or a D ip-op is used to divide the frequency
to the desired value. See Figures 2.5 and 2.6 for complete electrical schematics.
2.1.9 Audio DAC

2
The audio DA converter TDA1387T accepts serial input data of 16-bit word length, using I S-bus data
format (time multiplex, two's complement). This chip has an internal PLL and needs no external clock to be
driven, only the data clock is required. This avoids the use of another oscillator circuit and allows the DSP to
control the sampling rate of the DAC. An external circuit with a voltage amplier is used to control the volume
of the radio (see schematics 2.8 and datasheet [12]).
2.1.10 External memories

In addition to the internal memory of the Blackn, external memory is required: the SD-RAM block will
store some data if needed and the Flash memory will store the instructions of the software when the DSP boots
from its internal memory.
SD-RAM
A 133 MHz 16 Mbytes SD-RAM can be used to store some data during the execution of the program. The
memory chosen is a Micron MT48LC8M16A2TG-75 IT with 4 banks, each containing 2 millions words of 16
bits (4096 rows by 512 columns). The SD-RAM is not currently used but is here in prevision of a future need.
Flash
To store the program instructions, a Flash memory is required. The memory used on this board is a Spansion
S29JL032H90. This memory has a storage capacity of 32 Mbits (2 M words of 16 Bits) organized in two banks
(one of 8 Mbits and one of 24 Mbits).
2.1.11 UART
To allow a connection between the DSP and an external device, a ICL3221CAZ chip is used to convert the
UART signals into RS-232 signals. The SUB-D9 connector can then be used to connect the board to the serial
port of a PC for example.
2.1.12 Power supply

To reduce the amount of time of development, an external power supply board is used. This board can
provide 8.5V (600mA), 5V (1.4A) and 3.3V (1A) power supplies from a 14V supply.
2.1.13 Electrical schemes
23
Figure 2.2: Electrical schematics: connection with the power supply board and the JTAG
24
Figure 2.3: Electrical schematics: DSP

25
Figure 2.4: Electrical schematics: SD-RAM and Flash

26
Figure 2.5: Electrical schematics: Tuner and its clock

27
Figure 2.6: Electrical schematics: Mixer and local oscillator

28
Figure 2.7: Electrical schematics: AD converter

29
Figure 2.8: Electrical schematics: DA converter, audio output and UART

30
Figure 2.9: Layout
31
Figure 2.10: Photo of the board
32
2.2. SOFTWARE PART
2.2 Software part

2.2.1 Data reception
Principle
The 16 output data bits of the AD converter are sent to the 16 inputs of the Parallel Peripheral Interface
(PPI) and directly transferred into the internal memory with a DMA transfer (see Figure 2.11). After the
transmission of 32 samples, the DMA controller generates an interruption and the data processing begins, while
the sampling goes on.
Figure 2.11: Principle of data transmission
PPI conguration
Several options are available to congure the PPI with the PPI_CONTROL register.
Sampling edge The PPI samples data on falling edge of PPI_CLK.
Data length: 16 bits The PPI reads 16-bit words. This congures the accurate number of "Programmable
Flags" pins as PPI data pins.
Skip data This allows to skip a part of transmitted data (often one of two samples) when using frame syncs
(not used here)
Receive mode The PPI can be either in Receive mode or in Transmit mode.
Port conguration 0 frame syncs is used (up to 3 are available)
33
Internal trigger To initiate the transmission of data, an internal or external trigger can be used. An internal
trigger is generated by the software and an external one by a single pulse on the 1st frame syncs pin
(PPI_FS1).
DMA transfer
The DMA transfers regarding the PPI are descriptor based and not register based as on the development
board. A descriptor is simply a variable that contains the address of a register where to write data in and the
address of the following descriptor to read. This allows the processing of an array while a DMA transfer into
another one.
DMA link The DMA peripheral map must be congured to link one DMA channel to the PPI. Here, the
DMA channel 0 is used.
Next descriptor This gives the address of the next descriptor to use. This descriptor contains the address in
the memory where data will be stored. Two descriptors are used to write into two dierent arrays and
these descriptors points to each other as well to in
Inner loop count Thirty-two words are transferred, so the value of DMA0_X_COUNT is 32.
Inner loop address increment This increment is the stride that is applied to the Current Address Reg-
ister after transferring each element. The PPI transfers 16-bit words, hence the value of the register
DMA0_X_MODIFY is 2 (2 bytes).
Descriptor list mode DMA is performed in a continuous way as long as a currently used descriptor points
to another one. After the completion of a DMA transfer, the next descriptor is loaded and a new transfer
begins.
DMA direction Set to "Write" to specify that this transfer is a write operation.
Clocks
Core and system clocks From a 18 MHz clock (produced by an external quartz), a 396 MHz core clock and a
132 MHz system clock are produced by choosing DF=0, MSEL=22, CSEL=0 and SSEL=3. The corresponding
conguration register values are 0x0003 for PLL_DIV and 0x2c00 for PLL_CTL (see section 1.2.1 for more
explanations) .
Clocks for the AD converter To set the sampling frequency of the AD converter to 1.2 MHz, the DSP
generates the convert signal with one of its timer (Timer 0). The period of this timer is 110 times the period
of the system frequency, thus the register TIMER0_PERIOD is set to 0x0000006e. In order to save one timer,
the convert signal is the same as the read signal: when the timer signal is low, the sampling of the input signal
begins while the previous sample is transferred to the DSP.
The external quartz (18 MHz) that drives the DSP is chosen especially to be able to generate a sampling
frequency of 1.2 MHz with core and system clocks close to their maximum. This sampling frequency makes the
computation easier, for the mixing to obtain the I and Q signals consists only of multiplications by 1, i, −1 and
−i.
Clocks for the audio DA converter The DA converter has an integrated PLL and needs no external clock
to be driven. The serial data clock and the frame synchronization clock are generated by the DSP by conguring
internal registers. To choose the sampling period (or frame synchronization period) and the serial data clock,
34
2.2. SOFTWARE PART
the adequate values of the register TCLK_DIV and TFS_DIV must be set according to the following formula
(valid in stereo mode):
TSCLK0 frequency
SPORT0TFS frequency =
2(SPORT0_TFSDIV + 1)
System CLK frequency
SPORT0TSCLK frequency =
2(SPORT0_TCLKDIV + 1)
Here, the sampling frequency is 37.5 kHz, the System clock frequency 396 MHz and 20 data clock cycles are
required to transmit one sample for each audio channel, hence a data clock frequency of 2 × 20 × fs = 1500 kHz.
Thus it is obtained: TCLK_DIV = 40 = 0x0000002b and TFS_DIV = 19 = 0x00000013.
2.2.2 Signal processing

After the reception of 32 samples, the signal processing begins. It consists on a succession of lters and
mathematical operations.
Bandpass ltering
First, the 32 samples are ltered through a 63th order bandpass FIR lter to remove all components of the
signal outside the frequency range 150 kHz - 450kHz (see Figure 2.12).
Figure 2.12: Bandpass lter
Mixing and lowpass ltering

The I and Q components of the signal are then obtained by multiplying by cos(2π × 300.103 × t) and
3
sin(−2π × 300.10 × t) and by ltering to remove frequencies over 150 kHz. The signal is in fact multiplied by
the 32 values of an array containing a sequence of 0's, 1's and -1's and the ltering is performed with a 63th
order lowpass FIR lter to keep the same delay between I and Q (see appendix B for further explanations).
35
Demodulation
Since the sampling frequency of the audio output is 37.5 kHz, only one audio sample out of the 32 input
samples needs to be demodulated. The rst two values of the I and Q signals are used to calculate the phase
dierence between the two rst values of the complex signal (I+jQ).
Audio ltering
The nal step in the data processing is the audio ltering. Two goals are aimed: rst deemphasize the high
frequencies, and then remove the noise.
The deemphasis lter is a 2nd order IIR lowpass lter used to retrieve the original audio signal: in an FM
system the higher frequencies contribute more to the noise than the lower frequencies. Therefore, FM radios use
preemphasis (a highpass lter) before the modulation. After the demodulation, the opposite operation must be
done (see Figure 2.13 ).
Figure 2.13: Deemphasis lter
The second lter is a FIR lowpass lter that removes all frequencies over 15 kHz.The bandwidth of the lter
is tweaked to achieve the best hearing.
2.2.3 Data transmission

Principle
The audio signal is sent to the DA converter using the the serial port 0 of the DSP and a DMA. The clocks
required for the transfer are generated by the DSP (cf section 2.2.1).
SPORT conguration
2
The DA converter accepts only I S data. The serial port must therefore be congured to send clock and
2 2
data signals according to the I S specication (cf. Figure 2.14). The particularity of the I S format is that
36
2.2. SOFTWARE PART
frame syncs are held constant to indicate which audio signal is sent (left or right) and that data are driven with
the rising edges of the serial clock whereas frames syncs are driven with the falling edges of the serial clock.
2
Figure 2.14: I S format
2
The conguration to meet the I S specications is the following:
Internal CLK The data clock is produced by the DSP.

Internal frame sync The synchronization signal is produced by the DSP.
Early frame syncs The rst bit of the receive data word is sampled one serial clock cycle after the frame sync
is asserted.
Transmit Frame Sync Required A frame sync signal is needed before each data word (not before the rst
data word only). This gives better control on the data in case of a missing bit.
Driving edge for data and frame syncs Drive data and internal frame sync with falling edge of TSCLK.
2
(This is a trade o between the I S format and what the Blackn can do with an internal frame syncs)
MSB rst The most signicant bit is sent rst, the least signicant is sent last.
Data length The sound is encoded with 16 bits.
Secondary side disabled Only one data channel is needed here.
Stereo frame sync enabled This is used for stereo audio codec and changes the frame synchronization signal
into a left/right signal.
Left / Right order The left stereo channel is sent rst.

Active High TFS The synchronization signal is active when its value is high. In a stereo mode, it indicates
when the right channel is active.
DMA conguration
The DMA transfer is register based and generates an interruption after each transfer to load the audio signal
into the source register.
DMA link The DMA peripheral map must be congured to link one DMA channel to SPORT0. Here, the
DMA2 channel is used.
Start address Address in the memory where data will be read: an array of two 16-bit words is created and
the register DMA2_START_ADDR points to this table.
Inner loop count Two words are transferred, the value of DMA2_X_COUNT is 2.
Inner loop address increment SPORT0 transfers 16-bit words, hence the value of the register DMA2_X_MODIFY
is 2 (2 bytes).
Autobuer mode DMA is performed in a continuous way. After the completion of a DMA transfer, all
parameters are reloaded and a new transfer begins.
DMA direction Set to "Read" to specify that this transfer is a read operation.
37

38
2.3. RADIO MEASUREMENTS
2.3 Radio measurements

This section deals with measurements of the performance of the radio in comparison with a standard radio
receiver.
2.3.1 SNR and THD

The signal-to-noise ratio (SNR) and total harmonic distortion (THD) are measured, for dierent levels of
RF signals (see Figure 2.15). First, a 1 kHz sine wave signal is modulated with a carrier frequency of 98 MHz
and sent into the antenna input at dierent frequency levels (from 0.1 µV to 1 V). The audio output level
is then measured. After this rst measurement, the modulation is switched o and the noise is measured for
dierent input levels. A at lter with a bandwidth between 20 Hz and 20 kHz is applied to the noise to keep
only the "hearable" noise. In Figure 2.15, we see that the demodulation works only for an input signal over
20 µV (this is due to a lack of sensibility). Over a level of 100 µV, the SNR is around 25 dB, whereas the SNR
for a common radio receiver is around 65 dB (see Figure 2.16).
Figure 2.15: Signal, noise and THD for dierent RF levels
The THD is measured by applying a narrow 1 kHz notch lter to remove the sound wave and by measuring
the other unwanted signal components. The THD is the ratio between these components and the expected
audio signal and is expressed in percent. Note that the noise is also measured with this experiment, so it is
often referred as "THD + noise" measurement. When the THD is below 5%, the distortion is not heard. Here
the THD is around 3.5%. A THD of 1% is commonly sought.
39
Figure 2.16: Signal, noise and THD of a reference radio receiver
2.3.2 Frequency response

An audio signal with a frequency from 20 Hz to 20 kHz is modulated with an input RF signal level of 250 µV.
A preemphasis lter is also applied on the audio signal. The frequency response is observed on Figure 2.17.
It can be seen that the frequency response is globally at (the deemphasis lter compensates the preemphasis
well).
2.4 Source of problems

The poor performance come from the link from the output of the tuner to the input of the DSP: the mixer
and its clock, the AD converter and its dierential amplier.
2.4.1 Clock alignment

First, the clock of the mixer is not aligned to the IF frequency: the tuner provides a modulated signal with
a carrier frequency of 10.7 MHz ± 30 ppm (related with the precision of the 4 MHz quartz). The 41.6 MHz
clock of the mixer has also a precision of 30 ppm (the frequency oset is around 1 kHz). It is therefore dicult
to obtain precisely a carrier frequency of 300 kHz at the output of the mixer. This frequency dierence triggers
an audio output with a not null mean value (constant is the 41.6 MHz clock is xed, or varying if the frequency
of this clock is not stable).
40
2.4. SOURCE OF PROBLEMS
Figure 2.17: Audio frequency response (fc = 98 MHz, RF level = 250 µV)
2.4.2 Clock shape

The D ip-op before the mixer produces a high overshoot when switching state that needs to be ltered.
The shape of the LO signal is therefore changed, and rising and falling edges are not perfectly clean (see
gure 2.18). The mixer can therefore consider that there is a clock signal when there is only an overshoot.
2.4.3 Range and saturation of components

Another source of loss of performance is saturation of the ICs.
First, the mixer current output can saturate: this can happen on several chips and not on others. This is
due to defects in several chips (perhaps because of a high stress on previous tests).
Moreover, the operational amplier that drives the AD converter is supplied by a single 5 V voltage and
is quite dicult to congure: if too much gain is used, the output saturates and if too low gain is used, the
number of eective bits used by the AD converter is low and the SNR increases. What is complicated here is
that the input RF signal goes from 1 µV to 10 mV in common situations.
In the software demodulation chain, if the clock of the mixer is not aligned with the clock of the tuner, the
value of the audio signal is expected to be not zero. If this mean value is too high, the output (calculated with
xed point numbers can saturate). However, this has never been experienced during the tests.
41
Figure 2.18: Output of the D ip-op before and after ltering
2.5 Possible improvements

2.5.1 Hardware improvements
A lot of improvements can be done on the clocks of the mixer: a suitable D ip-op (i.e. fast and not
producing overshoots) will make the clock edges cleaner. And a PLL or a software controlled local oscillator
can help to align clocks and reduce the THD. Moreover, the clocks of mixers in radio receivers are normally
regulated dynamically by measuring the DC output of the audio signal: this mean value corresponds to the
frequency dierence and is stored in a register read by the (hardware) clock to change its frequency. Another
solution is to work on the software clock (300 kHz) used for the mixing inside the DSP, by using look up tables
to generate dynamically the clock. But this will use much more ressources.
To use always most of the range of the AD converter, the gain controller can be used. It is possible, by
2
sending I C intructions to the tuner, to change its output gain (of IF signal). By measuring the input level of
the sampled signal, it would be possible to use this feature. This would prevent the AD converter from saturing
and allow him to use its full range. The SNR would then increase.
The driver of the AD converter is used to amplify the analog signal and create a dierential input. Since
it gives a lot of problems of conguration (choice of polarization, of resistances), another solution to create a
dierential input could be investigated, such as a transformer.
Finally, it should be noted that some chips can also replace the mixer, the AD convertera nd the driver of
the AD converter and provide a sampled signal (modulated with a carrier frequency of 300 kHz) from the IF
signal. This solution often used in commercial car radio receivers.
With these improvements, other features can be designed more easily: with reduced noise and distortion, it
would be possible to extract the stereo pilot to obtain the two stereo channels, and to extract the RDS signal.
2.5.2 Software improvements

The DSP uses only one third of its computation capability. This gives space for future improvements:
stereo decoding, dynamic lters to have a better selectivity, RDS... Moreover, 63
rd order lters are used for
convenience: similar results can be obtained with lower order lters. Besides, some calculations do not need to
be done at a frequency of 1200 kHz: after the mixing, a decimation can be performed to work at a frequency of
600 kHz (or lower). Finally, there is still the possibility to write the critical code in assembler.
42
2.5. POSSIBLE IMPROVEMENTS
Conclusion
This project has shown the capability of the Blackn DSP to work in a radio environment. The rst
prototype built from a development board was designed rapidly and gave encouraging results that allowed the
design of a complete board. This gave also useful information of how much computation was required, how to
link the peripherals to the DSP and which Blackn to use.
The second prototype was a complete board built "from scratch", using an external power supply and a
tuner. This board fullled the minimal r equirements, since it is possible to listen to close FM radio emitters by
simply plugging an external antenna. However, the quality of the receiver is far from a commercial one, but the
main problems have been localized and the hardware parts to improve identied. For future developments, the
choice of the mixer and the components producing the clocks has to be carefully made, since it is critical for the
overall radio. Software alignment of the clock of the mixer is also compulsory. Moreover, software improvements
and developments of other features are realizable: only one third of the ressource of DSP were used and the
source code occupied less than 25 kbytes in the DSP memory. It is therefore possible to use a Blackn as a
basis of a complete radio module.
Regarding an automotive application, other studies are required: several parameters like thermic and mag-
netic dissipations were not taken into account and are critical for an automotive application. Moreover, the
ability to interface the Blackn with other audio sources such as a CD was not tested. There are therefore still
a lot of developments to do to build a fully functional platform.
43
44
Appendix A
Source code
Pe
A.1 Main
1 / ∗ Purpose : Read in continous streams of data from the ADC. The data is read into a
memory buffer ( " sPPI_RxBuffer (1 −2) " ) via the PPI interface of the −
ADSP BF532 . A
3 double buffering scheme is implemented so that data in one half is available for
processing while the other half is being filled with new data via DMA operations .
5 A flag ( " Ping_Pong " ) indicates which half is ready for processing .
∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗/
7
9
#include " radioBF .h"
11
// Declare Exception Handler
13 EX_EXCEPTION_HANDLER( e x _ h a n d l e r ) ;
15
fract16
// Declare t h e DMA i n p u t buffer ///////////////////////////////
17
fract16
s P P I _ R x B u f f e r 1 [ Number_of_Samples ] ;
s P P I _ R x B u f f e r 2 [ Number_of_Samples ] ;
19
fract16
/ / Output buffer ///////////////////////////////////////////////
21
fract16
TxBuffer [ 2 ] ;
fract16
AudioLeft ;
23 AudioRight ;
25 // set up DMA descriptors ( sequence = 1 st half , then second half , then repeat )
tDMA_descriptor
// small descriptor model , only start address needs to be fetched
27
tDMA_descriptor
DMA_RX_second ; // declaration
tDMA_descriptor
DMA_RX_first = {&DMA_RX_second , sPPI_RxBuffer1 } ;
29 DMA_RX_second = {&DMA_RX_first , sPPI_RxBuffer2 } ;
31 // flag to indicate which buffer can be worked on by the user
short
// i . e . points to the half that DMA is NOT using
33 Ping_Pong = 0; // 1 = sPPI_RxBuffer1 0 = sPPI_RxBuffer2
35
37
// T r i g o tables for demodulation //////////////////////////////
45
IF Digital Radio Based on Blackn Processor APPENDIX A. SOURCE CODE
39 fract16
#include
cosinus [ ] = {
" cosinus . in "

41 };
43 fract16
#include
sinus [ ] = {
" sinus . in "

45
fract16
};
fract16
cosinus_modif [ 3 2 ] ;
47
char
sinus_modif [ 3 2 ] ;
sinus_size ;
49
51 // / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / /
// F i l t e r s
53
/ ∗
55 complex_fract16 coeffs_lowpass []={
#i n c l u d e " coeffs_cplx_lowpass . in "
57 }; ∗/
// c o m p l e x _ f r a c t 1 6 fir_delayc [ 6 4 ] ;
59 // c f i r _ s t a t e _ f r 1 6 fir_structur_lowpass ;
61
fract16
// Bandpass ( 3 0 0 kHz )
#include " coeffs_bandpass3 . in "

coeffs_bandpass []={
63
fract16
};
65
fir_state_fr16
fir_delay_bandpass [ 6 4 ] ;
fir_structur_bandpass ;
67
fract16
// Lowpass
69
#include " coeffs_lowpass . in "
coeffs_lowpass_reI []={
71
fract16
};
#include " coeffs_lowpass . in "

coeffs_lowpass_reQ []={
73
fract16
};
75
fract16
fir_delay_I [ 6 4 ] ;
short
fir_delay_Q [ 6 4 ] ;
77
fir_state_fr16
coeff_size ;
fir_state_fr16
fir_structur_lowpass_I ;
79 fir_structur_lowpass_Q ;
81
fract16
// Audio FIR
#include " coeffs_audio . in "

coeffs_audio []={
83
short
};
85
fract16
coeff_size_audio ;
fir_state_fr16
fir_delay [ 6 4 ] ;
87 fir_structur_audio ;
89
iirdf1_state_fr16
// Audio IIR
#define
iir_structur_audio ;
91 NSTAGES 1
const float
// Deemphasis
93 ∗
const float
b_coeffs [ ( 2 NSTAGES) + 1] = {0.3064933 , 0.3064933 , 0};
∗ −0.091342 , −0.295471};
fract16
a_coeffs [(2 NSTAGES) ] = {
95 ∗
fract16
df1_coeffs [(4 NSTAGES) + 2];
delay_iir [(4 ∗ NSTAGES) + 2];
97
46
A.1. MAIN
/ ∗
99 const float a_coeffs [(2 ∗ NSTAGES) ] = {
#i n c l u d e " c o e f f s _ i i r _ a . dat "
101 };
const float b_coeffs [ ( 2 ∗ NSTAGES) + 1] = {
103 #i n c l u d e " c o e f f s _ i i r _ b . dat "
}; ∗/
105 // / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / /
int
// C o u n t e r s
107
int
counter_sample ; / / To plot data ( input / output )
counter_in , counter_out ; // Incremented after each interruption ( used to see if
109 // some data are lost )
111 // f r a c t 1 6 signal_out_plot [ 5 4 5 ] ;
113 void main ( ) {
115 s y s r e g _ w r i t e ( reg_SYSCFG , 0 x32 ) ; // I n i t i a l i z e System Configuration Register
117 Init_PLL ( ) ; // C l o c k Setup
119 r e g i s t e r _ h a n d l e r ( i k _ e x c e p t i o n , e x _ h a n d l e r ) ; // init exception handler
/ / InitSDRAM ( ) ;
121
// Reset t h e DMA s e m a p h o r e s
123
sizeof
Ping_Pong = 0;
sizeof
c o e f f _ s i z e= ( coeffs_lowpass_reI ) /2;
125 c o e f f _ s i z e _ a u d i o= ( coeffs_audio ) /2;
127 // IF filter initialization
f i r _ i n i t ( fir_structur_lowpass_I , coeffs_lowpass_reI , fir_delay_I , coeff_size , 1 ) ;
129 f i r _ i n i t ( fir_structur_lowpass_Q , coeffs_lowpass_reQ , fir_delay_Q , c o e f f _ s i z e , 1 ) ;
f i r _ i n i t ( fir_structur_bandpass , coeffs_bandpass , fir_delay_bandpass , c o e f f _ s i z e
,1) ;
131 // c f i r _ i n i t ( f i r _ s t r u c t u r _ l o w p a s s , coeffs_lowpass , fir_delayc , coeff_size ) ;
133 // Audio filter initialization
f i r _ i n i t ( fir_structur_audio , coeffs_audio , fir_delay , coeff_size_audio , 1 ) ;
135 iirdf1_init ( i i r _ s t r u c t u r _ a u d i o , d f 1 _ c o e f f s , d e l a y _ i i r , NSTAGES) ;
coeff_iirdf1_fr16 ( a _ c o e f f s , b _ c o e f f s , d f 1 _ c o e f f s , NSTAGES) ; / / c o e f f s in fract16
137
139 // Creation of mixing arrays of the same size as the input buffer ( to increase
sizeof
// performance and use hardware loops )
141
int
s i n u s _ s i z e= ( sinus ) /2;
for
k;
143 ( k = 0 ; k<Number_of_Samples ; k++){
c o s i n u s _ m o d i f [ k ]= c o s i n u s [ k % 4 ] ; // The Blackfin does not like divisions
145 s i n u s _ m o d i f [ k ]= s i n u s [ k % 4 ] ; // inside arrays
147
149 // initialize Hardware
InitPPI () ;
151 InitSport0 () ;
InitInterrupts () ;
153 EnablePortsDMA ( ) ;
Init_Timer ( ) ;
155 asm ( " nop ;" ) ;
47
157 // MAIN loop
// waits indefinetely for interrupts f r o m DMA
159 // When an interrupt has occured , the flag PingPong indicates which half of the
while
// received data the main loop can process
161 (1) {
163 }
165 } // main
167
169
171 // Exception handler
// do nothing , just stall
173 EX_EXCEPTION_HANDLER( e x _ h a n d l e r )
while
{
175 (1) ;
A.2 Initialization
A.2.1 Clocks
1 /∗ PLL S e t u p . c : c o n f i g u r e s t h e i n t e r n a l PLL o f t h e BF532 t o s e t t h e c l o c k s
∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗/
3
5 #include " radioBF .h"
7 void Init_PLL ( void )
9 s y s r e g _ w r i t e ( reg_SYSCFG , 0 x32 ) ; // I n i t i a l i z e System Configuration Register
// 396 MHz, 132 MHz
11 ∗pSIC_IWR = 0 x1 ; / /Wake up only by PLL
∗pPLL_DIV = 0 x0003 ;
13 ∗pPLL_CTL = 0 x2c00 ;
ssync () ;
15 idle () ;
17
} // end Init_PLL
A.2.2 Communication ports

/ ∗ Init PPI . c : − c o n f i g u r e s t h e PPI and t h e SPORT0
2 − c o n f i g u r e s t h e DMA t r a n s f e r s
− c o n f i g u r e TIMER0 ( s a m p l e c l o c k )
4 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗/
6 #include " radioBF .h"
8 void InitPPI ( void )
10 / /GP mode , RX mode , 0 frame syncs , internal trigger , sample on falling edge
∗pPPI_CONTROL = 0 x787c ;
12 ∗pPPI_DELAY = 0 x0000 ; // not used
48
A.2. INITIALIZATION
∗pPPI_COUNT = 0 x0000 ; // not used
14
// Map DMA0 to PPI
16 ∗pDMA0_PERIPHERAL_MAP = 0 x0000 ;
// configure PPI DMA (DMA 0 ) Using Descriptors
18 ∗pDMA0_CONFIG = FLOW | 0 x0400 | DI_EN | WDSIZE_16 | WNR; / / disable DMA transfer
and enable large descriptor mode 1d mode ( word size = 16 b i t )
// Address of next descriptor
20 ∗pDMA0_NEXT_DESC_PTR = (&DMA_RX_first ) ;
// Inner loop address increment
22 ∗pDMA0_X_MODIFY = 2;
/ / DMA inner loop count
24 ∗pDMA0_X_COUNT = Number_of_Samples ;
26
void InitSport0 ( void )
28 {
// Sport0 transmit configuration
30 // External CLK, External Frame sync , MSB first , Active Low
// 16 −bit data , Secondary side enable , Stereo frame sync enable
32 ∗pSPORT0_TCR1 = TFSR | TCKFE | ITFS | ITCLK ;

∗pSPORT0_TCR2 = SLEN_16 | TSFSE ;
34 ∗pSPORT0_TCLKDIV= 0 x 0 0 0 0 0 0 2 b ; / / f o r Fs = 3 7 . 5 kHz
∗pSPORT0_TFSDIV= 0 x 0 0 0 0 0 0 1 3 ; / / 2 0 b i t s p e r s i d e
36
// Set up DMA2 to transmit
38 // Map DMA2 to Sport0 TX
∗pDMA2_PERIPHERAL_MAP = 0 x2000 ;
40
// Configure DMA2 Using register
42 // 32 −bit transfers , Autobuffer mode
∗pDMA2_CONFIG = WDSIZE_16 | FLOW_1 | DI_EN ;
44 // Start address of data buffer
∗pDMA2_START_ADDR = TxBuffer ;
46 / / DMA inner loop count
∗pDMA2_X_COUNT = 2;
48 // Inner loop address increment
∗pDMA2_X_MODIFY = 2;
50 }
52
void EnablePortsDMA ( void )
54 {
∗pDMA0_CONFIG = ∗pDMA0_CONFIG | DMAEN; // enable DMA0 ( PPI not enabled yet )
56 asm ( " ssync ;" ) ;

∗pDMA2_CONFIG = ∗pDMA2_CONFIG | DMAEN; // enable DMA2 (SPORT0 not enabled yet )
58 asm ( " ssync ;" ) ;
60 ∗pSPORT0_TCR1 |= TSPEN ; // enable SPORT0
asm ( " ssync ;" ) ;

62 ∗pPPI_CONTROL |= PORT_EN; // enable PPI
asm ( " ssync ;" ) ;
64 }
66 void Init_Timer ( void )
{ / / The timer drives the sampling period of the ADC and the reading of data
68 / / Timer Configuration Registers p.685
/ /PWM_OUT mode , count to end of period
70 ∗pTIMER0_CONFIG = PWM_OUT | PERIOD_CNT ;
49
∗pTIMER0_PERIOD = 0 x0000006e ; / / 1 2 0 0 kHz
72 ∗pTIMER0_WIDTH = 0 x00000020 ; // 80 ns > 20 ns ( 0 x08 )
∗pTIMER_ENABLE = TIMEN0 ; // Enable Timer 0
74 }
A.2.3 Header le

#ifndef
#define
__INCLUDE_DEFINED
2 __INCLUDE_DEFINED
4 #include
#include
<c d e f B F 5 3 2 . h>
#include
< s y s \ e x c e p t i o n . h>
6 " sysreg .h"

#include " ccblkfn .h"
8
#include
#include
< s t d i o . h>
10
#include
<math . h>
#include
<c o m p l e x . h>
12 < f r a c t . h>
14
#ifndef
#include
__FILTER_DEFINED
16
#endif
< f i l t e r . h>
18
/ ∗ ∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗
20 Symbolic constants
∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗/
22
#define
// ADC CONSTANTS
24
#define
Number_of_ADC_bits 16
#define
Number_of_Samples 32 // Block size of words / c h a n n e l to b e DMA ' d from ADC
26 Word_Size 16
28
#define
// SPORT0 word length
SLEN_16 0 x000f
30
#define
/ / DMA flow mode
32 FLOW_1 0 x1000
34 / ∗ ∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗
Prototypes
36 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗/
38 void void
void void
InitSDRAM ( ) ;
void void
InitFlash ( ) ;
40
void void
Init_PLL ( ) ;
void void
InitPPI ( ) ;
42
void void
InitSport0 ( ) ;
void void
InitInterrupts ( ) ;
44
void void
EnablePortsDMA ( ) ;
void void
Init_Timer ( ) ;
46
void void
Process_Data ( ) ;
Demodulation ( ) ;
48 EX_INTERRUPT_HANDLER( PPI_RX_Isr ) ;
EX_INTERRUPT_HANDLER( Sport0_TX_ISR ) ;
50
/ ∗ ∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗
52 Global variables
50
A.3. HANDLING OF INTERRUPTIONS
∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗/
54 extern fract16
extern fract16
sPPI_RxBuffer1 [ ] ;
extern fract16
sPPI_RxBuffer2 [ ] ;
56
extern fract16
TxBuffer [ 2 ] ;
extern fract16
AudioLeft ;
58 AudioRight ;
60 extern short Ping_Pong ;
62 extern fract16
extern short
input [ ] ;
input_size ;
64
struct
struct
sDMA_descriptor {
66 ∗
volatile short ∗
sDMA_descriptor next_descriptor ;
start_address ;
68
typedef struct tDMA_descriptor
};
sDMA_descriptor ;
70
extern tDMA_descriptor DMA_RX_first ;
72
extern fir_state_fr16
fir_structur_audio ;
74
fir_structur_lowpass_I ;
fir_structur_lowpass_Q ;
76
extern iirdf1_state_fr16
fir_structur_bandpass ;
iir_structur_audio ;
78
extern int
extern int
counter_sample ;
80
extern int
counter_in ;
counter_out ;
82
84 extern fract16
extern fract16
cosinus [ ] ;
fract16
sinus [ ] ;
86
fract16
cosinus_modif [ ] ;
extern char
sinus_modif [ ] ;
88 sinus_size ;
90
92
extern fract16
// P l o t s
extern fract16
signal_in1_plot [ ] ;
94
extern fract16
signal_lowpass_plot1 [ ] ;
extern fract16
signal_lowpass_plot2 [ ] ;
96
extern fract16
signal_bandpass_plot [ ] ;
extern fract16
signal_lowpass1filt_plot [ ] ;
98
extern fract16
signal_lowpass2filt_plot [ ] ;
extern fract16
signal_out_plot [ ] ;
100
extern fract16
signal_out_norm_plot [ ] ;
input_signal [ ] ;
102
104
#endif
A.3 Handling of interruptions
/∗ Init Interrupts . c : c o n f i g u r e s DMA i n t e r r u p t s and t h e i r routine
2 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗/
51
4
6
void InitInterrupts ( void )
8 { // configure interrupts
10 // assign PPI ISR to interrupt vector 8
r e g i s t e r _ h a n d l e r ( ik_ivg8 , PPI_RX_Isr ) ;
12 // assign SPORT0 ISR to interrupt vector 9 (NB : IV8 has priority on IV9 )
r e g i s t e r _ h a n d l e r ( ik_ivg9 , Sport0_TX_ISR ) ;
14 // assign event vectors 8 and 9 to t h e DMA interrupts
∗ pSIC_IAR0 = 0 x f f f f f f f f ;
16 ∗ pSIC_IAR1 = 0 xfffff2f1 ; // x x x sp1tx sp1rx sp0tx sp0rx ppi
∗ pSIC_IAR2 = 0 x f f f f f f f f ;
18 / / unmask DMA interrupts
∗pSIC_IMASK = 0 x00000500 ; // enable DMA0( PPI ) and DMA2(SPORT0) interrupts
20
}
22
24
EX_INTERRUPT_HANDLER( PPI_RX_Isr ) / / PPI DMA Interrupt Service Routine
26 {
Ping_Pong = ( Ping_Pong + 1 ) %2; // Toggle Flag
28 // confirm interrupt handling ( NO Error Handling is implemented ! )
∗pDMA0_IRQ_STATUS |= 0 x0001 ; // Write 1 to clear
30 asm ( " ssync ;" ) ;
32
/ / / / Code to store input s i g n a l ////////////////
34 / / i f ( Ping_Pong ) {
// A u d i o L e f t= sPPI_RxBuffer1 [ 0 ] ;
36 / ∗ if ( c o u n t e r _ s a m p l e <94) {
f o r ( i = 0 ; i <Number_of_Samples ; i ++){
38 input [ counter_sample ∗32+ i ]= s P P I _ R x B u f f e r 1 [ i ];
40 c o u n t e r _ s a m p l e ++;
} ∗/
42 // }
// e l s e {
44 // A u d i o L e f t= sPPI_RxBuffer2 [ 0 ] ;
/ ∗ if ( c o u n t e r _ s a m p l e <94) {
46 f o r ( i = 0 ; i <Number_of_Samples ; i ++){
input [ counter_sample ∗32+ i ]= s P P I _ R x B u f f e r 2 [ i ];
48 }
c o u n t e r _ s a m p l e ++;
50 } ∗/
// }
52 / ∗ if ( c o u n t e r _ s a m p l e <3008) {
i n p u t [ c o u n t e r _ s a m p l e ]= A u d i o L e f t ;
54 c o u n t e r _ s a m p l e ++;
} ∗/
56 // / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / /
Process_Data ( ) ;
58 c o u n t e r _ i n ++; // c o u n t s the number of input blocks
60
EX_INTERRUPT_HANDLER( Sport0_TX_ISR ) / /SPORT0 DMA Interrupt Service Routine
62 {
52
A.4. DATA PROCESSING
// confirm interrupt handling
64 ∗pDMA2_IRQ_STATUS = 0 x0001 ;
66 // T e s t routine to force a sinusoid at output ///////
/ ∗ if ( c o u n t e r _ s a m p l e ==0){ A u d i o L e f t= 0 x0000 ; }
68 i f ( c o u n t e r _ s a m p l e ==1){ A u d i o L e f t= 0 x8000 ; }
i f ( c o u n t e r _ s a m p l e ==2){ A u d i o L e f t= 0 x0000 ; }
70 i f ( c o u n t e r _ s a m p l e ==3){ A u d i o L e f t= 0 x7fff ; }
c o u n t e r _ s a m p l e ++;
72 i f ( c o u n t e r _ s a m p l e ==4){ c o u n t e r _ s a m p l e =0; } ∗/
/ ∗
74 i f ( c o u n t e r _ s a m p l e ==0){ A u d i o L e f t= 0 x8000 ; }
i f ( c o u n t e r _ s a m p l e ==1){ A u d i o L e f t= 0 x7fff ; }
76 c o u n t e r _ s a m p l e ++;
i f ( c o u n t e r _ s a m p l e ==2){ c o u n t e r _ s a m p l e =0; } ∗/
78
/ / / / / Code to store output s i g n a l ////////////////////
80 //
/ ∗ if ( ( c o u n t e r _ o u t > 1 3 0 0 ) && ( c o u n t e r _ o u t <1845) ) {
82 s i g n a l _ o u t _ p l o t [ counter_out − 1300]= A u d i o R i g h t ;
} ∗/
84
// / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / /
86 TxBuffer [ 0 ] = AudioLeft ;
TxBuffer [ 1 ] = AudioRight ;
88 c o u n t e r _ o u t ++; // c o u n t s the number of output samples
A.4 Data processing

1 / ∗ process_data . c : function executed after the reception of each blocks .
Succesion of bandpass filter , mixing lowpass filter , audio filter
3 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗/
5
fract16
fract16
b u f f e r _ i n [ Number_of_Samples ] ;
7
fract16
b u f f e r I [ Number_of_Samples ] ;
fract16
b u f f e r Q [ Number_of_Samples ] ;
9
fract16
I [ Number_of_Samples ] ;
Q [ Number_of_Samples ] ;
11
fract16 signal_out , signal_out_f , signal_out_norm , signal_prec ;
13
15
short
void
k;
17 Process_Data ( )
19
short i ;
21 / / To measure performances : reset the CYCLES register to 0
/ ∗ asm (" r1 =0;") ;
23 asm ( "CYCLES=r 1 ; " ) ;
asm ( " CYCLES2=r 1 ; " ) ; ∗/

25
27
if
// Mixer /////////////////////////////////////////////
( Ping_Pong ) {
53
29 f i r _ f r 1 6 ( sPPI_RxBuffer1 , buffer_in , Number_of_Samples , &
fir_structur_bandpass ) ;
else
}
31 {
f i r _ f r 1 6 ( sPPI_RxBuffer2 , buffer_in , Number_of_Samples , &
fir_structur_bandpass ) ;
33
for
}
( i = 0 ; i <Number_of_Samples ; i ++){
35 b u f f e r I [ i ]= m u l t _ f r 1 x 1 6 ( b u f f e r _ i n [ i ] , cosinus_modif [ i ] ) ;
b u f f e r Q [ i ]= m u l t _ f r 1 x 1 6 ( b u f f e r _ i n [ i ] , sinus_modif [ i ] ) ;
37 }
39 // Lowpass filtering ( above 1 0 0 kHz ) ///////////
// c f i r _ f r 1 6 ( l o w p a s s , IQ , Number_of_Samples , &f i r _ s t r u c t u r _ l o w p a s s ) ;
41 fir_fr16 ( bufferI , I , 32 , &f i r _ s t r u c t u r _ l o w p a s s _ I ) ;
f i r _ f r 1 6 ( bufferQ , Q, 32 , &f i r _ s t r u c t u r _ l o w p a s s _ Q ) ;
43
// Use these functions to filter and decimate the signal
45 // f i r _ d e c i m a _ f r 1 6 ( b u f f e r I , I , 32 , &f i r _ s t r u c t u r _ l o w p a s s _ I ) ;
// f i r _ d e c i m a _ f r 1 6 ( b u f f e r Q , Q, 32 , &f i r _ s t r u c t u r _ l o w p a s s _ Q ) ;
47
49 // Demodulation /////////////////////////////////////
Demodulation ( ) ;
51
/ / asm ( " nop ; " ) ;
53
A u d i o L e f t=s i g n a l _ o u t _ n o r m ;
55 A u d i o R i g h t=s i g n a l _ o u t _ n o r m ;
// Plots ////////////////////////////////////////////
57 / ∗ s i g n a l _ o u t _ p l o t [ k ]= s i g n a l _ o u t ;
s i g n a l _ o u t _ n o r m _ p l o t [ k ]= s i g n a l _ o u t _ n o r m ;
59 for ( i = 0 ; i <Number_of_Samples ; i ++){
signal_lowpass_plot1 [ k ∗ Number_of_Samples+ i ]= b u f f e r I [ i ];
61 signal_lowpass_plot2 [ k ∗ Number_of_Samples+ i ]= b u f f e r Q [ i ];
s i g n a l _ l o w p a s s 1 f i l t _ p l o t [ k ∗ Number_of_Samples+ i ]= I [ i ] ;
63 s i g n a l _ l o w p a s s 2 f i l t _ p l o t [ k ∗ Number_of_Samples+ i ]=Q [ i ] ;
} ∗/
65 // }
67 }
69
71 void Demodulation ( void )
73 / / d e l t a _ p h i=a n g l e ( x ( i +1) . c o n j ( x ( i ) ) ) ;
75 fract16 A, B ;
// replace [1] by a higher number to have a higher volume ( but less
77 // precision )
A=a d d _ f r 1 x 1 6 ( m u l t _ f r 1 x 1 6 ( I [ 0 ] , I [ 1 ] ) , m u l t _ f r 1 x 1 6 (Q [ 0 ] , Q [ 1 ] ) ) ;
79 B=s u b _ f r 1 x 1 6 ( m u l t _ f r 1 x 1 6 ( I [ 0 ] , Q [ 1 ] ) , m u l t _ f r 1 x 1 6 ( I [ 1 ] , Q [ 0 ] ) ) ;
81 / / s i g n a l _ o u t=a t a n 2 _ f r 1 6 ( B , A) ; // ! ! ! ! wrong def of atan2 : a t a n 2 ( x , y )=a r g ( y+
ix )
s i g n a l _ o u t=s h l _ f r 1 x 1 6 ( a t a n 2 _ f r 1 6 ( B , A) , 3 ) ; // Volume ∗ 2^3 = 8
83
54
A.4. DATA PROCESSING
85 // Audio processing
/ / s i g n a l _ o u t _ n o r m=s i g n a l _ o u t ;
87
// Deemphasis
89 i i r d f 1 _ f r 1 6 (& s i g n a l _ o u t , &s i g n a l _ o u t _ n o r m , 1, &i i r _ s t r u c t u r _ a u d i o ) ;
91 // Other filtering
/ / f i r _ f r 1 6 (& s i g n a l _ o u t _ f , &s i g n a l _ o u t _ n o r m , 1, &f i r _ s t r u c t u r _ a u d i o ) ;
93
}
55
56
Appendix B
Theoretical results
B.1 Radio signal
B.1.1 Modulation
An audio signal can not be directly transmitted through the air over long distances. It has indeed a frequency
between 20 Hz and 20 kHz and the range would be very low with an electromagnetic medium. Moreover, if
another transmitter sends a second audio signal, the receiver will receive both signals without being able to
separate them.
To solve this problem, a high frequency electromagnetic wave that carries the audio signal is used. Therefore,
dierent audio signals can be sent using dierent carrier frequencies.
The carrier signal is a simple high frequency sinusoid: c(t) = cos(2πfc t) (fc is the carrier frequency).
The audio signal m(t) is modulated with the carrier signal to form the transmitted radio signal (bandpass
signal):
s(t) = a(t) cos(2πfc t + φ(t)) (B.1)
a(t) and φ(t) are parameters of m(t) (see section B.1.2 below).
Figure B.1: Spectrum of s(t)
B.1.2 AM and FM
Two kinds of modulation are used in analog auto radio communications: Amplitude Modulation (AM) and
Frequency Modulation (FM).
57
IF Digital Radio Based on Blackn Processor APPENDIX B. THEORETICAL RESULTS
AM modulation
The audio signal is modulated on the amplitude a(t) of the bandpass signal:
a(t) = k(1 + m(t)) (B.2)
Hence,
s(t) = k (1 + m(t)) cos(2πfc t) (B.3)
For radio communications, AM signals use carrier frequencies between 150 kHz and 285 kHz with a bandwidth
of 4.5 kHz. Radio using AM modulation are transmitted with high power (1 to 2 MW).
Spectrum of AM signal S(f ) is simply a frequency shift of M (f ) with a Dirac component:

δ(f − fc ) + δ(f + fc ) M (f − fc ) + M (f + fc )
S(f ) = k + (B.4)
2 2
FM modulation
The audio signal is modulated on the frequency f of the bandpass signal:
1 d
f = fc + (φ(t)) = fc + km(t) (B.5)
2π dt
Hence,
Z t
φ(t) = 2πk m(τ )dτ
0
and Z t
s(t) = S cos(2πfc t + 2πk m(τ )dτ ) (B.6)
0
Radios using FM, are carried by frequencies between 88 MHz and 108 MHz, and use a bandwidth around
155 kHz. The transmitted power is low (2 W).
Spectrum of a sinusoid with FM

If m(t) = Mmax cos(2πfm t), then s(t) = S cos 2πfc t + k Mfmax
m
sin(2πfm t) =
S cos (2πfc t + K sin(2πfm t)) (K is called the modulation indice).
To nd the spectrum of s(t), a expansion using Euler formula is required:
S j2πfc t jK sin(2πfm t)
s(t) = e e + e−j2πfc t e−jK sin(2πfm t) (B.7)
2
ejK sin(2πfm t) is continuous and periodic with period 1/fm , thus expandable as a Fourier series:
∞ Z 2π
x=2πfm t X 1
ejK sin(2πfm t) = ejK sin(x) = Cn ejnx with Cn = ejK sin(x) e−jnx dx
n=−∞
2π 0
Z 2π Z 2π
1 1
Cn = cos (K sin (x) − nx)dx + j × sin (K sin (x) − nx) dx
2π 0 2π 0
Z 2π
1
cos (K sin (x) − nx) dx = Jn (K) with Jn the nth order Bessel function of the rst kind.
2π 0
Z 2π Z π Z 2π
1 1 1
and sin (K sin (x) − nx) dx = sin (K sin (x) − nx) dx + sin (K sin (x) − nx) dx
2π 0 2π 0 2π π
Z π Z 0
1 1
= sin (K sin (x) − nx) dx + sin (K sin (x) − nx) dx
2π 0 2π π
=0
58
B.2. EQUIVALENT LOWPASS OF THE BASEBAND SIGNAL
Hence,
Cn = Jn (K)
∞
X
jK sin(2πfm t)
thus e = Jn (K)ejn2πfm t
n=−∞
∞
X
and, with the same method, e−jK sin(2πfm t) = ejK sin(−2πfm t) = Jn (K)e−jn2πfm t
n=−∞
Hence
∞
S X
ej2πfc t Jn (K)ejn2πfm t + e−j2πfc t Jn (K)e−jn2πfm t

s(t) =
2 n=−∞
∞
X
=S Jn (K) cos (2π (fc + nfm ) t)
n=−∞
The specter of s(t) is therefore

∞
S X
S(f ) = Jn (K) (δ [f − (fc + nfm )] + δ [f + (fc + nfm )])
2 n=−∞
and is thus composed of an innite number of rays around fc . An innite bandwidth is theoretically required to
transmit a FM signal. However, more than 90 % of the energy is located close to fc . A rule of thumb commonly
used to dene the bandwidth is Carson rule: B = 2(K + 1)fm .
B.2 Equivalent lowpass of the baseband signal
s(t) = <(A(t)ej2πfc t ) with A(t) = a(t)ejφ(t) (B.8)
or s(t) = I(t) cos(2πfc t) − Q(t) sin(2πfc t) with I(t) = a(t) cos(φ(t)) and Q(t) = a(t) sin(φ(t)) (B.9)
A(t) is the equivalent lowpass of the modulated signal ; I(t) and Q(t) are called in-phase and quadrature
components of the modulated signal. It should be noted that
I(t) + jQ(t) = A(t) = a(t)ejφ(t) (B.10)
B.3 Demodulation
The goal of the demodulation is to extract the information from the bandpass signal. The rst step is to
extract the equivalent lowpass A(t).
B.3.1 1st method

The point is to start from equation (B.9) and notice that s(t) is divided into two components, one in-phase
π
with the carrier signal, one with a phase oset of
2.
s(t).2 cos(2πfc t) = 2.I(t) cos2 (2πfc t) − 2.Q(t) sin(2πfc t) cos(2πfc t)

= I(t) + I(t) cos(4πfc t) − Q(t) sin(4πfc t)
s(t).(−2 sin(2πfc t)) = −2.I(t) cos(2πfc t) sin(2πfc t) + 2.Q(t) sin2 (2πfc t)

= −I(t) sin(4πfc t) + Q(t) − Q(t) cos(4πfc t)
Thus, by multiplying s(t) by 2 cos(2πfc t) and (−2 sin(2πfc t)), I(t) and Q(t) can be extracted after a lowpass
ltering. The removed component of frequency 2fc is called "image frequency" and appears every time a
multiplication of periodic signals is performed.
59
B.3.2 2nd method

Another equivalent method is to start from the spectral representation of the modulated signal. The goal is
to shift the highest part of the spectrum to the left (see Figure B.2).
The following operation is then performed: Y (f ) = 2S(f ) ∗ δ(f + f c) (the factor 2 is required to keep the
energy of the signal), or in the time domain: y(t) = 2s(t)e−j2πfc t = 2s(t)(cos(2πfc t) − j sin(2πfc t)). After a
lowpass ltering, A(t) can be extracted.
Figure B.2: Frequency shift (analog case)
B.3.3 Digital case

When the bandpass signal is sampled before the demodulation, particular care must be taken with the
bandwidth of the lowpass lter (see Figure B.3) if fc is close to fs /2. In addition to the component at frequency
−2fc , a component at fs − 2fc is created and must be removed by the lter.
Figure B.3: Frequency shift (digital case)
60
B.3. DEMODULATION
B.3.4 Lowpass lters

In previous paragraphs, lowpass lters are used to remove the image frequency. Moreover, to demodulate
accurately the modulated signal, the inphase and quadrature components I(t) and Q(t) must have the same
delay after the lowpass ltering, regardless of their frequency components. Which kind of lter must be used
to have such a property ? To simplify, only linear invarient lters are considered.
The lowpass lter must be such that for every eigen input signal x(t) = X sin(2πf t) the output of the lter
isy(t) = Y (f ) sin(2πf t + ϕ(f )) = Y (f ) sin (2πf (t − τ )) with τ a constant value independent of f . This leads
to ϕ(f ) = −2πf τ and the phase oset of the output signal is linear with the frequency. (All these relations are
true in discrete and continuous time-domain)
The transfer function of the lter is thus (in frequency domain) H(f ) = A(f )e−2πjτ f with A(f ) a real
function and τ a constant. Hence, the impulse response of the lter is h(t) = a(t) ∗ δ(t − τ ) (with ∗ the
convolution product). Since A(f ) is real, its time equivalent a(t) is an even function of time. Hence h(t) is such
that
∀t0 , h(τ − t0 ) = h(τ + t0 ) (there is a symetry axis)
Moreover, the lter used is necessarily causal, hence
for t < 0, h(t) = 0
With these two equations, we can see that
∀t > τ , h(τ − t) = 0 = h(τ + t)
and the impulse response of the lter is thus nite.

To obtain a lter producing the same delay for every sinusoidal input, this lter must have a nite impulse
response and a symetry axis on its time representation. Such a lter in discrete time domain is a FIR lter
with symetrical coecients.
Reciprocally, we consider a causal discrete FIR lter with symetrical coecients and time response h[n].
h[n] = a[n]∗δ[n−n0 ] with a[n] an even function (a[n] = a[−n])
If this lter is an even order lter, we can write
−2πjf n0
and 2n0 the order of the lter. Then the frequency response of the lter is H(f ) = A(f )e . Since a[n] is
even, A(f ) is real. If the input signal of this lter is a sinusoid of frequency f , the phase oset of the output is
ϕ(f ) = −2πf n0 (linear with the frequency) and the output has a constant time delay of n0 independent of f .
If the lter is an odd order lter, the Z-transform of the impulse response is:
H(z) = b0 + b1 z −1 + b2 z −2 + . . . + b2 z −(k−2) + b1 z −(k−1) + b0 z −k

k−1
2
X
= bi z −i + z −(k−i) k is the order of the lter
i=0
Hence the frequency response:
k−1 k−1
2 2
k k
X X
H(ν) = bi e−2πjiν + e−2πj(k−i)ν = bi e−2πjν(i− 2 ) + e−2πjν( 2 −i) e−πjkν
i=0 i=0
 k−1 
2
X k
= 2bi cos 2π(i − )ν  e−πjkν = A(ν)e−πjkν with A(ν) a real function
i=0
2
The phase oset of a sinusoidal output of frequencyf is thus ϕ(f ) = −πf k (linear with the frequency) and the
k
output has a constant time delay of independent of f .
2
Therefore, a FIR lter with symetrical coecients will produce a constant time delay, regardless of the
frequency of the input signal.
61
B.3.5 Extracting the audio signal

After obtaining A(t), the extraction of m(t) depends on the type of modulation.
AM
Here, the audio signal is modulated in the amplitude of A(t) and
p
m(t) = k 0 |A(t)| = I 2 (t) + Q2 (t) (B.11)
FM
The audio signal is modulated in the frequency of A(t). The phase of A(t) is therefore extracted and
dierentiated.
0 d

Q(t)
d
 k dt arctan I(t) if I(t) > 0
m(t) = k 0 (arg A(t)) = (B.12)
dt  k 0 d arctan Q(t) + π if I(t) < 0
dt I(t)
A way to implement it in discrete time is :
m(i) = k 0 arg (A(i)A(i − 1)) (B.13)
62
Appendix C
Master thesis proposal

C.1 Introduction
Siemens VDO Automotive (SV) Rambouillet is specialized in development and production of car radios and
multimedia systems for car manufacturers (GM, Renault, PSA, BMW ...). The study takes place inside the
radio program group which develops platforms (generic hardware and software which are then customized for
each customer) and more especially in the hardware key component group which is in charge of the development
and validation of radio components (microcontroller, DSP, power amplier, etc ...).
The latest generation of car radios uses a new kind of technology to perform the radio reception called
"IF digital". Previously, the FM/AM de-modulation was performed inside the tuner module with analog
components, and an analog signal, which was nearly the audio signal, was delivered to the DSP for nal
processing. With this latest generation of radio, the tuner module is only a front end doing the HF reception
and delivers a not demodulated signal called Intermediate Frequency (IF) to the DSP. This IF is digitalized
using an I/Q modulation and then ltered and demodulated in the DSP. Only a few IC suppliers are providing
specic DSP's and softwares for car radio with integrated mixers and lters. SV is interested in getting the full
knowledge of this system (hardware and software) in order to make its own improvement and to increase its
number of possible IC suppliers.
C.2 Problem denition

The goal of the study is to build a prototype based on a Blackn processor and a house-made digital tuner
able to demodulate FM and AM signals with the software needed. The hardware and software developments
must be documented and clear in order to be understandable and portable on other targets. Depending of
the time left after the prototype is working, some additional subjects can be studied, like stereo and RDS
demodulation, dynamic IF ltering, phase diversity etc...
C.2.1 Hardware part

The prototype will consist of the following hardware blocks (see Figure C.1):
Front end SV IF digital front end generation 2. This module is already existing: no development on this part
is needed.
I/Q Modulation Full study of this part is needed. This block must provide the baseband I/Q signals to be
digitalized. The choice of the component for the prototype is free but must be as much integrated as
possible. Another option is rst to digitalize the IF signal and then generate the I/Q signals internally in
the DSP.
A/D converter In a rst step, an audio A/D can be used in order to work with a mono signal. The second
step will be a study of an A/D converter allowing to digitalize the complete signal (with stereo and RDS)
with the maximum performance.
63
IF Digital Radio Based on Blackn Processor APPENDIX C. MASTER THESIS PROPOSAL
Figure C.1: Hardware blocks of the prototype
Blackn This chip is a hybrid between a microcontroller and a DSP, allowing to generate control signals and
perform signal processing calculations in the same chip. First step will be done using a development board
(ADSP-BF533 EZ-KIT Lite). A second step may be to develop a dedicated board.
C.2.2 Software part

The software must consist of at least the following blocks:
Framework The framework must provide the input/output function with control of the tuner module (I C
2
bus).
Selectivity ltering This block lters the I and Q signals to remove the adjacent channel. On a rst step,
the lter will be static but improvement can be made so this lter is dynamic to improve the adjacent
channel rejection when needed without decreasing the quality of the main channel.
Demodulation Demodulate the I and Q signals. This function must provide the AM and FM demodulation
and the basic information about the received signal (frequency oset and eld strength).
C.2.3 Possible additional developments and improvements (depending on the time

left)
Noise blanker This block removes the spikes from the received signal due to the ignition of the engine.
Stereo demodulation From the demodulated signal, this block detects the stereo pilot and demodulates the
stereo band.
RDS demodulation This extracts the RDS information from the demodulated signal. It must provide the
RDS clock and data. RDS decoding is not requested.
Phase diversity Build a second IF path using a second tuner module and antenna. From the two received
signals, the DSP builds a "clean" one using beam forming technique and a CMA algorithm.
C.3 Research Approach

The ADSP-BF533 EZ-KIT Lite is a development bord with a Blackn processor and several chips and
connectors such as an audio codec, a video codec, input and output audio connectors, an UART port, an
expansion interface, etc. Due to the limitation of the sampling frequency of the input connectors, an external
A/D converter must be used to sample the IF signal and connected directly to the appropriate data port of the
Blackn processor. The rst step of the study is thus to choose and purchase the appropriate converter, choose
64
C.4. EXPECTED RESULTS
the protocol for the transmission of the input datas on the data port, with regard to potential interferences
with the other components of the development board.
The second step is to weld the A/D converter on a printed circuit with its supply sources and surrounding
components and to connect it with the development board.
The third step is to build the software that will perform the demodulation of the signal. A rst version will
do a Talkthrough to test if the IF signal is received and handled accurately .
C.4 Expected Results

The minimal requirement is that the prototype works well with a mono audio signal received from an external
antenna. A complete optimization of the process is not required.
C.5 Time Plan

• 2005-09-01 to 2005-10-28: Hardware development Choice of components, choice of protocol, weld-
ing, connection and tests
• 2005-11-02 to 2005-12-23: Software development Talkthrough test, Demodulation

• 2006-01-02 to 2006-02-28: Additional development and improvements
65
IF Digital Radio Based on Blackn Processor APPENDIX C. MASTER THESIS PROPOSAL
66
Bibliography
[1] Analog Devices. AD7655 Data Sheet. http://www.analog.com/UploadedFiles/Data_Sheets/
309183105AD7655_b.pdf.
[2] Analog Devices. AD8138 Data Sheet. http://www.analog.com/UploadedFiles/Data_Sheets/
67526251AD8138_e.pdf.
[3] AnalogDevices. ADSP-BF533 Blackn Processor Hardware Reference. http://www.analog.
com/processors/epManualsDisplay/0,2795,,00.html?SectionWeblawId=207&ContentID=
69184&Language=English.
[4] Analog Devices. ADSP-BF533 EZ-KIT Liter Evaluation System Manual. http://www.analog.com/
UploadedFiles/Associated_Docs/179226691ADSP_BF533_EZ_KIT_Lite_Manual_Rev_2.0.pdf.
[5] AnalogDevices. ADSP-BF53x/BF56x Blackn Processor Programming Reference. http://www.
analog.com/processors/epManualsDisplay/0,2795,,00.html?SectionWeblawId=207&ContentID=
67993&Language=English.
[6] Analog Devices. Blacknr specications. http://www.analog.com/UploadedFiles/Data_Sheets/
320040195ADSP_BF531_2_3_b.pdf.
[7] Analog Devices. EZ-Kit features. http://www.analog.com/UploadedFiles/Product_Highlights/
52029341983041ADSP_BF533_EZKIT__C__final.pdf.
[8] Analog Devices. Getting started with Blacknr processors. http://www.analog.com/UploadedFiles/
Associated_Docs/59930206865030blk_ug_40_web.pdf.
[9] Jacques Antoine, Jean-Luc Colette, Gilles Duc, Hervé Guéguen, and Daniel Poulton. Signaux et systèmes.
a
Supélec, 2002. (01218/.. 2002).
[10] Dominique Beauvois, Laurent Le Brusquet, Marie-Anne Lefebvre, and Yves Tanguy. Introduction aux
signaux et systèmes. a
Supélec, 2002. (01217/.. 2002).
[11] Jean-Claude Dany, Jean-Louis Gutwiller, Lionel Husson, Pierre Leray, and Armelle Wautier. Signal et
communication. a
Supélec, 2003. (11127/.. 2003).
[12] Philips Semiconductors. TDA1387 Data Sheet. http://www.semiconductors.philips.com/acrobat_

download/datasheets/TDA1387T_2.pdf.
[13] RFMD. RF2713 Data Sheet. http://www.rfmd.com/DataBooks/db97/2713.pdf.
[14] Texas Instruments. ADS8402 Data Sheet. http://focus.ti.com/lit/ds/symlink/ads8402.pdf.
[15] Jens Zender, Ben Slimane, and Lars Ahlin. Principles of Wireless Communications. KTH, 2004.
67

If Digital Radio Based On Blackfin Processor

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

If Digital Radio Based On Blackfin Processor

Uploaded by

Copyright:

Available Formats

IF Digital Radio Based on Bla

Master's Degree Proje t

Sto kholm, Sweden

Rambouillet, February 2006

C Master thesis proposal 63

1.1 Hardware components

1.1.2 The development board: EZ-KIT Lite

• Blackn BF533SKBC600 DSP

• an AD1836 audio codec with input and output connectors

• general purpose LED and push buttons

• Evaluation suite of Visual DSP ++

1.1.3 The A/D converter : AD7655

Connection with the Blackn

1.1.4 Serial ports

1.1.5 Connection diagram

1.1.6 Audio codec AD1836

• the SPI port to send conguration values to the codec

• the SPORT0 port to send and receive data

Figure 1.2: Connection diagram of the A/D converter

Figure 1.3: AD converter and its external connection

Figure 1.4: Complete prototype

1.2 Software part

1.2.1 Data transfer

Figure 1.5: Principle of data transmission

converter and the format of its output data:

Secondary side disabled Only one data channel is needed here.

1.2.2 Data processing

Figure 1.7: Clock and data signals

Figure 1.8: Principle of demodulation (FM)

Choosing clocks and data format

Mixing the input signal

Figure 1.9: Lowpass lter for the IQ signal

Demodulation and audio ltering

Figure 1.10: Lowpass lter for the audio signal

Moving data to the audio codec

1.3 First results

1.3.1 Talkthrough test

Figure 1.11: Talkthrough test

1.3.2 Demodulation test

Figure 1.17: IQ signals

Figure 1.18: Output signal

Figure 1.19: Filtered output signal

2.1.1 Aim of this board and general layout

Figure 2.1: Components of the board

2.1.4 Dierential ADC Driver

2.1.5 Parallel port interface

• a 18 MHz circuit to drive the Blackn

• a 20.8 MHz circuit to drive the mixer

• a 100 kHz circuit to drive the tuner

2.1.9 Audio DAC

2.1.10 External memories

2.1.12 Power supply

2.1.13 Electrical schemes

Figure 2.3: Electrical schematics: DSP

Figure 2.4: Electrical schematics: SD-RAM and Flash

Figure 2.5: Electrical schematics: Tuner and its clock

Figure 2.6: Electrical schematics: Mixer and local oscillator

Figure 2.7: Electrical schematics: AD converter

Figure 2.8: Electrical schematics: DA converter, audio output and UART

Figure 2.9: Layout

Figure 2.10: Photo of the board

2.2 Software part

• Blackn BF533SKBC600 DSP

Connection with the Blackn

• the SPI port to send conguration values to the codec

Figure 1.9: Lowpass lter for the IQ signal

Demodulation and audio ltering

Figure 1.10: Lowpass lter for the audio signal

2.1.4 Dierential ADC Driver

• a 18 MHz circuit to drive the Blackn

Port conguration 0 frame syncs is used (up to 3 are available)

Figure 2.12: Bandpass lter

Mixing and lowpass ltering

Figure 2.13: Deemphasis lter

Left / Right order The left stereo channel is sent rst.

Figure 2.15: Signal, noise and THD for dierent RF levels

Figure 2.18: Output of the D ip-op before and after ltering