CALVIGNAC Yvan

CAMBONIE Pierre
4° Année – Groupe A

Practical Work Report :

PHYSICS AND MODELING

OF

SEMICONDUCTOR DEVICES

4-stage binary counter

08/01/2007
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Introduction :

Our counter is made by 4 D-registers cascaded. The clocking of each stage is simply carried
out by the previous counter, to form an asynchronous counter circuit. The 4-stage binary
counter displays number from 0 to 15, using a chain of four D-register cells (see on figure 1).

Figure 1 : Schematic of a 4-stage binary counter

We used edge trigged latches, where the information flows from the input D to the output Q
only on a rising edge of the clock, to build the counter. The structure of these latches, named
D-register, is a master-slave structure. We use 2 D-latches and a gate Not (see on figure 2).

Figure 2 : Diagram of a D-register

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The Not gate :

The first step was to do a Not gate. For that, we designed the gate using Microwind
(see on figure 3).

Figure 3 : Design of a Not gate (Microwind)

We can observe its good working on the simulation (see on figure 4).

Figure 4 : Simulation of a Not gate (Microwind)

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The D-Latch :

Then we did a D-latch (see on figure 5).

Figure 5 : The schematic diagram of a D Latch

In order to check the good working of this circuit we did a simulation using the software
DSCH3.1 on the following way (see on ficure 6) where ‘clk1’ and ‘clk3’ are respectively the
Clock and the input of the latch and ‘out1’ the output.

Figure 6 : The schematic diagram of a D Latch (Dsch3.1)

When the clock input is high, the latch output Q follows the changes of the input. The latch is
transparent. Now, when the clock input goes low, the latch is in memory mode, meaning that
it produces the value stored in the loop at the output Q.

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The result of the simulation is shown on the figure below (see on figure 7) :

Figure 7 : The logic simulation of a D Latch (Dsch3.1)

When performing the logic simulation, ‘out1’ starts with an undetermined state (appearing in
grey in figure 3). Once the clock (clk1) is active, ‘out1’ turns to a determinate state, as the
data input ‘clk3’ is transferred to ‘out1’. When the clock returns to level 0, the latch keeps its
last value.

The compact design of the D-Latch :

In order to obtain a compact design, complex gates should be used. Indeed, the direct
implementation (see Figure 1) uses 22 MOS devices whereas the complex gate one only 14
(see on figure 8). The complex gate solution also leads to shorter propagation delay.

Figure 8 : CMOS implementation with complex gates (14 transistors)

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Then we noticed the description of the complex function : s = ~((a&bc)
(see on figure 9).

Figure 9 : Description of the function s = ~((a&bc)

Now we can design the D-latch using Microwind.

First we designed the component shown on figure 9.

Figure 10 : Compact description of the function s = ~((a&bc)

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Then we designed the D-latch which is composed by 2 components as shown on figure 8 and
a Not gate (see on figure 11) where ‘clock1’ and ‘clock2’ are respectively the input and the
clock of the D-latch. ‘s3’ and ‘s4’ are respectively the output and the inverted output.

Figure 11 : Design of a D Latch (Microwind)

The result of the simulation is shown below (see on figure12).

Figure 12 : Simulation of a D Latch (Microwind)

Here we can notice the good working of the D-latch.

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The D-Register :

Once the D-latch was created, we build a D-Register based on a master-slave structure
combining two D-Latches and a Not gate following the schematic bellow (see on figure 13) :

Figure 13 : Diagram of a D-register

The first D-Latch's output is assigned to the second D-Latch's input and the clock enters
directly into the second D-Latch and through a Not gate into the first one.

We cabled this D-Register using Dsch3.1 to display this system's working as shown below
(see on figure 14) in order to validate it :

Figure 14 : The schematic diagram of a D-Register (Dsch3.1)

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Then we ran the simulation and we obtained the next results (see on figure 15) :

Figure 15 : The logic simulation of a D-Register (Dsch3.1)

We can see on this chronogram that the 'clk4' input's state is transferred to 'out2' on every
rising edge of the 'clk3' input. That is the D-Register's working so we are now able to validate
this system and we can start to generate it using Microwind.

We linked the two D-Registers and the Not gate as explained previously (see on figure 16) :
The first D-Register's metal output is linked to the second D-Register's not gate's silicon input
and the clock enters directly on the second D-Register's silicon clock input and through a not
gate on the first one's silicon clock input.

Figure 16 : Design of a D-Register (Microwind)

'Clk1' is the clock and 'Clk2' the data. 'S1' is the positive output and 'S2' the negative one.

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When we ran the simulation we obtained the next results (see on figure 17) :

Figure 17 : Simulation of a D-Register (Microwind)

We can see that this results are similar to the ones we obtained using dsch3.1 :
the 'clk2' input's state is transfered to 's1' output on every rising edge of 'clk1' and the 's2'
output is the opposite of 's1'. We have created a D-Register based on a master-slave structure.

The 4-stage binary counter :

Once we have created a D-Register, we are able to build a 4-stage binary counter.
Here you can see the way to link two D-Registers (see on figure 18) :

Figure 18 : The way to link two D-Registers in order to create a counter (DSCH3.1)

The negative output of each D-Register returns to its input and to the following D-Register’s
clock input. The positive output is one of the counter’s outputs.

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Following this way of linking the D-Registers together, we can build a 4-stage binary counter
as represented on the next figure (see on figure 19) :

The metal negative output of each D-Register returns to its silicon input and to the following
D-Register’s metal clock input. The metal positive output is one of the four 4-stage binary
counter’s outputs.

Figure 19 : Design of a 4-stage binary counter (Microwind)

There is only one input 'clock1' which is the first D-Register's clock input and four outputs
which are 's1', 's2', 's3', 's4' (one output for each D-Register).

Then we ran the simulation and we could check that the 4-stage binary counter increased from
0 to 15 on every clock’s rising edge (see on figure 20).

Figure 20 : Simulation of a 4-stage binary counter (Microwind)

We have created a 4-stage binary counter. The next steps could have been to add a reset input
or an other input allowing to choose if the counter increase or decrease on every clock’s rising
edge.

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Conclusion :

From just a few logic gates, we have created a 4-stage binary counter which is ready to be
realised on a silicon wafer (see on figure 21). Based on a 65 nm technology, its dimensions
are about 4 µm x 24 µm.

This practical work permits us to discover how to use the two software : ‘Microwind’ and
‘Dsch3.1’.

It also gave us the basic concepts to understand the operation of the transistors in order to
extract their models and to use them in complex analog or digital circuits.

Figure 21 : D-Register’s process view in 3D (Microwind)

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