Architectural Development and Functional Verification of SuperSpeed USB 3.0 PHY Layer Controller

JOURNAL OF COMPUTING, VOLUME 3, ISSUE 5, MAY 2011, ISSN 2151-9617
HTTPS://SITES.GOOGLE.COM/SITE/JOURNALOFCOMPUTING/
WWW.JOURNALOFCOMPUTING.ORG 1
Architectural Development and Functional

Verification of SuperSpeed USB 3.0
PHY Layer Controller
Hasan Baig and Jeong-A Lee*
Abstract— Universal serial bus has supported a wide variety of devices from keyboard, mouse, flash memory device, game peripheral, imaging up to
high speed broad band devices. In addition, user applications demand a higher performance connection between the PC and other increasingly sophisticated
peripherals. USB 3.0 addresses this need by adding even faster transfer rates. It promises a data transfer rate of 4.8 Gbps as compared to its predecessor
interface USB 2.0 which has a raw data rate at 480Mbps. This implementation of synthesizable Media Access (MAC) layer of SuperSpeed USB Memory
Device, with a pipelining concept of processing the packets, is proposed to support high speed transfer rate and high throughputs. Alongside, the use of
efficient handshaking signals complies with optimum performance of the overall device. Master controller has also been implemented to have a command
over MAC Layer and the other layers that will be implemented in a future research. This implementation meets the required specifications and ensures the
data rate of atleast 4.0Gbps [1].
Index Terms— USB 3.0, MAC Layer, Physical Layer Controller, FPGA.
——————————  ——————————
1 INTRODUCTION
T he physical layer classifies the PHY portion of a port

and the physical connection between a downstream
facing port (on a host or hub) and an upstream facing
little power.
The USB PHY Layer (PHY Chip depicted in Fig. 1)

port on a device. The SuperSpeed physical connection is handles the low level USB protocol and signaling. This
comprised of two differential data pairs, a transmit path includes features such as; data serialization and deseriali-
and a receive path (Fig. 1). zation, 8b/10b encoding, analog buffers, elastic buffers
The electrical aspects of each path are characterized as and receiver detection. The primary focus of this block is
a transmitter, channel, and receiver; these collectively to shift the clock domain of the data from the USB rate to
represent a unidirectional differential link. Each differen- one that is compatible with the general logic in the ASIC
tial link is AC-coupled with the capacitors located on the [1].
transmitter side of the differential link. The channel in-
cludes the electrical characteristics of the cables and con-
nectors [1].
At an electrical level, each differential link is initialized
by enabling its receiver termination. The transmitter is
responsible for detecting the far end receiver termination
as an indicator of a bus connection and informing the link
layer so the connect status can be factored into link opera-
tion and management.
When receiver termination is present but no signaling
is occurring on the differential link, it is considered to be
in the electrical idle state. When in this state, Low Fre- Fig 1: PHY/MAC Interface.
quency Periodic Signaling (LFPS) is used to signal initial-
ization and power management information. The LFPS is 2 MAC INTERFACES
relatively simple to generate and detect and uses very
Since the PIPE (PHY Interface for the PCI Express) is im-
———————————————— plemented for USB mode that supports 5.0GT/s, we have
 Hasan Baig is with the Chosun University, Gwangju, South Korea, 501- chosen 32 bits data paths with PCLK running at 125MHz
759. www.hasanbaig.webs.com [2]. The MAC Layer commands the communication of
 Jeong-A Lee *(corresponding author) is with the Chosun University, PHY Layer with the Link Layer and LTSSM (Link Train-
Gwangju, South Korea, 501-759.
ing and Status State Machine).
© 2011 Journal of Computing Press, NY, USA, ISSN 2151-9617

http://sites.google.com/site/journalofcomputing/
PHY layer controller itself is commanded by Master 2.1 Link Layer

Controller. The top level block diagram of MAC Layer (or A Super Speed link is a physical and logical connection be-
Physical Layer Controller)1 is shown in Fig. 2. It can be tween two ports, called link partners. A port has a physical
observed that the PHY Layer Controller itself comprises part and a logical part. The link layer identifies the logical
of some internal modules that will be described later in portion of a port and the communications between link
the following sub sections. partners. The main responsibility of link layer is to ensure
The MAC layer of USB 3.0 device interacts with Link the successful data transfer with the link partner and to
layer, LTSSM and is commanded by Master controller. maintain connectivity between them.
LTSSM and Link Layer are beyond the scope of this re-
search paper, so will be described briefly in the next sub
sections.
1Phy Layer Controller is also called Media Access (MAC) Layer. We
will use these terms interchangeably throughout this paper.
Fig 2: Top Level Block Diagram of PHY Layer Controller.

Layer, Protocol Layer and LTSSM, which would be in fact

2.2 Link Training and Status State Machine a future enhancement of this research. Top level block
The Link Training and Status State Machine (LTSSM) diagram of Master Controller is shown in Fig. 3.
behaves as a leading workhorse to maintain reliable link,
highly optimized power consumptions and efficiently 3.1 Decoding Path Controller
fast and perfect data transfer rate. It also implements var- The decoding process is to take packet from the PHY chip
ious algorithms for link’s reliability preservation and is and pass it to link layer controller (decoder) and so forth.
also liable to recover a link when an error arises. Master controller follows the protocols in the sequence men-
It is LTSSM who manages the power of a device profi- tioned below.
ciently and greatly reduces the link’s power consump-
tion. It also voids the condition that causes the wastage of
power. It co-ordinates and converse with PHY chip,
MAC Layer, Link Layer and Master Controller to per-
form it’s duties.
2.3 Dual Port Reference Memory
USB 3.0 specification [1] provides a complex hardware im-
plication. It has been emphasized to produce such an archi-
tecture that can be easily comprehended, incorporated and
implemented without an extraordinary knowledge of inter-
facing other layer in USB 3.0 device.
To achieve this, each layer is kept separated from the
other by inserting dual-port-memories (Fig. 2) in between
two successive layers. When one of the layers is done
with writing data to intermediate memory (dual-port-
memory), there is a primary need of notifiying the next
concerned layer to begin execution and process the valid
memory contents in the intermediate memory area. This
need is accomplished by using the Master Controller
which schedules the execution of layers in a pre-
determined sequence which is described in next section. Fig. 3: Top Level Block Diagram of Master Controller - showing IO inter-
face with each layer and LTSSM.
2.4 Buffer Interfaces
The primary reason of using buffer interfaces (Fig. 2) is to 1. When Phy Layer Decoder (Fig. 2) receives the
overcome the need of incorporating a memory controller into complete packet, it generates an indication signal
a layer’s main controller. In case, for example, if MAC layer is to master controller which in turn initializes the
instructed to start processing some valid memory contents, Link Layer (LL) decoder, provided that LL de-
there could be two possibilities – First MAC layer fetch the coder is not already in a busy state. Meanwhile,
memory contents by issuing address & data to enable ports of master controller also sends the packet size to
the memory with incrementing each time the address for the the LL decoder that it received from the Phy
next valid data and asserting the enable ports. Layer decoder at the complete reception of pack-
Second possiblity is that it has a separate module et.
which is notified of the number of bytes to be fetched
from memory and which is resposible of incrementing 2. When the packet is processed by the LL decoder,
the address each time it gets valid data for memory. In it generates an indication signal to master con-
order to simplify the implementation, it is recommended troller which in turn initializes the Protocol Lay-
to have separate entities so that hardware can be easily er (PL) decoder, provided that it is not already
comprehended and debugged or in another words the busy. Link layer decoder de-assembles the pack-
main controller will remain free from some extra burden
et received and sends the new packet size (pack-
while dealing with the memory.
et size changes after passing through the packet
Second approach is quite better. Thus buffer interface
de-assembler) to master controller. Master then
(or memory controllers) are used in the architecture just
sends this new packet size to protocol layer de-
beside intermdiate dual-port-memories.
coder at the time of its initialization.
3 MASTER CONTROLLER Fig. 4 depicts the timing diagram of decoding process.

Master Controller is developed to command the commu-
nication flow between each module. The centralized mas- Note: Master must deassert the initializing signal of Link Layer
ter controller monitors and controls the decoding and and Protocol Layer decoders as soon as they acknowledged.
encoding operation separately. It has been designed in
such a way that it can easily be integrated later with Link
Fig. 4: Timing diagram of decoding path controller.
Note: Master must deassert the initializing signal of Protocol

3.2 Encoding Path Controller
Layer, Link Layer and Phy Layer Encoders as soon as they
The controlling protocols, mentioned below, are followed acknowledged.
by the master controller in order to encode the packet
1. Protocol Layer (PL) Encoder is initialized when 4 INTERFACE SIGNALS

master-configuration valid signal is received by
the Master controller provided that the PL en- 4.1 MAC – LTSSM Interface Signals
coder must not already busy. As soon as the The MAC – LTSSM I/O signals are described in the Table
complete packet is encoded, PL encoder gener- 1. The signals described as inputs are received by MAC
ates an indicating signal (“pl_enc_done”, Fig. 3) and those described as outputs are driven by MAC.
to the master informing it the packet has been
transferred into the buffer and ready to be
4.2 MAC – Master Controller Interface Signals
fetched by Link Layer controller. Master control- The signals used to monitor and control the PHY Layer
ler then generates a signal to initialize the Link Controller are described in the Table 2. The signals are
Layer (LL) encoder, provided that LL encoder is described from the perspective of Master Controller. Thus
not already in a busy state. Meanwhile, master the signals described as “input” are received by the Mas-
also sends the packet size to the Link Layer en- ter and signals described as “output” are driven by the
Master.
coder; it had received from the PL encoder at the
complete reception of packet. 4.3 MAC Layer Internal Signals
Communication flow between intermediate modules of
2. After processing, assembling and transferring the PHY Layer Controller is shown in Fig. 2. The Phy Encod-
complete packet in the buffer, LL encoder gener- er – Read Buffer interface signals and Phy Decoder –
ates an indication signal (“ll_enc_done”, Fig. 3) to Write Buffer interface signals are described in the Table 3.
master controller which in turn initializes the The signals described here are from the perspective of
Phy Layer encoder, provided that it is not al- Phy Encoder and Phy Decoder. Thus a signal described as
ready busy. Link layer encoder also sends the an “output” is driven by Phy Encoder/Decoder and the
new packet size (packet size changes after pass- signal described as an “input” is received by the Phy En-
ing through the packet assembler) to master con- coder/Decoder.
troller. Master controller then sends this new
packet size to Phy layer encoder at the time of its 4.4 MAC – PHY Interface Signals
initialization. The MAC-PHY input and output signals are described in
the Table 4. The signals described here and later are de-
Master controller must deassert the initializing signal of fined from the perspective of a PHY Layer Controller
Protocol Layer, Link Layer and Phy Layer Encoders as (MAC Layer). Thus a signal described as an “output” is
soon as they acknowledged. Fig. 5 depicts the timing dia- driven by MAC and the signal described as an “input” is
gram of encoding process. received by the MAC.
Fig. 5: Timing diagram of encoding path controller.
TABLE 1
MAC – LTSSM I/O INTERFACE SIGNALS
Name Direction Active Level Description

Instruction for MAC to take PHY chip into the
[1:0] PowerDownLTSSM Input N/A Power State (P0, P1, P2 or P3) mentioned by
LTSSM.
Instruction for MAC to transmit Low Frequency
transmit_LFPS Input High Periodic Signaling (LFPS) when the PHY is in
P1, P2 or P3 state.
transmit Input High Instruction for MAC to begin transmission op-
eration followed by the proper protocols.
receiver_DO Input High Instruction for MAC to do receiver detection
operation.
[2:0] Rx_status_2LTSSM Output N/A Sends encoded receiver status to LTSSM.
Informs LTSSM the completion of several PHY
LTSSM_phy_status Output High functions including power management, state
transitions, rate change, and receiver detection.
do_rx_termination Input High Controls the presence of receiver terminations
commanded by LTSSM.
VBUS Output High Indicates the presence of VBUS to LTSSM
LFPS_detected Output High Indicates LTSSM that Low Frequency Periodic
Signaling (LFPS) is being detected.
4.5 MAC – Link Layer Controller Interface Signals That data is read and send (to PHY chip) by the Read Buffer
The MAC-Link Layer Controller I/O signals are described Interface and Phy Encoder respectively (See Fig. 2). Similar-
in the Table 5. The signals described as inputs are received ly, the data coming from the PHY chip is received by Phy
by MAC and those described as outputs are driven by decoder, and
MAC. DPRF (for Encoder) is used by the Link Layer Con- then written into DPRF (for Decoder) through the Write
troller to write the data in dual port memory. Buffer Interface, which is then used by Link Layer Control-
ler (See Fig. 2).
TABLE 2
MAC – MASTER CONTROLLER I/O INTERFACE SIGNALS

clk Input N/A Pclk coming from PHY chip.
Asserts after a complete transaction of packet
done Input High from Read Buffer interface to PHY chip.
Indicates that Encoder is active and fetching
phy_active_tx Input High data from Read Buffer interface.
rx_done Input High Informs the Master controller that one packet
has been fetched from PHY chip.
phy_active_rx Input High Indicates that decoder is in active state and read-
ing data from PHY chip.
[10:0]packet_size Input N/A Size of packet (calculated by Phy Decoder) re-
ceived from the PHY chip.
[8:0] pld_base_addr Input N/A Base address of next packet generated by Phy
decoder.
[8:0] pld_base_addr_en Output N/A Base address from which Phy Encoder needs to
read data.
[10:0] pack_size Output N/A Instruct Phy Encoder to fetch the given size of
packet.
reset_n Output Low Master reset
start_en Output High Starts encoding operation.
TABLE 3
MAC INTERNAL SIGNALS

ready_en Output High Signal used to inquire the Read Buffer Interface
whether it is ready to send data to Phy Encoder.
ack_en Input High Acknowledgment of “ready_en” signal from Read
Buffer interface.
[31:0]rd_data Input N/A 32-bits data bus used to fetch data from Read Buffer
Interface.
EOP Input High End Of Packet: indicates last packet from Read Buffer
interface.
valid Input High Indicates valid data at “rd_data” bus of Read Buffer
interface
buf_if_active_en Input High It signifies that Read Buffer is in active state and
fetching data from dprf.
phy_rd_valid Output High Indicates valid data, at 32-bits RxData bus, to Write
Buffer Interface.
Signal used to inquire the Write Buffer Interface
ready_de Output High whether it is ready to receive data from Phy Decoder.
32-bits data bus; used to write data into Write Buffer
[31:0]phy_wr_data_bus Output N/A interface.
phy_data_last Output High Indicates last packet from PHY chip
buf_if_active_de Input High It signifies that Write Buffer is in active state and writ-
ing data into dprf.
ack_de Input High Acknowledgment of “ready_de” signal from Write
Buffer interface.
TABLE 4
MAC-PHY I/O INTERFACE SIGNALS

Parallel USB data output bus. 32 bits represents the 4
symbols of transmit data. Bits [7:0] are the first symbol
to be transmitted, and bits [31:24] are the fourth sym-
[31:0]Txdata Output N/A bol.
Data/Control bit for the symbols of transmitted data.
For 32-bit interfaces, Bit 0 corresponds to the Low-byte
[3:0]TxdataK Output N/A of Txdata (i.e. bits [7:0]) and Bit 3 corresponds to the
Upper-byte (i.e. bits [31:24]). A value of “0” indicates a
Data byte and a value of “1” indicates a Control byte.
TxDetectRx Output High Request PHY to begin a receiver detection operation.
Force Tx lines to remain electrical idle when asserted in
all power states.
When deasserted while in P0 (as indicated by the Pow-
Encoder Tx_elec_idle Output High erDownLTSSM signals) indicates a valid data is present
on Txdata and TxdataK lines and must be transmitted.
[1:0] PowerDown Output N/A Power up or down the transceiver power states.
Used to communicate completion of several PHY func-
phy_status Input High tions including power management state transitions,
rate change, and receiver detection.
Encodes receiver status and error codes for the received
[2:0]Rx_status Input N/A data stream when receiving data.
Receiver is detected when Rx_status = 011.
Parallel USB data input bus. 32 bits represents the 4
symbols of received data. Bits [7:0] are the first symbol
[31:0]RxData Input N/A to be received, and bits [31:24] are the fourth symbol.
Data/Control bit for the symbols of received data. For
32-bit interfaces, Bit 0 corresponds to the Low-byte of
[3:0]RxDataK Input N/A RxData (i.e. bits [7:0]) and Bit 3 corresponds to the
Upper-byte (i.e. bits [31:24]). A value of “0” indicates a
Data byte and a value of “1” indicates a Control byte.
reset_rx_tx Output Low Resets the transmitter and receiver
Instructs PHY to perform a polarity inversion on the
RxPolarity Output High received data:
0: PHY doesn’t invert polarity
1: PHY does polarity inversion
Decoder Control the presence of receiver terminations:
RX_Termination Output High 0: Terminations removed
1: Terminations present
RxValid Input High Indicates valid data on RxData and RxDataK
Indicates receiver detection of an electrical idle. While
Rx_elec_idle Input High deasserted with PHY in P0, P1, P2 or P3 indicates the
detection of LFPS [1].
PowerPresent Input High Indicates the presence of VBUS.
Parallel interface differential data clock. All data
PCLK Input Rising Edge movement across the parallel data interface is synchro-
nized to this clock which operated at 125MHz (in USB
External case).
Signals Selects PHY operating mode
Phy_mode Output N/A 0: PCI Express
1: USB Mode
So it should always be kept High.
TABLE 5
MAC – LINK LAYER CONTROLLER I/O INTERFACE SIGNALS

[8:0]ll_wr_dprf_addr Input N/A Address from which Link Layer Controller starts writ-
ing the data in DPRF.
[31:0]ll_wr_dprf_din Input N/A 32-bits data input bus.
[31:0]ll_wr_dprf_wem Input N/A Write enable mask.
ll_wr_dprf_en Input High Enable DPRF for writing data.
[8:0]ll_rd_dprf_addr Input N/A Address from which Link Layer Controller wants to
read the data from DPRF.
ll_rd_dprf_en Input High Enable DPRF for reading data.
[31:0]ll_rd_dprf_dout Output N/A 32-bits data out.
Ignore Input High Force Phy Decoder to ignore the incoming packet of
data until lrty is found.
lrty_found Output High Informs the Link Layer Controller that header packet
is resending.
5 MEDIA ACCESS (MAC) LAYER OR PHYSICAL When an encoding process is done by Link Layer con-
troller, it asserts “ll_enc_done” (section III-B), informing
LAYER CONTROLLER master controller that a valid data has been placed in du-
The main object of this research is the implementation of al-port-memory and must be fetched by Phy Encoder.
MAC Layer encoder and decoder that runs in parallel Master controller then asserts “start_en” (Fig. 3) signal to
and hence ensures the concurrent in-out transaction of initialize Phy encoder and waits for being acknowledged
USB 3.0 protocols. by Phy encoder.
Before discussing the developed algorithm of MAC LTSSM controls the power state of PHY chip through
Encoder and Decoder, it is good to have a look at the Phy Encoder. Phy chip remains idle in P1 and P3 power
standard USB 3.0 packet [1] first. It is also portrayed in states [1]. In P2 state, encoder waits for the instruction
Fig. 6. Refer [1] for detailed description of packet sym- from LTSSM either to force Phy Chip to transmit LFPS [1]
bols. or to do receiver detection operation (Fig. 7). When a val-
id data is present in the buffers, LTSSM instructs Phy
Encoder to take Phy chip into P0 state. Encoder starts the
process of fetching data, from buffer, only when a posi-
tive edge of “transmit” is seen asserted.
When LTSSM asserts “transmit” signal, encoder re-
quests the data and waits for the acknowledgment from
Read Buffer Interface. When transaction begins, encoder
obtains the data payload size from the packet size (given
by master controller, in terms of bytes) and puts into the
register, named “data_pld_size”. The purpose of calculat-
ing the data payload size is to find out how many num-
ber of transactions are required to send the complete
packet to Phy chip. Since each transaction can have 4
symbols of transmit data (32-bit bus) [refer 1 for detailed
description], therefore a packet size is divided by 4 to
obtain the correct number of transactions required. Refer-
ring [2], TxDataK bus indicates Control or Data byte in a
current transaction.
The RTL of encoder is efficient enough to locate which
byte is a control byte or data byte in a current transaction.
Fig. 6: Standard USB 3.0 packet with maximum of 1024 data bytes Fig.4 depicts that there are two such transactions (1st and
5.1 MAC Layer Encoder (Phy Encoder) 6th) which have complete control symbols (bytes) in it.
The last transaction should have all control bytes, but it
It is recommended to refer [2] first for PHY Chip encod-
depends on the data payload size. If data payload size is
ing signals, in order to understand Phy Encoding algo-
not a multiple of 4, then there must be an ambiguity
rithm. Algorithmic State Machine Description (ASMD) of
which symbol is a control or a data byte, in 2nd last trans-
PHY Encoder is shown in Fig. 7.
action. Two least significant bits of “data_pld_size” indi-
cates the position of data byte in 2nd last transaction
(Fig.6).
5.2 MAC Layer Decoder (Phy Decoder) “PowerState” of Phy Decoder is again in a control of LTSSM.
Decoding process is pretty complicated and a challenging Phy Decoder remains idle in P1 & P2 states. In P3, LTSSM
task. It is recommended to refer [2] to grasp the PHY Chip asserts “receiver_DO” (See Fig. 2) signal when it requires “re-
decoding signals. ASMD of Phy Decoder is shown in Fig. 8. ceiver detection” operation to be performed.
Fig. 7: ASMD of Phy Encoder (see Fig. 2 for block level diagram)
Phy Decoder in-turn asserts “TxDetectRx” signal [2], request- As soon as LTSSM instructs Phy decoder to take PHY Chip
ing PHY chip to begin “receiver detection” operation. This into the power state P0, decoder starts looking for
signal should remain high until “phy_status” signal [2] from “Rx_elec_idle” signal. Phy Decoder informs the LTSSM about
Phy Chip is seen asserted. When the receiver detection opera- LFPS on the basis of “Rx_elec_idle” signal. It then goes into
tion is completed, PHY chip asserts “phy_status” signal [2]. “idle” state until valid data is present at “RxData” bus. When
Phy decoder then deasserts “TxDetectRx”, meanwhile in- the valid data is present, decoder interrogates the “Write
forms LTSSM, the status of receiver through Buffer Interface” (Fig. 2) whether it is ready to accept the in-
“Rx_status_2LTSSM” bus. coming data, and jumps to the “ackldg” (acknowledge) state.
Fig. 8:ASMD of Phy Decoder (see Fig. 2 for block level diagram)
It then waits for the acknowledgment from “Write TABLE 6

RESOURCE UTILIZATION BY PHY LAYER CONTROLLER
Buffer Interface”. As soon as the buffer acknowledges,
decoder starts fetching and sending data from Phy Chip
to Write Buffer Interface respectively (Fig. 2). Phy De- Resources Used Available Utilization
coder keeps on transferring packet from Phy Chip to Register 108 69120 0.15%
Write Buffer Interface unless the Link Layer Controller LUT 222 69120 0.32%
asserts “ignore” signal. Slice 116 17280 0.67%
When “ignore” is seen asserted, Phy decoder discards
the incoming data from the Phy Chip and starts looking TABLE 7
for LRTY [1]. Phy Decoder also calculates the size of RESOURCE UTILIZATION BY MASTER CONTROLLER
packet while transferring data from Phy chip to Write
Buffer interface. Fig. 4 depicts that a packet can have a Resources Used Available Utilization
maximum size of up to 1024 bytes (max data payload) + Register 50 69120 0.072%
28 bytes (standard protocol of each packet). LUT 51 69120 0.073%
The packet size is calculated in such a way that a coun- Slice 18 17280 0.1%
ter is incremented each time a transaction occurs. Decoder
continuously monitors RxDataK lines. Control byte is
indicated by RxDataK bus whenever its value is non-zero.
7 FUNCTIONAL VERIFICATION
Whenever a non-zero value is present at RxDataK lines, Although the whole of the USB Device is written in
another separated counter is incremented to monitor the synthesizable RTL code, this entity will be representing the
number of control byte transactions. Referring to the Fig. behavior of the Host plus the behavior of the PHY Chip. It is
4, it can be observed that there could only be 3 or 4 such meant only for simulation purposes and can never infer a
transactions which have control bytes in it, i.e. the first hardware at all. It can supress the concept of separate layers
transaction, the sixth transaction and the last transaction. and can accommodate the behavioral of the host entity and
There could be fourth control byte transaction when data PHY Chip as a single entity which is needed to derive the
payload size is not a multiple of 4 (i.e. first three of the MAC layer, appearing in the front-line of the upstream facing
last four control bytes can be a part of second last transac- port (USB Device).
tion). Random data is generated through a testbench and in-
Since the first and the sixth transaction is a complete puts to MAC Layer (assuming that it is coming from Link
control byte transaction, therefore one doesn’t need to Layer, See Fig. 1, and Fig. 2) and a pre-defined packet size
care about them. The problem arises after data pay load for each time a simulation runs. This data is processed by
due to variations in the data payload sizes. Phy Encoder via dual-port-memory and read buffer inter-
ASMD shown in Fig. 6 depicts that decoder repeatedly face (Fig. 2). Phy Encoder passes this data to PHY Chip
checks for “rxdataK_count” to become equal to 2. When (behavioral model) which loop backs that to Phy Decoder.
“rxdataK_count” become equal to 2, decoder checks the Phy decoder remains idle unless RxValid signal (from
value of RxDataK. RxDataK = 4’hF point towards that all behavioral of PHY, Fig. 2) is seen asserted. As soon as the
the four bytes are control bytes and a current transaction rising edge of RxValid signal is sensed, decoder requests
is End of Packet. RxDataK, other than 4’hF, clearly indi- Write Buffer Interface to received data coming from the
cates that the data payload size is not a multiple of 4 and Host. Once it acknowledges, the Phy decoders starts
the present transaction contains the data byte(s) along fetching the data and place it on the ports facing write
with the control byte(s). Also we would have fourth con- buffer interface which in turn place the data into the dual-
trol byte transaction. If RxDataK = 4’h8 (4’b1000), it port-memory (Fig. 2). Meanwhile it also looks for the con-
shows, there are 3 data bytes and 1 control byte. This one trol bytes (on RxData bus) on the basis of which it could
control byte is actually from the four of the last control find out the size of packet (See Section 4.2).
bytes (shown in Fig. 4). This means that there will be only
3 (remaining) control bytes in the next transaction and the
8 CONCLUSION AND FUTURE WORK
last byte will remain empty, thus a value of 1’b1 is sub-
tracted from the size of packet (shown in Fig. 6). Similar Since SuperSpeed protocols are intended for dual simplex
method is implemented for RxDataK = 4’hC and 4’hE. transmission lines, transmitting and receiving transactions in
parallel, there is an absolute need of having the architecture
which support such protocols.
6 HARDWARE UTILIZATION
In order to meet the requirements, separate encode
The RTL designs of both PHY Layer and Master Control- and decode paths work concurrently and independently.
lers are fully synthesized using Virtex-5 XC5VLX110T Thus encode path is associated with packet assemblers or
device. The resource utilization by PHY Layer Controller encoders while the decode path is associated with packet
and Master Controller are presented in Table 6 and Table disassembler or decoders. Encode and decode paths are
7 respectively. executed by the Master Controller State Machine to fulfill
the dual simplex capability of the bus.
This synthesizable implementation of MAC Layer
(Physical Layer Controller) follows the latest specification
of USB 3.0. It is designed in such a way that other layers integrated with this layer. The future objective could be
can be easily interfaced with it. complete USB 3.0 memory device whose top level
Link Layer, Protocol Layer and LTSSM will be diagram is shown in Fig. 9.
developed in future as an independent entity and
Fig. 9: The overall block diagram of proposed architecture.
REFERENCES Hasan Baig obtained his Bachelors of Engineering Degree

(Electronics) from NED University of Engineering and
[1]. “Universal Serial Bus 3.0 Specification”, Hewlett-Packard Compa-
Technology, Karachi, Pakistan, in January 2010. Currently
ny, Intel Corporation, Microsoft Corporation, NEC Corporation, ST- he is pursuing his MS Degree in Embedded Computing
NXP Wireless, and Texas Instruments, Revision 1.0, November 12, from Chosun University, Gwangju, South Korea. Also, he
2008. is serving as a Research Assistant to Prof. Jeong-A Lee in
[2]. “PHY Interface for the PCI Express TM and USB Architectures”, computer system lab. He is a recepient of Korean Global
Version 2.90, Intel Corporation, 2007-08.
IT Scholarship to carry out research and higher studies.
[3]. “Universal Serial Bus Specification”, Revision 2.0, April 27, 2000.
[4]. “On-The-Go Supplement to the USB 2.0 Specification”, Revision
He has conducted many workshops on behalf of IEEE
1.3, December 5, 2006. Students branch. His research interest includes embedded
[5]. “Inter-Chip USB Supplement to the USB 2.0 Specification”, system design, FPGAs, on-chip process variations
Revision 1.0, March 13, 2006. estimation, partially reconfigured embedded systems.
[6]. “USB System Architecture (USB 2.0)”, MindShare, Inc., Don
Anderson.
Jeong-A Lee is presently a Professor of Department of
[7]. “eXtensible Host Controller Interface for Universal Serial Bus
Computer Engineering, since joining Chosun University
(xHCI)”, Revision 1.0, 2010.
[8]. Peter J. Ashenden, “Digital Design: An Embedded System Ap- in 1995. She received the B.S. in Computer Engineering
proach using Verilog”, Elsevier, 2008. with from Seoul National University in 1982, M.S. in
Computer Science from Indiana University, Bloomington
in 1985 and Ph.D. in Computer Science from University of
California, Los Angeles in 1990. From 1990 to 1995, she
was an assistant professor at the Department of Electrical
and Computer Engineering, University of Houston. Her
research interests include computer architecture, fast digi-
tal and CORDIC arithmetic, application specific architec-
tures design and configurable computing. She is the au-
thor of more than 100 technical papers, was a guest editor
of a special issue on CORDIC, Journal of VLSI Signal Pro-
cessing Systems for Signal, Image, and Video Technology
in 2000, and has been working as a programming com-
mittee member for several international conferences and a
senior member of IEEE.

Architectural Development and Functional Verification of SuperSpeed USB 3.0 PHY Layer Controller

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Architectural Development and Functional Verification of SuperSpeed USB 3.0 PHY Layer Controller

Uploaded by

Copyright:

Available Formats

JOURNAL OF COMPUTING, VOLUME 3, ISSUE 5, MAY 2011, ISSN 2151-9617

Architectural Development and Functional

T he physical layer classifies the PHY portion of a port

The USB PHY Layer (PHY Chip depicted in Fig. 1)

© 2011 Journal of Computing Press, NY, USA, ISSN 2151-9617

PHY layer controller itself is commanded by Master 2.1 Link Layer

Fig 2: Top Level Block Diagram of PHY Layer Controller.

Layer, Protocol Layer and LTSSM, which would be in fact

3 MASTER CONTROLLER Fig. 4 depicts the timing diagram of decoding process.

Fig. 4: Timing diagram of decoding path controller.

Note: Master must deassert the initializing signal of Protocol

1. Protocol Layer (PL) Encoder is initialized when 4 INTERFACE SIGNALS

Fig. 5: Timing diagram of encoding path controller.

Name Direction Active Level Description

Name Direction Active Level Description

Name Direction Active Level Description

Name Direction Active Level Description

Name Direction Active Level Description

It then waits for the acknowledgment from “Write TABLE 6

Fig. 9: The overall block diagram of proposed architecture.

REFERENCES Hasan Baig obtained his Bachelors of Engineering Degree

You might also like