On-Chip Analog Sinewave Generator with Reduced Circuitry Resources

Manuel J Barragan, Diego Vazquez, Adoraci6n Rueda and Jose L. Huertas Instituto de Microelectr6nica de Sevilla- Centro Nacional de Microelectr6nica (IMSE-CNM-CSIC),
Universidad de Sevilla, Ed. CICA, Av. Reina Mercedes s/n, 41012 Sevilla, Spain. E-mail: manuelj(imse.cnm.es

Abstract-- This paper proposes an analog sinewave signal generator with minimal circuitry resources. It is based on a linear time variant filter that gives a high quality sine signal in response to a DC input. The proposed architecture has the attributes of digital programming and control capability, robustness and reduced area overhead, what make it suitable for BIST applications. Experimental results from a practical design demonstrate the feasibility of the approach.

use of a time variant linear filter to perform both the signal generation and its filtering to reduce the unwanted harmonics. The paper is organized as follows. Section II makes a revision of some previous works. Section III describes the proposed generator. The expected performance is analyzed in Section IV. Section V gives some results of a design example and compares them with previously proposed generators. Finally, Section VI gives some conclusions.

I. INTRODUCTION The increasing complexity of actual and future ICs has the associated issue of more complex, longer, and hence more expensive test. This issue is identified in the SIA Roadmap for Semiconductors [1] as one of the key problems for actual and future mixed-signal SoCs. The main test difficulties are due to the test of the analog parts. They are traditionally tested using costly functional approaches, but their sensitivity to loading effects, environmental conditions and process variations make their test a difficult task. Moreover, they demand high quality input stimuli, high data volume acquisition and processing capability, etc., requiring for that expensive ATEs (Automatic Test Equipments). It is well accepted that Built-In-Self-Test (BIST) techniques are a way to overcome some of the problems cited above by moving part of the required test resources (test stimuli generation, response evaluation, test control circuitry, etc.) into the chip [1]. An efficient BIST approach should have the attributes of low speed digital interface needs with ATE, programming capability, robustness against environmental noise and process variations, and low area overhead. Most of the mixed-signal subsystems in complex ICs (filters, ADCs, DACs, signal conditioners, etc.) can be characterized and tested (frequency domain specifications, linearity, etc.) using periodic signals (square, triangular, sinusoidal, etc.). So, the on-chip generation of this kind of stimuli is of main importance. Many interesting works have paid the attention to it [2]-[6]. In this line, this paper presents an efficient sinewave generator with reduced circuitry requirements, what make it very suite for BIST applications. The idea consists on the
This work is funded in part by the Spanish Government through the project TAMBIST, under contract #TEC2004-02949/MIC.

II. PREVIOUS WORKS Sinewave signals can be generated using an analog oscillator consisting on a filtering section and a non-linear feedback mechanism (Fig. 1). The last forces the oscillation while the filtering section removes the unwanted harmonics. The quality of the generated signal depends on the linearity and selectivity of the filter (the larger the selectivity is, the larger the purity of the sine signal) and the shape of the non-linear function (smooth functions are needed for low distortion). The tuning of the filter allows the programmability of the frequency. The work in [2] reports 44dB and 49dB of THD and SFDR respectively at 25MHz. Other approaches adapt digital techniques using the scheme shown in Fig.2, which facilitates a digital interface for control and programming tasks. A direct implementation using memory based synthesizers is not practical because of the area overhead. The works in [3]
control
I

tuning circuitry

filtering section

_AU
Fig. 1: Oscillator-based sinewave generator.
On-Chip signal generator
A

IEDigitlConrl/
/

\
-/
n-bits D
.

_1

Digital

interfac

Analog
Filter

e
L

Generator

Imaog iga
-I

Fig. 2: Block diagram of digital based analog signal generators.

1-4244-0173-9/06/$20.00 2006 IEEE.

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On-Chip signal generator

ATE

IClock

(f

cycontrol)

epw ise signal

\
sl

Eternal

interface Inp.t

IDC

-01

PI

~~~Filter

Analog

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Fig. 3: Variable gain Amplifier based sinewave generator.

and [4] avoid the use of the DAC by exploiting the noise shaping characteristics of IA encoding schemes. They consist on generating a 1-bit stream IA encoded version of an N-bit digital signal and match the shape of a filter with the noise shaping characteristics of the encoded bit stream. It is valid for single and multitone signals but requires large bit-stream lengths and a highly selective filter to remove the noise. In addition, the approach is frequency limited due to the need of very high oversampling ratios. Signals in the range of some MHz with 65dB SFDR with a 1-bit stream length of 1024 and a fourth order filter have been reported [3]. A very simple scheme for discrete-time periodic analog signal generation can be found in [5]-[6]. As shown in Fig.3, it consists on a variable gain step-wise switched-capacitor (SC) amplifier (VGA) where each gain step represents a value of a sampled and hold signal. The scheme in Fig.3 is in fact quite similar to that in Fig.2 if it is taken into account that the programmable VGA plays the role of the DAC in Fig.2. The main advantages of the approach are that both the amplitude and the frequency of the signal can be easily controlled by a DC input voltage and the clock frequency respectively, together with the simplicity and robustness of the logic and the SC circuitry. The main disadvantages however are the limited frequency range and that signal quality is limited by the accuracy and number of the generated steps. Experimental results from a prototype in [5] show a performance of 49dB of THD for a signal of 1kHz and lVpp. Improving such performance would require the use of a post-filtering stage to reduce the level of unwanted components.

domain, it can be straightforward extended to the discrete-time case. Let be a linear time variant filter with input ult) and output ylt) described in terms of the state-variables as, [x'(t)] = [a] [x(t)] + [b(t)]u(t) y(t) = [c] [x(t)] + d(t)u(t) where the coefficients [b(t)] and d(t), representing the dependence of the state variables [x(t)] and the output y(t) with respect to the input u(t), are time variant. Let us consider the case [b(t)]= [b]J(t) and d(t)=dJ(t), where [b] and d are constant andf(t) is a time variant function. Using the Laplace Transform, it can be shown from (1) that, Y(s) = H(s) {F(s) 09 U(s) } (2) y(t) = h(t) (0 {f(t)u(t)} where capital letters denote the Laplace Transform, H(s) is a transfer function of value,
H(s)
=

[c][sI-a] [b] +d

(3)

III. PROPOSED APPROACH In any of the schemes previously discussed, a filtering stage is needed to obtain a low distorted and high SFDR sinewave. We aim in this work to show how the idea in Fig.3 can be further improved by the use of a linear time-variant filter. The idea consists on merging both operations, signal generation and filtering in the filter itself. The proposed approach maintains the attributes of digital control, programmability, and robustness, and reduces significantly the area overhead with respect to the other discussed approaches.
A. Theoretical basis

First of all, it is convenient to remark that although the discussion will be restricted to the continuous-time

and h(t) is its Inverse Laplace Transform. From (2), it should be clear that the system in (1) performs, in the most general case, the filtering of the product g(t)=J(t)u(t), that is, it acts as a multiplier and a filter all in one. Restricting to its use as a signal generator (the use as a multiplier, although interesting, is out of the scope of the paper), it is obvious that if the input u(t)= u= cte, it acts as a signal generator where the generated output y(t) is the signalj(t) scaled by a factor u but filtered accordingly to h(t). In other words, for a DC input u, the system in (1) operates as a function generator and a filter all in one. Obviously, if ftt) is a sinusoidal-like waveform, the system can be used as a sinewave generator. B. Implementation considerations Concerning the function At), it may have different shapes. Good candidates, that can be easily generated are step-wise sinewaves, trapezoidal and triangular waveforms, etc. Of course, the larger the amplitude of the harmonics it introduces, the higher the order of the filter needed to obtain a given THD. With respect to its implementation, it depends on the kind of filters whenever the possibility of creating programmable devices exists. In particular, those devices which need to be programmable are those connecting the input to the core of the filter. It can be found a wide variety of programming strategies in the literature. In SC applications, it can be implemented by digitally programmable capacitors as in [5], but reduces its application to step-wise waveforms. In the OTA-C case, by programming the Gm value of the input OTAs [7]. Digitally programmable resistors are also reported in [8] for the MOSFET-C technique. Regarding the filter, what is needed is to match the transfer function of the filter to the shape and frequencies of interest in the application. In this sense, lowpass (LP) and bandpass (BP) shapes are clearly the most convenient whenever the main harmonic be in the passband and the unwanted harmonics in the rejection

639

band. In SC applications the frequency can be easily scaled through the clock frequency. In the continuous case (OTA-C, MOSFET-C, etc.) the unavoidable tuning circuitry can be used for this purpose.
IV. PERFORMANCE ESTIMATION This section intends to make a preliminary performance estimation of the proposed strategy. In order to be realistic in the estimation and analysis it is needed to make some considerations. On one hand, the value of the generated steps can be affected by errors (due to mismatching between devices, supply variations, etc.) which deviate them from their ideal values. It can be shown that such errors will contribute to the harmonic distortion. On the other hand, the type (lowpass, bandpass, etc.) of the filtering section, its order and its linearity also play a crucial role in the quality of the generated signal, since it will determine the magnitude of the unwanted harmonic components. The proposed strategy has been analyzed in terms of THD and SFDR taking into account the possible errors in the step levels and in the filtering characteristics. In this paper, we restrict our analysis to the case of step-wise sinewaves as J(t) functions with N steps per period of duration TI (so, the period of the sinewave is NTI). It means that signal J(t) will be composed by a main harmonic at frequency 1 NTI and unwanted harmonics at multiples of such frequency (kINTI; k= 2,

The objective is to place the frequencies of the unwanted harmonics in the rejection band while the main harmonic is placed in the passband of the filter. For simplicity, only second order lowpass and bandpass filtering sections of the form,
H(s)
=

KBP(wQ)s +KBPO

s+(W0 Q)s+w0

(4)

3,4,.)

will be considered (the effect of higher orders can be straightforward derived from them). Notice that KBP=1&KLP=O is for the bandpass case and viceversa for the lowpass. The best choice is clearly to make, c)o = 2 /NTs (5) it means that the frequency of the signal will be because close to the peak gain of the filter (for Q > 1/2 ) while the harmonics will be in the rejection band. A Monte Carlo analysis using errors of 0. 1%, 1% and 5% in the levels of the stepwise sinewave and applied to the filtering sections (with different pole quality factors Q) has been carried out to estimate the performance of the approach. Fig.4 shows the obtained worst cases of SFDR and THD for the lowpass and bandpass for a maximum error in the step level of 0.lI% as a function of the Q. On the other hand, Fig.5 shows the cases for Q=5 as a function of the error in the step levels. The results show that very good SFDR and THD can be obtained for a relatively low number of steps per period and a low order filter. However, these estimations are optimistic, since the non-linearity of the filter has not
115.
110 105

1301
120

THD (dashed line) and SFDR (solid line) Maximum error level = 0.1%

THD (dashed line) and SFDR (solid line) Maximum error level

01%

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50

60

70

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20

Number of levels, N

30

40

50

60

70

Fig. 4: SFDR and THD estimation for fixed maximum step error level of 0.1I% as a function of Q
THD(dashed line) and SFDR (solid line). Second order lowpass filter 0Q5
11C

Error level = 0.1% Error level = 1% 0 Error level = 5%

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THD(dashed line) and SFDR (solid line). Second order bandpass filter Q=5

100 0 Error level = 5%

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Fig. 5:SFDR and THD estimation for Q= =5 as a function of step effor level.

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been considered. That is, they mark the maximum achievable performance as it may be limited by the linearity of the filter. Nevertheless, it is convenient to remember that this limiting factor is unavoidable and common to any of the other approaches discussed in Section II.

(positive or negative) of the step. In this way, the resulting transconductance Gma(t) can be described as,
4

G,n,(t)
where

(Din(t) (Din(t)

k= I

y (Dk(t) G.k

(6)

V. DESIGN EXAMPLE An OTA-C based implementation has been carried out in a 0.35gm CMOS technology following the guidelines for this kind of structures given in [7]. Fig.6a shows the block diagram of the designed generator based on a 2nd-order LP architecture. The input transconductor Gma(t) is time variant and it is composed by four transconductors in parallel (Gml to Gm4) as depicted in Fig.6b, whose contributions are switched on or off in an incremental way accordingly to the time scheme shown in Fig.6c. It generates the required steps of a positive half sinewave, while the input switching scheme controlled by signal Di, (in Fig.6a) set the weight
a)
Variable

Gmk

sin

(j) -sin ((k -1)]

(7)

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DC

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GmB

GmctC2

Input

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Output

b)

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Ct)k

0-+

(Dk +t
0

7 +

Table I lists the values of the design parameters for a pole quality factor Q close to 6 and a center frequency around 41 MHz. Notice that if the input transconductor is maintained constant at Gma(t)=Gm =1.35mAIVj the circuit acts as a time invariant filter with the same Q and center frequency cited above. Fig.7 shows the transistor level schematic of the OTA. It is composed by a basic transconductor followed by a folded-cascode stage. In fact, the folded-cascode stage is used to provide impedance matching at every node and is shared (with proper scaling) by all the transconductors that are incident in the same node. Fig.8 shows the layout of the circuit. It occupies an area of 395gm*230gm (excluding pads). In order to know the limitations in terms of linearity imposed by the OTAs, a simulation was carried out using the extracted view and when the circuit is configured as a time invariant filter (Gma(t)=GM=].35mA1V) and excited with a 2OmVpp@41.4MHz pure sinewave (frequency of the peak gain). The performance data are in Table II. On the other hand, Fig.9 shows the output signal spectrum obtained when the circuit acts as a signal generator for Vreft2OmV, T =1.5ns and VDD=3.3V. The generated signal is 25OmV peak-to-peak. The obtained performance data are in Table II. The results are similar to the case of the filter, what means that the linearity of the OTAs is the main limitation to the quality of the generated signal, and not the switching scheme to implement the time variant transconductor. Table I: Design parameters.
GmA GmB
1.35mA/V 0.270mA/V GmC 1.35mA/V GmD 1.35mA/V

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Clock

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Output
Input

Fig. 6: a) Block diagram of the signal generator. b) Time variant transconductor implementation. c) Time scheme

Fig. 7: Transistor level schematic of the implemented OTAs.

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Table III shows a comparison between the presented generator and other reported approaches. It demonstrates that the proposed approach is more area efficient, and give the best results in terms of THD and SFDR with the exception of the analog IA oscillator [4], but this oscillator requires a very high filtering (6th order) and its application is reduced to low frequencies.

VI. CONCLUSIONS
A methodology for high quality analog sinewave generator with reduced circuitry resources has been presented. It is based on a linear time variant filter with a DC input, in such a way that the filter itself performs two operations: the signal generation and the filtering of the unwanted components. It reduces the required resources and saves a large amount of area with respect to other approaches in the literature. The performance and accuracy of the proposed methodology have been estimated theoretically and validated through an example using the OTA-C technique. In addition, the functionality, feasibility and area efficiency of the proposed approach have been validated through electrical simulations of a practical design.

VII. REFERENCES
Fig. 8: Layout of the designed generator.

Fig. 9: Generator output spectrum

Table 11: Performance data.

Frequency Filter 41.4 MHz Generator 41.4 MHz

Vpp 250 mV 250 mV

THD 66 dB 67 dB

SFDR 66 dB 67 dB

[1] SIA Roadmap for semiconductors. http: llpublic.itrs.net [2] J. Galan, R. G. Carvajal, A. Torralba, F. Munoz, J. Ramirez-Angulo,: " A low-power low-voltage OTA-C Sinusoidal oscillator with a large tuning range", IEEE Transactions on Circuits and Systems, vol. 52, no 2, February 2005. [3] B.Dufort and G.W.Roberts: "On-chip analog signal generation for mixed-signal Built-In-Self-Test". IEEE J. Solid-State Circuits, 1999, Vol 33, N 3, pp. 318-330 [4] A.K.Lu, G.W.Roberts and D.Johns: "A high quality analog oscillator using oversampling D/A conversion techniques". Trans. on Circuits and Systems II: Analog and digital processing', 1994, pp. 437-444. [5] M.G.M6ndez, A.Vald6s, J.Silva and E.Sanchez: "An On-Chip Spectrum Analyzer for Analog Built-in Testing", Journal of Electronic Testing: Theory and Applications", Springer Sciences, 2005, Vol 21, pp. 205-219. [6] H.C.Patangia and B.Zenone:" A programmable switched-capacitor sinewave generator". Proc. of 37th Midwest Symp. on Circ. and Systems, 1994, pp. 165-168. [7] J.E.Kardontchik: "Introduction to the design of Transconductor-Capacitor Filters". Ed. Kluwer Academic Publishers, 1992. [8] D.Vazquez, A.Rueda and J.L.Huertas: "On-Line Error Detection for Continuous-Time MOSFET-C Filters", Proc. 19th European Solid-State Circuits Conference (ESSCIRC), 1993, pp. 206-209.

Table III: Comparison with different approaches

Continuous-Time

Oscillator

[2]

Analog LA Oscillator [4]

FPGA + 6th order filter

ROM-based Generator

[3]

Step-Wise Generator

[5]

Proposed Approach

Technology Area
THD SFDR

0.8rm CMOS
0.63 mm2 44dB @25MHz 49dB @ 25MHz

0.8 rm BiCMOS 0.83 mm2 + 4th order filter not reported 65dB @ 10MHz

0.5rm CMOS
0.1

0.35 rm CMOS
0.1

mm2

mm2

84dB @5kHz 86dB @5kHz

49dB @ 10kHz 38dB @ 10kHz

67dB@41MHz
67dB @41MHz

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