TIMELY OPERATED ELECTRICAL APPLIANCE CONTROL SYSTEM

Abstract:

The aim of this project is to save electricity by the timely control of electronic appliance s ,this is helpful is the places where no one is there to control manually switch to on and off the device. For example street lights, lights at parks ECT. The proposed system consists of a microcontroller interfaced with a RTC, the user sets the time and microcontroller reads time from the RTC, when the TIME is equal the microcontroller on or off the device based on the program control.

BLOCK DIAGRAM:

LCD RELAYS

RELAYS RELAYS

RELAYS MEMORY RELAYS ULN2003

RTC 8051

KEYPAD

Modules in Block diagram: 1. 2. 3. 4. 5. 6. Microcontroller(P89v51rd2) RTC Memory Keypad ULN2003 Relay

Block Diagram Explanation: 1. Microcontroller: Micro Controller (P89V51RD2):

The P89V51RD2 is 80C51 microcontrollers with 64kB Flash and 1024 bytes of data RAM.
A key feature of the P89V51RD2 is its X2 mode option. The design engineer can choose to run the application with the conventional 80C51 clock rate (12 clocks per machine cycle) or select the X2 mode (6 clocks per machine cycle) to achieve twice the throughput at the same clock frequency. Another way to benefit from this feature is to keep the same performance by reducing the clock frequency by half, thus dramatically reducing the EMI.

The Flash program memory supports both parallel programming and in serial In-System Programming (ISP). Parallel programming mode offers gangprogramming at high speed, reducing programming costs and time to market. ISP allows a device to be reprogrammed in the end product under software control. The capability to field/update the application firmware makes a wide range of applications possible. The P89V51RD2 is also In-Application Programmable (IAP), allowing the Flash program memory to be reconfigured even while the application is running.

Features:

 80C51 Central Processing Unit  5 V Operating voltage from 0 MHz to 40 MHz  16/32/64 kB of on-chip Flash user code memory with ISP (In-System  Programming) and IAP (In-Application Programming)  Supports 12-clock (default) or 6-clock mode selection via software or ISP  SPI (Serial Peripheral Interface) and enhanced UART  PCA (Programmable Counter Array) with PWM and Capture/Compare functions  Four 8-bit I/O ports with three high-current Port 1 pins (16 mA each)  Three 16-bit timers/counters  Programmable watchdog timer  Eight interrupt sources with four priority levels  Second DPTR register  Low EMI mode (ALE inhibit)  TTL- and CMOS-compatible logic levels  Brown-out detection  Low power modes 1. Power-down mode with external interrupt wake-up 2. Idle mode  PDIP40, PLCC44 and TQFP44 packages

Block diagram

Pin Configuration:

Pin description

Functional Description:
Power-On reset code execution
Following reset, the P89V51RD2 will either enter the Soft ICE mode (if previously enabled via ISP command) or attempt to auto baud to the ISP boot loader. If this auto baud is not successful within about 400 ms, the device will begin execution of the user code.

In-System Programming (ISP)

In-System Programming is performed without removing the microcontroller from the system. The In-System Programming facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the P89V51RD2 through the serial port. This firmware is provided by Philips and embedded within each P89V51RD2 device. The Philips In-System Programming facility has made in-circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area. The ISP function uses five pins (VDD, VSS, TxD, RxD, and RST). Only a small connector needs to be available to interface your application to an external circuit in order to use this feature.

Input/output (I/O) ports

32 of the pins are arranged as four 8-bit I/O ports P0 P3. Twenty-four of these pins are dual purpose with each capable of operating as a control line or part of the data/address bus in addition to the I/O functions. Details are as follows: Port 0 This is a dual-purpose port occupying pins 32 to 39 of the device. The port is an open-drain bidirectional I/O port with Schmitt trigger inputs. Pins that have 1s written to them float and can be used as high-impedance inputs. The port may be used with external memory to provide a multiplexed address and data bus. In this application internal pull-ups are used when emitting 1s. The port also outputs the code bytes during EPROM programming. External pull-ups are necessary during program verification. Port 1 This is a dedicated I/O port occupying pins 1 to 8 of the device. The pins are connected via internal pull-ups and Schmitt trigger input. Pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs; as inputs, pins that are externally pulled low will source current via the internal pullups. The port also receives the low-order address byte during program memory verification. Pins P1.0 and P1.1 could also function as external inputs for the third timer/counter i.e.: (P1.0) T2 Timer/counter 2 external count input/clockout

(P1.1) T2EX Timer/counter 2 reload/capture/direction control Port 2 This is a dual-purpose port occupying pins 21 to 28 of the device. The specification is similar to that of port 1. The port may be used to provide the high-order byte of the address bus for external program memory or external data memory that uses 16-bit addresses. When accessing external data memory that uses 8-bit addresses, the port emits the contents of the P2 register. Some port 2 pins receive the high-order address bits during EPROM programming and verification. Port 3 This is a dual-purpose port occupying pins 10 to 17 of the device. The specification is similar to that of port 1. These pins, in addition to the I/O role, serve the special features of the 80C51 family; the alternate functions are summarized below: P3.0 RxD serial data input port P3.1 TxD serial data output port P3.2 INT0 external interrupt 0 P3.3 INT1 external interrupt 1 P3.4 T0 timer/counter 0 external input P3.5 T1 timer/counter 1 external input P3.6 WR external data memory writes strobe

P3.7 RD external data memory read strobe. Timers/counters 0 and 1 The two 16-bit Timer/Counter registers: Timer 0 and Timer 1 can be configured to operate either as timers or event counters (see Table 12 and Table 13). In the Timer function, the register is incremented every machine cycle. Thus, one can think of it as counting machine cycles. Since a machine cycle consists of six oscillator periods, the count rate is 16 of the oscillator frequency. In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T0 or T1. In this function, the external input is sampled once every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register in the machine cycle following the one in which the transition was detected. Since it takes two machine cycles (12 oscillator periods) for 1-to-0 transition to be recognized, the maximum count rate is 112 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle. In addition to the

Timer or Counter selection, Timer 0 and Timer 1 have four operating modes from which to select. The Timer or Counter function is selected by control bits C/T in the Special Function Register TMOD. These two Timer/Counters have four operating modes, which are selected by bit-pairs (M1, M0) in TMOD. Modes 0, 1, and 2 are the same for both Timers/Counters. Mode 3 is different. The four operating modes are described in the following text. TMOD - Timer/Counter mode control register (address 89H) bit allocation Not bit addressable; Reset value: 00000000B; Reset source(s): any source

TMOD - Timer/Counter mode control register (address 89H) bit description

TMOD - Timer/Counter mode control register (address 89H) M1/M0 operating mode

TCON - Timer/Counter control register (address 88H) bit allocation

Bit addressable; Reset value: 00000000B; Reset source(s): any reset

TCON - Timer/Counter control register (address 88H) bit description

Mode 0
Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit Counter with a fixed divide-by-32 prescaler. Figure 7 shows Mode 0 operation.

In this mode, the Timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the Timer interrupt flag TFn. The count input is enabled to the Timer when TRn = 1 and either GATE = 0 or INTn = 1. (Setting GATE = 1 allows the Timer to be controlled by external input INTn, to facilitate pulse width measurements). TRn is a control bit in the Special Function Register TCON (Figure 6). The GATE bit is in the TMOD register. The 13-bit register consists of all 8 bits of THn and the lower 5 bits of TLn. The upper 3 bits of TLn are indeterminate and should be ignored. Setting the run flag (TRn) does not clear the registers. Mode 0 operation is the same for Timer 0 and Timer 1 (see Figure 7). There are two different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).

Mode 1

Mode 1 is the same as Mode 0, except that all 16 bits of the timer register (THn and TLn) are used. See Figure 8.

Mode 2
Mode 2 configures the Timer register as an 8-bit Counter (TLn) with automatic reload, as shown in Figure 9. Overflow from TLn not only sets TFn, but also reloads TLn with the contents of THn, which must be preset by software. The reload leaves THn unchanged. Mode 2 operation is the same for Timer 0 and Timer 1.

Mode 3 When timer 1 is in Mode 3 it is stopped (holds its count). The effect is the same as setting TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two separate 8-bit counters. The logic for Mode 3 and Timer 0 is shown in Figure 10. TL0 uses the Timer 0 control bits: T0C/T, T0GATE, TR0, INT0, and TF0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the Timer 1 interrupt. Mode 3 is provided for applications that require an extra 8-bit timer. With Timer 0 in Mode 3, the P89V51RD2 can look like it has an additional Timer. Note: When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it into and out of its own Mode 3. It can still be used by the serial port as a baud rate generator, or in any application not requiring an interrupt.

Timer 2
Timer 2 is a 16-bit Timer/Counter which can operate as either an event timer or an event counter, as selected by C/T2 in the special function register T2CON. Timer 2 has four operating modes: Capture, Auto-reload (up or down counting), Clock-out, and Baud Rate Generator which are selected according to Table 17 using T2CON (Table 18 and Table 19) and T2MOD (Table 20 and Table 21).

Timer 2 operating mode

T2CON - Timer/Counter 2 control register (address C8H) bit allocation

T2CON - Timer/Counter 2 control register (address C8H) bit description

T2MOD - Timer 2 mode control register (address C9H) bit allocation

T2MOD - Timer 2 mode control register (address C9H) bit description

Capture mode
In the Capture Mode there are two options which are selected by bit EXEN2 in T2CON. If EXEN2 = 0 Timer 2 is a 16-bit timer or counter (as selected by C/T2 in T2CON) which upon overflowing sets bit TF2, the Timer 2 overflow bit. The capture mode is illustrated in Figure 11.

This bit can be used to generate an interrupt (by enabling the Timer 2 interrupt bit in the IEN0 register). If EXEN2 = 1, Timer 2 operates as described above, but with the added feature that a 1- to 0 transition at external input T2EX causes the current value in the Timer 2 registers, TL2 and TH2, to be captured into registers RCAP2L and RCAP2H, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2 like TF2 can generate an interrupt (which vectors to the same location as Timer 2 overflow interrupt). The Timer 2 interrupt service routine can interrogate TF2 and EXF2 to determine which event caused the interrupt. There is no reload value for TL2 and TH2 in this mode. Even when a capture event occurs from T2EX, the counter keeps on counting T2 pin transitions or fosc/6 pulses. Since once loaded contents of RCAP2L and RCAP2H registers are not protected, once Timer2 interrupt is signalled it has to be serviced before new

capture event on T2EX pin occurs. Otherwise, the next falling edge on T2EX pin will initiate reload of the current value from TL2 and TH2 to RCAP2L and RCAP2H and consequently corrupt their content related to previously reported interrupt. Auto-reload mode (up or down counter) In the 16-bit auto-reload mode, Timer 2 can be configured as either a timer or counter (via C/T2 in T2CON), then programmed to count up or down. The counting direction is determined by bit DCEN (Down Counter Enable) which is located in the T2MOD register (see Table 20 and Table 21). When reset is applied, DCEN = 0 and Timer 2 will default to counting up. If the DCEN bit is set, Timer 2 can count up or down depending on the value of the T2EX pin. Figure 12 shows Timer 2 counting up automatically (DCEN = 0).

In this mode, there are two options selected by bit EXEN2 in T2CON register. If EXEN2 = 0, then Timer 2 counts up to 0FFFFH and sets the TF2 (Overflow Flag) bit upon overflow. This causes the Timer 2 registers to be reloaded with the 16-bit value in RCAP2L and RCAP2H. The values in RCAP2L and RCAP2H are preset by software means. Auto reload frequency when Timer 2 is counting up can be determined from this formula:

Where Supply Frequency is either fosc (C/T2 = 0) or frequency of signal on T2 pin (C/T2 = 1). If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at input T2EX. This transition also sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be generated when either TF2 or EXF2 is 1 . Microcontroller s hardware will need three consecutive machine cycles in order to recognize falling edge on T2EX and set EXF2 = 1: in the first machine cycle pin T2EX has to be sampled as 1 ; in the second machine cycle it has to be sampled as 0 , and in the third machine cycle EXF2 will be set to 1 .

In Figure 13, DCEN = 1 and Timer 2 is enabled to count up or down. This mode allows pin T2EX to control the direction of count. When a logic 1 is applied at pin T2EX Timer 2 will count up. Timer 2 will overflow at 0FFFFH and set the TF2 flag, which can then generate an interrupt, if the interrupt is enabled. This timer overflow also causes the 16-bit value in RCAP2L and RCAP2H to be reloaded into the timer registers TL2 and TH2.

When a logic 0 is applied at pin T2EX this causes Timer 2 to count down. The timer will underflow when TL2 and TH2 become equal to the value stored in RCAP2L and RCAP2H. Timer 2 underflow sets the TF2 flag and causes 0FFFFH to be reloaded into the timer registers TL2 and TH2. The external flag EXF2 toggles

when Timer 2 underflows or overflows. This EXF2 bit can be used as a 17th bit of resolution if needed. Baud rate generator mode Bits TCLK and/or RCLK in T2CON allow the UART) transmit and receive baud rates to be derived from either Timer 1 or Timer 2 (See Section 7.5 UARTs on page 35 for details). When TCLK = 0, Timer 1 is used as the UART transmit baud rate generator. When TCLK = 1, Timer 2 is used as the UART transmit baud rate generator. RCLK has the same effect for the UART receive baud rate. With these two bits, the serial port can have different receive and transmit baud rates Timer 1 or Timer 2. Figure 14 shows Timer 2 in baud rate generator mode:

The baud rate generation mode is like the auto-reload mode, when a rollover in TH2 causes the Timer 2 registers to be reloaded

with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. The baud rates in modes 1 and 3 are determined by Timer 2 s overflow rate given below: Modes 1 and 3 Baud Rates = Timer 2 Overflow Rate/16 The timer can be configured for either timer or counter operation. In many applications, it is configured for timer' operation (C/T2 = 0). Timer operation is different for Timer 2 when it is being used as a baud rate generator. Usually, as a timer it would increment every machine cycle (i.e., 16 the oscillator frequency). As a baud rate generator, it increments at the oscillator frequency. Thus the baud rate formula is as follows:
Modes 1 and 3 Baud Rates =

Where: (RCAP2H, RCAP2L) = The content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. The Timer 2 as a baud rate generator mode is valid only if RCLK and/or TCLK = 1 in T2CON register. Note that a rollover in TH2 does not set TF2, and will not generate an interrupt. Thus, the Timer 2 interrupt does not have to be disabled when Timer 2 is in the baud rate generator mode. Also if the EXEN2 (T2 external enable flag) is set, a 1-to-0 transition in

T2EX (Timer/counter 2 trigger input) will set EXF2 (T2 external flag) but will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2). Therefore when Timer 2 is in use as a baud rate generator, T2EX can be used as an additional external interrupt, if needed. When Timer 2 is in the baud rate generator mode, one should not try to read or write TH2 and TL2. Under these conditions, a read or write of TH2 or TL2 may not be accurate. The RCAP2 registers may be read, but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers. Table 22 shows commonly used baud rates and how they can be obtained from Timer 2. Summary of baud rate equations Timer 2 is in baud rate generating mode. If Timer 2 is being clocked through pin T2(P1.0) the baud rate is: Baud rate = Timer 2 overflow rate / 16 If Timer 2 is being clocked internally, the baud rate is: Baud rate = fosc / (16 (65536 - (RCAP2H, RCAP2L))) Where fosc = oscillator frequency

To obtain the reload value for RCAP2H and RCAP2L, the above equation can be rewritten as: RCAP2H, RCAP2L = 65536 - fosc / (16 baud rate) Table 22: Timer 2 generated commonly used baud rates

UART
The UART operates in all standard modes. Enhancements over the standard 80C51 UART include Framing Error detection, and automatic address recognition. Mode 0

Serial data enters and exits through RxD and TxD outputs the shift clock. Only 8 bits are transmitted or received, LSB first. The baud rate is fixed at 16 of the CPU clock frequency. UART configured to operate in this mode outputs serial clock on TxD line no matter whether it sends or receives data on RxD line. Mode 1 10 bits are transmitted (through TxD) or received (through RxD): a start bit (logical 0), 8 data bits (LSB first), and a stop bit (logical 1). When data is received, the stop bit is stored in RB8 in Special Function Register SCON. The baud rate is variable and is determined by the Timer 12 overflow rate. Mode 2 11 bits are transmitted (through TxD) or received (through RxD): start bit (logical 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logical 1). When data is transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of 0 or (e.g. the parity bit (P, in the PSW) could be moved into TB8). When data is received, the 9th data bit goes into RB8 in Special Function Register SCON, while the stop bit is ignored. The baud rate is programmable to either

116 or 132 of the CPU clock frequency, as determined by the SMOD1 bit in PCON. Mode 3 11 bits are transmitted (through TxD) or received (through RxD): a start bit (logical 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logical 1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable and is determined by the Timer 1/2 overflow rate.

Table 23: SCON - Serial port control register (address 98H) bit allocation

Table 24: SCON - Serial port control register (address 98H) bit description

Table 25: SCON - Serial port control register (address 98H) SM0/SM1 mode definition

Framing error
Framing error (FE) is reported in the SCON.7 bit if SMOD0 (PCON.6) = 1. If SMOD0 = 0, SCON.7 is the SM0 bit for the UART, it is recommended that SM0 is set up before SMOD0 is set to 1 . More about UART mode 1 Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divideby-16 counter is immediately reset to align its rollovers with the boundaries of the incoming bit times. The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done for noise rejection. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to0 transition. This is to provide rejection of false start bits. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is

generated: (a) RI = 0, and (b) Either SM2 = 0, or the received stop bit = 1. If either of these two conditions is not met, the received frame is irretrievably lost. If both conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF, and RI is activated. More about UART modes 2 and 3 Reception is performed in the same manner as in mode 1. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: (a) RI = 0, and (b) Either SM2 = 0, or the received 9th data bit = 1. If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set. If both conditions are met, the received 9th data bit goes into RB8, and the first 8 data bits go into SBUF. Multiprocessor communications UART modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received or transmitted. When data is received, the 9th bit is stored in RB8. The UART can be programmed so that when the stop bit is received, the serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit SM2 in SCON. One way to use this feature in multiprocessor systems is as follows:

When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in a way that the 9th bit is 1 in an address byte and 0 in the data byte. With SM2 = 1, no slave will be interrupted by a data byte, i.e. the received 9th bit is 0 . However, an address byte having the 9th bit set to 1 will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed or not. The addressed slave will clear its SM2 bit and prepare to receive the data (still 9 bits long) that follow. The slaves that weren t being addressed leave their SM2 bits set and go on about their business, ignoring the subsequent data bytes. SM2 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the stop bit, although this is better done with the Framing Error flag. When UART receives data in mode 1 and SM2 = 1, the receive interrupt will not be activated unless a valid stop bit is received.

2. RTC (DS1307):
FEATURES  Real-time clock (RTC) counts seconds, minutes, hours, date of the month, month, day of the week, and year with leap-year compensation valid up to 2100  56-byte, battery-backed, nonvolatile (NV) RAM for data storage  Two-wire serial interface  Programmable square wave output signal  Automatic power-fail detect and switch circuitry  Consumes less than 500nA in battery backup mode with oscillator running  Optional industrial temperature range: -40C to +85C  Available in 8-pin DIP or SOIC  Underwriters Laboratory (UL) recognized PIN ASSIGNMENT

PIN DESCRIPTION VCC - Primary Power Supply X1, X2 - 32.768kHz Crystal Connection VBAT - +3V Battery Input GND - Ground SDA - Serial Data SCL - Serial Clock

SQW/OUT - Square Wave/Output Driver DESCRIPTION The DS1307 Serial Real-Time Clock is a low-power; full binary-coded decimal (BCD) clock/calendar plus 56 bytes of NV SRAM. Address and data are transferred serially via a 2-wire, bi-directional bus. The clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The end of the month date is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with AM/PM indicator. The DS1307 has a built-in power sense circuit that detects power failures and automatically switches to the battery supply.

TYPICAL OPERATING CIRCUIT

OPERATION The DS1307 operates as a slave device on the serial bus. Access is obtained by implementing a START condition and providing a device identification code followed by a register address. Subsequent registers can be accessed sequentially until a STOP condition is executed. When VCC falls below 1.25 x VBAT the device terminates an access in progress and resets the device

address counter. Inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from an out of tolerance system. When VCC falls below VBAT the device switches into a lowcurrent battery backup mode. Upon power-up, the device switches from battery to VCC when VCC is greater than VBAT + 0.2V and recognizes inputs when VCC is greater than 1.25 x VBAT. The block diagram in Figure 1 shows the main elements of the serial RTC.

DS1307 BLOCK DIAGRAM Figure 1

SIGNAL DESCRIPTIONS VCC, GND DC power is provided to the device on these pins. VCC is the +5V input. When 5V is applied within normal limits, the device is fully accessible and data can be written and read. When a 3V battery is connected to the device and VCC is below 1.25 x VBAT, reads and writes are inhibited. However, the timekeeping function continues unaffected by the lower input voltage. As VCC falls below VBAT the RAM and timekeeper are switched over to the external power supply (nominal 3.0V DC) at VBAT. VBAT Battery input for any standard 3V lithium cell or other energy source. Battery voltage must be held between 2.0V and 3.5V for proper operation. The nominal write protect trip point voltage at which access to the RTC and user RAM is denied is set by the internal circuitry as 1.25 x VBAT nominal. A lithium battery with 48mAhr or greater will back up the DS1307 for more than 10 years in the absence of power at 25C. UL recognized to ensure against reverse charging current when used in conjunction with a lithium battery. See Conditions of Acceptability at http://www.maximic.com/TechSupport/QA/ntrl.htm. SCL (Serial Clock Input) SCL is used to synchronize data movement on the serial interface. SDA (Serial Data Input/Output) SDA is the input/output pin for the 2-wire serial interface. The SDA pin is open drain which requires an external pullup resistor. SQW/OUT (Square Wave/Output Driver) When enabled, the SQWE bit set to 1, the SQW/OUT pin outputs one of four square wave frequencies (1Hz, 4kHz, 8kHz, 32kHz). The SQW/OUT pin is open drain and requires an external pull-up resistor. SQW/OUT will operate with either Vcc or Vbat applied. X1, X2 Connections for a standard 32.768kHz quartz crystal. The internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (CL) of 12.5pF. For more information on crystal selection and crystal layout considerations, please consult Application Note 58, Crystal Considerations with Dallas Real-Time Clocks. The DS1307 can also be driven by an external 32.768kHz oscillator. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated.

RECOMMENDED LAYOUT FOR CRYSTAL

CLOCK ACCURACY The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional error will be added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the oscillator circuit may result in the clock running fast. See Application Note 58, Crystal Considerations with Dallas Real-Time Clocks for detailed information. Please review Application Note 95, Interfacing the DS1307 with a 8051Compatible Microcontroller for additional information. RTC AND RAM ADDRESS MAP The address map for the RTC and RAM registers of the DS1307 is shown in Figure 2. The RTC registers are located in address locations 00h to 07h. The RAM registers are located in address locations 08h to 3Fh. During a multi-byte access, when the address pointer reaches 3Fh, the end of RAM space, it wraps around to location 00h, the beginning of the clock space. DS1307 ADDRESS MAP Figure 2

CLOCK AND CALENDAR The time and calendar information is obtained by reading the appropriate register bytes. The RTC registers are illustrated in Figure 3. The time and calendar are set or initialized by writing the appropriate register bytes. The contents of the time and calendar registers are in the BCD format. Bit 7 of register 0 is the clock halt (CH) bit. When this bit is set to a 1, the oscillator is disabled. When cleared to a 0, the oscillator is enabled. Please note that the initial power-on state of all registers is not defined. Therefore, it is important to enable the oscillator (CH bit = 0) during initial configuration. The DS1307 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the 12- or 24-hour mode select bit. When high, the 12hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10 hour bit (20-23 hours). On a 2-wire START, the current time is transferred to a second set of registers. The time information is read from these secondary registers, while the clock may continue to run. This eliminates the need to reread the registers in case of an update of the main registers during a read. DS1307 TIMEKEEPER REGISTERS Figure 3

CONTROL REGISTER
The DS1307 control register is used to control the operation of the SQW/OUT pin.

OUT (Output control): This bit controls the output level of the SQW/OUT pin when the square wave output is disabled. If SQWE = 0, the logic level on the SQW/OUT pin is 1 if OUT = 1 and is 0 if OUT = 0. SQWE (Square Wave Enable): This bit, when set to a logic 1, will enable the oscillator output. The frequency of the square wave output depends upon the value of the RS0 and RS1 bits. With the square wave output set to 1Hz, the clock registers update on the falling edge of the square wave. RS (Rate Select): These bits control the frequency of the square wave output when the square wave output has been enabled. Table 1 lists the square wave frequencies that can be selected with the RS bits. SQUAREWAVE OUTPUT FREQUENCY Table 1

2-WIRE SERIAL DATA BUS The DS1307 supports a bi-directional, 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter and

a device receiving data as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are referred to as slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The DS1307 operates as a slave on the 2wire bus. A typical bus configuration using this 2-wire protocol is show in Figure 4. TYPICAL 2-WIRE BUS CONFIGURATION Figure 4

Figures 5, 6, and 7 detail how data is transferred on the 2-wire bus. _ Data transfer may be initiated only when the bus is not busy. _ During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is high will be interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain HIGH. Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition. Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition. Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is not limited, and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a

ninth bit. Within the 2-wire bus specifications a regular mode (100 kHz clock rate) and a fast mode (400 kHz clock rate) are defined. The DS1307 operates in the regular mode (100 kHz) only. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.

DATA TRANSFER ON 2-WIRE SERIAL BUS Figure 5

Depending upon the state of the R/W bit, two types of data transfer are possible: 1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of

data bytes. The slave returns an acknowledge bit after each received byte. Data is transferred with the most significant bit (MSB) first. 2. Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit. This is followed by the slave transmitting a number of data bytes. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a not acknowledge is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus will not be released. Data is transferred with the most significant bit (MSB) first. The DS1307 may operate in the following two modes: 1. Slave receiver mode (DS1307 write mode): Serial data and clock are received through SDA and SCL. After each byte is received an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and *direction bit (See Figure 6). The address byte is the first byte received after the start condition is generated by the master. The address byte contains the 7 bit DS1307 address, which is 1101000, followed by the *direction bit (R/W ) which, for a write, is a 0. After receiving and decoding the address byte the device outputs an acknowledge on the SDA line. After the DS1307 acknowledges the slave address + write bit, the master transmits a register address to the DS1307 this will set the register pointer on the DS1307. The master will then begin transmitting each byte of data with the DS1307 acknowledging each byte received. The master will generate a stop condition to terminate the data write. DATA WRITE SLAVE RECEIVER MODE Figure 6

2. Slave transmitter mode (DS1307 read mode): The first byte is received and handled as in the slave receiver mode. However, in this mode, the *direction bit will indicate that the transfer direction is reversed. Serial data is transmitted on SDA by the DS1307 while the serial clock is input on SCL.

START and STOP conditions are recognized as the beginning and end of a serial transfer (See Figure 7). The address byte is the first byte received after the start condition is generated by the master. The address byte contains the 7-bit DS1307 address, which is 1101000, followed by the *direction bit (R/W ) which, for a read, is a 1. After receiving and decoding the address byte the device inputs an acknowledge on the SDA line. The DS1307 then begins to transmit data starting with the register address pointed to by the register pointer. If the register pointer is not written to before the initiation of a read mode the first address that is read is the last one stored in the register pointer. The DS1307 must receive a not acknowledge to end a read. DATA READ SLAVE TRANSMITTER MODE Figure 7

3. Memory:
FEATURES

Low power CMOS technology Hardware write protect Two wire serial interface bus, I2C compatible 5.0V only operation Self-timed write cycle (including auto-erase) Page-write buffer 1ms write cycle time for single byte 1,000,000 Erase/Write cycles guaranteed Data retention >200 years 8-pin DIP/SOIC packages Available for extended temperature ranges - Commercial (C): 0C to +70C - Industrial (I): -40C to +85C - Automotive (E): --40C to +125C

DESCRIPTION

The Microchip Technology Inc. 24C01A/02A/04A is a 1K/2K/4K bit Electrically Erasable PROM. The device is organized as shown, with a standard two wire serial interface. Advanced CMOS technology allows a significant reduction in power over NMOS serial devices. A special feature in the 24C02A and 24C04A provides hardware write protection for the upper half of the block. The 24C01A and 24C02A have a page write capability of two bytes and the 24C04A has a page length of eight bytes. Up to eight 24C01A or 24C02A devices and up to four 24C04A devices may be connected to the same two wire bus. This device offers fast (1ms) byte write and extended (-40C to 125C) temperature operation. It is recommended that all other applications use Microchip s 24LCXXB.

4. Keypad: Here we have used a normal 4x3 matrix key pad. Which can be used to give input of numbers from 0 to 9, * and #. 5. ULN2003 The eight NPN Darlington connected transistors in this family of arrays are ideally suited for interfacing between low logic level digital circuitry (such as TTL, CMOS or PMOS/NMOS) and the higher current/voltage requirements of lamps, relays, printer hammers or other similar loads for a broad range of computer, industrial, and consumer applications. All devices feature open collector outputs and freewheeling clamp diodes for transient suppression. MAXIMUM RATINGS (TA = 25C and rating apply to any one device in the package, unless otherwise noted.)

TEST FIGURES (See Figure Numbers in Electrical Characteristics Table)

TYPICAL CHARACTERISTIC CURVES TA = 25C, unless otherwise noted Output Characteristics

Input Characteristics

Figure 12. Representative Schematic Diagrams

6. Relay: Here we are using relay as switch. to make device ON and OFF automatically /********************************************************* Source code for the project ---------------------------Main program *********************************************************/ //****************************************************************** ***************************/ // PROJECT NAME : TIMELY OPERATED ELECTRICAL APPLIANCE CONTROL SYSTEM // MODULE NAME : MAIN // FILE NAME // ABSTRACT : MAIN.C : THIS FILE IMPLEMENTS A DEVICE FOR

P89V51RD2 TO DEVOLOP A SYSTEM WHICH WILL // TIMELY OPERATE THE ELECTRICAL APPLIANCE

CONNECTED TO THE DEVICE

// COMPILER // AUTHOR // Date :

: KEIL 3 : V.V.GUPTA FOR AKSHARA TECHNOLOGIES 13 APR 2009

//REVISED DATE : // WARNING:THIS FILE HAS BEEN AUTOMATICALLY

GENERATE.DO NOT EDIT THIS FILE IF U // INTEND TO REGENERATE IT .

//****************************************************************** ****************************/ //=================================================== =] // Include Librarry Files

//=================================================== =] #include <reg51F.H> #include"rtc.c" #include"kb2p.h" #include"lcd.C"

#include"i2c.C" sbit relay = P3^5; sbit reset= P3^4; sbit Watch_dog_refresh =WDTC^1; sbit Watch_dog_status=WDTC^2;

unsigned char hour=0x12, min=0x59, sec=0x00;

void iitoa(unsigned char a) { int c1,c2; c2=a; c1=a&0x0f; c1=c1|0x30; c2=c2>>4; c2=c2|0x30;

LCD_DATA_WRT(c2); LCD_DATA_WRT(c1);

} void m_delay() { long int a; for (a=0;a<4400;a++);

void s_delay() { long int a; for (a=0;a<9999;a++);

void delay() { long i; for(i=0;i<99999;i++); } unsigned char ch,ch_h,ch_m,ch_s, h_l,h_m,key, al_hr_on[10],al_min_on[10], al_hr_off,al_min_off; int index; int j=0;

/******************************************************************* ************************ main starts here ******************************************************************** ***********************/ main()

{ int k,s=0,q,m=0;

P2 =0xFF;

IE=0x85; EX1=1; //Enable external interrupt 1 EX0=1; //Enable external interrupt 0 EA=1; //Global interrupt enable

LCD_INIT(); PRINTLCD("Akshara Technologies"); s_delay(); s_delay(); LCD_CMD_WRT(0x01);

while(1) { LCD_CMD_WRT(0x0C); LCD_CMD_WRT(0x85); ch_h= R_ReadBYTE(0x02);

iitoa(ch_h); LCD_DATA_WRT(':'); //send_char(':'); ch_m= R_ReadBYTE(0x01);

iitoa(ch_m); //send_char(':'); LCD_DATA_WRT(':'); ch_s= R_ReadBYTE(0x00);

q = R_ReadBYTE(0x03); iitoa(ch_s); for(k=0;k<=10;k++) {

al_hr_on[k] = ReadBYTE(0x00+(0x10*k)); al_min_on[k] = ReadBYTE(0x08+(0x10*k)); if(ch_h == al_hr_on[k] && ch_m == al_min_on[k] && ch_s == 0x00 && q!=0x01) { relay=0; break; } else if(ch_h == al_hr_on[k] && ch_m == al_min_on[k] && ch_s == 0x03 && q!=0x01) { relay=1; break; }

s_delay(); m_delay();

//if(Watch_dog_status == 1) //{ //WDTC =0x00; //Watch_dog_status = 1; //} //send_string("\n\r"); } }

void current_time(void) interrupt 0

{ unsigned char day, d_m,d_l, month, m_m,m_l, year, y_l,y_m; LCD_CMD_WRT(0x01); PRINTLCD(" Enter Time");

LCD_CMD_WRT(0xC5); //LCD_CMD_WRT(0x01); PRINTLCD("hh:mm "); LCD_CMD_WRT(0xC5); //getting hour from the user key = scan_key(); LCD_DATA_WRT(key); s_delay(); h_m = key&0x0f; h_m = h_m<<0x04; key = scan_key(); LCD_DATA_WRT(key);

s_delay(); h_l = key&0x0f; hour= h_m|h_l;

LCD_CMD_WRT(0xC8); // getting mins from the user key = scan_key(); LCD_DATA_WRT(key); s_delay(); h_m = key&0x0f; h_m = h_m<<0x04; key = scan_key(); LCD_DATA_WRT(key); s_delay(); h_l = key&0x0f; min= h_m|h_l;

R_WriteBYTE(0x00,sec); R_WriteBYTE(0x01,min); R_WriteBYTE(0x02,hour);

LCD_CMD_WRT(0x01);

PRINTLCD(" Enter DATE");

LCD_CMD_WRT(0xC5); PRINTLCD("DD/MM/YY"); LCD_CMD_WRT(0xC5); key = scan_key(); LCD_DATA_WRT(key); s_delay();

d_m = key&0x0f; d_m = d_m<<0x04; key = scan_key(); LCD_DATA_WRT(key); s_delay(); d_l = key&0x0f; day = d_m|d_l;

LCD_CMD_WRT(0xC8); key = scan_key(); LCD_DATA_WRT(key); s_delay(); m_m = key&0x0f; m_m = m_m<<0x04; key = scan_key(); LCD_DATA_WRT(key); s_delay();

m_l = key&0x0f; month = m_m|m_l;

LCD_CMD_WRT(0xCB); key = scan_key(); LCD_DATA_WRT(key); s_delay(); y_m = key&0x0f; y_m = y_m<<0x04; key = scan_key(); LCD_DATA_WRT(key); s_delay(); y_l = key&0x0f; year = y_m|y_l; LCD_CMD_WRT(0x01);

R_WriteBYTE(0x04,day); R_WriteBYTE(0x05,month); R_WriteBYTE(0x06,year);

PRINTLCD(" Enter DAY"); LCD_CMD_WRT(0xC5); key = scan_key(); LCD_DATA_WRT(key); s_delay(); d_m = key&0x0f; d_m = d_m<<0x04; key = scan_key(); LCD_DATA_WRT(key); s_delay(); d_l = key&0x0f;

day = d_m|d_l; R_WriteBYTE(0x03,day); LCD_CMD_WRT(0x01); }

void set_schedule(void) interrupt 2 { unsigned char ch,f=1;

{ while(1) { LCD_CMD_WRT(0x01); PRINTLCD("1: ADD ON time "); LCD_CMD_WRT(0xC0); PRINTLCD("2: EXIT "); ch=scan_key();

if (ch == '1') { LCD_CMD_WRT(0x01); PRINTLCD(" enter ON time");

LCD_CMD_WRT(0xC5); PRINTLCD("hh:mm "); LCD_CMD_WRT(0xC5); key = scan_key(); LCD_DATA_WRT(key); s_delay(); h_m = key&0x0f; h_m = h_m<<0x04; key = scan_key(); LCD_DATA_WRT(key); s_delay();

h_l = key&0x0f; al_hr_on[j]= h_m|h_l;

WriteBYTE((0x00+(0x10*j)),al_hr_on[j]);

LCD_CMD_WRT(0xC8); key = scan_key(); LCD_DATA_WRT(key); s_delay(); h_m = key&0x0f; h_m = h_m<<0x04; key =scan_key(); LCD_DATA_WRT(key); s_delay(); h_l = key&0x0f; al_min_on[j]= h_m|h_l;

WriteBYTE((0x08+(0x10*j)),al_min_on[j]); ++j; LCD_CMD_WRT(0x01); }

else if (ch == '2') { LCD_CMD_WRT(0x01); index=j; break; } } } }