Calibration techniques for

Pipeline ADCs
Dr. Jose Silva-Martinez
Department of ECE
Texas A&M University
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State of the art
WiMAX
100mW @10MHz
10mW @10MHz
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Pipelined ADC: Design Issues
High speed and high resolution can be achieved with
pipelined ADCs.
The conversion process is divided into several stages
Digital correction (comparator redundancy)
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Reference voltages
Errors in reference voltages are a large source of distortion.
Bondwire inductance and switching activity in the pipeline can
cause ringing
The clock speed in the graph below was 100 MHz
For comparison: the quantization level of a 14 bit ADC is in the
order of 10
-4
V.
2.5 mV
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Traditionally, a large off-chip capacitor is used to
stabilize the reference voltages
One possible solution: a distributed set of buffers, but
Gain and offsets errors will result in static reference
errors which can easily be corrected for through
calibration.
Consider adding on-chip Low-Drop-Out regulators
Reference voltages
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Digital Calibration Techniques for
High-Resolution, High-Speed
Pipelined ADCs
Motivation:
Non-calibrated Pipeline ADCs achieve < 11 bits
Can the pipeline ADC be improved to achieve >14 bits resolution?
Analog resolutions is getting worse with technology scaling
Digital Assisted ADCs are more attractive for deep submicron
technologies
Digital is more robust and cheap for high-performance and complex
processing
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Calibration may be required to correct for the errors
There are two main categories of calibration schemes:
Foregound (off-line) calibration: the conversion process is
interrupted
Background (online) calibration: the calibration process runs in
the background without manual interaction
Calibration
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Newer nano-meter CMOS technologies suffer
from large component non-linearities
This makes analog calibration techniques
unreliable (move to digital domain)
Non-linear errors are difficult to correct for
Static errors (such as capacitor mismatch, and
linear finite op-amp gain) can be effectily corrected
for through digital calibration
Calibration Techniques
9
Calibration Methodology
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Non-idealities include
capacitor mismatch ratio
finite (and possibly non-linear) amplifier gain
reference voltages errors
charge injection and offsets
Calibration Issues
Historical Lessons:
Learn from the past, otherwise your destiny is to repeat common
and historical mistakes
The word NEW means new! Then before claiming that this is
new (novel, innovative), etc. double check the literature!
50 years of Micro-electronics. It makes sense to expect many
architectures not being extensively used, but interesting! Many
things to learn from those old papers, but hard to find the good
ones! Shannon developed the digital communication theory back in
the 30s but extensively used till the 90s.
People in the past were more accustom to use pencil and then they
got very good insides
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Existing Calibration Techniques
If you can measure then you can compensate or fix it
Apply an on-chip generated very linear ramp to find the INL
response of the ADC, then calibrate in digital.
Requires additional area and power for ramp generation
Calibration only occurs when the ramp is applied (doesnt
automatically track time-varying errors)
Digital based
calibration
technique, but..
Linearity of the ramp
should be better than
the resolution of the
calibrated ADC
Option: Digital ramp
with very linear DAC!
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This is an example of an Analog Calibration:
Low speed
Calibration is done during the interframe intervals
Take advantage of the particular implementation and idle times available
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Analog Calibration: Measure the gain using capacitor
dividers, then use capacitive banks to compensate it
Effects of the parasitic capacitors?
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LMS Calibration schemes
This is an example of an Un-calibrated ADC:
Errors due to C1 and C2 are sampled but what about C3 and C4?
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Low speed ADC
SNR =12 bits
SDR=15 bits
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Have a look on the floor Planning
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20
21
22
23
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Error is
digitized
here!
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27
28
29
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Randomization:
Dynamic Element
Matching!
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33
34
REF in res
bV V V = 2
Digital Residue
This is a paper
everybody should
read!
Many good ideas, not
all new but very
good!
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The error is then obtained after LP filtering. PN is a pseudo-Random sequence
integral of PN after a number of samples goes to zero.
The Verror can be measured in digital format, and then it can be calibrated
( )
REF
Digital
error
V V
PN Filtering LP After
c + ~
=
1
1 :
2
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Extensive digital processing
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Extensive digital processing
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40
41
42
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LMS Calibration Schemes
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Open-loop amplifiers will
significantly reduce power
consumption, but bring in other
relevant issues
A calibration scheme to correct for
non-linearities switched between
two residue curves and measurer
the distance between the two
responses.
Uses a complex digital statistical
estimation algorithm to find the non-
linearity.
LMS Calibration schemes
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LMS Calibration LMS based
Background calibration scheme with a digital Least-Mean-Square
(LMS) algorithm
Find the error between the output of the ADC and an reference ADC
Update a set of calibration parameters based on the error information
The reference ADC is much slower than the main ADC
Automatically tracks changes in the ADC over time
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For practical implementations only the first few stages will require
calibration
Calibration Algorithm:
1. Initialize calibration parameters b
i
2. Compute error =D
ideal
- D
out
3. Modify b
i
as:
i
old i new i
b
b b
c
c
=
c
u
, ,
is the step-size of the LMS algorithm (programmable)
To avoid multipliers, a sign-sign version can be used:
) ( * ) ( *
, , out old i new i
D sign sign b b c u

+ =
LMS Calibration LMS based
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Only the sign of the error and the output is required
Therefore, an entire ADC in parallel is unnecessary
) D ( sign ) ( sign b b
out old , i new , i
c u + =

Calibration update equation:
Calibration Methodology
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Simulation results (target resolution was 14-bits):
SFDR (dB) SNDR (dB) INL (LSBs) DNL (LSBs)
Corr. with NL 96.5 80.2 1 0.45
Uncorr. with NL 49.9 47.7 70 132
Corr. without NL 97.1 80.0 1.2 0.8
Uncorr. without NL 55.3 52.7 41 71
Corr. - only linear cal.
param. with NL.
65.8 62.4 6 5
LMS Calibration LMS based
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Yung Chiu, TCAS-2004, January
Calibrating signal
Reference signal
Simulation results:
GBW effects only!
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Calibration Techniques
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Region A: D
i
= 0 & sign(D
out
)=1 => sign(error)=-1
Region B: D
i
= 1 & sign(D
out
)=0 => sign(error)=+1
Main issues: Measure the zero crossing and slope errors.
If so, you can calibrate it in digital
Calibration Methodology
53
( )
) ( sign
) D ( sign ) ( sign
D Dout F D
old new
est old new
out est
c u + | = |
c u + o = o
| + o = =

Calibration Methodology [5]

Andreas will cover this topic in more detail
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For a 1.5 bit/stage pipeline with
finite amplifier gain, A
capacitor mismatch ratio
non-ideal reference, V
ref
=>*V
ref
|
|
.
|

\
|
+
+ +
=
2
1
2
1
1
1
2
C
C
A
A
C
C
ideal
o
2
1
2
1
1
2
C
C
C
C
V V
ref ref ideal
+
= |
The calibration parameters will converge to this unique solution with
enough samples
Calibration Methodology
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It is sometimes desirable to convert more bits in the first stage, the
MSB stage (to reduce over-all power requirements and for accuracy
reasons).
Shown below is the residue curve of a 2.5 bit/stage pipeline stage
Region Comparator
threshold
(differential)
Binary output
[D2 D1 D0]
1 -5Vref/8 000
2 -3Vref/8 001
3 -Vref/8 010
4 Vref/8 011
5 3Vref/8 100
6 5Vref/8 101
7 110
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This stage can be implemented with
a single op-amp like before, but with
more capacitors to obtain a gain of
four.
0
4
0
3
0
2
0
1
C
C
C
C
C
C
C
C
C + + + =
( )
( ) ,
C
C
V
C
C
V
C
C
V C 1 V
C 1
A
1
1
1
V
0
3
3 , r
0
2
2 , r
0
1
1 , r in out
o +
|
|
.
|

\
|
+
+ +
=
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Analytical expressions for , :
( )
3 ,
3 ,
1
1
4
r
r
ideal
C A
A C
+
+ +
= o
3 ,
3 , 1 ,
1
4
3
r
r ref ref ideal
C
C V V
+
= |
3 ,
2 , 2 ,
1
4
2
r
r ref ref ideal
C
C V V
+
= |
3 ,
1 , 3 ,
1
4
r
r ref ref ideal
C
C V V
+
= |
=
=
i
k
i
i r
C
C
C
1
0
,
Simulations show that we loose several dB of SNDR if only one
parameter is used for all three regions
Therefore, we need either three ideal comparators, or one
comparator with adjustable reference levels
Only one comparator leads to extra circuitry for switching the
reference levels
58
The critical issue of this
scheme is the need of quasi-
ideal comparators
They must have very small
offsets and will require
individual offset cancellation
schemes
For a 14-bit ADC with V
ref
=1
V, the resolution is roughly
100 V (=1 LSB)
When the offset is refereed
to the input, it should be <
0.5 LSB
Upper limit of about 50 V
for the offset
Calibration Methodology: Practical issues
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Shown below is the output power spectrum vs normalized
frequency
No comparator offset 0.5 LSB comparator offset
Calibration Methodology
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Open problems:
Offset cancellation scheme for comparators; still looking for best
implementation
One or three comparators for the MSB stage?
On-chip reference voltage generation (using band-gap circuits and
LDOs)?
Calibration Methodology
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References
[1] B. Provost, E. Snchez-Sinencio, A Practical Self-Calibration Scheme
Implementation for Pipeline ADC. IEEE TRANSACTIONS ON
INSTRUMENTATION AND MEASUREMENT, VOL. 53, NO. 2, APRIL 2004
[2] U. K. Moon, B. S. Song,Background Calibration Techniques for Pipelined
ADCs, IEEE Transactions on Circuits and Systems-II, SC-44, no. 2, pp.102
109, Feb 1997.
[3 A. Savla, J. Leonard, A. Ravindran, Error Correction Ii Pipelined ADCs Using
Arbitrary Radix Calibration, Proceedings of the 17th International Conference
on VLSI Design (VLSID04)
[4] B. Murmann, B.E. Boser. A 12-bit 75-MS/s pipelined ADC using open-loop
residue amplification. IEEE JSSC, 38(12): 2040-2050, Dec. 2003
[5] A. Larsson, et.al., A Background Calibration Scheme for Pipelined ADCs
Including Non-linear Operational Amplifier Gain and Reference Error
Correction, IEEE SOC Conference, Sept. 2004