Influence of the State of Polysilicon/Silicon Dioxide Interface on MOS Properties

N. Lifhitz s. LWyi
Bell Laboratories Murray Hill, New Jersey 07974

ABSTRACT We suggest a that thin (5100 A) resistive sublayer of polysilicon near the oxideinterfacecanhaveapronouncedeffect on the MOScapacitance-voltagecharacteristics. On the depletion side of the C-V curve the lower effective work-function difference leads threshold inversion. higher a to for strong On the accumulation side the MOS capacitance is lowered due to the added thickness of the depletion sublayer. With the help of the sublayer model we attempt to explain the anomalous behavior observed often in MOS capacitors with silicide/polysilicon gates. The sublayer depletion activates traps due to the heavy impurities (Cu, and Fe, Ta) interface, at the considerable amount of which were observed in these samples by Auger spectroscopy.
1. INTRODUCTION

compared to that in the bulk

to enhanced resistivity.

of polysilicon which also contributes

The presence

of this resistive sublayer would produce

little

effect on such characteristics as

sheet resistivity of the polysilicon.

On the other hand it should manifest itself through a degradation of MOS C-V characteristics.Qualitatively, substrate,the becomesless effect is twofold.Firstly, steepandthreshold for n-poly gateand pthe slope of C-V curves n-channeldevices is

Voltageof

shiftedtohighervoltages.Secondly,the flat-band to weak-accumulationregion MOS capacitance-voltage curves and duetothe finite thickness

MOS capacitancein the

of the C-V curve is lower The latter

It is well

known that

of the resistive sublayer.

MOSFET thresholds are sensitive to the presence of various states in and oxide at the silicon-oxide interface [I]. One is usually withcharged

side effect is unobservable on the depletion disappears in strong accumulation.

of the curve and

concerned with the state of the Si/Si02 interface or states within the gate oxide rarely but

The purpose of this work is to suggest a possible explanation to the unusual behavior often observed in MOS devices containing a silicide-polysilicon gate structure with the metal silicide produced by sputtering and sintering. They consistently exhibited degraded characteristics after high temperature sintering. believe We that
our model which postulates the existence of a resistive sublayer at

with those on theouter thelatter is well

interface of the oxides. Of course, neglecting justified when the layerimmediatelyover highly doped polysilicon.

the oxide is ametal or

C-V

The situation may be quite different when the doping profile in a polysilicon gate is nonuniform.In very thin
(-100

particular,one

may havea

poly/Si02interfacecanaccountfor observedbehavior.From

all essentialfeatures

of the

A)

but sublayer resistive polysilicon of the gateoxide. Theexistence of sucha

theobserved

C-V curves we make an

immediatelyadjacentto

estimate of the requiredthickness of the resistivelayer to be of order 60 A, which is not unreasonable. Furthermore, our model indirectly supported by Auger data [4] which showed large a poly/SiO2 interface.It segregate at the is is

layer can be brought about by the very presence of the poly/oxide boundary which serves as a natural stop for the diffusion of certain deep level impurities, such as

Cu and Fe. Moreover, in the vicinity

concentration of heavy impurities at the probable that impurities these

of the interface a greater percentage of donor impurities is inactive

(Cu and Fe)

interface during the sintering step.

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CH1832-5/82/0000-0054 $00.75 0 1982 IEEE

11. EXPERIMENTAL

theouterinterface,

viz. SiO2/poly,ratherthan

that of theinner

Thermal oxide
<loo>

4000

oxide interface, that was responsible for the degradation of the CV thick was grown on Wacker ptype characteristics.

orientedwafers.Thewaferswereimplantedthroughthe

oxide with boron to achieve a carrier concentration

06 of 4 . 1 l cm-3

To confirm this hypothesis we took some of the samples which exhibited the after-sintering characteristic (b) etched and the were still

at the S i i O z interface. The oxide was subsequently etched away anda

250

thickgateoxide

was grown. A polysiliconlayer of with phosphorus by

(2500

silicide away. After step measured this the curves identical to (b). However, after

thickness 3500

A was then deposited and doped

15 minutes of phosphorus

diffusion from PBr3source.Tantalumsilicidelayer cosputtered on polysilicon The surface.structure patternedandreactiveionetched with poly/silicide upper electrodes.
so astoform

A) was

diffusion at 9OO'C the MOS characteristics returned to their original undistorted shape, cf. curve in (c) Fig. 1. In our view, this

was then

MOS capacitors

experiment gives a conclusive evidence

of the importance of the

outer interface since a brief diffusion step could not possibly affect the inner interface.
30 min [2]. It was
111. THE MODEL

After patterning, the samples were sintered at 900'C for in Ar atmosphere to form a stable low-resistivity TaSi2 noticed that after the high temperature C-V sintering,

Our model assumes heavy impurities (e.g.,

that during the

high temperature sintering silicide

characteristics underwent a drastic change. A typical result is shown in Fig. 1. Before sintering the shape of the curve (a) is similar to that usually obtained with polysilicon gate (withoutsilicide).Aftersintering the CV curves(b)behaveina

Cu or Fe) which are present in the

or polysilicondiffuseinpolysilicontowards theinterface, giving rise toa high density

the oxide and sink at of surface traps of

acceptor On other type. the hand, dopant the concentration in polysiliconduringhightemperaturesintering is decreased dueto

manner similar to that usually attributed to the presence of a large number of interface traps 13). This characteristic behavior includes adegradedandvnevenslopeas well asawashedoutthreshold the

diffusion of phosphorus into silicides. The compensation effect of the surface trapsbrings about the formation layer in polysilicon. Next we consider the band diagram of the gate structure, Fig. 2. of ahighlyresistive

point. The unwelcome changes were clearly introduced during temperature sintering. Although the C-V characteristics shown in

can Fig. 1 (a,b)

Atequilibrium,Vo

= 0, the siliconlayerunder

the oxide is in of

undoubtedly be explained in a conventional way, assuming interface traps fixed and oxide charges atthe Si/SiOZ interface,suchan of crd hoc

depletion, Fig. 2a. The broken lines correspond to the presence

a depleted sublayer of polysilicon and solid lines show the case of a uniformly and heavily doped polysilicon. Consider now how our model explains the essential features of Firstly, the observed C-V characteristics. we note the that

explanation necessarily number would involve a assumptions.Inparticular,onewouldhavetopostulateaspecial

combination of interface traps and fixed oxide charges in order to explain theobservedintersection of curvesaand

b. Moreover,
to result from a

existence of the resistive layer lowers the built-in voltage between the n-polysilicon gate and the p s i substrate. This clearly increases the threshold voltage for strong inversion. In depletion at the same applied voltage, e.g., at Vr = 0, the electric field in the oxide is less

such a peculiar combination would appear unlikely

short 900'C sintering step. We were, therefore, led to consider an

alternativeexplanation,based

on the idea that it was the state of

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than in the ideal case, cf. Fig. 2a. This leads to narrower depletion region insiliconandhencehighercapacitance.Qualitatively,this effect is similar to the usual case when the traps are on the Si/Si02 interface. As usual, charging and discharging of the fast traps leads to a degraded slope of the C-V curve [31. However, the crossing of the original and degradedcurves In peculiar to our model. weak accumulation 2b) (Fig. the
lower capacitance. It

of the capacitor. However, during temperature high treatment redistribution of phosphorus between Furthermore, it is likely thatthesource contained the within poly and occurs. TaSi2 of heavy impurities is

T a i l layer so that the during

high-

temperature sintering the density of these impurities in polysilicon is is increased due to diffusion from the source. Quite effect of the heavyimpurities is depletethe mobilecharge. generally, the

is compensatingastheytrapand

existence of a depleted sublayer results in

In Fig.3 we plotsheetresistanceofa

easy to show that this sublayer of thickness d gives rise to a relative change in the capacitance AC/C given by:
AC -=--

poly layer 4000 A thick covered by a TaSil layer as a function of sintering temperature min. Ar). each (30 in After temperature cycle the silicidelayer was plasma-etchedandsheetresistance of

d do,

Cox

'
The

the poly layermeasured.Originalsheetresistance grew to 59 O D during the 900'Csintering processstep.It is plausible thatthischange

was 20 O D . It which is astandard is associated with a

where do, is the oxide thickness (-250

A)

and cox, c are,

respectively, the oxide and the polysilicon dielectric constants. maximum AC/C occurs at Vo givesd

= -1.4

v and equals

= 7% which

combination of depletion and compensation from the oxide interface.

of polysilicon away

60 A. Suchthickness of the resistivelayer seemsto us

As discussed above effects these are

notunreasonable.WecanalsoestimatefromPoisson'sequation the required density N- of fixed negative charge which accounts for the band bendingin thedepleted layer of polysilicon.With the

more nearboundary. such severe the Under conditions the detrimental effects of the contaminated interface come intoplay.
IV. CONCLUSION

above value for d one finds, typically,

N- of order lOI9 cm-). The by the it varies

actual amount of this charge is determined self-consistently position of the bands with respect to the Fermi level and higher negative voltages with the applied bias. At

We havesuggestedamodel circumstances state the of

which shows thatunder outer the oxide interface

certain

the depleted id4

(polysilicon/SiOz) havetangible can a detrimental effect the on

region is no longerpresentandthecapacitancereachesthe value associated only with the oxide. Auger spectroscopy studies (41 of samples consisting

MOS properties of capacitors and transistors with polysilicon gates.

It is an essential part of our model that a thin ( 5 100 A) depleted

of a

sublayercanexistinpolysiliconnear

the oxideboundary.In

the

sandwich of SiOl, polysilicon and Ta silicide give further support to our model. High density of impurities, such as Cu, Fe and Ta, was found the at poly-SiOz interface of the samples. The bulk of of any of these impurities. The

presence of the depleted sublayer impurities, such as Co, Fe and Ta which readily diffuse through form at traps the poly layer and are stopped by oxide,

poly-SiOz interface degrade and the

MOS

polysilicon did not show presence

properties of the structure. suggested tentative a explanation

With the help of our model we have for the observed anomalous

results indicate that the poly-Si02 interface indeed behaves as a sink for impurities.Whenpolysilicon under silicide is heavilydoped to the the MOS properties

behavior of MOS capacitors with silicide/polysilicon gates. Furtherexperimental work is clearly required interestarethe to confirm or mechanisms

with the mobile uniformly charge extending down contaminated interface, the latter cannot affect

reject our hypothesis.Ofparticular

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responsible for formation destruction the and

of the depleted
I .o

sublayer. We have suggested that the sublayer is formed during the sintering step due to diffusion of heavy impurities from a naturally contaminated tantalum silicide. (It be that should noted we

---

-- -.
(C)

ae -

-.-.-

observed quite similar effects on samples covered with CoSiJ. We are less certain aboat the mechanism responsible for the

rehabilitation of the MOS properties of the same devices at the end of the MOSFET fabrication sequence. our In experiments the "cure" was broughtaboutduring
900'C, with silicide removed. It is

3 Y 0.4 0.2

0.6

SILICIDE \

PL OY

a brief phosphorus diffusion at possible that during this step an the interface into
a mere

-4
I

GATE OXIDE p-SILICON SUBSTRATE

out-diffusion of heavy impurities occurred from the bulk of polysilicon

[5].

On hand, the other

t
Fig. 1

-2 GATE VOLTAGE

enhancement of the mobile charge concentration by the diffusion of phosphorus could

also eliminate the depleted sublayer.

(VI

To

C-Vcharacteristics of MOS capacitor with silicide gates.

(a) Before sintering. (b) After 30 min. sintering at 900'C. (c) subsequent After phosphorus diffusion (15 min, 900'C) with silicide layer removed.

distinguish between these and other of a future study.

possibilities will be the subject

REFERENCES

E. H. Nicollian and J. R. Brews, MOS Physics and Technology, Wiley (1982) and references therein. 2. S.P. Murarka, D. B. Fraser, J. Appl. Phys. 51(3), 1593, 1980. 3. A. S. Grove, Physics Ttchnology and or Semiconductor Devices, Wiley, 1967.
1.
4.

C.C. Chpng, private communications.

5. This mechanism was suggested to us by

H.J. Levinstein.

( 0 ) VG = o DEPLETION

fl

(b)

vGc0

ACCUMULATION

\
900 950 1000 SINTERING TEMPERATURE P C )

Fig. 3

Sheet resistance of 4000 A polysilicon film after 30 min. sintering with a tantalum silicide cap. The increasein resistivity is associated with thedepletion of phosphorus caused by its diffusion into the silicide.

Fig. 3

Sheet resistance of 4000 A polysilicon film after 30 min. sintering with a tantalum silicide cap. The increasein resistivity is associated with the depletionof phosphorus caused by its diffusion into the silicide.

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