Nokialcd

LDS176
Data Sheet
396 Segment (132 x 3) + 132 Common 4,096 Color One-Chip MLA Driver
Feb. 15, 2005
PRELIMINARY
LDS176
132 x 132 (RGB), 4k-Color STN Driver
Version 0.10
CONTENTS
1 2 3 4 5 DESCRIPTION FEATURES BLOCK DIAGRAM PIN DESCRIPTION FUNCTIONAL DESCRIPTION
5.1
5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6
1 1 2 3 5
MPU INTERFACE ........................................................................................................................................ 5

Interface Type Selection .................................................................................................................................... 5 General Protocol ................................................................................................................................................ 5 8080-Series Parallel Interface (PS0 = "High", PS1="High").............................................................................. 6 6800-Series Parallel Interface (PS0 = "Low", PS1="Low") ............................................................................... 8 Serial Interface (PS0= "Low") .......................................................................................................................... 10
5.1.5.1 5.1.6.1 5.1.6.2 5.1.6.3 Write Mode ............................................................................................................................................................... 10 Parallel Interface Pause ........................................................................................................................................... 13 Serial Interface Pause .............................................................................................................................................. 13 Read Mode ............................................................................................................................................................... 14 Method 1................................................................................................................................................................... 15 Method 2................................................................................................................................................................... 15
Interface Pause................................................................................................................................................ 13
5.1.7
Display Module Data Transfer Modes ............................................................................................................. 15

5.1.7.1 5.1.7.2
5.2
DISPLAY DATA RAM (DDRAM)................................................................................................................16

5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 Display Data Formats ...................................................................................................................................... 16 Address Counter .............................................................................................................................................. 20 Memory Map .................................................................................................................................................... 22 Normal Display On or Partial Mode On, Vertical Scroll Off ............................................................................. 23 Vertical Scroll ................................................................................................................................................... 24
5.2.5.1 5.2.5.2 Rolling and Non-Rolling Scroll ................................................................................................................................. 24 Vertical Scroll Example ............................................................................................................................................ 26 Tearing Effect Line Modes ....................................................................................................................................... 28 Tearing Effect Line Timing ....................................................................................................................................... 29
5.2.6
Tearing Effect Output Line............................................................................................................................... 28

5.2.6.1 5.2.6.2
5.2.7
Colour Depth Conversion Look Up Tables ...................................................................................................... 30
5.3 5.4 5.5 5.6 5.7
INSTRUCTION DECODER & REGISTER ................................................................................................31 GRAY SIGNAL GENERATOR ...................................................................................................................31 GRAY SELECTOR.....................................................................................................................................31 SYSTEM CLOCK GENERATOR ...............................................................................................................31 OSCILLATOR.............................................................................................................................................31
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5.8 5.9
SEGMENT DRIVER ...................................................................................................................................31 BLOCK COUNTER ....................................................................................................................................31
5.10 COMMON DRIVER ....................................................................................................................................31 5.11 LCD POWER GENERATION CIRCUIT.....................................................................................................32

5.11.1 LCD Power Generation Scheme ..................................................................................................................... 32 5.11.2 Booster1 Circuit ............................................................................................................................................... 33 5.11.3 Voltage Regulator1 Circuit............................................................................................................................... 33
5.11.3.1 Voltage Regulator1 Circuit ....................................................................................................................................... 33 5.11.3.2 Built-in Resistor for VXH2 Voltage Regulation......................................................................................................... 33 5.11.3.3 Constant Voltage Source and Electronic Volume Control Circuit............................................................................ 34
5.11.4 Voltage Divider & Voltage Follower Circuit...................................................................................................... 35 5.11.5 Booster2 Circuit ............................................................................................................................................... 35 5.11.6 Voltage Regulator2 Circuit............................................................................................................................... 35 5.11.7 Booster3 Circuit ............................................................................................................................................... 36 5.11.8 Power Circuit Application Example.................................................................................................................. 36 5.11.9 Temperature Compensation ............................................................................................................................ 37
5.11.9.1 Temperature Sensor ................................................................................................................................................ 37 5.11.9.2 Contrast Adjustment................................................................................................................................................. 38 5.11.9.3 Frame Frequency Adjustment.................................................................................................................................. 41
5.12 POWER ON/OFF SEQUENCE..................................................................................................................42

5.12.1 Case 1 !RES line is held High or Unstable by Host at Power On ................................................................ 42 5.12.2 Case 2 !RES line is held Low by host at Power On ..................................................................................... 43
5.13 UNCONTROLLED POWER OFF ..............................................................................................................43 5.14 POWER FLOW CHART FOR DIFFERENT POWER MODES .................................................................44
INSTRUCTION DESCRIPTION
6.1
6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.1.7 6.1.8 6.1.9
45
INSTRUCTION CODE 0 (ISS=0, MESSI-8) ..............................................................................................45

Instruction Code Table..................................................................................................................................... 45 NOP (00h) ........................................................................................................................................................ 48 SWRESET: Software Reset (01h)................................................................................................................... 49 BSTROFF: Booster Off (02h) (Only for Test Purposes).................................................................................. 50 BSTRON: Booster ON (03h) (Only for Test Purposes)................................................................................... 52 RDDID: Read Display ID (04h) ........................................................................................................................ 54 RDDST: Read Display Status (09h) ................................................................................................................ 55 SLPIN: Sleep In (10h) ...................................................................................................................................... 57 SLPOUT: Sleep Out (11h) ............................................................................................................................... 59
6.1.10 PTLON: Partial Display Mode On (12h) .......................................................................................................... 61 6.1.11 NORON: Normal Display Mode On (13h)........................................................................................................ 62 6.1.12 INVOFF: Display Inversion Off (20h)............................................................................................................... 63 6.1.13 INVON: Display Inversion On (21h)................................................................................................................. 64 6.1.14 APOFF: All Pixels Off (22h) (Only for Test Purposes) .................................................................................... 65 LEADIS Technology CONFIDENTIAL
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6.1.15 APON: All Pixels On (23h) (Only for Test Purposes) ...................................................................................... 66 6.1.16 WRCNTR: Write Contrast (3Fh) ...................................................................................................................... 67 6.1.17 DISPOFF: Display Off (28h) ............................................................................................................................ 68 6.1.18 DISPON: Display On (29h) .............................................................................................................................. 69 6.1.19 CASET: Column Address Set (2Ah)................................................................................................................ 70 6.1.20 RASET: Row Address Set (2Bh) ..................................................................................................................... 72 6.1.21 RAMWR: Memory Write (2Ch) ........................................................................................................................ 74 6.1.22 RAMRD: Memory Read (2Eh) ......................................................................................................................... 75 6.1.23 RGBSET: Colour Set for 256-Color Display (2Dh).......................................................................................... 76 6.1.24 PTLAR: Partial Area (30h) ............................................................................................................................... 77 6.1.25 SCRLAR: Scroll Area (33h) (Not used: Removed in this driver)..................................................................... 79 6.1.26 TEOFF: Tearing Effect Line OFF (34h) ........................................................................................................... 82 6.1.27 TEON: Tearing Effect Line ON (35h)............................................................................................................... 83 6.1.28 MADCTR: Memory Data Access Control (36h)............................................................................................... 84 6.1.29 VSCSAD: Vertical Scroll Start Address of RAM (37h) (Not used: Removed in this driver) ............................ 86 6.1.30 IDMOFF: Idle Mode Off (38h) .......................................................................................................................... 88 6.1.31 IDMON: Idle Mode On (39h)............................................................................................................................ 89 6.1.32 COLMOD: Interface Pixel Format (3Ah).......................................................................................................... 91 6.1.33 RDID1: Read ID1 Value (DAh) ........................................................................................................................ 92 6.1.34 RDID2: Read ID2 Value (DBh) ........................................................................................................................ 93 6.1.35 RDID3: Read ID3 Value (DCh) ........................................................................................................................ 94 6.1.36 CLKINT: Internal Oscillator (B0h) .................................................................................................................... 95 6.1.37 CLKEXT: External Oscillator (B1h).................................................................................................................. 96 6.1.38 FRMSEL: Frame frequency in normal mode (B4h) ......................................................................................... 97 6.1.39 FRM8SEL: Frame frequency in idle mode (8-color mode) (B5h).................................................................... 98 6.1.40 TMPRNG: Temperature Range Set for Frame Frequency Adjustment (B6h) .............................................. 100 6.1.41 TMPHYS: Temperature Hysteresis Set for Frame Frequency Adjustment (B7h)......................................... 101 6.1.42 TMPREAD: Temperature Read-back (B8h) .................................................................................................. 102 6.1.43 DISCTR: Display Control (BAh)..................................................................................................................... 103 6.1.44 EPVOL: Electrical Volume set for EEPROM (BBh)....................................................................................... 105 6.1.45 EPWROUT: EEPROM Write Out (D0h) ........................................................................................................ 107 6.1.46 EPWRIN: EEPROM Write In (D1h) ............................................................................................................... 108 6.1.47 RDEV: Read Electrical Volume Value (3Fh) ................................................................................................. 109 6.1.48 RDRR: Read Resistor Ratio Value (D5h)...................................................................................................... 110 6.1.49 TEST1: Test Command1 (E-h) ...................................................................................................................... 111 6.1.50 TEST2: Test Command2 (F-h) ...................................................................................................................... 111
6.2
INSTRUCTION CODE 1 (ISS=1).............................................................................................................112

6.2.1 6.2.2 6.2.3 6.2.4 Instruction Code Table................................................................................................................................... 112 NOP (25h) ...................................................................................................................................................... 115 OSCON: Oscillator On (D1h)......................................................................................................................... 115 OSCOFF: Oscillator Off (D2h) ....................................................................................................................... 115
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6.2.5 6.2.6 6.2.7 6.2.8 6.2.9
BSTRON: Power All On (20h) ....................................................................................................................... 115 BSTROFF: Power All Off (21h)...................................................................................................................... 115 SLPIN: Sleep In (95h) .................................................................................................................................... 115 SLPOUT: Sleep Out (94h) ............................................................................................................................. 116 PTLOUT: Partial Display Mode Off (A9h)...................................................................................................... 116
6.2.10 PTLIN: Partial Area Set & Partial Display Mode On (A8h)............................................................................ 116 6.2.11 DISNOR: Normal Display Mode (Inversion Off) (A6h) .................................................................................. 117 6.2.12 DISINV: Display Inversion On (A7h).............................................................................................................. 117 6.2.13 DISPOFF: Display Off (AEh) ......................................................................................................................... 117 6.2.14 DISPON: Display On (AFh) ........................................................................................................................... 117 6.2.15 CASET: Column Address Set (15h) .............................................................................................................. 118 6.2.16 RASET: Row Address Set (75h).................................................................................................................... 118 6.2.17 RAMWR: Memory Write (5Ch) ...................................................................................................................... 118 6.2.18 RAMRD: Memory Read (5Dh) ....................................................................................................................... 118 6.2.19 RGBSET: Colour Set for 256-Color Display (CEh) ....................................................................................... 119 6.2.20 ASCSET: Scroll Area Set (AAh) .................................................................................................................... 120 6.2.21 VSCSAD: Vertical Scroll Start Address of RAM (ABh) ................................................................................. 120 6.2.22 DATCTR: Data Access Control (BCh)........................................................................................................... 122 6.2.23 RMWIN: Read Modify Write In (E0h)............................................................................................................. 122 6.2.24 RMWOUT: Read Modify Write Out (EEh) ..................................................................................................... 122 6.2.25 VOLCTR: Electrical Volume Control (81h) .................................................................................................... 123 6.2.26 VOLUP: Electrical Volume Increment (D6h) ................................................................................................. 123 6.2.27 VOLDOWN: Electrical Volume Decrement (D7h) ......................................................................................... 123 6.2.28 DISCTR: Display Control (BAh)..................................................................................................................... 124 6.2.29 FRMSEL: Frame frequency in normal mode (B4h) ....................................................................................... 125 6.2.30 FRM8SEL: Frame frequency in idle mode (8-color mode) (B5h).................................................................. 125 6.2.31 TMPRNG: Temperature Range Set for Frame Frequency Adjustment (B6h) .............................................. 125 6.2.32 TMPHYS: Temperature Hysteresis Set for Frame Frequency Adjustment (B7h)......................................... 126 6.2.33 TMPREAD: Temperature Read-back (B8h) .................................................................................................. 126 6.2.34 EPVOL: Electrical Volume set for EEPROM (C0h) ....................................................................................... 127 6.2.35 EPWRIN: EEPROM Write Start (CDh) .......................................................................................................... 127 6.2.36 EPWROUT: EEPROM Write End (CCh) ....................................................................................................... 127 6.2.37 RDEV: Read Electrical Volume Value (7Ch)................................................................................................. 128 6.2.38 RDRR: Read Resistor Ratio Value (7Dh)...................................................................................................... 128 6.2.39 RDID1: Read ID1 Value (DAh) ...................................................................................................................... 128 6.2.40 RDID2: Read ID2 Value (DBh) ...................................................................................................................... 128 6.2.41 RDID3: Read ID3 Value (DCh) ...................................................................................................................... 129 6.2.42 IDMOFF: Idle Mode Off (38h) ........................................................................................................................ 129 6.2.43 IDMON: Idle Mode On (39h).......................................................................................................................... 129 6.2.44 TEOFF: Tearing Effect Line OFF (34h) ......................................................................................................... 130 6.2.45 TEON: Tearing Effect Line ON (35h)............................................................................................................. 130
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6.2.46 TEST1: Test Command1 (6-h) ...................................................................................................................... 130 6.2.47 TEST2: Test Command2 (0-h) ...................................................................................................................... 130
6.3
RESET TABLE (DEFAULT VALUE) ........................................................................................................131

6.3.1 6.3.2 Instruction Code0 (ISS=0) ............................................................................................................................. 131 Instruction Code1 (ISS=1) ............................................................................................................................. 132 Initializing with the Built-in Power Supply Circuits ......................................................................................... 133 Power OFF Sequence ................................................................................................................................... 135 EEPROM Program Sequence ....................................................................................................................... 137
6.4
INSTRUCTION SETUP FLOW ................................................................................................................133

6.4.1 6.4.2 6.4.3
SPECIFICATIONS
7.1 7.2 7.3 7.4 7.5 7.6
138
ABSOLUTE MAXIMUM RATINGS ..........................................................................................................138 ESD PROTECTION LEVEL .....................................................................................................................138 LATCH-UP PROTECTION LEVEL ..........................................................................................................138 LIGHT SENSITIVITY................................................................................................................................138 MAXIMUM SERIES RESISTANCE .........................................................................................................139 DC CHARACTERISTICS .........................................................................................................................140
7.6.1 7.6.2 Basic Characteristics ..................................................................................................................................... 140 Current Consumption..................................................................................................................................... 141 Parallel Interface Characteristics (8080-series MPU) ................................................................................... 142 Parallel Interface Characteristics (6800-series MPU) ................................................................................... 143 Serial Interface Characteristics...................................................................................................................... 144 Reset Input Timing......................................................................................................................................... 145 Measurement Conditions for Parallel and Serial Interfaces .......................................................................... 146
7.7.5.1 7.7.5.2 tDOA, tDOD Measurement Condition ......................................................................................................................... 146 tACC, tODE Measurement Condition.......................................................................................................................... 147
7.7
AC CHARACTERISTICS .........................................................................................................................142
7.7.1 7.7.2 7.7.3 7.7.4 7.7.5
REFERENCE APPLICATIONS
8.1
8.1.1 8.1.2 8.1.3
149
MICROPROCESSOR INTERFACE.........................................................................................................149
Interfacing with 8080-series MPU 8-Bit Bus (PS0 = "H", PS1 = "H") ............................................................ 149 Interfacing with 6800-series MPU 8-Bit Bus (PS0 = "H", PS1 = "L).............................................................. 149 3-Line Serial mode (PS0 = "L", PS1 = "L" or "H").......................................................................................... 150
8.2
CONNECTIONS WITH LCD PANEL .......................................................................................................151
CHIP INFORMATION
9.1 9.2
152
CHIP OVERVIEW ....................................................................................................................................152 BUMP INFORMATION.............................................................................................................................154

9.2.1 9.2.2 COM/SEG Output Pad Format ...................................................................................................................... 154 Input Pad Format ........................................................................................................................................... 155
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9.3
PAD COORDINATES...............................................................................................................................156
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LDS176
Version 0.10
Document No: LTT176DS-010
Prepared by: Ted Park
REVISION HISTORY
Date May 22, 2004 Feb. 15, 2005 Contents - Preliminary Version 0.0 - Final Version 0.1 - Page 2, 4 and 157: ROWM pad changed to TEST6 - Page 3 and 156: TESTF pad changed to TESTF1 to TESTF26 - Page 3 and 157: ID2/ID1/ID0 pads changed to TEST7 SRGB/SMX/SMY pads changed to TEST8 - Page 151: Section 8.2 updated Version Ver 0.00 (Preliminary) Ver 0.10 (Final Version)
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LDS176
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DESCRIPTION
LDS176 is a single chip low power CMOS LCD controller/driver for color STN displays of 132 rows and 132xRGB columns. It has a 209k-bit (132 x 12bit x 132) display RAM and a full set of control functions. LDS176 uses the Multiple Line Addressing technique in order to achieve better optical performance with lower power consumption. LDS176 offers 3 microprocessor interfaces: 8080-system, 6800-system and 3-line serial interface.
FEATURES
Single chip LCD controller/driver 132 row and 396 (132 x RGB) column outputs Low cross talk by mixed control (FRC + PWM) Display mode Color modes: - Full colors (Idle mode off): 4096-color (16-gray scale) - Reduced color (Idle mode on): 8-colors (3-bit binary mode) Interface modes: Color modes on the display host interface: - 8 bit/pixel: (RGB) = (332) using the 209k-bit frame memory and a look up table (LUT) - 12 bit/pixel: (RGB) = (444) using the 209k-bit frame memory directly - 16 bit/pixel: (RGB) = (565) using the 209k-bit frame memory with dithering (16 bit/pixel to 12 bit/pixel) Display data RAM (frame memory): 132 x 132 x 12-bit = 209k bit Interfaces: 3-line serial interface 8-bit interface with 8080-series MPU 8-bit interface with 6800-series MPU Display features Area scrolling Partial display mode Software programmable color depth mode N-line inversion for low cross talk On chip: Oscillator for display system requires no external components (external clock also possible) Generation of VLCD Temperature compensation of VLCD Logic supply voltage range VDD1 to VSS 1.65 to 1.95V Analog supply voltage range for VLCD generation VDD2 to VSS2: 2.6 to 2.9V Display supply voltage range (VLCD=VH-VL) Max 18V Low power consumption, suitable for battery operated systems CMOS compatible inputs Optimized layout for COG assembly
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BLOCK DIAGRAM
LCD Panel (4k-Color)
S0 - - - - - - - - - - S395
C0 - - - - - C131 VH VXH2 VXH1 VC VXL1 VXL2 VL FPC
396 Segment Drivers
132 Common Drivers
CAP
Latch & Gray selector Row (Page) Address Counter Display Data RAM 132 x 132 x 12 = 209,088 bits Scan (Line) Address Counter
COM Counter
Booster Circuit
Column Address Counter RAM Data Generator (LUT) Gray Control
C5M C5P VOUTL C3M C2M C1M C2P C1P VOUT2 VOUT CX1P CX1M CX2P CX2M
CAP
EEPROM
Instruction Control
System Clock Generator
MPU I/F & Data Latch

(8-bit parallel & 3-pin serial)
Bus Holder
Oscillator
Connect Capacitor TEST6 (ROWM) ISS EXTB TE (TEST2) TEST1 OSC TEST3 to TEST5 VDD1 VSS VDD2
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D0 (SDA) to D7 !RD !WR D/!C (SCL) !RES !CS (!SCE) PS0, PS1
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PIN DESCRIPTION
Pin Description
Table 4.1.1
Name
Type
Description
LCD row and column pins S0 to S395 O LCD segment (column) driver outputs C0 to C131 O LCD common (row) driver outputs Power supply pins VDD1 P Power supply for I/O system VDD2 P Power supply for logic, analog system and boosting input voltage VSS P System ground for internal system VSS1 P System ground for a manufacturers special use. Should be connected to VSS. LCD supply pins *1) VH I/O LCD common driver bias level *1) VXH2 I/O LCD segment driver bias level *1) VXH1 I/O LCD segment driver bias level *1) VC I/O LCD segment/common driver bias level *1) VXL1 I/O LCD segment driver bias level *1) VXL2 I/O LCD segment driver bias level (Connect to VSS pad) *1) VL I/O LCD common driver bias level LCD supply voltage generation I/O Capacitor connection pin for booster1 circuit. CX1P, CX2P CX1M, CX2M Output of booster1 circuit (output of 3-times booster). VOUT O Connect capacitor to VSS (GND) Output of booster1 circuit (output of 2-times booster). VOUT2 O Connect capacitor to VSS (GND) I/O Capacitor connection pin for booster2 circuit. C1P, C2P C1M to C3M VOUTL O Output of booster2 circuit. Connect capacitor to VSS (GND) C5M I/O Capacitor connection pin for booster3 circuit. C5P I/O Capacitor connection pin for booster3 circuit. Clock input and ID pins OSC I Oscillator input for test purpose. Test pins TEST1 O Test pin, not accessible to user must be left open. TEST3, TEST4, I Test input pins, should be connected to VDD1 or VSS. TEST5 TESTF1 to I Test input pins, should be left open. TESTF26 TEST7, TEST8 I Test input pins, should be connected to VDD1 or VSS.
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Table 4.1.2
Pin Description (continued)
Name Type Host interface pins ISS I PS0, PS1 I !RES I
Description Instruction set selection (0: code set0, 1: code set1). Interface mode setting (Refer Section 5.1 MPU INTERFACE) External reset This signal will reset the device and must be applied to properly initialize the chip. Signal is active low. Chip select input pin (Low enable). This pin can be permanently fixed Low in parallel interface mode only. If !CS is connected to ground in Parallel interface mode, there will be no abnormal visible effect to the display module. Also there will be no restriction on using the Parallel Read/Write protocols, Power On/Off Sequences or other functions. Furthermore there will be no influence to the Power Consumption of the display module. Display data / Command selection pin in parallel interface. In serial interface, this pin used as serial clock (SCL). Write enable in 8080-series parallel interface. Read write selection in 6800-series parallel interface. In serial interface, connect this to VDD1 or VSS. Read enable in 8080-series parallel interface. Read/write enable in 6800-series parallel interface. In serial interface, connect this to VDD1 or VSS. Tearing effect output. 8-Bit bi-directional display data / command bus for 8-bit parallel interface. In serial interface, D0 is used as serial data input/output (SDA). In serial interface, unused pins (D7 to D1) can be open or connect to VDD1 or VSS.
!CS (!SCE)
D/!C (SCL)
!WR (R/!W)
!RD (E) TE D7 to D0(SDA) Mode Select
I O I/O
Extended command code access pin. To use extended command set (like EEPROM program), please connect this to VSS. During normal operation, please open this pin. TEST input pin TEST6 I Please connect this to VSS. NOTE: DUMMY These pins should be open (float). EXTB I *1) Voltages should have the following relationship: VH VXH2 VXH1 VC VXL1 VXL2 (VSS) VL VOUTL 2) When in serial mode (PS0 = Low) then if some data or signal appears on !WR, !RD and D7 to D1 then it will have no influence to the system. Also in Parallel mode (PS0 =High) there will be no influence to the serial interface. 3) When !CS is high, there is no influence to the serial or parallel interfaces. 4) If !CS is connected to ground in Parallel Interface mode, there will be no abnormal visible effect to the display module. Also there will be no restriction on using the Parallel Read/Write protocols, Power On/Off Sequences or other functions. Furthermore, there will be no influence to the Power Consumption of the Display Module.
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FUNCTIONAL DESCRIPTION
5.1 MPU INTERFACE

LDS176 can interface with MPU at high speed. However, if the interface cycle time is faster than the limit, MPU needs to have dummy wait(s) to meet the cycle time limit.
5.1.1
Interface Type Selection
The selection of a given interfaces are done by setting PS0, PS1 and PS2 pins as shown in Table 5.1.1.
Table 5.1.1 Interface Type Selection
PS0 PS1 Interface 0 - 3-Line Serial 1 0 6800 MPU 8-bit Parallel 1 1 8080 MPU 8-bit Parallel
Read back select Via the read instruction (8-bit, 24-bit and 32-bit read parameter) E strobe (8-bit read data and 8-bit read parameter) !RD strobe (8-bit read data and 8-bit read parameter)
5.1.2
General Protocol
For programming of the LCD driver, the general supported protocol is shown in Fig. 5.1.1
TB
TB
TB
TB
TB
TB
S: Start data tranamission P: Stop data tranamission TB: tranamission byte
Fig. 5.1.1
Programming protocol
If data write or parameter write is interrupted by any other command, data write command or parameter write command should be done again to write the remained data or parameter.
Command1 code (with 3 parameter) CMD1 PARA11 PARA12 PARA13
Command1 code is interrupped by command2

CMD1
PARA11
CMD2
CMD1
PARA11
st
PARA12
PARA13
Command1 with 1 parameter (PARA11) should be executed again to write remained parameter (PARA12 and PARA13)
Fig. 5.1.2
Write interrupt sequence
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5.1.3
8080-Series Parallel Interface (PS0 = "High", PS1="High")
The 8080-series bi-directional interface can be used for communication between the micro controller and the LCD driver chip. The selection of this interface is done with PS0 and PS1 pin. The interface functions of the parallel interface (8080-series) are given in Table 5.1.2.
Table 5.1.2 Parallel Interface Function
8080-series Function D/!C !RD !WR Write 8-bit display data or 8-bit parameter (D7 to D0) 1 1 Write 8-bit command (D7 to D0) 0 1 Read 8-bit display data (D7 to D0) 1 1 *1) Read 8-bit parameter or status (D7 to D0) 1 1 NOTE: = rising edge *1) Applied for command code0 : DAh, DBh, DCh, 04h and 09h command code1: DAh, DBh and DCh The parallel interface timing diagram is given in Fig. 5.1.3 and Fig. 5.1.4.
1-byte command 2-byte command n-byte command (number of parameter = n-1)
CMD
CMD
PA 1
CMD
PA 1
PA n-2
PA n-1
!CS D/!C !RD !WR D[7:0] Host D[7:0] (MPU to LCD) Driver D[7:0] (LCD to MPU)
CMD CMD PA 1 CMD PA 1 PA n-2 PA n-1
CMD
CMD
PA 1 Hi-Z
CMD
PA 1
PA n-2
PA n-1
CMD: Write command code PA: Write parameter or RAM data
Signals on D[7:0], D/!C, !RD and !WR pins during !CS=H or PS0=L are ignored.
Fig. 5.1.3
8080-Series parallel bus protocol, write to register or display RAM
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Read parameter
Read display RAM data
CMD
DM
PA
CMD
DM
Data
Data
!CS D/!C !RD !WR D[7:0] Host D[7:0] (MPU to LCD) Driver D[7:0] (LCD to MPU)
CMD DM PA CMD DM PA Hi-Z
PA
CMD Hi-Z
Hi-Z
CMD Hi-Z
Hi-Z
DM
PA
DM
PA
Hi-Z
PA
CMD: Read command code PA: Read parameter DM: Dummy read data / parameter
Signals on D[7:0], D/!C, !RD and !WR pins during !CS=H or PS0=L are ignored.
NOTE: If both D/!C and !RD is Low, there is no damage on the driver and there is no visible effect on the display, It will be considered as NOP (No operation).
Fig. 5.1.4
8080-Series parallel bus protocol, read from register
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5.1.4
6800-Series Parallel Interface (PS0 = "Low", PS1="Low")
The 6800-series bi-directional interface can be used for communication between the micro controller and the LCD driver chip. The selection of this interface is done with PS0 and PS1 pin. The interface functions of the parallel interface (6800-series) are given in Table 5.1.3.
Table 5.1.3 Parallel Interface Function
6800-series Function D/!C R/!W E Write 8-bit display data or 8-bit parameter (D7 to D0) 1 0 Write 8-bit command (D7 to D0) 0 0 Read 8-bit display data (D7 to D0) 1 1 *1) Read 8-bit parameter or status (D7 to D0) 1 1 NOTE: = falling edge *1) Applied for command code0 : DAh, DBh, DCh, 04h and 09h command code1: DAh, DBh and DCh The parallel interface timing diagram is given in Fig. 5.1.5 and Fig. 5.1.6.
1-byte command 2-byte command n-byte command (number of parameter = n-1)
CMD
CMD
PA 1
CMD
PA 1
PA n-2
PA n-1
!CS D/!C R/!W E D[7:0] Host D[7:0] (MPU to LCD) Driver D[7:0] (LCD to MPU)
CMD CMD PA 1 CMD PA 1 PA n-2 PA n-1
CMD
CMD
PA 1 Hi-Z
CMD
PA 1
PA n-2
PA n-1
CMD: Write command code PA: Write parameter or RAM data
Signals on D[7:0], D/!C, R/!W and E pins during !CS=H or PS0=L are ignored.
Fig. 5.1.5
6800-Series parallel bus protocol, write to register or display RAM
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Read parameter
Read display RAM data
CMD
DM
PA
CMD
DM
Data
Data
!CS D/!C R/!W E D[7:0] Host D[7:0] (MPU to LCD) Driver D[7:0] (LCD to MPU)
CMD Hi-Z
DM
PA
CMD
DM
PA
PA
CMD Hi-Z
Hi-Z
CMD Hi-Z
Hi-Z
DM
PA
DM
PA
Hi-Z
PA
CMD: Read command code PA: Read parameter DM: Dummy read data / parameter
Signals on D[7:0], D/!C, R/!W and E pins during !CS=H or PS0=L are ignored.
Fig. 5.1.6
6800-Series parallel bus protocol, read from register
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5.1.5
Serial Interface (PS0= "Low")
Communication with the microprocessor can also be done via a clock-synchronized serial peripheral interface. The selection of this interface is done with PS0 pin. The serial interface is a 3-line bi-directional interface for communication between the micro controller and the LCD driver chip. The 3-lines serial use: !SCE (chip enable), SCL (serial clock) and SDA (serial data input/output). Serial clock (SCL) is used for interface with MPU only, so it can be stopped when no communication is necessary. 5.1.5.1 Write Mode
The write mode of the interface means the micro controller writes commands and data to the LDS176. 3-Line serial data packet contains a control bit D/!C and a transmission byte. If D/!C is low, the transmission byte is interpreted as command byte. If D/!C is high, the transmission byte is stored in the display data RAM (Memory write command), or command register as parameter. Any instruction can be sent in any order to the LDS176. The MSB is transmitted first. The serial interface is initialized when !SCE is high. In this state, SCL clock pulse and SDA data have no effect. A falling edge on !SCE enables the serial interface and indicates the start of data transmission.
3-Line Serial Data Stream Format
Transmission byte (TB) may be a Command or a Data
MSB
LSB
D/!C D7 D6 D5 D4 D3 D2 D1 D0
D/!C
TB
D/!C
TB
D/!C
TB
Fig. 5.1.7
Serial data stream, write mode
It is possible to invoke a pause by !SCE while transferring display data or multiple parameter data. If !SCE is high after a whole byte of display data or multiple parameter data has been completed, then LDS176 will wait and continue the display data or multiple parameter data transmission from the point where it was paused as shown in Fig. 5.1.8.
TB
TB
!SCE Host
(MPU to Driver)
SCL SDA
D/!C
D7
D6
D5
D4
D3
D2
D1
D0
D/!C
D7
D6
D5
D4
D3
D2
D1
D0
Command / parameter / data
Command / parameter / data
SCE can be H between command and parameter/command SCL and SDA during !SCE = H is invalid
Fig. 5.1.8
Serial bus protocol, write to register with control bit in transmission
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Data Transfer Recovery If there is a break in data transmission by !RES or !SCE pulse, while transferring a Command or Frame Memory Data or Multiple Parameter command Data, before Bit D0 of the byte has been completed, then LDS176 will reject the previous bits and have reset the interface such that it will be ready to receive the same byte re-transmitted when the chip select line (!SCE) is next activated after !RES have been High state. See the following example (See Fig. 5.1.9)
TB
TB
!SCE !RES Host

(MPU to Driver)
Wait for more than 10s
SCL SDA
D/C
D7
D6
D5
D4
D3
D2
D/C
D7
D6
D5
D4
D3
D2
D1
D0
Command / Parameter / Data
Command
SCL and SDA during !RES = L is invalid and next byte becomes command
Fig. 5.1.9
Serial bus protocol, write mode interrupted by !RES
TB
TB
!SCE SCL Host

(MPU to Driver)
SDA
D/!C
D7
D6
D5
D4
D/!C
D7
D6
D5
D4
D3
D2
D1
D0
Break
Fig. 5.1.10
Serial bus protocol, write mode interrupted by !SCE
If 1, 2 or more parameter command is being sent and a break occurs while sending any parameter before the last one and if the host then sends a new command rather than re-transmitting the parameter that was interrupted, then the parameters that were successfully sent are stored and the parameter where the break occurred is rejected. The interface is ready to receive next byte as shown
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Break
PARA11 is sucessfully sended but PARA12 is breaked and need to be transfered again
CMD1
PARA11
PARA12
CMD2
CMD1
PARA11
st
PARA12
PARA13
Command1 with 1 parameter (PARA11) should be executed again to write remained parameter (PARA12 and PARA13)
Fig. 5.1.11
Write interrupt recovery
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5.1.6
Interface Pause
It will be possible when transferring a Command, Frame Memory Data or Multiple Parameter Data to invoke a pause in the data transmission. If the Chip Select Line is released after a whole byte of a Frame Memory Data or Multiple Parameter Data has been completed, then LDS176 will wait and continue the Frame Memory Data or Parameter Data Transmission from the point where it was paused. If the Chip Select Line is released after a whole byte of a command has been completed, then the Display Module will receive either the commands parameters (if appropriate) or a new command when the Chip Select Line is next enabled as shown below. This applies to the following 4 conditions: 1) Command-Pause-Command 2) Command-Pause-Parameter 3) Parameter-Pause-Command 4) Parameter-Pause-Parameter 5.1.6.1 Parallel Interface Pause
!CS D/!C !RD !WR D[7:0]

D7 to D0
Pause
D7 to D0
Command / Parameter
Pause
Command / Parameter
Fig. 5.1.12
Parallel bus protocol, write mode paused by !SCE
5.1.6.2
Serial Interface Pause
TB
TB
!SCE Host
(MPU to Driver)
Pause
SCL SDA
D/!C
D7
D6
D5
D4
D3
D2
D1
D0
D/!C
D7
D6
D5
D4
D3
D2
D1
D0

SCL and SDA during !SCE = H is invalid
Fig. 5.1.13
Serial bus protocol, write mode paused by !SCE
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5.1.6.3
Read Mode
The read mode of the interface means that the micro controller reads register value from the LDS176. To do so the micro controller first has to send a command (Read ID or Read Register command) and then the following byte is transmitted in the opposite direction. After that !SCE is required to go high before a new command is send (see Fig. 5.1.14). The LDS176 samples the SDA (input data) at the rising edges, but shifts SDA (output data) at the falling SCL edges with some delay (see AC characteristics section). Thus the micro controller is supported to read data at the rising SCL edges. After the read status command has been sent, the SDA line must be set to tri-state no later than at the falling SCL edge of the last bit (see Fig. 5.1.14).
3-Line Serial Protocol (for RDID1/RDID2/RDID3 command: 8-bit read)
S TB TB P S
!SCE
Host
SCL SDA (SDI)

D/!C D7 D6 D5 D4 D3 D2 D1 D0
High-Z
D/!C
Driver
SDA (SDO)
High-Z
D7
D6
D5
D4
D3
D2
D1 D0
3-Line Serial Protocol (for RDDID command: 24-bit read)

S TB TB P S
!SCE
Host
SCL SDA (SDI)

D/!C D7 D6 D5 D4 D3 D2 D1 D0
High-Z
D/!C
Driver
SDA (SDO)
High-Z
D23
D22 D21
D20 D19
D3
D2
D1 D0
Dummy Clock Cycle
3-Line Serial Protocol (for RDDST command: 32-bit read)

S TB TB P S
!SCE
Host
SCL SDA (SDI)

D/!C D7 D6 D5 D4 D3 D2 D1 D0
High-Z
D/!C
Driver
SDA (SDO)
High-Z
D31 D30 D29
D28 D27
D3
D2
D1 D0
Dummy Clock Cycle
Fig. 5.1.14
Serial bus protocol, read mode
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5.1.7
Display Module Data Transfer Modes
The Module has three kinds color modes for transferring data to the display RAM. These are 8-bit color per pixel, 12-bit color per pixel and 16-bit color per pixel. The data format is described for each interface. Data can be downloaded to the Frame Memory by 2 methods. 5.1.7.1 Method 1
The Image data is sent to the Frame Memory in successive Frame writes, each time the Frame Memory is filled, the Frame Memory pointer is reset to the start point and the next Frame is written.
Start Start Frame Memory Image Data Image Data Image Data
Stop Any Command
5.1.7.2
Method 2
Image Data is sent and at the end of each Frame Memory download, a command is sent to stop Frame Memory Write. Then Start Memory Write command is sent, and a new Frame is downloaded.
Start Start Frame Memory Image Data Any Command

Start Frame Memory Write
Image Data
Any Command
Stop Any Command
Note: 1) These apply to all Data Transfer Color modes on both Serial and Parallel interfaces. 2) The Frame Memory can contain both odd and even number of pixels for both Methods. Only complete pixel data will be stored in the Frame Memory.
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5.2 DISPLAY DATA RAM (DDRAM)

The LDS176 has an integrated 132x132x12-bit graphic type static RAM. This 209k-bit memory allows to store on-chip a 132x132 (RGB) image with a 12-bpp resolution (4k-color). There will be no abnormal visible effect on the display when there is a simultaneous Panel Read and Interface Write to the same location of the Frame Memory.
Display Data RAM Organization

LCD Glass
(130 x 130 x RGB)
MPU I/F
Look-up table & Dithering Row (Page) Address Counter Column Address Counter
Latch
Display Data RAM

(132 x 132 x 12-bit)
Line Address Counter Scan Address Counter
Host Interface
5.2.1
Display Data Formats
Different display data formats are available for three color depth supported by the LDS176 listed below. 4k colors, RGB 4-4-4-bits input (see Table 5.2.1 and Table 5.2.2) 256 colors, RGB 3-3-2-bits input (see Table 5.2.3) 65k colors, RGB 5-6-5-bits input (see Table 5.2.4)
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Table 5.2.1
Write data for RGB 4-4-4-bits input (Type A)
4k Color data D/!C MEMWR 0 1st write 2nd write 3rd write 1 1 1
D7 R13 B13 G23
D6 D5 D4 D3 D2 D1 Memory Write Command Code R12 B12 G22 R11 B11 G21 R10 B10 G20 G13 R23 B23 G12 R22 B22 G11 R21 B21
D0 G10 R20 B20
Memory Write 1st pixel data write (R1/G1/B1) 2nd pixel data write (R2/G2/B2)
Frame memory
R1 G1 B1
R2 G2 B2
R3 G3 B3
4k Color data D/!C MEMWR 0 1st write 2

nd
D7 R13 B13
D6 D5 D4 D3 D2 D1 Memory Write Command Code R12 B12 R11 B11 R10 B10 G13 R23 G12 R22 G11 R21
D0 G10 R20
st
Memory Write 1 pixel data write (R1/G1/B1) Memory write mode terminated -
1 1 0 0 1 1 1
write
CMD MEMWR 1st write 2

nd rd
The other command Memory Write Command Code R23 B23 G33 R22 B22 G32 R21 B21 G31 R20 B20 G30 G23 R33 B33 G22 R32 B32 G21 R31 B31 G20 R30 B30
2 pixel data write (R2/G2/B2) 3rd pixel data write (R3/G3/B3)

st
write
nd
3 write
R23 to R20 of the 1 MEMWR command will be lost and are not used as pixel data.
Frame memory
R1 G1 B1
R2 G2 B2
R3 G3 B3
NOTE: 3 bytes are used to transfer 2 pixels or 2 bytes are used to transfer1 pixel with the 12-bit color depth information. The most significant bits are: Rx3, Gx3 and Bx3. The least significant bits are: Rx0, Gx0 and Bx0. Only complete pixels are stored to the frame memory.
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Table 5.2.2
Write data for RGB 4-4-4-bits input (Type B)
X : Dont care
4k Color data D/!C MEMWR 0 1st write 2

nd
D7 X G13 X G23
D6 D5 D4 D3 D2 D1 Memory Write Command Code X G12 X G22 X G11 X G21 X G10 X G20 R13 B13 R23 B23 R12 B12 R22 B22 R11 B11 R21 B21
D0 R10 B10 R20 B20

nd st
Memory Write 1 pixel data write (R1/G1/B1) 2 pixel data write (R2/G2/B2)
1 1 1 1
write
3rd write 4 write

th
Frame memory
R1 G1 B1
R2 G2 B2
R3 G3 B3
NOTE: 2 bytes are used to transfer 1 pixel with the 12-bit color depth information. The most significant bits are: Rx3, Gx3 and Bx3. The least significant bits are: Rx0, Gx0 and Bx0.
Table 5.2.3
Write data for RGB 3-3-2-bits input
256 Color data D/!C MEMWR 0 1st write 2

nd
D7 R12 R22
D6 D5 D4 D3 D2 D1 Memory Write Command Code R11 R21 R10 R20

8-bit
D0 B10 B20
Memory Write 1st pixel data write (R1/G1/B1) 2nd pixel data write (R2/G2/B2)
1 1
G12 G22
G11 G21
8-bit
G10 G20
B11 B21
write
Look-Up Table for 256 Color data mapping (8-bit to 12-bit)

12-bit 12-bit
Frame memory
R1 G1 B1
R2 G2 B2
R3 G3 B3
NOTE: In one byte, 1 pixel is transferred with the 8-bit color depth information. The most significant bits are: Rx2, Gx2 and Bx1. The least significant bits are: Rx0, Gx0 and Bx0.
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Table 5.2.4
Write data for RGB 5-6-5-bits input
65k Color data D/!C MEMWR 0 1st write 2nd write 3rd write 4th write 1 1 1 1
D7 R14 G12 R24 G22
D6 D5 D4 D3 D2 D1 Memory Write Command Code R13 G11 R23 G21 R12 G10 R22 G20
16-bit
D0 G13 B10 G13 B20
Memory Write 1st pixel data write (R1/G1/B1) 2 pixel data write (R2/G2/B2)
nd
R11 B14 R21 B24
R10 B13 R20 B23

16-bit
G15 B12 G25 B22
G14 B11 G24 B21
Dithering for 65k Color data mapping (16-bit to 12-bit)

12-bit 12-bit
Frame memory
R1 G1 B1
R2 G2 B2
R3 G3 B3
NOTE: 2 bytes are used to transfer 1 pixel with the 16-bit color depth information. The most significant bits are: Rx4, Gx5 and Bx4. The least significant bits are: Rx0, Gx0 and Bx0. Only complete pixels are stored to the memory.
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5.2.2
Address Counter
The address counter sets the addresses of the display data RAM for writing. Data is written pixel-wise into the RAM matrix of LDS176. The data for one pixel or two pixels is collected (RGB 4-4-4-bit), according to the data formats. As soon as this pixel-data information is complete the Write access is activated on the RAM. The locations of RAM are addressed by the address pointers. The address ranges are X=0 to X=131 (83hex) and Y=0 to Y=131 (83h). Addresses outside these ranges are not allowed. Before writing to the RAM a window must be defined into which will be written. The window is programmable via the command registers XS, YS designating the start address and XE, YE designating the end address. For example the whole display contents will be written, the window is defined by the following values: XS=0 (0h) YS=0 (0h) and XE=131 (83h), YE=131 (83h). In vertical addressing mode (MV=1), the Y-address increments after each byte, after the last Y-address (Y=YE), Y wraps around to YS and X increments to address the next column. In horizontal addressing mode (V=0), the X-address increments after each byte, after the last X-address (X=XE), X wraps around to XS and Y increments to address the next row. After the every last address (X=XE and Y=YE) the address pointers wrap around to address (X=XS and Y=YS). For flexibility in handling a wide variety of display architectures, the commands CASET, RASET and MADCTL (code0) or DATCTL (code1) (see section 6 INSTRUCTION DESCRIPTION), define flags MX and MY, which allows mirroring of the X-address and Y-address. All combinations of flags are allowed. Fig. 5.2.1 show the available combinations of writing to the display RAM. When MX, MY and MV will be changed the data bust be rewritten to the display RAM. For each image condition, the controls for the column and row counters apply as below: Condition When RAMWR/RAMRD command is accepted Column Counter Return to Start Column (XS) Complete Pixel Read / Write action Increment by 1 The Column counter value is larger than End Column (XE) Return to Start Column (XS) The Column counter value is larger than End Column (XE) and Return to Start the Row counter value is larger than End Row (YE) Column (XS) Row Counter Return to Start Row (YS) No change Increment by 1 Return to Start Row (YS)
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Fig. 5.2.1
Frame Data Write Direction According to the MADCTR parameters (MV, MX and MY)
Display Data Direction Normal
MADCTR Parameter MV MX MY 0 0 0
Image in the Host (MPU)

B
Image in the Driver (DDRAM)

H/W position (0,0) X-Y address (0,0) B
E H/W position (0,0) E
Y-Mirror
X-Y address (0,0) H/W position (0,0)
B B X-Y address (0,0)
X-Mirror
X-Mirror Y-Mirror
B H/W position (0,0) X-Y address (0,0) B
X-Y address (0,0)
X-Y Exchange
X-Y Exchange Y-Mirror
X-Y address (0,0) H/W position (0,0)
B B X-Y address (0,0)
X-Y Exchange X-Mirror
X-Y Exchange X-Mirror Y-Mirror
X-Y address (0,0)
NOTE: MV=D5 parameter of MADCTL command, MX=D6 parameter of MADCTL command, MY=D7 parameter of MADCTL command
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5.2.3
Memory Map
Pixel1
Pixel2
---
Pixel131
Pixel132
SEG Out
S0
RGB=0
S1
RGB=1
S2
S3
RGB=0
S4
RGB=1
S5
--RGB Order
S390 S391 S392 S393 S394 S395

RGB=0 RGB=1 RGB=0 RGB=1
RA MY=0 MY=1 0 131 R13-0 1 130 2 129 3 128 4 127 5 126 6 125 7 124 8 123 9 122 10 121 11 120 : : : : : : : : : : : : : : : : : : 124 7 125 6 126 5 127 4 128 3 129 2 130 1 131 0 MX=0 CA MX=1
SA ML=0 ML=1 0 131 1 130 2 129 3 128 4 127 5 126 6 125 7 124 8 123 9 122 10 121 11 120 : : : : : : : : : : : : 124 7 125 6 126 5 127 4 128 3 129 2 130 1 131 0
G13-0
B13-0
R23-0
G23-0
B23-0
---
R1303-0 G1303-0 B1303-0 R1313-0 G1313-0 B1313-0
: : : : : :
Display Pattern Data

: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
-------------------------
: : : : : :
0 131
1 130
---------------------
RN3-0
GN3-0
BN3-0
130 1
131 0
NOTE: RA = Row Address, CA = Column Address, SA = Scan Address, MX = Mirror X-axis (Column address direction parameter), D6 parameter of MADCTL command MY = Mirror Y-axis (Row address direction parameter), D7 parameter of MADCTL command ML = Scan direction parameter, D4 parameter of MADCTL command RGB= Red, Green and Blue pixel position change, D3 parameter of MADCTL command
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5.2.4
Normal Display On or Partial Mode On, Vertical Scroll Off
In this mode, contents of the frame memory within an area where column pointer is 01h to 82h and page pointer is 01h to 82h is displayed. To display a dot on leftmost top corner, store the dot data at (column pointer, row pointer) = (1,1). Example1) Normal Display On
SEG128 SEG129
SEG1
SEG2
SEG3
00h 00 01 02 03 04 05 01h 10 11 12 13 14 02h 20 21 22 03h 30 31 32 04h 40 41 42 05h 50 51 : : 7Eh U0 U1 7Fh V0 V1 V2 80h W0 W1 W2 81h X0 X1 X2 82h Y0 Y1 Y2 Y3 Y4 83h Z0 Z1 Z2 Z3 Z4 Z5
0V 0W 0X 0Y 0Z 1W 1X 1Y 1Z 2X 2Y 2Z 3X 3Y 3Z 4Y 4Z 5Y 5Z
SEG4
00h 01h 02h 03h -
- 81h 82h 83h 1 2

st
COM1 COM2 COM3 : : COM124 COM125 COM126 COM127 COM128 COM129 COM130
11 12 13 14 21 22 31 32 41 42 51
1W 1X 1Y 2X 2Y 3X 3Y 4Y 5Y
nd
3rd 4
th
5th : :
132 lines
132 x 132 x 12bit Frame memory
130 x 130 LCD panel
SEG130
Scan Order
: : :
UY UZ 126th VX VY VZ 127th WXWYWZ 128th XX XY XZ 129th YW YX YY YZ 130th ZV ZW ZX ZY ZZ

-
U1 V1 V2 W1 W2 X1 X2 Y1 Y2 Y3 Y4
UY VX VY WX WY XX XY YW YX YY
Displaying area = 130 lines
Example2) Partial Display On: PSL [7:0] = 7Fh, PEL [7:0] = 03h, MADCTR (ML)=0
SEG128 SEG129 SEG1 SEG2 SEG3 SEG4
00h 01h 02h 03h -
- 81h 82h 83h 1st 2nd 3

rd
00h 00 01 02 03 04 05 01h 10 11 12 13 14 02h 20 21 22 03h 30 31 32 04h 40 41 42 05h 50 51 : : 7Eh U0 U1 7Fh V0 V1 V2 80h W0 W1 W2 81h X0 X1 X2 82h Y0 Y1 Y2 Y3 Y4 83h Z0 Z1 Z2 Z3 Z4 Z5
0V 0W 0X 0Y 0Z 1W 1X 1Y 1Z 2X 2Y 2Z 3X 3Y 3Z 4Y 4Z 5Y 5Z
SEG130
Scan Order
: : :
COM1 COM2 COM3 COM4
11 12 13 14 21 22 31 32 41 42 51
1W 1X 1Y 2X 2Y 3X 3Y 4Y 5Y
Displaying area = 3 lines Nondisplaying area = 123 lines Displaying area = 4 lines
: : COM125 COM126
130 x 130 LCD panel

U1 V1 V2 W1 W2 X1 X2 Y1 Y2 Y3 Y4 UY VX VY WX WY XX XY YW YX YY
UY UZ VX VY VZ WXWYWZ XX XY XZ YW YX YY YZ ZV ZW ZX ZY ZZ
4 5
th th
COM127 COM128 COM129 COM130
6th 7th -
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5.2.5
5.2.5.1
Vertical Scroll
Rolling and Non-Rolling Scroll
There are 2 types of vertical scrolling, which are determined by the commands Vertical Scrolling Definition (33h) and Vertical Scrolling Start Address (37h).
TFA VSA
TFA VSA
TFA VSA
BFA Origin al
BFA Rollin g scrollin g
BFA Non -rollin g scrollin g
Fig. 5.2.2
Difference between Rolling Scrolling and Non-rolling scrolling
Type 1
When Vertical Scrolling Definition Parameters (TFA+VSA+BFA)=130. In this case, rolling scrolling is applied as shown below. Not used area (lines) is just over BFA. Example1) Panel size=130 x 130, TFA =2, VSA=126, BFA=2, SSA=4, MADCTR (ML)=0: Rolling Scroll
SEG128 SEG129 SEG1 SEG2 SEG3 SEG4
00h 01h 02h 03h -
- 81h 82h 83h
TFA
00h 00 01 02 03 04 05 01h 10 11 12 13 14 02h 20 21 22 03h 30 31 32 04h 40 41 42
0V 0W 0X 0Y 0Z
1st
0 1 2 3 4 5 : : SSA
COM1 COM2 COM3 COM4 COM5 COM6 : : COM127 COM128 COM129 COM130
1W 1X 1Y 1Z 2nd 2X 2Y 2Z 127th 3X 3Y 3Z 128 5Y 5Z

4th : :
th
01 02 03 04 05 11 12 13 14 41 42 51 52
0V 0W 0X 0Y 1W 1X 1Y 4X 4Y 5X 5Y
SEG130
Scan Order SA
: : :
TFA
4Y 4Z 3rd
VSA
05h 50 51 : : 7Eh U0 U1 U2 7Fh V0 V1 V2
U1 U2 V1 V2
21 22 31 32 33
130 x 130 LCD panel
UX UY VX VY
2X 2Y 3W 3X 3Y
VSA
UX UY UZ 125th 126 VX VY VZ 126th 127

WXWY WZ XX XY XZ
128 129
Not Used BFA
80h W0 W1 W2 81h X0 X1 X2 82h Y0 Y1 Y2 Y3 Y4 83h Z0 Z1 Z2 Z3 Z4 Z5
Y1 Y2 Y3 Y4 Z1 Z2 Z3 Z4 Z5
YW YX YY ZV ZW ZX ZY
YW YX YY YZ 129th 130 ZV ZW ZX ZY ZZ 130th 131

Scan Address
BFA
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Example2) Panel size=130 x 130, TFA =2, VSA=126, BFA=2, SSA=4, MADCTR (ML)=1: Rolling Scroll (TFA and BFA are exchanged)
SEG128 SEG129 SEG130
SEG1
SEG2
SEG3
BFA Not Used
00h 00 01 02 03 04 05 01h 10 11 12 13 14 02h 20 21 22 03h 30 31 32 04h 40 41 42 05h 50 51 :
0V 0W 0X 0Y 0Z 130th 131 1W 1X 1Y 1Z 129th 130 2X 2Y 2Z 3X 3Y 3Z

129 128
COM1 COM2 COM3 COM4 COM5 COM6 : : COM127
SEG4
00h 01h 02h 03h -
- 81h 82h 83h
Scan Order SA
: : :
01 02 03 04 05 11 12 13 14
W1 W2 X1 X2
0V 0W 0X 0Y 1W 1X 1Y
WX WY XX XY
BFA
4Y 4Z 126th 127 5Y 5Z 125th

126 : : 5 4 3 2 1 0 Scan Address SSA
41 42 51 52
4X 4Y
VSA
: 7Eh U0 U1 U2 7Fh V0 V1 V2 80h W0 W1 W2 81h X0 X1 X2
: :
130 x 130 LCD panel
5X 5Y
VSA
UX UY UZ 4th VX VY VZ 3rd
WXWY WZ 128th XX XY XZ 127th
U1 U2 V1 V2 Y1 Y2 Y3 Y4 Z1 Z2 Z3 Z4 Z5
UX UY VX VY YW YX YY ZV ZW ZX ZY
COM128 COM129 COM130
TFA
82h Y0 Y1 Y2 Y3 Y4 83h Z0 Z1 Z2 Z3 Z4 Z5
YW YX YY YZ 2nd ZV ZW ZX ZY ZZ
1
st
TFA
Type 2
When Vertical Scrolling Definition Parameters (TFA+VSA+BFA) = 131 or 132. In this case, non-rolling Scrolling is applied. New data can be written into the extra memory lines, If (TFA+VSA+BFA)=131 then one line is available for inserting new data. If (TFA+VSA+BFA)=132 then two lines are available for inserting new data. Example1) Panel size=130 x 130, TFA =2, VSA=128, BFA=2, SSA=4, MADCTR (ML)=0: Non-Rolling Scroll
SEG128 SEG129 SEG1 SEG2 SEG3
TFA
00h 00 01 02 03 04 05 01h 10 11 12 13 14 02h 20 21 22 03h 30 31 32 04h 40 41 42 05h 50 51 :
0V 0W 0X 0Y 0Z 2X 2Y 2Z 3X 3Y 3Z 4Y 4Z 5Y 5Z
1W 1X 1Y 1Z 2
nd
1 2 3 4 5 : : SSA
COM1 COM2 COM3 COM4 COM5 : : COM126 COM127
01 02 03 04 05 11 12 13 14 41 42 51 52
0V 0W 0X 0Y 1W 1X 1Y 4X 4Y 5X 5Y
st
SEG4
00h 01h 02h 03h -
- 81h 82h 83h
SEG130
SA Scan Order
3
rd th
TFA
VSA
: :
U1 U2 V1 V2
W1 W2 X1 X2
130 x 130 LCD panel
UX UY VX VY
WX WY XX XY
VSA
UX UY UZ 125th 126 VX VY VZ 126

XX XY XZ 128
th
127
WXWY WZ 127th 128

th
New Data
COM128 COM129 COM130
129
Y1 Y2 Y3 Y4 Z1 Z2 Z3 Z4 Z5
YW YX YY ZV ZW ZX ZY
BFA
82h Y0 Y1 Y2 Y3 Y4 83h Z0 Z1 Z2 Z3 Z4 Z5
YW YX YY YZ 129th 130 ZV ZW ZX ZY ZZ 130

th
BFA
131 Scan Address
Note: In this example it was assumed that prior to sending the Vertical Scrolling Start Address, New Data had been written to the Frame Memory in the area described and the Vertical Scrolling Start Address was (Current Position-2Lines).
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Example2) Panel size=130 x 130, TFA =2, VSA=128, BFA=2, SSA=4, MADCTR (ML)=1: Non-Rolling Scroll (TFA and BFA are exchanged)
SEG128 SEG129
SEG1
SEG2
SEG3
BFA
00h 00 01 02 03 04 05 01h 10 11 12 13 14 02h 20 21 22 03h 30 31 32 04h 40 41 42 05h 50 51 :
0V 0W 0X 0Y 0Z
2X 2Y 2Z 3X 3Y 3Z
1W 1X 1Y 1Z 2
nd
130 129 128 127 126 : : 5 4 3 2 1 0 Scan Address SSA
COM1 COM2
01 02 03 04 05 11 12 13 14
21 22 31 32
0V 0W 0X 0Y 1W 1X 1Y
2X 2Y 3X 3Y
st
131
SEG4
00h 01h 02h 03h -
- 81h 82h 83h
SEG130
SA Scan Order
3
rd th
BFA
New Data
COM3 COM4 COM5 COM6 : : COM127 COM128 COM129 COM130
4Y 4Z 5Y 5Z
41 42 51 52
4X 4Y
VSA
: :
130 x 130 LCD panel
5X 5Y
VSA
UX UY UZ 125th VX VY VZ 126
th
U1 U2 V1 V2 Y1 Y2 Y3 Y4 Z1 Z2 Z3 Z4 Z5
UX UY VX VY YW YX YY ZV ZW ZX ZY
WXWYWZ 127th XX XY XZ 128th YW YX YY YZ 129th ZV ZW ZX ZY ZZ 130

th
TFA
82h Y0 Y1 Y2 Y3 Y4 83h Z0 Z1 Z2 Z3 Z4 Z5
TFA
5.2.5.2
Vertical Scroll Example
There are 2 types of vertical scrolling, which are determined by the commands Vertical Scrolling Definition (33h) and Vertical Scrolling Start Address (37h). Case 1: TFA + VSA + BFA<130 N/A. Do not set TFA + VSA + BFA<130. In that case, unexpected picture will be shown. Case 2: TFA + VSA + BFA=130 (Rolling Scrolling) Example1) When MADCTR parameter ML=0, TFA=0, VSA=130, BFA=0 and VSCSAD=40.
Memory Physical Axis (0,0)
Physical Line Pointer

2
Display Axis (0,0)
VSCSAD
1
Never been used Frame Memory

Increment VSCSAD
Display

2
Display Axis (0,0)

1
VSCSAD
2 1
Never been used Frame Memory Display
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Example2) When MADCTR parameter ML=1, TFA=30, VSA=100, BFA=0 and VSCSAD=80.
Display Axis (0,0)
Never been used

2 3
VSCSAD
3
TFA
TFA
Frame Memory
Display
Increment VSCSAD
Display Axis (0,0)
Never been used

2
VSCSAD
3
3 2 1
TFA
TFA
Frame Memory
Display
Case3: TFA + VSA + BFA =132 (Scrolling with 2line buffer) Example) When MADCTR parameter ML=0, TFA=20, VSA=82, BFA=30 and VSCSAD=60.
Memory Physical Axis (0,0) TFA

1 3
Display Axis (0,0) TFA

1
Line Buffer for New Line Data (Invisible) VSCSAD

Frame Memory
2 3 4 4
BFA
Display
Increment VSCSAD
BFA
Memory Physical Axis (0,0) TFA

1 3 4
Display Axis (0,0) TFA

1 2
Line Buffer for New Line Data (Invisible)
3 45
VSCSAD BFA
BFA
Frame Memory
Display
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5.2.6
Tearing Effect Output Line
The Tearing Effect output line supplies to the MPU a Panel synchronization signal. This signal can be enabled or disabled by the Tearing Effect Line Off & On commands. The signal can be used by the MPU to synchronize Frame Memory Writing when displaying video images.
5.2.6.1 Tearing Effect Line Modes
Mode 1, the Tearing Effect Output signal consists of V-Sync (tVHD) information only before Super-frames start (only during every 4th frame and every 4th field).
tvdh = The LCD display is updating the end (4th frame) of the previous Super-frame from the Frame memory tvdl = The LCD display is updated 1st, 2nd and 3rd frames (It is possible that the begin of the 4th frame is also included for this timing) from the Frame Memory.
Mode 2, the Tearing Effect Output signal consists of only H-Sync (1 frame) information, there is one high pulse and 1 low pulse during every frame.
thdh = The LCD display is updated the end of the frame field from the Frame Memory. thdl = The LCD display is updated the begin of the frame field from the Frame Memory.
O ne super-fram e O ne fram e O ne field Fram e clock (internal) Fram e num ber Field clock (internal) Field num ber
4 th field 1 st field 2 nd field 3 rd field 4 th field 1 st field 2 nd field 3 rd field 4 th field 1 st field 2 nd field 3 rd field 4 th field 1 st field 2 nd field 3 rd field 4 th field 1 st field
1 st fram e
2 nd fram e
3 rd fram e
4 th fram e
1 st fram e
t VD L
t VD H
TE (M ode1)
tH D L tH D H
TE (M ode2)
Note: During Sleep In Mode, the Tearing Effect Output Pin is active Low.
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5.2.6.2
Tearing Effect Line Timing
The Tearing Effect signal is described below:
TE (M ode1)
t VD H t VD L
TE (M ode2)
tH D H tH D L
Table 5.2.5
AC characteristics of Tearing Effect Signal
Idle Mode Off (Frame Rate = 100Hz)

Symbol tVDL tVDH tHDL tHDH Parameter Vertical Timing Low Duration Vertical Timing High Duration Horizontal Timing Low Duration Horizontal Timing High Duration min 37.5 2.5 7.5 2.5 max unit ms ms ms ms description Mode1 Mode2
NOTE: The timings in Table 5.2.5 apply when MADCTL B4=0 and B4=1 The signals rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns.
tr tf
0.8*VDD 1
0.8*V DD1
0.2*VDD 1
0.2*V DD 1
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5.2.7
Color RED
Colour Depth Conversion Look Up Tables

Look Up Table Outputs Frame Memory Data (4-bit) R003 R002 R001 R000 R013 R012 R011 R010 R023 R022 R021 R020 R033 R032 R031 R030 R043 R042 R041 R040 R053 R052 R051 R050 R063 R062 R061 R060 R073 R072 R071 R070 G003 G002 G001 G000 G013 G012 G011 G010 G023 G022 G021 G020 G033 G032 G031 G030 G043 G042 G041 G040 G053 G052 G051 G050 G063 G062 G061 G060 G073 G072 G071 G070 B003 B002 B001 B000 B013 B012 B011 B010 B023 B022 B021 B020 B033 B032 B031 B030 RGBSET parameter 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Look Up Table Inputs 256 Color Data 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 00 01 10 11
GREEN
BLUE
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5.3 INSTRUCTION DECODER & REGISTER

The instruction decoder identifies command words arriving at the interface and routes the following data type bytes to their destination. The command set can be found in 6 INSTRUCTION DESCRIPTION section.
5.4 GRAY SIGNAL GENERATOR

As grayscale driving scheme the frame rate control (FRC) with carefully controlled mixing of the FRC pattern on each pixel and pulse width modulation (PWM) is used. The special mixing assures that the pattern placed on each pixel is different to each of its neighbors. In the Frame Rate Control 4 frames form a super frame. All 4 frames have the same duration.
5.5 GRAY SELECTOR

This block selects gray signal from gray signal generator block according to the display data RAM outputs.
5.6 SYSTEM CLOCK GENERATOR

The timing generator produces the various signals to drive the internal circuitry. Internal chip operation is not affected by operations on the data bus.
5.7 OSCILLATOR
LDS176 has on-chip oscillator which does not require external components. This oscillator output signal is used for system clock generation for internal display operation
5.8 SEGMENT DRIVER

The segment driver section includes 132x3 column outputs (S0 to S395), which should be connected directly to the LCD. The segment output signals are generated in the data processing block after the data is read out of the RAM and after processing with the appropriate orthogonal function, which represent the simultaneous selected rows. When less then 396 segments are required the unused segment outputs should be left open-circuit.
5.9 BLOCK COUNTER

This counter counts common signal block, which is composed of concurrently selected line.
5.10 COMMON DRIVER

The row driver section includes 132 row outputs (C0 to C131) which should be connected directly to the LCD.
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5.11 LCD POWER GENERATION CIRCUIT

5.11.1 LCD Power Generation Scheme
LCD power circuit generates voltages required to drive liquid crystal. The power circuit consists of booster circuits (booster1, booster2 and booster3), voltage regulators (regulator1 and regulator2) and voltage followers. Each circuit can be turn on or off separately by command (command code 1, PWRCNT) or concurrently by command (command code 2, BSTROFF/BSTRON). LCD power generation scheme is illustrated in Fig. 5.11.1.
Booster1 (x3) (x2)
Booster3 (x2) VOUT VOUT2 VXH2, VXH1, VC, VM1 generation circuit (Voltage Regulator1 & Follower)
VH VOUT
= (7/4) (VXH2-VSS)
VXH2 = (4/4) (VXH2-VSS) VXH1 = (3/4) (VXH2-VSS) VC = (2/4) (VXH2-VSS)
VDD2 VSS
VXL1 = (1/4) (VXH2-VSS) VXL2 = VSS

Discharging resistor = 3MOhm
VSS
Booster2 (x3) & Regulator2 VL VOUTL = -(3/4) (VXH2-VSS)
* VOUT is used as source power of VXH2 regulator, VOUT2 is used as source power of VXH1 and VC voltage follower, VXL1 follower use VDD2 as source power.
Fig. 5.11.1 LCD power generation scheme
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5.11.2 Booster1 Circuit

Booster1 circuit triples the voltage of VDD2-VSS and the boosted voltage is output at VOUT pin.
V DD VD D 1 VD D 2 VO U T C X 2P C X 2M VO U T 2 C X 1P C X 1M VSS VSS
C2 C2 C2 C2
V CI VO U T | VO U T -V S S | = | 3 x (V DD 2 -V S S ) | | VO U T 2-V S S | = | 2 x (V DD 2 -V S S ) |
VO U T 2
V D D2
VSS
Fig. 5.11.2
LCD power generation scheme
5.11.3 Voltage Regulator1 Circuit

5.11.3.1 Voltage Regulator1 Circuit
Voltage regulator1 circuit generates the liquid crystal drive voltage VXH2 using VOUT from the booster1 circuit. LDS176 incorporates the high-precision constant voltage source, 64-step electronic volume control function and resister to regulate VXH2 voltage. The voltage regulator circuit covers a wider temperature range with ROM look-up table function.
VOUT
VXH2 V EV B uilt-in R b
B uilt-in R a VSS
Fig. 5.11.3
Voltage regulator1 circuit (with built-in Ra and Rb)
5.11.3.2
Built-in Resistor for VXH2 Voltage Regulation
Using this resistor and the electronic volume control function allows you to control the liquid crystal drive voltage VXH2 to an optimum level for the LCD panel with the command alone, without resorting to external resistors. VXH2 output voltage can be determined from [Equation1] as long as the relation VXH2 < VOUT is met. VXH2 = (1 + Rb/Ra) * VEV = (1 + Rb/Ra) * (1 (+2*2)/218*2) * VREG VREG = 1.6V (Typ.) at Temp = 25C constant voltage source [Equation1]
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Rb/Ra in [Equation1] is the resistance ratio of the built-in VXH2 voltage-regulating resistance. This ratio can be varied in 8 levels by changing parameter RR [2:0] of electronic volume control command. Reference ratios of 1+Rb/Ra are shown in Table 5.11.1.
Table 5.11.1 Resistance Ratio according to the Parameter RR [2:0]
RR2 0 0 0 0 1 1 1 1
RR1 0 0 1 1 0 0 1 1
RR0 0 1 0 1 0 1 0 1
1 + Rb/Ra 2.9032 3.1914 3.4090 3.6585 3.8793 4.0909 4.3269 4.5454
VXH2 voltage value Small
Large
5.11.3.3
Constant Voltage Source and Electronic Volume Control Circuit
The constant voltage generates VREG - the reference voltage inside the IC. The electronic volume control circuit varies in [Equaion1] according to parameters EV [6:0] of electronic volume control command and offset value (EOF [4:0]) read from EEPROM (for the relationship between EV, EOF and EV_IN, see section 6.1.41). Table 5.11.2 lists relationship between EV_IN [6:0] and .
Table 5.11.2 Relationship between EV_IN [6:0] and
EV_IN6 EV_IN5 EV_IN4 EV_IN3 EV_IN2 EV_IN1 EV_IN0
0 0 0 0 : : 1 1 1 1
0 0 0 0 : : 1 1 1 1
0 0 0 0 : : 1 1 1 1
0 0 0 0 : : 1 1 1 1
0 0 0 0 : : 1 1 1 1
0 0 1 1 : : 0 0 1 1
0 1 0 1 : : 0 1 0 1
127 126 125 125 : : 3 2 1 0
VXH2 voltage value Small
Large
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5.11.4 Voltage Divider & Voltage Follower Circuit

The voltage divider & follower circuit generates driving voltage VXH1, VC and VXL1 from regulator output VXH2. VXH1 = (3/4) VXH2 VC = (2/4) VXH2 VXL1 = (1/4) VXH2

The booster2 circuit triples the voltage of VDD2-VSS to the negative direction and the boosted voltage is output at VOUTL pin.
VDD V DD1 VDD2 VO UTL C3M open C2M C2P C1M C1P VSS
C2 C2 C2
VCI VDD2
V SS
| VO U TL-V D D 2 | = | 3 x (V D D 2 -V SS ) |
VO U TL
Fig. 5.11.4
Booster2 circuit external cap connection
5.11.6 Voltage Regulator2 Circuit

The voltage regulator2 circuit generates the liquid crystal drive voltage VL using VOUTL as power and VXL1 as reference voltage.
V X L1 VDD2 B uilt-in R a
B uilt-in R b VL VSS
V O U TL
Fig. 5.11.5
Voltage regulator2 circuit
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The booster3 circuit doubles the voltage of VL-VC to the positive direction and the boosted voltage is used as liquid crystal drive voltage VH.
V DD VD D 1 VD D 2 VH C 5P C 5M
C2 C2
VCI VH
VC
| VH -VL | = | 2 x (VC -VL) |
VSS
VL
Fig. 5.11.6
Booster3 circuit external cap connection
5.11.8 Power Circuit Application Example

V DD VD D 1 VD D 2 C 5P C2 C 5M C1 VO U T L C 3M open C 2M C2 C 2P C 1M C2 C 1P C2 VO U T C2 VO U T 2 C X 1P C2 C X 1M C X 2P C2 C X 2M VH VX H 2 VX H 1 VC VX L1 VX L2 VL
C2 C2 C2 C2 C2 C2
VCI
C 1 = 1.0F ~ 4.7F C 2 = 0.47F ~ 1.0F VSS
Fig. 5.11.7
Power circuit application example
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5.11.9 Temperature Compensation

5.11.9.1 Temperature Sensor
The LDS176 requires temperature compensation implemented as a look up table in ROM as shown in Table 5.11.3. The temperature of the display module is sensed on chip and converted to a 7 bit digital value. Over the temperature range of 35 to +92C, the digital output of the sensor has a nominal resolution of 1C. The digital output of the temperature sensor can be read by using temperature read function (see TMPREAD command). The output of the temperature sensor can be calibrated as follows: 1. A reset is applied to the driver to trigger a temperature measurement. 2. Wait 200ms for temperature measurement to be completed. 3. At a known temperature the output value of the temperature sensor is read. 4. The temperature value read from the chip is compared with the expected value at the given temperature The temperature sensor measures the temperature about every 10 seconds and the first temperature sensing happens about 250msec after oscillator on start operation (by SLPOUT command). While the temperature conversion is being made the Busy flag is set. The read temperature value is only valid when the busy flag is zero.
!RES
SLEEP
In
Out tMEAS1 250ms Invalid
tMEAS2 10sec TEMP1 TEMP2
TD [6:0]
Fig. 5.11.8
Reset-Temperature Sense Timing
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5.11.9.2
Contrast Adjustment
The 7-bit output of the temperature sensor (TD [6:0]) is used as an address for the look up table ROM. The ROM contains 128 7-bit words EV_2, which are used as a temperature dependent offset to make EV_IN for reference voltage. LDS176 have two LUT ROM to support two different kinds liquid crystal panel, LUT can be selected by ID2 bit 4. If ID2 [4] = 0, the 1st LUT (R176_00) will be applied and if ID2 [4] = 1, the 2nd LUT (R176_01) will be applied for contrast adjustment according to the temperature.
Table 5.11.3
shows default ROM LUT output (EV_2) according to the temperature.
TEMP Sensor
LUT ROM
TD [6:0]
EV_2
EV_1 = 63
EV_IN
EV_1 is default contrast value and EV_2 is LUT value to fit the contrast according to the temperature. EV_IN is the resultant contrast value for LCD power generation circuit.
Fig. 5.11.9 Internal Contrast Adjustment Circuit
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Table 5.11.3
ROM Look-up-Table Data (R176_00) : for Kyocera Panel (RR=4)
TD [6:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
EV_2 -28 -28 -28 -26 -26 -28 -28 -26 -26 -26 -26 -24 -24 -24 -24 -22 -22 -24 -22 -22 -22 -20 -20 -20 -18 -18 -18 -16 -16 -16 -16 -14
TEMP -35 -34 -33 -32 -31 -30 -29 -28 -27 -26 -25 -24 -23 -22 -21 -20 -19 -18 -17 -16 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4
TD [6:0] 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
EV_2 -14 -14 -14 -12 -12 -12 -10 -10 -10 -10 -8 -8 -8 -6 -6 -6 -6 -4 -4 -4 -4 -4 0 0 0 0 2 2 4 4 4 4
TEMP -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
TD [6:0] 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95
EV_2 4 4 6 8 8 8 8 10 10 12 12 14 14 14 16 16 16 16 18 18 18 18 20 20 20 20 22 22 22 22 24 24
TEMP 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
TD [6:0] 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127
EV_2 24 22 24 24 26 26 28 28 28 30 30 28 28 28 30 28 28 28 28 28 28 30 30 28 28 28 28 28 28 28 28 26
TEMP 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92
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Table 5.11.4
ROM Look-up-Table Data (R176_01) : for CTZ Panel (RR=5)
TD [6:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
EV_2 63 63 63 60 56 52 48 44 40 36 34 32 30 28 26 26 26 24 24 24 24 24 24 24 24 24 24 22 22 22 22 22
TEMP -35 -34 -33 -32 -31 -30 -29 -28 -27 -26 -25 -24 -23 -22 -21 -20 -19 -18 -17 -16 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4
TD [6:0] 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
EV_2 22 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 22 22 22 22 22 22 24 24 24 26 26 26 26 26
TEMP -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
TD [6:0] 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95
EV_2 26 26 26 26 28 28 28 28 28 28 28 30 30 30 30 30 30 32 32 32 32 32 32 32 32 30 30 30 30 30 30 30
TEMP 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
TD [6:0] 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127
EV_2 30 30 30 30 30 30 30 30 30 30 30 28 28 26 24 24 22 20 20 18 18 16 14 12 10 10 8 6 4 4 2 2
TEMP 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92
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5.11.9.3
Frame Frequency Adjustment
The 7-bit output of the temperature sensor (TD [6:0]) is also used for an automatic frequency adjustment circuit. When the read temperature is decreasing state, the frame frequency is adjusted as the temperature crosses the preset boundary values, TA, TB, and TC as shown below. When the read temperature is increasing state, the frame frequency is adjusted at the preset boundary values + TH in order to avoid unstable display when the measured temperature changes around a preset boundary value.
FA [4:0] to FD [4:0] F8A [4:0] to F8D [4:0]
TEMP Sensor
Dividing Factor Selector

TD [6:0] Dividing Factor
Display Clock
TA [6:0] TB [6:0] TC [6:0] TH [3:0]
Frequency Divider
OSC
Fig. 5.11.10
Frame Frequency Adjustment Circuit
fFR (Hz)
200 180 160 140 120 100 80 60 40 10 20 (-25) (-15) 30 (-5) 40 50 60 70 80 90 100 110 120 (+5) (+15) (+25) (+35) (+45) (+55) (+65) (+75) (+85) FA TA FB TB TH FC TC FD
TD [6:0] (C)
Fig. 5.11.11
Default Frame Frequency Adjustment Chart
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5.12 POWER ON/OFF SEQUENCE

VDD1 and VDD2 can be applied in any order. VDD2 and VDD1 can be powered down in any order. During power off, if LCD is in the Sleep Out mode, VDD2 and VDD1 must be powered down minimum 120msec after !RES has been released. During power off, if LCD is in the Sleep In mode, VDD1 or VDD2 can be powered down minimum 0msec after !RES has been released. !SCE can be applied at any timing or can be permanently grounded. !RES has priority over !SCE. There will be no damage to the display module if the power sequences are not met. There will be no abnormal visible effects on the display panel during the Power On/Off Sequences. There will be no abnormal visible effects on the display between end of Power On Sequence and before receiving Sleep Out command. Also between receiving Sleep In command and Power Off Sequence. If !RES line is not held stable by host during Power On Sequence as defined in Sections 5.12.1 and 5.12.2, then it will be necessary to apply a Hardware Reset (!RES) after Host Power On Sequence is complete to ensure correct operation. Otherwise function is not guaranteed. The power on/off sequence is illustrated below:
5.12.1 Case 1 !RES line is held High or Unstable by Host at Power On

If !RES line is held High or unstable by the host during Power On, then a Hardware Reset must be applied after both VDD2 and VDD1 have been applied otherwise correct functionality is not guaranteed. There is no timing restriction upon this hardware reset.
TrPW = +/- no limit
tfPW
+/- no limit
VDD1 VDD2
Time when the latter signal rises up to 90% of its Typical Value. e.g. When VDD2 comes later, This time is defined at the cross point of 90% of 2.75V, not 90% of 2.6V. Time when the former signal falls down to 90% of its Typical Value. e.g. When VDD2 falls earlier, This time is defined at the cross point of 90% of 2.75V, not 90% of 2.6V.
tfPW!CS = +/- no limit trPW!CS = +/- no limit
!CS
H or L
trPW!RES1 = + no limit
!RES
(Power down in Sleep Out mode)
30%
tfPW!RES1 = min.120ms trPW!RES1 = + no limit
!RES
(Power down in Sleep In mode)
30%
tfPW!RES2 = min.0ns
tfPW!RES1 is applied to !RES falling in the Sleep Out Mode. tfPW!RES2 is applied to !RES falling in the Sleep In Mode.
Note: Unless otherwise specified, timings herein show cross point at 50% of signal/power level.
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LDS176
Version 0.10
5.12.2 Case 2 !RES line is held Low by host at Power On

If !RES line is held Low (and stable) by the host during Power On, then the !RES must be held low for minimum 10sec after both VDD2 and VDD1 have been applied.
TrPW = +/- no limit
tfPW
+/- no limit
VDD1 VDD2
Time when the latter signal rises up to 90% of its Typical Value. e.g. When VDD2 comes later, This time is defined at the cross point of 90% of 2.75V, not 90% of 2.6V. Time when the former signal falls down to 90% of its Typical Value. e.g. When VDD2 falls earlier, This time is defined at the cross point of 90% of 2.75V, not 90% of 2.6V.
tfPW!CS = +/- no limit trPW!CS = +/- no limit
!CS
H or L
trPW!RES1 = min.10s
!RES
(Power down in Sleep Out mode)
tfPW!RES1 = min.120ms trPW!RES1 = min.10s
!RES
(Power down in Sleep In mode)
tfPW!RES2 = min.0ns
tfPW!RES1 is applied to !RES falling in the Sleep Out Mode. tfPW!RES2 is applied to !RES falling in the Sleep In Mode.
Note: Unless otherwise specified, timings herein show cross point at 50% of signal/power level.
5.13 UNCONTROLLED POWER OFF

The uncontrolled power off means a situation when e.g. there is removed a battery without the controlled power off sequence. There will not be any damages for the display module or the display module will not cause any damages for the host or lines of the interface. At an uncontrolled power off the display will go blank and there will not be any visible effects on the display.
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LDS176
Version 0.10
5.14 POWER FLOW CHART FOR DIFFERENT POWER MODES

Normal display mode on = NORON Partial mode on = PTLON Idle mode off = IDMOFF
Idle mode on = IDMON Sleep out = SLPOUT Sleep in = SLPIN
Power on sequence
HW reset SW reset
NORON PTLON Sleep out Normal display mode on Idle mode off
SLPIN SLPOUT Sleep in Normal display mode on Idle mode off
NORON PTLON
IDMON
IDMOFF
IDMON
IDMOFF
SLPIN Sleep out Normal display mode on Idle mode on SLPOUT Sleep in Normal display mode on Idle mode on
SLPIN Sleep out Partial mode on Idle mode off SLPOUT Sleep in Partial mode on Idle mode off
IDMON
IDMOFF
IDMON
IDMOFF
PTLON NORON
Sleep out Partial mode on Idle mode on
SLPIN SLPOUT
Sleep in Partial mode on Idle mode on
PTLON NORON
Sleep out
Sleep in
Note 1: There is not any abnormal visual effect when there is changing from one power mode to another power mode. 2: There is not any limitation, which is not specified by this spec, when there is changing from one power mode to another power mode.
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INSTRUCTION DESCRIPTION
Instruction Code Table
Instruction Code0 (ISS=0)
6.1 INSTRUCTION CODE 0 (ISS=0, MESSI-8)

6.1.1
Table 6.1.1
-: Dont care
Instruction
NOP SWRESET BSTROFF BSTRON RDDID
Refer ISS D/!C !WR !RD

6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
D7
0 0 0 0 0 ID17 ID27 ID37 0 -
D6
0 0 0 0 0 ID16 ID26 ID36 0 -
D5
0 0 0 0 0 ID15 ID25 ID35 0 -
D4
0 0 0 0 0 ID14 ID24 ID34 0 -
D3
0 0 0 0 0 ID13 ID23 ID33 1 -
D2
0 0 0 0 1 ID12 ID22 ID32 0 -
D1
0 0 1 1 0 ID11 ID21 ID31 0 -
D0
0 1 0 1 0 ID10 ID20 ID30 1 -
(Code) Function
(00h) (01h) (02h) (03h) (04h) (09h) (10h) (11h) (12h) (13h) (20h) (21h) (22h) (23h) (25h) (28h) (29h) (2Ah) (2Bh) (2Ch) (2Eh) No Operation Software reset Booster off (only for test purpose) Booster on (only for test purpose) Read Display ID Dummy read ID1 read ID2 read ID3 read Read Display Status Dummy read Sleep in & booster off Sleep out & booster on Partial mode on Partial off (Normal) Display inversion off (normal) Display inversion on All pixel off (only for test purpose) All pixel on (only for test purpose) Write contrast EV = 0 to 127 Display off Display on Column address set X_ADR start: 0 XS 83h X_ADR end: XS XE 83h Row address set Y_ADR start: 0 YS 83h Y_ADR end: YS YE 83h Memory write Write data Memory read Dummy read Read data
RDDST
6.1.7
0 0 0 0 0 0
ST31 ST30 ST29 ST28 ST27 ST26 ST25 ST24 ST23 ST22 ST21 ST20 ST19 ST18 ST17 ST16 ST15 ST14 ST13 ST12 ST11 ST10 ST7 0 0 0 0 0 0 0 0 0 0 0 0 XS7 XE7 0 YS7 YE7 0 D7 0 D7 ST6 0 0 0 0 0 0 0 0 0 EV6 0 0 0 XS6 XE6 0 YS6 YE6 0 D6 0 D6 ST5 0 0 0 0 1 1 1 1 1 EV5 1 1 1 XS5 XE5 1 YS5 YE5 1 D5 1 D5 ST4 1 1 1 1 0 0 0 0 0 EV4 0 0 0 XS4 XE4 0 YS4 YE4 0 D4 0 D4 ST3 0 0 0 0 0 0 0 0 0 EV3 1 1 1 XS3 XE3 1 YS3 YE3 1 D3 1 D3 ST2 0 0 0 0 0 0 0 0 1 EV2 0 0 0 XS2 XE2 0 YS2 YE2 1 D2 1 D2 ST9 ST1 0 0 1 1 0 0 1 1 0 EV1 0 0 1 XS1 XE1 1 YS1 YE1 0 D1 1 D1 ST8 ST0 0 1 0 1 0 1 0 1 1 EV0 0 1 0 XS0 XE0 1 YS0 YE0 0 D0 0 D0
SLPIN SLPOUT PTLON NORON INVOFF INVON APOFF APON WRCNTR DISPOFF DISPON CASET
6.1.8 6.1.9 6.1.10 6.1.11 6.1.12 6.1.13 6.1.14 6.1.15 6.1.16 6.1.17 6.1.18 6.1.19
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RASET 6.1.20 RAMWR RAMRD 6.1.21 6.1.22
0 0 0 0 0 0 0
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LDS176
Version 0.10
Table 6.1.2
Instruction Code0 (ISS=0 Continued)
-: Dont care
Instruction
RGBSET

6.1.23 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 1 0 1 1 1 0 0 1 0 1 0 1 0 0 0 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
D7
0 : : : 0
D6
0 : : : 0
D5
1 : : : 1
D4
0 : : : 1
D3
1 R3 : R3 G3 : G3 B3 : B3 0
D2
1 R2 : R2 G2 : G2 B2 : B2 0
D1
0 R1 : R1 G1 : G1 B1 : B1 0
D0
1 R0 : R0 G0 : G0 B0 : B0 0
(Code) Function
(2Dh) : : : (30h) (33h) (34h) (35h) (36h) (37h) (38h) (39h) (3Ah) (DAh) (DBh) (DCh) Color set for 256 color display Red tone (000) : Red tone (111) Green tone (000) : Green tone (111) Blue tone (00) : Blue tone (11) Partial start/end address set Start address (0,1,2, , 131) End address (0,1,2, , 131) Scroll area set (2-line unit) TFA = 0,1,2, , 132 VSA = 0,1,2, , 132 BFA = 0,1,2, , 132 Tearing effect line off Tearing effect mode set & on 0: mode1, 1: mode2 Memory data access control Scroll start address of RAM SSA = 0, 1, 2, , 131 Idle mode off Idle mode on Interface pixel format Interface format Read ID1 Dummy read Read parameter Read ID2 Dummy read Read parameter Read ID3 Dummy read Read parameter
PTLAR
6.1.24
0 0 0
PSL7 PSL6 PSL5 PSL4 PSL3 PSL2 PSL1 PSL0 PEL7 PEL6 PEL5 PEL4 PEL3 PEL2 PEL1 PEL0 0 0 1 1 0 0 1 1 TFA7 TFA6 TFA5 TFA4 TFA3 TFA2 TFA1 TFA0 VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0 BFA7 BFA6 BFA5 BFA4 BFA3 BFA2 BFA1 BFA0 0 0 0 MY 0 0 0 0 1 ID17 1 ID27 1 ID37 0 0 0 MX 0 0 0 0 1 ID16 1 ID26 1 ID36 1 1 1 MV 1 1 1 1 0 ID15 0 ID25 0 ID35 1 1 1 ML 1 1 1 1 1 ID14 1 ID24 1 ID34 0 0 0 RGB 0 1 1 1 1 ID13 1 ID23 1 ID33 1 1 1 1 0 0 0 P2 0 ID12 0 ID22 1 ID32 0 0 1 1 0 0 1 P1 1 ID11 1 ID21 0 ID31 0 1 M 0 1 0 1 0 P0 0 ID10 1 ID20 0 ID30
SCRLAR
6.1.25
0 0 0 0
TEOFF TEON MADCTR VSCSAD IDMOFF IDMON COLMOD RDID1
6.1.26 6.1.27 6.1.28 6.1.29 6.1.30 6.1.31 6.1.32 6.1.33
0 0 0 0 0 0 0 0 0 0 0 0 0 0
SSA7 SSA6 SSA5 SSA4 SSA3 SSA2 SSA1 SSA0
RDID2
6.1.34
0 0 0
RDID3
6.1.35
0 0 0
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LDS176
Version 0.10
Table 6.1.3
Instruction Code0 (ISS=0 Extended code set, EXTB=0)
-: Dont care
Instruction
CLKINT CLKEXT FRMSEL

6.1.36 6.1.37 6.1.38 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 1 0 0 0 1 1 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
D7
1 1 1 1 1 1 1 BF 1 1 1 1 1 1 1 1
D6
0 0 0 0 0 TA6 TB6 TC6 0 0 T6 0 0 1 1 1 EV6 1 1 1
D5
1 1 1 1 1 TA5 TB5 TC5 1 1 T5 1 1 0 0 0 EV5 0 1 1
D4
1 1 1 FA4 FB4 FC4 FD4 1
D3
0 0 0 FA3 FB3 FC3 FD3 0
D2
0 0 1 FA2 FB2 FC2 FD2 1
D1
0 0 0 FA1 FB1 FC1 FD1 0
D0
0 1 0 FA0 FB0 FC0 FD0 1
(Code) Function
(B0h) (B1h) (B4h) (B5h) (B6h) (B7h) (B8h) (BAh) (BBh) (D1h) (D0h) (D4h) (D5h) (E-h) (F-h) Internal oscillator select External oscillator select Frame frequency select Frame frequency in Temp range A Frame frequency in Temp range B Frame frequency in Temp range C Frame frequency in Temp range D Frame frequency select (8-color) Frame frequency in Temp range A Frame frequency in Temp range B Frame frequency in Temp range C Frame frequency in Temp range D Temp range set Temp range A Temp range B Temp range C Temp hysteresis range set Hysteresis value set Temperature read back Dummy read Read parameter Display control F1/F2 pattern FR inversion-set value Electronic volume offset EV offset Dummy RR offset EEPROM write start EEPROM write end Read internal contrast (EV_IN) Dummy read Read parameter Read internal resistor ratio (RR_IN) Dummy read Read parameter Test command1. Test command2.
FRM8SEL
6.1.39
0 0 0 0 0
F8A4 F8A3 F8A2 F8A1 F8A0 F8B4 F8B3 F8B2 F8B1 F8B0 F8C4 F8C3 F8C2 F8C1 F8C0 F8D4 F8D3 F8D2 F8D1 F8D0 1 TA4 TB4 TC4 1 1 T4 1 FINV 1 1 1 1 EV4 1 0 1 0 TA3 TB3 TC3 0 TH3 1 T3 1 NL3 1 0 0 0 EV3 0 1 TA2 TB2 TC2 1 TH2 0 T2 0 FS2 NL2 0 0 0 1 EV2 1 RR2 1 TA1 TB1 TC1 1 TH1 0 T1 1 FS1 NL1 1 0 0 0 EV1 0 RR1 0 TA0 TB0 TC0 1 TH0 0 T0 0 FS0 NL0 1 1 0 0 EV0 1 RR0 -
TMPRNG
6.1.40
0 0 0 0
TMPHIS TMPREAD
6.1.41 6.1.42
0 0 0 0 0
DISCTR
6.1.43
0 0 0
EPVOL
6.1.44
0 0 0 0
EOF5 EOF4 EOF3 EOF2 EOF1 EOF0 ROF2 ROF1 ROF0
EPWRIN EPWROUT RDEV
6.1.45 6.1.46 6.1.47
0 0 0 0 0
RDRR
6.1.48
0 0 0
TEST1 TEST2
6.1.49 6.1.50
0 0
NOTE: 1) After the H/W reset by !RES pin or S/W reset by SWRESET command, each internal register becomes default state (Refer RESET TABLE section) 2) To use extended code set, EXTB should be connected to VSS. Normally, expended code set is just used for module test. If extended code is not enabled all the extended code set will be ignored and regarded as NOP (00h) command. 3) Undefined commands are treated as NOP (00 h) command. 4) Commands 10h, 12h, 13h, 20h, 21h, 25h, 28h, 29h, 30h, 33h, 36h (ML parameter only), 37h, 38h and 39h are updated during V-sync when Module is in Sleep Out Mode to avoid abnormal visual effects. During Sleep In mode, these commands are updated immediately. Read status (09h) of these commands is updated immediately both in Sleep In mode and Sleep Out mode. LEADIS Technology CONFIDENTIAL
47
LDS176
Version 0.10
6.1.2
ISS 00 00
NOP (00h)
Inst / Para NOP Parameter No Parameter D/!C 0 !WR !RD 1 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 (Code) (00h)
This command is empty command. It does not have effect on the display module. Description However it can be used to terminate RAM data write or read as described in RAMWR (Memory Write), RAMRD (Memory Read) and parameter write commands. Restriction Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value N/A N/A N/A
Register Availability
Default
Flow Chart
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LDS176
Version 0.10
6.1.3
ISS 0 0
SWRESET: Software Reset (01h)

Inst / Para SWRESET Parameter No Parameter D/!C 0 !WR !RD 1 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 1 (Code) (01h)
When the Software Reset command is written, it causes a software reset. It resets the commands and parameters to their S/W Reset default values and all segment & common Description outputs are set to VC (display off: blank display). (See default tables in each command description) Note: The Frame Memory contents are not affected by this command. It will be necessary to wait 5msec before sending new command following software reset Restriction The display module loads all display suppliers factory default values to the registers during this 5ms. If Software Reset is applied during Sleep Out mode, it will be necessary to wait 120msec before sending Sleep out command. Software Reset command cannot be sent during Sleep Out sequence.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value N/A N/A N/A
Default
SWRESET Legend Display whole blank screen Flow Chart

Set Commands to S/W Default Value
Command Parameter Display Action Mode Sequential transfer
Sleep In Mode
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LDS176
Version 0.10
6.1.4
ISS 0 0
BSTROFF: Booster Off (02h) (Only for Test Purposes)

Inst / Para BSTROFF Parameter D/!C !WR !RD 1 0 No Parameter D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 1 D0 0 (Code) (02h)
This command turns off booster related circuit (Oscillator and DC/DC Converter) and panel scanning is stopped.
COM/SEG Output
STOP STOP DISCHARGE 0V
Memory scan operation
DC charge in the capacitor
Description
LCD Driving voltage (Plus)
0V 0V
LCD Driving voltage (Minus)
Internal Oscillator
Stop
MCU interface and memory are still working and the memory keeps its contents It will be necessary to wait 5msec before sending next command, this is to allow time for the supply voltages and clock circuits to stabilise, but to discharge all the capacitor value to ground, it will take about 120msec. Restriction This command has no effect when module is already in Booster Off mode. Booster Off Mode can be exit by the Booster On Command (03h) or Sleep Out Command (11h).
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value Booster off mode Booster off mode Booster off mode
Default
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It takes more than 120msec to get into Booster Off mode after BSTROFF command issued. The results of booster off can be checked by RDDST (09h) command Bit31.
BSTROFF Stop DC/DC Converter Display whole blank
Legend
Command Parameter
Flow Chart
screen (Automatic No effect to DISP ON/OFF Command)
Stop Internal Oscillator
Display Action Mode
Booster off Mode TBD Sequential transfer
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LDS176
Version 0.10
6.1.5
ISS 0 0
BSTRON: Booster ON (03h) (Only for Test Purposes)

Inst / Para BSTRON Parameter D/!C !WR !RD 1 0 No Parameter D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 1 D0 1 (Code) (03h)
This command turns on booster related circuit (Oscillator and DC/DC converter) and panel scanning is started.
COM/SEG Output
STOP
Memory Contents
(If DISPON 29h is set)

Description
DC charge in the capacitor LCD Driving voltage (Plus) LCD Driving voltage (Minus) Internal Oscillator
0V 0V 0V Start Stop
CHARGE
Restriction
This command has no effect when module is already in Booster On mode. Booster On Mode can be exit by the Booster Off Command (02h) or Sleep In Command (10h). It will be necessary to wait 120msec for the supply voltages and clock circuits to stabilize. During 120msec after BSTRON command, display on register will be blocked to L (off).
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value Booster off mode Booster off mode Booster off mode
Default
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LDS176
Version 0.10
It takes 120msec to get into Booster On mode after BSTRON command issued. The results of booster on can be checked by RDDST (09h) command Bit31.
BSTRON Start Internal Oscillator
Legend
Command Display Memory contents In accordance with the current command table settings Parameter Display Action Mode
Flow Chart
Start DC/DC Converter
TBD
Booster On Mode
Sequential transfer
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LDS176
Version 0.10
6.1.6
ISS 0 0 0 0 0
RDDID: Read Display ID (04h)

Inst / Para RDDID Dummy Read 2nd parameter 3rd parameter 4th parameter D/!C 0 1 1 1 1 !WR 1 1 1 1 !RD 1 D7 0 D6 0 D5 0 D4 0 D3 0 D2 1 D1 0 D0 0 (Code) (04h) -
ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 1 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30
This read byte returns 24-bit display identification information. The 1st parameter is dummy data The 2nd parameter (ID17 to ID10): LCD modules manufacturer ID. The 3rd parameter (ID26 to ID20): LCD module/driver version ID The 4th parameter (ID37 to UD30): LCD module/driver ID. NOTE: Commands RDID1/2/3(DAh, DBh, DCh) read data correspond to the parameters 2,3,4 of the command 04h, respectively.
Description
Restriction
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Availability Yes Yes Yes Yes Yes Default Value ID2 (binary) 80 ~ FFh (Not Fixed) 80 ~ FFh (Not Fixed) 80 ~ FFh (Not Fixed)
Default
Power On Sequence S/W Reset H/W Reset
ID1 45h 45h 45h
ID3 03h 03h 03h
Serial I/F Mode (PS0=Low)

RDDID (04h)
Parallel I/F Mode (PS0=High)

RDDID (04h)
Host Driver
Legend
Command Parameter Display
Dummy Clock
Dummy Read
Flow Chart
Send ID1[7:0] Send ID1[7:0]
Action Mode
Send ID2[7:0]
Send ID2[7:0] Sequential transfer
Send ID3[7:0]
Send ID3[7:0]
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LDS176
Version 0.10
6.1.7
ISS 0 0 0 0 0 0
RDDST: Read Display Status (09h)

Inst / Para RDDST Dummy Read 2nd parameter 3rd parameter 4th parameter 5th parameter D/!C 0 1 1 1 1 1 !WR 1 1 1 1 1 !RD 1 D7 0 ST31 ST23 ST15 ST7 D6 0 ST30 ST22 ST14 ST6 D5 0 ST29 ST21 ST13 ST5 D4 0 ST28 ST20 ST12 ST4 D3 1 ST27 ST19 ST11 ST3 D2 0 ST26 ST18 ST10 ST2 D1 0 ST25 ST17 ST9 ST1 D0 1 ST24 ST16 ST8 ST0 (Code) (09h) -
This command indicates the current status of the display as described in the table below:
Bit ST31 ST30 ST29 ST28 ST27 ST26 ST25 ST24 ST23 ST22 ST21 ST20 ST19 ST18 ST17 ST16 ST15 ST14 ST13 ST12 ST11 ST10 ST9 ST8 ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST0 Description Booster Voltage Status Row Address Order Column Address Order Row/Column Order (MV) Scan Address Order RGB/BGR Order Not Used Not Used Not Used Interface Colour Pixel Format Definition Idle Mode On/Off Partial Mode On/Off Sleep In/Out Display Normal Mode On/Off Vertical Scrolling Status Not Used Inversion Status All Pixels On All Pixels Off Display On/Off Tearing Effect Line On/Off Not Used Not Used Not Used Tearing effect line mode Not Used Not Used Not Used Not Used Not Used Value 1=Booster on, 0=off 1=Decrement, 0=Increment 1=Decrement, 0=Increment 1= Row/column exchange (MV=1) 0= Normal (MV=0) 1=Decrement, 0=Increment 1=BGR, 0=RGB 0 0 0 010 = 8-bit / pixel, 011 = 12-bit / pixel type A 101 = 16-bit / pixel, 110 = 12-bit / pixel type B 1 = On, 0 = Off 1 = On, 0 = Off 1 = In, 0 = Out 1 = Partial Display, 0 = Normal Display 1 = Scroll on, 0 = Scroll off 0 1 = On, 0 = Off 1 = mode On, 0 = mode Off 1 = mode On, 0 = mode Off 1 = On, 0 = Off 1 = On, 0 = Off 0 0 0 0 = mode1, 1 = mode2 0 0 0 0 0
Description
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LDS176
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Restriction
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value 0000 0000_0011 0010_0000 0000_0000 0000 0XXX XX00_0XXX 0010_0000 0000_0000 0000 0000 0000_0011 0010_0000 0000_0000 0000
Default
XXX: No Change Serial I/F Mode (PS0=Low)

RDDST (09h)

RDDST (09h)
Host Driver
Legend
Dummy Clock
Dummy Read
Flow Chart
Send ST[31:24]
Send ST[31:24]
Action Mode
Send ST[23:16]
Send ST[23:16]
Sequential transfer
Send ST[15:8]
Send ST[15:8]
Send ST[7:0]
Send ST[7:0]
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LDS176
Version 0.10
6.1.8
ISS 0 0
SLPIN: Sleep In (10h)

Inst / Para SLPIN Parameter D/!C !WR !RD 1 0 No Parameter D7 0 D6 0 D5 0 D4 1 D3 0 D2 0 D1 0 D0 0 (Code) (10h)
This command causes the LCD module to enter the minimum power consumption mode. In this mode the DC/DC converter is stopped, Internal display oscillator is stopped, and panel scanning is stopped.
COM/SEG Output
Blank
STOP (Blank Display) STOP DISCHARGE 0V
Description
DC charge in the capacitor
LCD Driving voltage (Plus)
0V 0V
LCD Driving voltage (Minus)
Internal Oscillator
Stop
MCU interface and memory are still working and the memory keeps its contents This command has no effect when module is already in sleep in mode. Sleep In Mode can only be exit by the Sleep Out Command (11h). Restriction It will be necessary to wait 5msec before sending next command, this is to allow time for the supply voltages and clock circuits to stabilize. It will be necessary to wait 120msec after sending Sleep Out command (when in Sleep In Mode) before Sleep In command can be sent.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value Sleep in mode Sleep in mode Sleep in mode
Default
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LDS176
Version 0.10
It takes 120 msec to get into Sleep In mode (booster off state) after SLPIN command issued. The results of booster off can be checked by RDDST (09h) command Bit31.
SPLIN Stop DC/DC Converter
Legend
Command Parameter
Flow Chart
Display whole blank screen (Automatic No effect to DISP ON/OFF Command)
Stop Internal Oscillator
Display Action Mode
Sleep In Mode TBD Sequential transfer
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LDS176
Version 0.10
6.1.9
ISS 0 0
SLPOUT: Sleep Out (11h)

Inst / Para SLPOUT Parameter D/!C !WR !RD 1 0 No Parameter D7 0 D6 0 D5 0 D4 1 D3 0 D2 0 D1 0 D0 1 (Code) (11h)
This command turns off sleep mode. In this mode the DC/DC converter is enabled, Internal display oscillator is started, and panel scanning is started.
COM/SEG Output
STOP (Blank display)
Blank
Memory Contents
(If DISPON 29h is set)

Description
DC charge in the capacitor LCD Driving voltage (Plus) LCD Driving voltage (Minus) Internal Oscillator
0V 0V 0V Start Stop
CHARGE
This command has no effect when module is already in sleep out mode. Sleep Out Mode can only be exit by the Sleep In Command (10h). Restriction
It will be necessary to wait 5msec before sending next command, this is to allow time for the supply voltages and clock circuits to stabilize. It will be necessary to wait 120msec after sending Sleep In command (when in Sleep Out mode) before Sleep
Out command can be sent.

Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value Sleep in mode Sleep in mode Sleep in mode
Default
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It takes 120msec to become Sleep Out mode (booster on mode) after SLPOUT command issued. The results of booster on can be checked by RDDST (09h) command Bit31.
SLPOUT Start Internal Oscillator
Legend
Command Display whole blank screen for 2 frames (Automatic No effect to DISP ON/OFF Commands) Parameter Display Action Mode
Flow Chart
Start DC-DC Converter
TBD
Display Memory contents in accordance with the current command table settings
Sequential transfer
Sleep Out Mode
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6.1.10 PTLON: Partial Display Mode On (12h)

ISS 0 0 Inst / Para PTLON Parameter D/!C !WR !RD 1 0 No Parameter D7 0 D6 0 D5 0 D4 1 D3 0 D2 0 D1 1 D0 0 (Code) (12h)
Description Restriction
This command turns on Partial mode. The partial mode window is described by the Partial Area command (30H) Exit from PTLON by Normal Display Mode On command (13H) There is no abnormal visual effect during mode change between Normal mode On <-> Partial mode On. This command has no effect when Partial mode is active.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value Partial mode off Partial mode off Partial mode off
Default
Flow Chart
See Partial Area (30h)
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6.1.11 NORON: Normal Display Mode On (13h)

ISS 0 0 Inst / Para NORON Parameter D/!C !WR !RD 1 0 No Parameter D7 0 D6 0 D5 0 D4 1 D3 0 D2 0 D1 1 D0 1 (Code) (13h)
This command returns the display to normal mode. Normal display mode on means Partial mode off, Scroll mode Off. Exit from NORON by the Partial mode On command (12h) There is no abnormal visual effect during mode change between Normal mode On <-> Partial mode On. This command has no effect when Normal Display mode is active.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value Normal Mode On Normal Mode On Normal Mode On
Default
Flow Chart
See Partial Area and Vertical Scrolling Definition Descriptions for details of when to use this command
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6.1.12 INVOFF: Display Inversion Off (20h)

ISS 0 0 Inst / Para INVOFF Parameter D/!C !WR !RD 1 0 No parameter D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 0 (Code) (20h)
This command is used to recover from display inversion mode. This command makes no change of contents of frame memory. This command does not change any other status. (Example) Memory Description Display
Restriction
This command has no effect when module is already inversion off mode. NOTE: In case of normally black panel, resultant display after INVOFF and INVON will be exchanged.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value Display Inversion off Display Inversion off Display Inversion off
Default
Legend Display Inversion On Mode

Flow Chart
INVOFF
Action Mode
Display Inversion OFF Mode
Sequential transfer
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6.1.13 INVON: Display Inversion On (21h)

ISS 0 0 Inst / Para INVON Parameter D/!C !WR !RD 1 0 No Parameter D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 1 (Code) (21h)
Description
This command is used to enter into display inversion mode This command makes no change of contents of frame memory. This command does not change any other status. To exit from Display Inversion On, the Display Inversion Off command (20h) should be written. (Example) Memory Display
Restriction
This command has no effect when module is already Inversion On mode. NOTE: In case of normally black panel, resultant display after INVOFF and INVON will be exchanged.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value Display Inversion off Display Inversion off Display Inversion off
Default
Display Inversion OFF Mode
Legend
Flow Chart
INVON
Action Mode
Display Inversion ON Mode
Sequential transfer
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6.1.14 APOFF: All Pixels Off (22h) (Only for Test Purposes)
ISS 0 0 Inst / Para APOFF Parameter D/!C !WR !RD 1 0 No Parameter D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 1 D0 0 (Code) (22h)
Description
This command is only used for test purpose e.g. pixel response time (on/off) measurements on the passive matrix display. Therefore, it is possible that this command is not used for final product software. All driver outputs become Low data state and display becomes black. This command makes no change of contents of display memory. This command does not change any other status. Exit commands are All Pixels On, Normal Display Mode On and Partial Display On. The display is showing the contents of the frame memory after Normal Display Mode On and Partial Display On commands. (Example) Memory Display
Restriction
This command has no effect when module is already All Pixel Off mode.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value All pixel off mode disable All pixel off mode disable All pixel off mode disable
Default
Normal Display Mode
Legend
Command Parameter
Flow Chart
APOFF
Display Action Mode
All Pixel OFF Mode
Sequential transfer
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6.1.15 APON: All Pixels On (23h) (Only for Test Purposes)

ISS 0 0 Inst / Para APON Parameter D/!C !WR !RD 1 0 No Parameter D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 1 D0 1 (Code) (23h)
Description
This command is only used for test purpose e.g. pixel response time (on/off) measurements on the passive matrix display. Therefore, it is possible that this command is not used for final product software. All driver outputs become High data state and display becomes white. This command makes no change of contents of display memory. This command does not change any other status. Exit commands are All Pixels Off, Normal Display Mode On and Partial Display On. The display is showing the contents of the frame memory after Normal Display Mode On and Partial Display On commands. (Example) Memory Display
Restriction
This command has no effect when module is already All Pixel On mode.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value All pixel on mode disable All pixel on mode disable All pixel on mode disable
Default
Normal Display Mode
Legend
Command Parameter
Flow Chart
APON
Display Action Mode
All Pixel ON Mode
Sequential transfer
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6.1.16 WRCNTR: Write Contrast (3Fh)

ISS 0 Inst / Para WRCNTR D/!C 0 1 !WR !RD 1 1 D7 0 D6 0 EV6 D5 1 EV5 D4 0 EV4 D3 0 EV3 D2 1 EV2 D1 0 EV1 D0 1 EV0 (Code) (25h) -
0 Parameter NOTE: - Dont care
This command is used to fine tuning the contrast of the current display. This contrast values can effect segment and common outputs. Parameter range: 0-127dec. MSB is EV6 and LSB is EV0. Default value: 63dec (3Fh) Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value 3Fh 3Fh 3Fh
Default
WRCNTR
EV [6:0]
Legend
Flow Chart
New Contrast value Loaded
Action Mode Sequential transfer
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6.1.17 DISPOFF: Display Off (28h)

ISS 0 0 Inst / Para DISPOFF Parameter D/!C !WR !RD 1 0 No Parameter D7 0 D6 0 D5 1 D4 0 D3 1 D2 0 D1 0 D0 0 (Code) (28h)
Description
This command is used to enter into DISPLAY OFF mode. In this mode, the output from Frame Memory is disables and blank page inserted. This command makes no change of contents of frame memory. This command does not change any other status. There will be no abnormal visible effect on the display. Exit from this command by Display On (29h) (Example) Memory Display
Restriction
This command has no effect when module is already in Display Off mode.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value Display off Display off Display off
Default
Legend Display On Mode

Flow Chart
DISPOFF
Action Mode
Display Off Mode
Sequential transfer
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6.1.18 DISPON: Display On (29h)

ISS 0 0 Inst / Para DISPON Parameter D/!C !WR !RD 1 0 No Parameter D7 0 D6 0 D5 1 D4 0 D3 1 D2 0 D1 0 D0 1 (Code) (29h)
This command is used to recover from DISPLAY OFF mode. Output from the Frame Memory is enabled. This command makes no change of contents of frame memory. This command does not change any other status. (Example) Memory Description Display
Restriction
This command has no effect when module is already in Display On mode.

Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value Display off Display off Display off
Default
Display Off Mode
Legend Command Parameter
Flow Chart
DISPON
Display Action
Display On Mode
Mode Sequential transfer
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6.1.19 CASET: Column Address Set (2Ah)

ISS 0 0 0 Inst / Para CASET 1 Parameter 2nd Parameter
st
D/!C 0 1 1
!WR
!RD 1 1 1
D7 0 XS7 XE7
D6 0 XS6 XE6
D5 1 XS5 XE5
D4 0 XS4 XE4
D3 1 XS3 XE3
D2 0 XS2 XE2
D1 1 XS1 XE1
D0 0 XS0 XE0
(Code) (2Ah) -
This command is used to define area of frame memory where MCU can access. This command makes no change on the other driver status. The value of XS [7:0] and XE [7:0] are referred when RAMWR command comes. Each value represents one column line in the Frame Memory. (Example)
XS [7:0]
Description
XE [7:0]
Restriction
XS [7:0] always must be equal to or less than XE [7:0] When XS [7:0] or XE [7:0] is greater than 83h, data of out of range will be ignored. (Parameter range: 0 XS [7:0] XE [7:0] 131(83h))
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value XS [7:0] 01h (1d) 01h (1d) 01h (1d) XE [7:0] 82h (130d) 82h (130d) 82h (130d)
Status
Default
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CASET
1 parameter XS [7:0] 2 parameter XE [7:0]

nd
st
RASET
Legend Command
1 parameter YS [7:0]
st
Parameter Display
Flow Chart
2 parameter YE [7:0]
nd
IF Needed
RAMWR
Video Data D1[7:0],D2[7:0].. Dn[7:0]
Any Command
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6.1.20 RASET: Row Address Set (2Bh)

ISS 0 0 0 Inst / Para RASET 1 parameter 2nd parameter
st
D/!C 0 1 1
!WR
!RD 1 1 1
D7 0 YS7 YE7
D6 0 YS6 YE6
D5 1 YS5 YE5
D4 0 YS4 YE4
D3 1 YS3 YE3
D2 0 YS2 YE2
D1 1 YS1 YE1
D0 1 YS0 YE0
(Code) (2Bh) -
This command is used to define area of frame memory where MCU can access. This command makes no change on the other driver status. The value of YS [7:0] and YE [7:0] are referred when RAMWR command comes. Each value represents one column line in the Frame Memory. (Example) Description
YS [7:0]
YE [7:0]
YS [7:0] always must be equal to or less than YE [7:0] When YS [7:0] or YE [7:0] is greater than 83h, data of out of range will be ignored. (Parameter range: 0 YS [7:0] YE [7:0] 131(83h))
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes
Restriction
Status
Default Value YS [7:0] 01h (1d) 01h (1d) 01h (1d) YE [7:0] 82h (130d) 82h (130d) 82h (130d)
Default
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IF Needed
CASET
1 parameter XS [7:0] 2 parameter XE [7:0]

nd
st
RASET
Legend Command
1 parameter YS [7:0]
st
Parameter Display Action
Flow Chart
2 parameter YE [7:0]
nd
RAMWR
IF Needed
Video Data D1[7:0],D2[7:0].. Dn[7:0]
Any Command
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6.1.21 RAMWR: Memory Write (2Ch)

ISS 0 0 : 0 Inst / Para RAMWR Data write : Data write D/!C 0 1 : 1 !WR : !RD 1 1 : 1 D7 0 D7 : D7 D6 0 D6 : D6 D5 1 D5 : D5 D4 0 D4 : D4 D3 1 D3 : D3 D2 1 D2 : D2 D1 0 D1 : D1 D0 0 D0 : D0 (Code) (2Ch) : -
Description
Restriction
This command is used to transfer data MCU to frame memory. This command makes no change to the other driver status. When this command is accepted, the column register and the row register are reset to the Start Column/Start Row positions. The Start Column/Start Row positions are different in accordance with MADCTL setting. (See section 5.2.2) Then D[7:0] is stored in frame memory and the column register and the row register incremented as in Fig. 5.2.1. Frame Write can be canceled by sending any other command. In all color modes, there is no restriction on length of parameters.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value Contents of memory is set randomly Contents of memory is remained Contents of memory is remained
Default
RAMWR
Legend Command Parameter
Video Data
Flow Chart
D1[7:0],D2[7:0], .,Dn[7:0]
Display Action Mode Sequential transfer
Any Command
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6.1.22 RAMRD: Memory Read (2Eh)

ISS 0 0 0 : 0 Inst / Para RAMRD Dummy read Data read : Data read D/!C 0 1 1 : 1 !WR 1 1 : 1 !RD 1 : D7 0 D7 : D7 D6 0 D6 : D6 D5 1 D5 : D5 D4 0 D4 : D4 D3 1 D3 : D3 D2 1 D2 : D2 D1 1 D1 : D1 D0 0 D0 : D0 (Code) (2Eh) : -
Description
Restriction
This command is used to transfer data from frame memory to MCU. This command makes no change to the other driver status. When this command is accepted, the column register and the row register are reset to the Start Column/Start Row positions. The Start Column/Start Row positions are different in accordance with MADCTL setting. (See section 5.2.2) Then D[7:0] is read back from the frame memory and the column register and the row register incremented as in Fig. 5.2.1. Frame Read can be canceled by sending any other command. In all color modes, the Frame Read is always 12-bit so there is no restriction on length of parameters. Note-Memory Read is only possible via the Parallel Interface.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value Contents of memory is set randomly Contents of memory is remained Contents of memory is remained
Default
RAMRD
Legend Command
Dummy
Parameter Display
Flow Chart
Video Data D1[7:0],D2[7:0].. Dn[7:0]
Any Command
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6.1.23 RGBSET: Colour Set for 256-Color Display (2Dh)

ISS 0 0 0 0 0 0 0 0 0 0 Inst / Para RGBSET 1 parameter : th 8 parameter 9th parameter : th 16 parameter 17th parameter : 20th parameter
st
D/!C 0 1 1 1 1 1 1 1 1 1
!WR
!RD 1 1 1 1 1 1 1 1 1 1
D7 0 -
D6 0 -
D5 1 -
D4 0 -
D3 1 R03 Rn3 R73 G03 Gn3 G73 B03 Bn3 B33
D2 1 R02 Rn2 R72 G02 Gn2 G72 B02 Bn2 B32
D1 0 R01 Rn1 R71 G01 Gn1 G71 B01 Bn1 B31
D0 1 R00 Rn0 R70 G00 Gn0 G70 B00 Bn0 B30
(Code) (2Dh) -
Description
Restriction
This command is used to define the LUT for 8bit-to-12bit color depth conversations. (See also section 5.2.7) 20 Bytes must be written to the LUT regardless of the color mode. Only the values in Section 5.2.7 are referred. This command has no effect on other commands/parameters and Contents of frame memory. Visible change takes effect next time the Frame Memory is written to. Do not send any command before the last data is sent or LUT is not defined correctly.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value Random values Contents of the look-up table protected Random values
Default
RGBSET
Legend Command
Flow Chart
1 parameter R0 [3:0] : 8th parameter R7 [3:0] 9th parameter G0 [3:0] : 16th parameter G7 [3:0] th 17 parameter B0 [3:0] : 20th parameter B3 [3:0]
st
Parameter Display Action Mode Sequential transfer
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6.1.24 PTLAR: Partial Area (30h)

ISS 0 0 0 Inst / Para PTLAR 1 parameter 2nd parameter
st
D/!C 0 1 1
!WR
!RD 1 1 1
D7 0
D6 0
D5 1
D4 1
D3 0
D2 0
D1 0
D0 0
(Code) (30h) -
PSL7 PSL6 PSL5 PSL4 PSL3 PSL2 PSL1 PSL0 PEL7 PEL6 PEL5 PEL4 PEL3 PEL2 PEL1 PEL0
This command defines the partial modes display area. There are 2 parameters associated with this command, the first defines the Start Line (PSL) and the second the End Line (PEL), as illustrated in the figures below. PSL and PEL refer to the Frame Memory Line counter. If End Line > Start Line when MADCTL ML=0:
COM0: Not displayed Start Line Non-displaying Area
PSL [7:0]
Partial Display Area
PEL [7:0]
End Line Non-displaying Area COM131: Not displayed
If End Line > Start Line when MADCTL ML=1:

End Line Non-displaying Area Non-displaying Area COM0: Not displayed
PEL [7:0]
Description
PSL [7:0]
Start Line (Row1) Non-displaying Area COM131: Not displayed
If End Line < Start Line when MADCTL ML=0:

End Line COM0: Not displayed
PEL [7:0]
Non-displaying Area
PSL [7:0]
Start Line (Row1) COM131: Not displayed
* Row1: Frame memory row address 1. If End Line = Start Line then the Partial Area will be one block (4-line) deep.
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Restriction
PSL[7:0] and PEL[7:0] is based on block(4-line) unit, so, lower 2-bits (PSL[1:0], PEL[1:0]) are always assumed to 0. PSL[7:0]=00h, 04h, 08h, 0Ah, , 80h PEL[7:0]= 00h, 04h, 08h, 0Ah, , 80h PSL[7:0] and PEL[7:0] have offset address (-4) in this driver. So, to display COM0 to COM32 in partial mode partial address should be PSL[7:0] = 80h, PEL[7:0] = 28h
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value PSL [7:0] 00h 00h 00h PEL [7:0] 80h 80h 80h
Status
Default
1. To Enter Partial Mode
2. To Exit Partial Mode
PTLAR
Partial Mode
DISPOFF
PSL [7:0]
Optional To prevent Tearing Effect Image display
PEL [7:0]
NORON Legend
PTLON
Partial Mode OFF

Flow Chart
Partial Mode
RAMRW
Video Data D1[7:0],D2[7:0].. Dn[7:0]
DISPON
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6.1.25 SCRLAR: Scroll Area (33h) (Not used: Removed in this driver)
ISS 0 0 0 0 Inst / Para SCRLAR 1 parameter 2nd parameter 3rd parameter
st
D/!C 0 1 1 1
!WR
!RD 1 1 1 1
D7 0
D6 0
D5 1
TFA5 BFA5
D4 1
TFA4 VSA4 BFA4
D3 0
TFA3 VSA3 BFA3
D2 0
TFA2 VSA2 BFA2
D1 1
TFA1 VSA1 BFA1
D0 1
TFA0 VSA0 BFA0
(Code) (33h) -
TFA7 TFA6 BFA7 BFA6
VSA7 VSA6 VSA5
This command defines the Vertical Scrolling Area of the display. When MADCTL ML=0 The 1st parameter TFA [7:0] describes the Top Fixed Area (in No. of lines from Top of the Frame Memory and Display). The 2nd parameter VSA [7:0] describes the height of the Vertical Scrolling Area (in No. of lines of the Frame Memory [not the display] from the Vertical Scrolling Start Address) The first line appears immediately after the bottom most line of the Top Fixed Area. The 3rd parameter BFA [7:0] describes the Bottom Fixed Area (in No. of lines from Bottom of the Frame Memory and Display). TFA, VSA and BFA refer to the Frame Memory Line Pointer. Description
Top Fixed Area
(0,0)
TFA [7:0]
Scroll Area
VSA [7:0]
Bottom Fixed Area
BFA [7:0]
Restriction
The condition is (TFA+VSA+BFA) 130, otherwise Scrolling mode is undefined. In Vertical Scroll Mode, MADCTL parameter MV should be set to 0-this only affects the Frame Memory Write. TFA[7:0], VSA[7:0] and BFA[7:0] is based on 1-line unit. TFA[7:0]= 00h, 01h, 02h, 03h, , 84h VSA[7:0]= 00h, 01h, 02h, 03h, , 84h BFA[7:0]= 00h, 01h, 02h, 03h, , 84h
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Status
Default
Power On Sequence S/W Reset H/W Reset 1.To enter Vertical Scroll Mode:
Normal Mode
TFA [7:0] 00h 00h 00h
Default Value VSA [7:0] 84h 84h 84h
BFA [7:0] 00h 00h 00h
Legend
Command Parameter
SCRLAR
st
Parameter TFA[7:0]
Display Action
nd
Parameter VSA[7:0] Mode
rd
Parameter BFA[7:0]
Sequential transfer
CASET
st
Parameter XS[7:0]
nd
Parameter XE[7:0]
RASET
Redefines the Frame Memory Window that the scroll data will be written to. See NOTE
Flow Chart
Only required for non-rolling scrolling
st
Parameter YS[7:0]
nd
Parameter YE[7:0]
MADCTL
Parameter
Optional It may be necessary to redefine the Frame Memory Write Direction.
RAMRW
Scroll Video Data
VSCSAD 1
st
Parameter SSA[7..0]
Scroll Mode
NOTE: The Frame Memory Window size must be defined correctly otherwise undesirable image will be displayed.
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2. Continuous Scroll:
Normal Mode
Legend
Command
CASET
st
Parameter XS[7:0]
nd
Parameter XE[7:0]
RASET
Only required for non-rolling scrolling
st
Parameter YS[7:0]
nd
Parameter YE[7:0]
RAMRW
Scroll Video Data
VSCSAD
Flow Chart
1
st
Parameter SSA[7:0]
3. To Exit Vertical Scroll Mode:

Scroll Mode
DISPOFF NORON/PTLON
Scroll Mode OFF
RAMRW
Video Data D1[7:0],D2[7:0].. Dn[7:0]
DISPON
NOTE: Scroll Mode can be exit by both the Normal Display Mode On(13h) and Partial Mode On (12h) commands.
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6.1.26 TEOFF: Tearing Effect Line OFF (34h)

ISS 0 0 Inst / Para TEOFF Parameter D/!C !WR !RD 1 0 No Parameter D7 0 D6 0 D5 1 D4 1 D3 0 D2 1 D1 0 D0 0 (Code) (34h)
Description This command is used to turn OFF (Active Low) the Tearing Effect output signal from the TE signal line. Restriction This command has no effect when Tearing Effect output is already OFF.
Status
Default Value Tearing effect off Tearing effect off Tearing effect off
Default
Legend
Command
TE Line Output ON
Parameter Display
Flow Chart
TEOFF
Action Mode
TE Line Output OFF
Sequential transfer
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6.1.27 TEON: Tearing Effect Line ON (35h)

ISS 0 0 Inst / Para TEON Parameter D/!C 0 1 !WR !RD 1 1 D7 0 D6 0 D5 1 D4 1 D3 0 D2 1 D1 0 D0 1 M (Code) (35h) -
Description
This command is used to turn ON the Tearing Effect output signal from the TE signal line. This output is not affected by changing MADCTL bit ML. The Tearing Effect Line On has one parameter, which describes the mode of the Tearing Effect Output Line. (-=Dont Care). See section 5.2.6 for more information.
Note: During Sleep In Mode with Tearing Effect Line On, Tearing Effect Output pin will be active Low.
Restriction
This command has no effect when Tearing Effect output is already OFF.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In
Status Power On Sequence S/W Reset H/W Reset
Availability Yes Yes Yes Yes Yes

Default Value Tearing effect off & M=0 Tearing effect off & M=0 Tearing effect off & M=0
Default
TE Line Output OFF
Legend
Command Parameter
TEON Flow Chart M
TE Line Output ON
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LDS176
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6.1.28 MADCTR: Memory Data Access Control (36h)

ISS 0 0 Inst / Para MADCTR Parameter D/!C 0 1 !WR !RD 1 1 D7 0 MY D6 0 MX D5 1 MV D4 1 ML D3 0 RGB D2 1 D1 1 D0 0 (Code) (36h) -
This command defines read/write scanning direction of frame memory. This command makes no change on the other driver status. Note: B4 affects to Partial Area (30h), Vertical Scrolling Definition (33h), Vertical Scrolling Start address (37h), Partial On (12h) commands Bit Assignment
Bit MY MX MV ML RGB NAME ROW ADDRESS ORDER COLUMN ADDRESS ORDER ROW/COLUMN SELECTION LINE ADDRESS ORDER RGB-BGR ORDER DESCRIPTION These 3bits controls MCU to memory write/read direction. (See Section 5.2.2 MCU to memory write/read direction) LCD refresh direction control Color selector switch control (0=RGB color filter panel, 1=BGR color filter panel)
ML: Line (Scan) Address Order ML=0

Memory
Sent First Sent 2nd Sent 3rd
Display
Sent last
Description
ML=1
Memory
Sent last
Display
Sent 3rd Sent 2nd Sent First
RGB=0
RG B
RGB: RGB-BGR Order RGB=1

RG B RG B
SIG1 SIG1
Driver IC SIG2 SIG2
SIG130 SIG130
RG B RG B
SIG1 SIG1
Driver IC SIG2 SIG2
RG B
SIG130 SIG130
BGR BGR
RG B RG B RG B RG B
BGR BGR BGR BGR
LCD Panel
LCD Panel
Restriction
D2, D1 and D0 of the 1st parameter are set to 000internally.
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Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset
Availability Yes Yes Yes Yes Yes Default Value MY=0,MX=0,MV=0,ML=0,RGB=0 No Change MY=0,MX=0,MV=0,ML=0,RGB=0
Default
MADCTL
Legend
Command Parameter
1 parameter
st
Flow Chart
(MY, MX, MV, ML, RGB)
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6.1.29 VSCSAD: Vertical Scroll Start Address of RAM (37h) (Not used: Removed in this driver)
ISS 0 0 Inst / Para VSCSAD Parameter D/!C 0 1 !WR !RD 1 1 D7 0 D6 0 D5 1 D4 1
SSA4
D3 0
SSA3
D2 1
SSA2
D1 1
SSA1
D0 1
SSA0
(Code) (37h) -
SSA7 SSA6 SSA5
This command is used together with Vertical Scrolling Definition (33h). These two commands describe the scrolling area and the scrolling mode. The Vertical Scrolling Start Address command has one parameter which describes which line in the Frame Memory will be written as the first line after the last line of the Top Fixed Area on the display as illustrated below: This command Start the scrolling. Exit from V-scrolling mode by commands Partial mode On (12h) or Normal mode On (13h). When MADCTL ML=0 Example: When Top Fixed Area=Bottom Fixed Area=00, Vertical Scrolling Area=130 and Vertical Scrolling Pointer SSA=3. (Example) (0,0) scan address Display Memory
SSA [7:0]
Scroll start address
Description
0 1 2 3 4 : ; ; 130 131
COM0 COM1 COM2 : : : : COM129 COM130 COM131
(0,131)
When MADCTL ML =1 Example: When Top Fixed Area= Bottom Fixed Area=00, Vertical Scrolling Area=130 and SSA=3 (Example) (0,0) scan address Display Memory
SSA [7:0]
Scroll start address
131 130 : : : 4 3 2 1 0
COM0 COM1 COM2 : : : COM129 COM130 COM131
(0,131)
NOTE: When new Pointer position and Picture Data are sent, the result on the display will happen at the next Panel Scan to avoid tearing effect. SSA refers to the Frame Memory line Pointer. Since the value of the Vertical Scrolling Start Address is absolute (with reference to the Frame Memory), it must not enter the fixed area (defined by Vertical Scrolling Definition (33h)-otherwise undesirable image will be displayed on the Panel. SSA[7:0] is based on 1-line unit. SSA[7:0] = 00h, 01h, 02h, 03h, , 83h
Restriction
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LDS176
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Availability Yes Yes No No Yes Default Value 00 00 00
Default
Flow Chart
See Vertical Scrolling Definition (33h) description.
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6.1.30 IDMOFF: Idle Mode Off (38h)

ISS 0 0 Inst / Para IDMOFF Parameter D/!C !WR !RD 1 0 No Parameter D7 0 D6 0 D5 1 D4 1 D3 1 D2 0 D1 0 D0 0 (Code) (38h)
Description
Restriction
This command is used to recover from Idle mode on. There will be no abnormal visible effect on the display mode change transition. In the idle off mode, 1. LCD can display maximum 4k colors. 2. Normal frame frequency is applied. This command has no effect when module is already in idle off mode.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value Idle mode off Idle mode off Idle mode off
Default
Idle on mode
Legend
Command Parameter
IDMOFF Display
Flow Chart
Idle off mode
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6.1.31 IDMON: Idle Mode On (39h)

ISS 0 0 Inst / Para IDMON Parameter D/!C !WR !RD 1 0 No Parameter D7 0 D6 0 D5 1 D4 1 D3 1 D2 0 D1 0 D0 1 (Code) (39h)
This command is used to enter into Idle mode on. There will be no abnormal visible effect on the display mode change transition. In the idle on mode, 1. Color expression is reduced. The primary and the secondary colors using MSB of each R, G and B in the Frame Memory, 8 color depth data is displayed. 2. 8-Color mode frame frequency is applied. 3. Exit from IDMON by Idle Mode Off (38h) command (Example) Memory Display
Description
Color Black Blue Red Magenta Green Cyan Yellow White
R 3 R 2 R 1 R0 0XXX 0XXX 1XXX 1XXX 0XXX 0XXX 1XXX 1XXX
G3 G2 G1 G0 0XXX 0XXX 0XXX 0XXX 1XXX 1XXX 1XXX 1XXX
X: dont care B 3 B4 B 1 B0 0XXX 1XXX 0XXX 1XXX 0XXX 1XXX 0XXX 1XXX
Restriction
This command has no effect when module is already in idle on mode.

Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value Idle mode off Idle mode off Idle mode off
Default
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Idle off mode
Legend
Command Parameter
IDMON Display
Flow Chart
Idle on mode
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LDS176
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6.1.32 COLMOD: Interface Pixel Format (3Ah)

ISS 0 0 Inst / Para COLMOD Parameter D/!C 0 1 !WR !RD 1 1 D7 0 D6 0 D5 1 D4 1 D3 1 D2 0 P2 D1 1 P1 D0 0 P0 (Code) (3Ah) -
Description This command is used to define the format of RGB picture data, which is to be transferred via the MCU Interface. The formats are shown in the table.
Interface Format Not Defined Not Defined 8Bit/Pixel 12Bit/Pixel (Type A) Not Defined 16Bit/Pixel 12Bit/Pixel (Type B) Not Defined D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1
NOTE: In 8 Bit/Pixel mode, the LUT is applied to transfer data into the Frame Memory. The 16bit/pixel format is dithered to 12bit/pixel to transfer data into Frame Memory
Restriction There is no visible effect until the Frame Memory is written to.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value 12Bit/Pixel (Type A) No Change 12Bit/Pixel (Type A)
Default
Example:
16Bit/Pixel Mode
Legend
Command Parameter
COLMOD
Display Action
Flow Chart
011
12Bit/Pixel (Type A) Mode
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6.1.33 RDID1: Read ID1 Value (DAh)

ISS 0 0 0 Inst / Para RDID1 Dummy read 2nd Parameter D/!C 0 1 1 !WR 1 1 !RD 1 D7 1 D6 1 D5 0 D4 1 D3 1 D2 0 D1 1 D0 0 (Code) (DAh) -
ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10
This read byte returns 8-bit LCD modules manufacturer ID Description The 1st parameter is dummy data The 2nd parameter (ID17 to ID10): LCD modules manufacturer ID. NOTE: See command RDDID (04h), 2nd parameter.
Restriction
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value 45h 45h 45h
Default

RDID1 (DAh)

RDID1 (DAh)
Legend
Command Parameter
Flow Chart
Send 2 parameter
nd
Host Driver
Display Action Mode
Dummy Read
Send 2 parameter
nd
Sequential transfer
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6.1.34 RDID2: Read ID2 Value (DBh)

ISS 0 0 0 Inst / Para RDID2 Dummy read 2nd Parameter D/!C 0 1 1 !WR 1 1 !RD 1 D7 1 1 D6 1 D5 0 D4 1 D3 1 D2 0 D1 1 D0 1 (Code) (DBh) -
ID26 ID25 ID24 ID23 ID22 ID21 ID20
This read byte returns 8-bit LCD module/driver version ID The 1st parameter is dummy data Description The 2nd parameter (ID26 to ID20): LCD module/driver version ID Parameter Range: ID=80h to FFh NOTE: See command RDDID (04h), 3rd parameter. Restriction
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value 80 ~ FFh (Not Fixed) 80 ~ FFh (Not Fixed) 80 ~ FFh (Not Fixed)
Default

RDID2 (DBh)

RDID2 (DBh)
Legend
Command Parameter
Host Driver
Display Action Mode
Flow Chart
Send 2 parameter
nd
Dummy Read
Send 2 parameter
nd
Sequential transfer
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6.1.35 RDID3: Read ID3 Value (DCh)

ISS 0 0 0 Inst / Para RDID3 Dummy read 2nd Parameter D/!C 0 1 1 !WR 1 1 !RD 1 D7 1 D6 1 D5 0 D4 1 D3 1 D2 1 D1 0 D0 0 (Code) (DCh) -
This read byte returns 8-bit LCD module/driver ID. Description The 1st parameter is dummy data The 2nd parameter (ID37 to ID30): LCD module/driver ID. NOTE: See command RDDID (04h), 4th parameter. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value 03h 03h 03h
Restriction
Default

RDID3 (DCh)

RDID3 (DCh)
Legend
Command Parameter
Host Driver
Display Action Mode
Flow Chart
Send 2 parameter
nd
Dummy Read
Send 2 parameter
nd
Sequential transfer
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6.1.36 CLKINT: Internal Oscillator (B0h)

ISS 0 0 Inst / Para CLKINT Parameter D/!C !WR !RD 1 0 No Parameter D7 1 D6 0 D5 1 D4 1 D3 0 D2 0 D1 0 D0 0 (Code) (B0h)
Select and using internal oscillator. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value Internal OSC mode Internal OSC mode Internal OSC mode
Default
External OSC Mode
Legend
Command Parameter
CLKINT Display
Flow Chart
Internal OSC Mode
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6.1.37 CLKEXT: External Oscillator (B1h)

ISS 0 0 Inst / Para CLKEXT Parameter D/!C !WR !RD 1 0 No Parameter D7 1 D6 0 D5 1 D4 1 D3 0 D2 0 D1 0 D0 1 (Code) (B1h)
Select and using external oscillator. When an external oscillator is used the external oscillator is connected to the OSC pad.
Availability Yes Yes Yes Yes Yes Default Value Internal OSC mode Internal OSC mode Internal OSC mode
Default
Internal OSC Mode
Legend
Command
CLKEXT
Parameter Display
Flow Chart
External OSC Mode
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6.1.38 FRMSEL: Frame frequency in normal mode (B4h)

ISS 0 0 0 0 0 Inst / Para FRMSEL 1 parameter 2nd parameter 3rd parameter 4th parameter
st
D/!C 0 1 1 1 1
!WR
!RD 1 1 1 1 1
D7 1 -
D6 0 -
D5 1
-
D4 1
FA4 FB4 FC4 FD4
D3 0
FA3 FB3 FC3 FD3
D2 1
FA2 FB2 FC2 FD2
D1 0
FA1 FB1 FC1 FD1
D0 0
FA0 FB0 FC0 FD0
(Code) (B4h) -
Select frame frequency in normal display mode. 1st parameter: Frame frequency value set in TEMP range 0(35C) to TA 2nd parameter: Frame frequency value set in TEMP range TA to TB 3rd parameter: Frame frequency value set in TEMP range TB to TC 4th parameter: Frame frequency value set in TEMP range TC to 127(92C) NOTE: For the relationship between FA[4:0] ~ FD[4:0] and frame frequency, see Table 6.1.4 For more detail about frequency adjustment method, see section 5.11.9.3 Frame Frequency Adjustment.
Description
Restriction
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value FA [4:0] FB [4:0] FC [4:0] FD [4:0] 03h (46Hz) 07h (66Hz) 07h (66Hz) 07h (66Hz) 03h (46Hz) 07h (66Hz) 07h (66Hz) 07h (66Hz) 03h (46Hz) 07h (66Hz) 07h (66Hz) 07h (66Hz)
Status
Default
FRMSEL
Legend Command
Flow Chart
1 parameter: FA [4:0] 2nd parameter: FB [4:0] 3rd parameter: FC [4:0] 4th parameter: FD [4:0]
st
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6.1.39 FRM8SEL: Frame frequency in idle mode (8-color mode) (B5h)

ISS 0 0 0 0 0 Inst / Para FRM8SEL 1 parameter 2nd parameter 3rd parameter 4th parameter
st
D/!C 0 1 1 1 1
!WR
!RD 1 1 1 1 1
D7 1 -
D6 0 -
D5 1 -
D4 1
F8A4 F8B4
D3 0
F8A3 F8B3
D2 1
F8A2 F8B2
D1 0
F8A1 F8B1
D0 1
F8A0 F8B0
(Code) (B5h) -
F8C4 F8C3 F8C2 F8C1 F8C0 F8D4 F8D3 F8D2 F8D1 F8D0
Select frame frequency in idle display mode (8-color mode). 1st parameter: Frame frequency value set in TEMP range 0(35C) to TA 2nd parameter: Frame frequency value set in TEMP range TA to TB 3rd parameter: Frame frequency value set in TEMP range TB to TC 4th parameter: Frame frequency value set in TEMP range TC to 127(92C) NOTE: For the relationship between F8A[4:0] ~ F8D[4:0] and frame frequency, see Table 6.1.4 For more detail about frequency adjustment method, see section 5.11.9.3 Frame Frequency Adjustment.
Description
Restriction
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value F8A[4:0] F8B[4:0] F8C[4:0] F8D[4:0] 03h (46Hz) 07h (66Hz) 07h (66Hz) 07h (66Hz) 03h (46Hz) 07h (66Hz) 07h (66Hz) 07h (66Hz) 03h (46Hz) 07h (66Hz) 07h (66Hz) 07h (66Hz)
Status
Default
FRM8SEL
Legend Command
Flow Chart
1 parameter: F8A [4:0] 2nd parameter: F8B [4:0] 3rd parameter: F8C [4:0] 4th parameter: F8D [4:0]
st
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Table 6.1.4
Frame frequency value according to the parameter of FRMSEL (FRM8SEL) command
FA[4:0] to FD[4:0] F8A[4:0] to F8D[4:0] 0 (00h)
fFR (frame frequency)
FA[4:0] to FD[4:0] F8A[4:0] to F8D[4:0]
fFR (frame frequency)
30.1 Hz 109.8 Hz 16 (10h) 35.2 Hz 115.4 Hz 1 (01h) 17 (11h) 40.0 Hz 120.3 Hz 2 (02h) 18 (12h) 46.1 Hz 125.5 Hz 3 (03h) 19 (13h) 50.0 Hz 131.3 Hz 4 (04h) 20 (14h) 54.9 Hz 134.8 Hz 5 (05h) 21 (15h) 60.1 Hz 140.9 Hz 6 (06h) 22 (16h) 65.7 Hz 143.8 Hz 7 (07h) 23 (17h) 70.4 Hz 151.4 Hz 8 (08h) 24 (18h) 75.7 Hz 155.9 Hz 9 (09h) 25 (19h) 79.9 Hz 159.8 Hz 10 (0Ah) 26 (1Ah) 83.9 Hz 164.9 Hz 11 (0Bh) 27 (1Bh) 88.9 Hz 167.8 Hz 12 (0Ch) 28 (1Ch) 95.1 Hz 173.5 Hz 13 (0Dh) 29 (1Dh) 100.0 Hz 177.8 Hz 14 (0Eh) 30 (1Eh) 105.6 Hz 184.5 Hz 15 (0Fh) 31 (1Fh) During duty selected partial mode, frame frequency will be changed according to the predetermined dividing ratio. (Refer Section 5.11.10)
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6.1.40 TMPRNG: Temperature Range Set for Frame Frequency Adjustment (B6h)
ISS 0 0 0 0 Inst / Para TMPRNG 1 parameter 2nd parameter 3rd parameter
st
D/!C 0 1 1 1
!WR
!RD 1 1 1 1
D7 1 -
D6 0
TA6 TB6 TC6
D5 1
TA5 TB5 TC5
D4 1
TA4 TB4 TC4
D3 0
TA3 TB3 TC3
D2 1
TA2 TB2 TC2
D1 1
TA1 TB1 TC1
D0 0
TA0 TB0 TC0
(Code) (B6h) -
Temperature range set for automatic frame frequency adjustment operation according the current temperature value.
Description
1st parameter: Temperature range A value set 2nd parameter: Temperature range B value set 3rd parameter: Temperature range C value set NOTE: For the relationship between TA[6:0] to TC[6:0] and frame frequency, see section 5.11.9.3 Frame Frequency Adjustment.
Restriction
Status
Default
TA [6:0] 2Dh 2Dh 2Dh
Default Value TB [6:0] 7Fh 7Fh 7Fh
TC [6:0] 7Fh 7Fh 7Fh
TMPRNG
Legend Command
1 parameter: TA [6:0] 2nd parameter: TB [6:0] 3rd parameter: TC [6:0] Flow Chart
st
TMPHYS
1 parameter: TH [6:0]
st
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6.1.41 TMPHYS: Temperature Hysteresis Set for Frame Frequency Adjustment (B7h)
ISS 0 0 Inst / Para TMPHYS Parameter D/!C 0 1 !WR !RD 1 1 D7 1 D6 0
-
D5 1
-
D4 1
-
D3 0
TH3
D2 1
TH2
D1 1
TH1
D0 1
TH0
(Code) (B7h) -
Temperature hysteresis range set for frame frequency adjustment. Parameter: Temperature hystetesis range set. The relationship between temperature state and temperature range value is shown below.
Description
TEMP Range Value Frequency changing point A Frequency changing point B Frequency changing point C Temperature Rising State TA [6:0] + TH [3:0] TB [6:0] + TH [3:0] TC [6:0] + TH [3:0] Temperature Falling State TA [6:0] TB [6:0] TC [6:0]
NOTE: For the relationship between Frequency changing point and frame frequency, see section 5.11.9.3 Frame Frequency Adjustment. Restriction Temperature hysteresis value should be smaller than the gap of temperature range.
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value 05h 05h 05h
Default
TMPRNG
Legend Command
1st parameter: TA [6:0] 2nd parameter: TB [6:0] 3rd parameter: TC [6:0] Flow Chart
TMPHYS
1 parameter: TH [3:0]
st
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6.1.42 TMPREAD: Temperature Read-back (B8h)

ISS 0 0 0 Inst / Para TMPREAD Dummy read 2nd parameter D/!C 0 1 1 !WR 1 1 !RD 1 D7 1 TBF D6 0 TD6 D5 1 TD5 D4 1 TD4 D3 1 TD3 D2 0 TD2 D1 0 TD1 D0 0 TD0 (Code) (B8h) -
Temperature read-back from the built-in temperature device.

Description The 1st parameter is dummy data The 2nd parameter (TBF and TD6 to TD0): Temperature read busy and temperature value. NOTE: For the relationship between TD [6:0] and temperature, see section 5.11.9 Temperature Compensation.
Restriction
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value -
Default
Legend
Command Parameter
TMPREAD
TMPREAD Host Display
Flow Chart
Send 2 Parameter
nd
Dummy Read
Send 2 Parameter
nd
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6.1.43 DISCTR: Display Control (BAh)

Display timing related signal setup.
ISS 0 0 0 Inst / Para DISCTR 1st parameter 2nd parameter D/!C 0 1 1 !WR !RD 1 1 1 D7 1 D6 0 D5 1 D4 1 FINV D3 1 NL3 D2 0 FS2 NL2 D1 1 FS1 NL1 D0 0 FS0 NL0 (Code) (BAh) -
Display timing related signal set.

The 1st parameter is FI switching period FS [2:0] FI switching period 0 1 block (4-line) 1 2 block (8-line) 2 4 block (16-line) 3 6 block (24-line) 4 8 block (32-line) 5 10 block (40-line) 6 16 block (64-line) 7 Field nd The 2 parameter (FINV, NL[3:0]) : Description
FINV: Super-frame inversion set, NL [3:0]: N-block inversion FINV NL [3:0] Inversely highlighted lines 1 0 Super-frame inversion 1 1 Super-frame inversion + 2 block (8-line) 1 2 Super-frame inversion + 3 block (12-line) 1 3 Super-frame inversion + 4 block (16-line) : : : 1 15 Super-frame inversion + 16 block (64-line) 0 0 1 block (4-line) 0 1 2 block (8-line) 0 2 3 block (12-line) 0 3 4 block (16-line) : : : 0 15 16 block (64-line)
Restriction
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LDS176
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Status
Default
FS [2:0] 7h 7h 7h
Default Value FINV 1 1 1
NL [3:0] 5h 5h 5h
DISCTR
Legend Command
1 parameter: FS [2:0] 2nd parameter: FINV, NL [3:0] Flow Chart
st
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LDS176
Version 0.10
6.1.44 EPVOL: Electrical Volume set for EEPROM (BBh)

ISS 0 0 0 0 Inst / Para EPVOL 1 parameter 2nd parameter 3rd parameter
st
D/!C 0 1 1 1
!WR
!RD 1 1 1 1
D7 1 -
D6 0 -
D5 1
-
D4 1
-
D3 1
-
D2 0
-
D1 1
-
D0 1
-
(Code) (BBh) Dummy -
Specify the voltage regulator circuits electronic volume offset value (which will be stored in EEPROM).
The 1st parameter: Electrical Volume (EV) offset value.
EOF [5] 0 0 : 0 1 1 : 1 EOF [4:0] 00h 01h : 1Fh 00h 01h : 1Fh Resultant Electrical Volume Value (EV_IN) EV_IN = EV + EOF[4:0] = EV + 0 EV_IN = EV + EOF[4:0] = EV + 1 : EV_IN = EV + EOF[4:0] = EV + 31 EV_IN = EV + EOF[4:0] = EV - 0 EV_IN = EV + EOF[4:0] = EV - 1 : EV_IN = EV + EOF[4:0] = EV - 31
Description
The 2nd parameter: Dummy byte. The 3rd parameter: Resistance ratio (RR) offset value.
ROF [2] 0 0 0 0 1 1 1 1 ROF [1:0] 0h 1h 2h 3h 0h 1h 2h 3h Resultant Resistance Ratio Value (RR_IN) RR_IN = RR + ROF[1:0] = RR + 0 RR_IN = RR + ROF[1:0] = RR + 1 RR_IN = RR + ROF[1:0] = RR + 2 RR_IN = RR + ROF[1:0] = RR + 3 RR_IN = RR + ROF[1:0] = RR - 0 RR_IN = RR + ROF[1:0] = RR - 1 RR_IN = RR + ROF[1:0] = RR - 2 RR_IN = RR + ROF[1:0] = RR - 3 Default (RR=4) 4 5 6 7 4 3 2 1
NOTE: If EV_IN < 0, EV_IN becomes 0, and if EV_IN 127, EV_IN value becomes 127. If RR_IN < 0, RR_IN becomes 0, and if RR_IN 7, RR_IN value becomes 7. Restriction
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value -
Default
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EEPVOL
Legend Command
1 parameter: EOF [5:0] Flow Chart 2 parameter: Dummy

nd
st
Parameter Display Action Mode
3 parameter: ROF [2:0]
rd
Sequential transfer
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6.1.45 EPWROUT: EEPROM Write Out (D0h)

ISS 0 0 Inst / Para EPWROUT Parameter D/!C !WR !RD 1 0 No Parameter D7 1 D6 1 D5 0 D4 1 D3 0 D2 0 D1 0 D0 0 (Code) (D0h)
Description EEPROM write mode disable. Restriction It will be necessary to wait more than 100msec after EEPROM write mode start (EPWRIN).
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability No No No No Yes Default Value EEPROM write out EEPROM write out EEPROM write out
Default
EEPVOL
Legend Command
1st parameter: EOF [5:0] 2nd parameter: Dummy 3rd parameter: ROF [2:0]
EEPROM Register Set
WRID2
Flow Chart 1st parameter: ID2 [6:0]
Sequential transfer
EPWRIN
EEPROM Data write Enable EEPROM Data write Disable
EPWROUT
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6.1.46 EPWRIN: EEPROM Write In (D1h)

ISS 0 0 Inst / Para EPWRIN Parameter D/!C !WR !RD 1 0 No Parameter D7 1 D6 1 D5 0 D4 1 D3 0 D2 0 D1 0 D0 1 (Code) (D1h)
EEPROM write mode start. Before EPWRIN command, EOF [5:0] and ROF [2:0] parameter of EEPVOL command and ID2 [6:0] of WRID2 command need to be pre-set. And it will be necessary to wait more than 1.5sec before exiting EEPROM write mode (EPWROUT).
Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability No No No No Yes Default Value EEPROM write out EEPROM write out EEPROM write out
Default
EEPVOL
Legend Command
1st parameter: EOF [5:0] 2nd parameter: Dummy 3rd parameter: ROF [2:0]
EEPROM Register Set
WRID2
Sequential transfer
Flow Chart
1st parameter: ID2 [6:0]
EPWRIN
EEPROM Data write Enable EEPROM Data write Disable
EPWROUT
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6.1.47 RDEV: Read Electrical Volume Value (3Fh)

ISS 0 0 0 Inst / Para RDEV Dummy read 2nd parameter D/!C 0 1 1 !WR 1 1 !RD 1 D7 1 D6 1 EV6 D5 0 EV5 D4 1 EV4 D3 0 EV3 D2 1 EV2 D1 0 EV1 D0 0 EV0 (Code) (D4h) -
This read byte returns 7-bit Electrical Volume Value. Description Restriction The 1st parameter is dummy data The 2nd parameter (EV6 to EV0): Internal Electrical Volume Value. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value 3Fh 3Fh 3Fh
Default

RDEV (D4h)

RDEV (D4h)
Legend
Command Parameter
Host Driver
Display Action Mode
Flow Chart
Send 2 parameter
nd
Dummy Read
Send 2 parameter
nd
Sequential transfer
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6.1.48 RDRR: Read Resistor Ratio Value (D5h)

ISS 0 0 0 Inst / Para RDRR Dummy read 2nd parameter D/!C 0 1 1 !WR 1 1 !RD 1 D7 1 D6 1 D5 0 D4 1 D3 0 D2 1 RR2 D1 0 RR1 D0 1 RR0 (Code) (D5h) -
This read byte returns 3-bit Resistor Ratio Value. Description Restriction The 1st parameter is dummy data The 2nd parameter (RR2 to RR0): Internal Resistor Ratio Value. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value 04h 04h 04h
Default

RDRR (D5h)

RDRR (D5h)
Legend
Command Parameter
Host Driver
Display Action Mode
Flow Chart
Send 2 parameter
nd
Dummy Read
Send 2 parameter
nd
Sequential transfer
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6.1.49
ISS 0
TEST1: Test Command1 (E-h)

Inst / Para TEST1 D/!C 0 !WR !RD 1 D7 1 D6 1 D5 1 D4 0 D3 D2 D1 D0 (Code) (E-h)
This instruction is a testing instruction code for Leadis. Please do not use it.
6.1.50 TEST2: Test Command2 (F-h)

ISS 0 Inst / Para TEST2 D/!C 0 !WR !RD 1 D7 1 D6 1 D5 1 D4 1 D3 D2 D1 D0 (Code) (F-h)
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6.2 INSTRUCTION CODE 1 (ISS=1)

6.2.1 Instruction Code Table
Instruction Code1 (ISS=1) Table 6.2.1
-: Dont care
Instruction
NOP OSCON OSCOFF BSTRON BSTROFF SLPIN SLPOUT PTLOUT PTLIN

6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 6.2.9 6.2.10 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1 1 0 1 1 0 1 0 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
D7
0 1 1 0 0 1 1 1 1
D6
0 1 1 0 0 0 0 0 0
D5
1 0 0 1 1 0 0 1 1
D4
0 1 1 0 0 1 1 0 0
D3
0 0 0 0 0 0 0 1 1
D2
1 0 0 0 0 1 1 0 0
D1
0 0 1 0 0 0 0 0 0
D0
1 1 0 0 1 1 0 1 0
(Code) Function
(25h) (D1h) (D2h) (20h) (21h) (95h) (94h) (A9h) (A8h) (A6h) (A7h) (AEh) (AFh) (15h) (75h) (5Ch) (5Dh) (CEh) : : : (AAh) (ABh) No operation Oscillator on Oscillator off All power on All power off Sleep in Sleep out Partial display off Partial area set & on Partial start line address Partial end line address Display inversion off (normal) Display inversion on Display off Display on Column address set X_ADR start: 0 XS 83h X_ADR end: XS XE 83h Row address set Y_ADR start: 0 YS 83h Y_ADR end: YS YE 83h Memory write Write data Memory Read Dummy read Read data Color set for 256 color display Red tone (000) : Red tone (111) Green tone (000) : Green tone (111) Blue tone (00) : Blue tone (11) Scroll area set Scroll start line Scroll end line Scroll specified line Area scroll mode Scroll start address set Start scroll line address of RAM
PSL7 PSL6 PSL5 PSL4 PSL3 PSL2 PSL1 PSL0 PEL7 PEL6 PEL5 PEL4 PEL3 PEL2 PEL1 PEL0 1 1 1 1 0 XS7 XE7 0 YS7 YE7 0 D7 0 D7 1 : : : 1 0 0 0 0 0 XS6 XE6 1 YS6 YE6 1 D6 1 D6 1 : : : 0 1 1 1 1 0 XS5 XE5 1 YS5 YE5 0 D5 0 D5 0 : : : 1 0 0 0 0 1 XS4 XE4 1 YS4 YE4 1 D4 1 D4 0 : : : 0 0 0 1 1 0 XS3 XE3 0 YS3 YE3 1 D3 1 D3 1 R3 : R3 G3 : G3 B3 : B3 1 1 1 1 1 1 XS2 XE2 1 YS2 YE2 1 D2 1 D2 1 R2 : R2 G2 : G2 B2 : B2 0 1 1 1 1 0 XS1 XE1 0 YS1 YE1 0 D1 0 D1 1 R1 : R1 G1 : G1 B1 : B1 1 0 1 0 1 1 XS0 XE0 1 YS0 YE0 0 D0 1 D0 0 R0 : R0 G0 : G0 B0 : B0 0
DISNOR DISINV DISPOFF DISPON CASET
6.2.11 6.2.12 6.2.13 6.2.14 6.2.15
1 1 1 1 1 1 1
RASET
6.2.16
1 1 1
RAMWR RAMRD
6.2.17 6.2.18
1 1 1 1 1
RGBSET
6.2.19
1 1 1 1 1 1 1 1 1 1
ASCSET
6.2.20
1 1 1 1 1
SSL7 SSL6 SSL5 SSL4 SSL3 SSL2 SSL1 SSL0 SEL7 SEL6 SEL5 SEL4 SEL3 SEL2 SEL1 SEL0 SFL7 SFL6 SFL5 SFL4 SFL3 SFL2 SFL1 1 0 1 0 1 0 1 SF0 1 SMD1 SMD0
VSCSAD
6.2.21
1 1
SSA7 SSA6 SSA5 SSA4 SSA3 SSA2 SSA1 SSA0
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Table 6.2.2
Instruction Code1 (ISS=1, Continued)
-: Dont care
Instruction
DATCTR

6.2.22 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 0 1 0 1 1 0 1 1 1 0 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
D7
1 1 1 1 1 1 1 1 1 1 1 1 BF 1 1 1 0 0 -
D6
0 1 1 0 EV6 1 1 0 0 0 0 TA6 TB6 TC6 0 0 T6 1 1 1 1 EV6 1 -
D5
1 1 1 0 EV5 0 0 1 1 1 1 TA5 TB5 TC5 1 1 T5 0 0 0 1 EV5 1 -
D4
1 0 0 0 EV4 1 1 1 FINV 1 FA4 FB4 FC4 FD4 1
D3
1 0 1 0 EV3 0 0 1 NL3 0 FA3 FB3 FC3 FD3 0
D2
1 MV GS2 0 1 0 EV2 RR2 1 1 0 FS2 NL2 1 FA2 FB2 FC2 FD2 1
D1
0 MX GS1 0 1 0 EV1 RR1 1 1 1 FS1 NL1 0 FA1 FB1 FC1 FD1 0
D0
0 MY RGB GS0 0 0 1 EV0 RR0 0 1 0 FS0 NL0 0 FA0 FB0 FC0 FD0 1
(Code) Function
(BCh) (E0h) (EEh) (81h) (D6h) (D7h) (BAh) (B4h) (B5h) (B6h) (B7h) (B8h) (C0h) (CDh) (CCh) (7Ch) (7Dh) Data control Row/column address control RGB Gray-scale setup Read & modify write on Read & modify write off Electronic volume control VXH2 volume value
RMWIN RMWOUT VOLCTR
6.2.23 6.2.24 6.2.25
1 1 1 1 1
Resistance ratio set

EV increment EV decrement Display control F1/F2 pattern FR inversion-set value Frame frequency select Frame frequency in Temp range A Frame frequency in Temp range B Frame frequency in Temp range C Frame frequency in Temp range D Frame frequency select (8-color) Frame frequency in Temp range A Frame frequency in Temp range B Frame frequency in Temp range C Frame frequency in Temp range D Temp range set Temp range A Temp range B Temp range C Temp hysteresis range set Hysteresis value set Temperature read back Dummy read Read parameter Electronic volume offset EV offset Dummy byte RR offset EEPROM write start EEPROM write end Read internal contrast (EV_IN) Dummy read Read parameter Read internal resistor ratio (RR_IN) Dummy read Read parameter
VOLUP VOLDOWN DISCTR
6.2.26 6.2.27 6.2.28
1 1 1 1 1
FRMSEL
6.2.29
1 1 1 1 1
FRM8SEL
6.2.30
1 1 1 1 1
F8A4 F8A3 F8A2 F8A1 F8A0 F8B4 F8B3 F8B2 F8B1 F8B0 F8C4 F8C3 F8C2 F8C1 F8C0 F8D4 F8D3 F8D2 F8D1 F8D0 1 TA4 TB4 TC4 1 1 T4 0 0 0 1 EV4 1 0 TA3 TB3 TC3 0 TH3 1 T3 0 1 1 1 EV3 1 1 TA2 TB2 TC2 1 TH2 0 T2 0 1 1 1 EV2 1 RR2 1 TA1 TB1 TC1 1 TH1 0 T1 0 0 0 0 EV1 0 RR1 0 TA0 TB0 TC0 1 TH0 0 T0 0 1 0 0 EV0 1 RR0
TMPRNG
6.2.31
1 1 1 1
TMPHIS TMPREAD
6.2.32 6.2.33
1 1 1 1 1
EPVOL
6.2.34
1 1 1 1
EPWRIN EPWROUT RDEV
6.2.35 6.2.36 6.2.37
1 1 1 1 1
RDRR
6.2.38
1 1 1
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Table 6.2.3
Instruction Code1 (ISS=1, Continued)
-: Dont care
Instruction
RDID1

6.2.39 1 1 1 0 1 1 0 1 1 0 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
D7
0 ID17 0 ID27 0 ID37 0 0 0 0 0 0
D6
0 ID16 0 ID26 0 ID36 0 0 0 0 1 0
D5
1 ID15 1 ID25 1 ID35 1 1 1 1 1 0
D4
0 ID14 0 ID24 0 ID34 1 1 1 1 0 0
D3
1 ID13 1 ID23 1 ID33 1 1 0 0 -
D2
0 ID12 0 ID22 1 ID32 0 0 1 1 -
D1
1 ID11 1 ID21 0 ID31 0 0 0 0 -
D0
0 ID10 1 ID20 0 ID30 0 1 0 1 -
(Code) Function Default

(DAh) (DBh) (DCh) (38h) (39h) (34h) (35h) (6-h) (0-h) Read ID1 Dummy read Read parameter Read ID2 Dummy read Read parameter Read ID2 Dummy read Read parameter Idle mode off Idle mode on Tearing effect line off Tearing effect line on Test command1 Test command2
RDID2
6.2.40
1 1 1
RDID3
6.2.41
1 1 1
IDMOFF IDMON TEOFF TEON TEST1 TEST2
6.2.42 6.2.43 6.2.44 6.2.45 6.2.46 6.2.47
1 1 1 1 1 1
NOTE: 1) After the H/W reset by !RES pin or S/W reset by SWRESET command, each internal register becomes default state (Refer RESET TABLE section) 2) Undefined commands are treated as NOP (00 h) command.
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6.2.2
ISS 1 1
NOP (25h)
Inst / Para NOP Parameter D/!C !WR !RD 0 1 No Parameter D7 0 D6 0 D5 1 D4 0 D3 0 D2 1 D1 0 D0 1 (Code) (25h)
No operation. This command can be used to interrupt an on-going instruction.
6.2.3
ISS 1 1
OSCON: Oscillator On (D1h)

Inst / Para OSCON Parameter D/!C !WR !RD 0 1 No Parameter D7 1 D6 1 D5 0 D4 1 D3 0 D2 0 D1 0 D0 1 (Code) (D1h)
Turn on the internal oscillator circuit.
6.2.4
ISS 1 1
OSCOFF: Oscillator Off (D2h)

Inst / Para OSCOFF Parameter D/!C !WR !RD 0 1 No Parameter D7 1 D6 1 D5 0 D4 1 D3 0 D2 0 D1 1 D0 0 (Code) (D2h)
Turn off the internal oscillator circuit.
6.2.5
ISS 1 1
BSTRON: Power All On (20h)

Inst / Para BSTRON Parameter D/!C !WR !RD 0 1 No Parameter D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 0 (Code) (20h)
Turn on all the internal power circuit.
6.2.6
ISS 1 1
BSTROFF: Power All Off (21h)

Inst / Para BSTROFF Parameter D/!C !WR !RD 0 1 No Parameter D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 1 (Code) (21h)
Turn on all the internal power circuit.
6.2.7
SLPIN: Sleep In (95h)
Enter power down mode, sleep mode. In the sleep mode output voltages of all LCD driver pins are ground, the DC-DC converters and oscillator are switched off. Before using sleep in command, it is necessary to turn off the display by entering the display off command.
ISS 1 1 Inst / Para SLPIN Parameter D/!C !WR !RD 0 1 No Parameter D7 1 D6 0 D5 0 D4 1 D3 0 D2 1 D1 0 D0 1 (Code) (95h)
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6.2.8
SLPOUT: Sleep Out (94h)
Switching off sleep IN mode. When leaving the sleep IN mode, it might be necessary to wait for a certain time before the power circuits become stable.
ISS 1 1 Inst / Para SLPOUT Parameter D/!C !WR !RD 0 1 No Parameter D7 1 D6 0 D5 0 D4 1 D3 0 D2 1 D1 0 D0 0 (Code) (94h)
6.2.9
ISS 1 1
PTLOUT: Partial Display Mode Off (A9h)

Inst / Para PTLOUT Parameter D/!C !WR !RD 0 1 No Parameter D7 1 D6 0 D5 1 D4 0 D3 1 D2 0 D1 0 D0 1 (Code) (A9h)
Exit partial display mode.
6.2.10 PTLIN: Partial Area Set & Partial Display Mode On (A8h)
The partial area command sets the partial display area and display the RAM content of these area. In partial display mode the driving voltage and frame frequency are same as the normal display mode but the current consumption is reduced.
ISS 1 1 1 Inst / Para PTLIN 1st parameter 2nd parameter D/!C 0 1 1 !WR !RD 1 1 1 D7 1 D6 0 D5 1 D4 0 D3 1 D2 0 D1 0 D0 0 (Code) (A8h) -
PSL7 PSL6 PSL5 PSL4 PSL3 PSL2 PSL1 PSL0 PEL7 PEL6 PEL5 PEL4 PEL3 PEL2 PEL1 PEL0
The following steps must be performed to enter partial mode: - Set partial start line address PSL [7:0] - Set partial end line address PEL [7:0] When Setting the addresses the following conditions must be ensured: 0 PSL 131, 0 PEL 131 During partial display mode, display window are divided as displaying area and non-displaying area, and in the non-displaying area COM outputs become VC and SEG outputs become VXH1 or VXL1 according to the internal alternating signal.
Fame Memory Row0 Display Panel Non-Displaying Area Displaying Area PEL [7:0] Non-Displaying Area PSL [7:0] Row131 Case1: PSL < PEL Line131 Displaying Area Case2: PSL > PEL Line131 Line0 Displaying Area PSL [7:0] Non-Displaying Area Display Panel Line0 PEL [7:0]
Fig. 6.2.1
Partial display mode
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6.2.11 DISNOR: Normal Display Mode (Inversion Off) (A6h)

Turns the display into a normal screen without modifying the display data RAM.
ISS 1 1 Inst / Para INVOFF Parameter D/!C !WR !RD 0 1 No Parameter D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 1 D0 0 (Code) (A6h)
6.2.12 DISINV: Display Inversion On (A7h)

Turns the display into a inverted screen without modifying the display data RAM.
ISS 1 1 Inst / Para INVON Parameter D/!C !WR !RD 0 1 No Parameter D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 1 D0 1 (Code) (A7h)
6.2.13 DISPOFF: Display Off (AEh)

Turn off the display as of the blank screen with no regard to the display data RAM.
ISS 1 1 Inst / Para DISPOFF Parameter D/!C !WR !RD 0 1 No Parameter D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 1 D0 0 (Code) (AEh)
6.2.14 DISPON: Display On (AFh)

Turn on the display screen according to the current display data RAM content and the display timing and setting.
ISS 1 1 Inst / Para DISPON Parameter D/!C !WR !RD 0 1 No Parameter D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 1 D0 1 (Code) (AFh)
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6.2.15 CASET: Column Address Set (15h)

The display data RAM parameters XS and XE define the column address range of the display data RAM, for writing data. The XS and XE are defined between 0 and 131 (83hex) and XS must be smaller then XE.
ISS 1 1 1 Inst / Para CASET 1 parameter 2nd parameter
st
D/!C 0 1 1
!WR
!RD 1 1 1
D7 0 XS7 XE7
D6 0 XS6 XE6
D5 0 XS5 XE5
D4 1 XS4 XE4
D3 0 XS3 XE3
D2 1 XS2 XE2
D1 0 XS1 XE1
D0 1 XS0 XE0
(Code) (15h) 00h 81h
6.2.16 RASET: Row Address Set (75h)

The display data RAM parameters YS and YE define the row address range of the display data RAM, for writing data. The YS and YE are defined between 0 and 131 (83hex) and YS must be smaller then YE.
ISS 1 1 1 Inst / Para RASET 1st parameter 2nd parameter D/!C 0 1 1 !WR !RD 1 1 1 D7 0 YS7 YE7 D6 1 YS6 YE6 D5 1 YS5 YE5 D4 1 YS4 YE4 D3 0 YS3 YE3 D2 1 YS2 YE2 D1 0 YS1 YE1 D0 1 YS0 YE0 (Code) (75h) 02h 83h
6.2.17 RAMWR: Memory Write (5Ch)

Data written to the display memory (RAM) is validated by this command. Entering this command always returns the row address and column address to the start address. Contents of the display data RAM is written by the data entered following this command and at the same time the row address or column address is incremented. The data write mode turned on by this command can be automatically cancelled by entering another command.
ISS 1 1 : 1 Inst / Para RAMWR Data write : Data write D/!C 0 1 : 1 !WR : !RD 1 1 : 1 D7 0 D7 : D7 D6 1 D6 : D6 D5 0 D5 : D5 D4 1 D4 : D4 D3 1 D3 : D3 D2 1 D2 : D2 D1 0 D1 : D1 D0 0 D0 : D0 (Code) (5Ch) : -
6.2.18 RAMRD: Memory Read (5Dh)

Data read from the display memory (RAM) is validated by this command. Entering this command always returns the row address and column address to the start address. Contents of the display data RAM is read via the D7 to D0 pad following this command and at the same time the row address or column address is incremented. The data read mode turned on by this command can be automatically cancelled by entering another command.
ISS 1 1 1 : 1 Inst / Para RAMRD Dummy read Data read : Data read D/!C 0 1 1 : 1 !WR 1 1 : 1 !RD 1 : D7 0 D7 : D7 D6 1 D6 : D6 D5 0 D5 : D5 D4 1 D4 : D4 D3 1 D3 : D3 D2 1 D2 : D2 D1 0 D1 : D1 D0 1 D0 : D0 (Code) (5Dh) : -
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6.2.19 RGBSET: Colour Set for 256-Color Display (CEh)

With this command a mapping from 256 color or 4k-color to the 65k-color RAM of the LDS176 is done.
ISS 1 1 1 1 1 1 1 1 1 1 D/!C !WR 0 st 1 parameter 1 : 1 8th parameter 1 th 9 parameter 1 : 1 th 16 parameter 1 17th parameter 1 : 1 20th parameter 1 Inst / Para RGBSET !RD 1 1 1 1 1 1 1 1 1 1 D7 1 D6 1 D5 0 D4 0 D3 1 R03 Rn3 R73 G03 Gn3 G73 B03 Bn3 B33 D2 1 R02 Rn2 R72 G02 Gn2 G72 B02 Bn2 B32 D1 1 R01 Rn1 R71 G01 Gn1 G71 B01 Bn1 B31 D0 0 R00 Rn0 R70 G00 Gn0 G70 B00 Bn0 B30 (Code) (CEh) 00h 00h 00h 00h 00h 00h 00h 00h 00h
This command is used to define the LUT for 8bit-to-12bit color depth conversations. (See Also Table 5.2.3) 20 Bytes must be written to the LUT regardless of the color mode. Only the values in Section 5.2.6 are referred. This command has no effect on other commands/parameters and Contents of frame memory. Visible change takes effect next time the Frame Memory is written to.
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6.2.20 ASCSET: Scroll Area Set (AAh)

The scroll area command sets the scroll display area and display the RAM content of these area. By using VSCSAD (Vertical Scroll Start Address) command, the display data within scroll area can be scrolled up and down.
ISS 1 1 1 1 1 Inst / Para ASCSET 1 parameter 2nd parameter 3rd parameter 4th parameter
st
D/!C 0 1 1 1 1
!WR
!RD 1 1 1 1 1
D7 1
D6 0
D5 1
D4 0
D3 1
D2 0
D1 1
D0 0
(Code) (AAh) -
SSL7 SSL6 SSL5 SSL4 SSL3 SSL2 SSL1 SSL0 SEL7 SEL6 SEL5 SEL4 SEL3 SEL2 SEL1 SEL0 SFL7 SFL6 SFL5 SFL4 SFL3 SFL2 SFL1 SFL0 SMD1 SMD0 -
In table below the used parameters are explained with their reset states (see also Fig. 6.2.2). Parameter SSL [7:0] SEL [7:0] SFL [7:0] SMD [1:0] Description Top scroll line address Bottom scroll line address Number of scroll specified line Scroll mode Reset state 00h 00h 00h 3 Scroll area set register change SSL [7:0] SEL [7:0] SFL [7:0] No change No change No change No change No change 00h No change 83h SEL [7:0] 00h 83h SEL [7:0]
SMD [1:0]: Scroll mode set parameter (see also Fig. 6.2.3). SMD1 0 0 1 1 SMD0 0 1 0 1 Scroll Mode Center screen scroll mode Top screen scroll mode Bottom screen scroll mode Whole screen scroll mode
6.2.21 VSCSAD: Vertical Scroll Start Address of RAM (ABh)

Scroll start address set.
1 Parameter 1 SSA7 SSA6 SSA5 SSA4 SSA3 SSA2 SSA1 SSA0 1 NOTE: Scroll start address should be in scroll area (should not be in top or bottom fixed area). ISS 1 Inst / Para VSCSAD D/!C 0 !WR !RD 1 D7 1 D6 0 D5 1 D4 0 D3 1 D2 0 D1 1 D0 1 (Code) (ABh) -
The following steps must be performed to enter scroll mode: Define the scroll area - Set scroll start block: SSL [7:0] - Set scroll end block: SEL [7:0] - Set scroll specified block: SFL [7:0] - Set scroll mode: SMD [1:0] Vertical scroll start address set: SSA [7:0]
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Display Data RAM Row0 SSL [7:0] SSA = SSL SSA
Display Data RAM
Display Panel Top Fixed Area
Scroll Area
SFL [7:0] Bottom Fixed Area SEL [7:0] Row131
Fig. 6.2.2
Vertical scroll & display window partition
Center screen scroll Top Fixed Area
Top screen scroll
Bottom screen scroll Top Fixed Area
Whole screen scroll
Scroll Area Scroll Area Scroll Area Scroll Area
Bottom Fixed Area SMD [1:0] = (00)b
Bottom Fixed Area SMD [1:0] = (01)b SMD [1:0] = (10)b SMD [1:0] = (11)b
Fig. 6.2.3
Vertical scroll mode according to the SMD [1:0] value
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6.2.22 DATCTR: Data Access Control (BCh)

The display data RAM access conditions RAM can be defined using the following command.
ISS 1 1 1 1 Inst / Para DATCTR 1st parameter 2nd parameter 3rd parameter D/!C 0 1 1 1 !WR !RD 1 1 1 1 D7 1 D6 0 D5 1 D4 1 D3 1 D2 1 MV GS2 D1 0 MX GS1 D0 0 MY RGB GS0 (Code) (BCh) -
In table below the used single control bits are explained with their reset states. Parameter MY MX MV RGB 0 (Reset state) No mirror Y No mirror X RAM write in X direction RGB order 1 Mirror Y Mirror X RAM write in Y direction BGR order
GS [2:0]: Gray-scale number set parameter GS2 GS1 GS0 Description 0 0 1 256 Color 0 1 0 4k Color type A 1 0 0 4k Color type B 1 0 1 65k Color
6.2.23 RMWIN: Read Modify Write In (E0h)

Modify read mode on command. This instruction stops the automatic increment of the column address by the read display data operation, but the column address is still increased by the write display data instruction. And it reduces the load of microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others.
ISS 1 1 Inst / Para RMWIN Parameter D/!C !WR !RD 0 1 No Parameter D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 0 D0 0 (Code) (E0h)
6.2.24 RMWOUT: Read Modify Write Out (EEh)

Modify read mode off command. Modify read mode is disables and column row address returns to the initial value just before the RMWIN command.
ISS 1 1 Inst / Para RMWOUT Parameter D/!C !WR !RD 0 1 No Parameter D7 1 D6 1 D5 1 D4 0 D3 1 D2 1 D1 1 D0 0 (Code) (EEh)
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6.2.25 VOLCTR: Electrical Volume Control (81h)

Specify the voltage regulator circuits electronic volume value and resistance ratio of built-in voltage regulating resistor.
ISS 1 1 1 Inst / Para VOLCTR 1st parameter 2nd parameter D/!C 0 1 1 !WR !RD 1 1 1 D7 1 D6 0 EV6 D5 0 EV5 D4 0 EV4 D3 0 EV3 D2 0 EV2 RR2 D1 0 EV1 RR1 D0 1 EV0 RR0 (Code) (81h) -
EV [6:0]: Specify VXH2 electronic volume value. RR [2:0]: Specify resistance ratio of the internal resistor.
6.2.26 VOLUP: Electrical Volume Increment (D6h)

This command increases electronic volume value EV [6:0] by 1. If the value is set to 7F (hex), after this command, the value wrap to 0.
ISS 1 1 Inst / Para VOLUP Parameter D/!C !WR !RD 0 1 No Parameter D7 1 D6 1 D5 0 D4 1 D3 0 D2 1 D1 1 D0 0 (Code) (D6h)
6.2.27 VOLDOWN: Electrical Volume Decrement (D7h)

This command decreases electronic volume value EV [6:0] by 1. If the value is set to 0 (hex), after this command, the value wrap to 7F (hex).
ISS 1 1 Inst / Para VOLDOWN Parameter D/!C !WR !RD 0 1 No Parameter D7 1 D6 1 D5 0 D4 1 D3 0 D2 1 D1 1 D0 1 (Code) (D7h)
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6.2.28 DISCTR: Display Control (BAh)

Display timing related signal setup.
ISS 1 1 1 Inst / Para DISCTR 1st parameter 2nd parameter D/!C 0 1 1 !WR !RD 1 1 1 D7 1 D6 0 D5 1 D4 1 FINV D3 1 NL3 D2 0 FS2 NL2 D1 1 FS1 NL1 D0 0 FS0 NL0 (Code) (BAh) -
The 1st parameter is FI switching period FS [2:0] FI switching period 0 1 block (4-line) 1 2 block (8-line) 2 4 block (16-line) 3 6 block (24-line) 4 8 block (32-line) 5 10 block (40-line) 6 16 block (64-line) 7 Field The 2nd parameter (FINV, NL [3:0]): FINV: Super-frame inversion set, NL [3:0]: N-block inversion FINV NL [3:0] Inversely highlighted lines 1 0 Super-frame inversion 1 1 Super-frame inversion + 2 block (8-line) 1 2 Super-frame inversion + 3 block (12-line) 1 3 Super-frame inversion + 4 block (16-line) : : : 1 15 Super-frame inversion + 16 block (64-line) 0 0 1 block (4-line) 0 1 2 block (8-line) 0 2 3 block (12-line) 0 3 4 block (16-line) : : : 0 15 16 block (64-line)
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6.2.29 FRMSEL: Frame frequency in normal mode (B4h)

Select frame frequency in normal display mode. 1st parameter: Frame frequency value set in TEMP range 0(35C) to TA 2nd parameter: Frame frequency value set in TEMP range TA to TB 3rd parameter: Frame frequency value set in TEMP range TB to TC 4th parameter: Frame frequency value set in TEMP range TC to 127(92C)
FA4 FA3 FA2 FA1 FA0 1 1 1st parameter 1 nd FB4 FB3 FB2 FB1 FB0 1 1 2 parameter 1 FC4 FC3 FC2 FC1 FC0 1 1 3rd parameter 1 th FD4 FD3 FD2 FD1 FD0 1 1 4 parameter 1 NOTE: For the relationship between FA[5:0] ~ FD[5:0] and frame frequency, see Table 6.1.4 For more detail about frequency adjustment method, see section 5.11.9.3 Frame Frequency Adjustment. ISS 1 Inst / Para FRMSEL D/!C 0 !WR !RD 1 D7 1 D6 0 D5 1 D4 1 D3 0 D2 1 D1 0 D0 0 (Code) (B4h)
6.2.30 FRM8SEL: Frame frequency in idle mode (8-color mode) (B5h)

Select frame frequency in normal display mode. 1st parameter: Frame frequency value set in TEMP range 0(35C) to TA 2nd parameter: Frame frequency value set in TEMP range TA to TB 3rd parameter: Frame frequency value set in TEMP range TB to TC 4th parameter: Frame frequency value set in TEMP range TC to 127(92C)
F8A4 F8A3 F8A2 F8A1 F8A0 1 1 1st parameter 1 nd F8B4 F8B3 F8B2 F8B1 F8B0 1 1 2 parameter 1 F8C4 F8C3 F8C2 F8C1 F8C0 1 1 3rd parameter 1 th F8D4 F8D3 F8D2 F8D1 F8D0 1 1 4 parameter 1 NOTE: For the relationship between F8A[5:0] ~ F8D[5:0] and frame frequency, see Table 6.1.4 For more detail about frequency adjustment method, see section 5.11.9.3 Frame Frequency Adjustment. ISS 1 Inst / Para FRM8SEL D/!C 0 !WR !RD 1 D7 1 D6 0 D5 1 D4 1 D3 0 D2 1 D1 0 D0 1 (Code) (B5h)
6.2.31 TMPRNG: Temperature Range Set for Frame Frequency Adjustment (B6h)
Temperature range set for automatic frame frequency adjustment operation according the current temperature value. 1st parameter: Temperature range A value set 2nd parameter: Temperature range B value set 3rd parameter: Temperature range C value set
ISS 1 1 1 1 NOTE: Inst / Para TMPRNG D/!C 0 !WR !RD 1 D7 1 D6 0 D5 1
TA5 TB5 TC5
D4 1
TA4 TB4 TC4
D3 0
TA3 TB3 TC3
D2 1
TA2 TB2 TC2
D1 1
TA1 TB1 TC1
D0 0
TA0 TB0 TC0
(Code) (B6h) -
1st parameter 1 1 1 2nd parameter 1 rd 1 3 parameter 1 For the relationship between TA[6:0] Adjustment.
TA6 TB6 TC6 to TC[6:0]
and frame frequency, see section 5.11.9.3 Frame Frequency
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6.2.32 TMPHYS: Temperature Hysteresis Set for Frame Frequency Adjustment (B7h)
Temperature hysteresis range set for frame frequency adjustment. Parameter: Temperature hystetesis range set. Temperature hysteresis value should be smaller than the gap of temperature range.
ISS 1 1 Inst / Para TMPHYS Parameter D/!C 0 1 !WR !RD 1 1 D7 1 D6 0
-
D5 1
-
D4 1
-
D3 0
TH3
D2 1
TH2
D1 1
TH1
D0 1
TH0
(Code) (B7h) -
The relationship between temperature state and temperature range value is shown below.
TEMP Range Value Frequency changing point A Frequency changing point B Frequency changing point C Temperature Rising TA [6:0] + TH [3:0] TB [6:0] + TH [3:0] TC [6:0] + TH [3:0] Temperature Falling TA [6:0] TB [6:0] TC [6:0]
NOTE: For the relationship between Frequency changing point and frame frequency, see section 5.11.9.3 Frame
Frequency Adjustment.
6.2.33 TMPREAD: Temperature Read-back (B8h)

Temperature read-back from the built-in temperature sensing device. The 1st parameter is dummy data. The 2nd parameter (TBF and TD6 to TD0): Temperature read busy and temperature value.
1 Dummy read 1 1 nd TBF TD6 TD5 TD4 TD3 TD2 TD1 TD0 1 2 parameter 1 1 NOTE: For the relationship between TD [6:0] and temperature, see section 5.11.9 Temperature Compensation. ISS 1 Inst / Para TMPREAD D/!C 0 !WR !RD 1 D7 1 D6 0 D5 1 D4 1 D3 1 D2 0 D1 0 D0 0 (Code) (B8h)
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6.2.34 EPVOL: Electrical Volume set for EEPROM (C0h)

Specify the voltage regulator circuits electronic volume offset value (which will be stored in EEPROM). The 1st parameter: Electrical Volume offset value The 2nd parameter: Dummy byte The 3rd parameter: Resistance Ratio offset value
ISS 1 1 1 1 Inst / Para EPVOL 1st parameter 2 parameter 2 parameter
nd nd
D/!C 0 1 1 1
!WR
!RD 1 1 1 1
D7 1 -
D6 1
-
D5 0
-
D4 0
-
D3 0
-
D2 0
-
D1 0
-
D0 0
-
(Code) (C0h) Dummy byte -
6.2.35 EPWRIN: EEPROM Write Start (CDh)

Write start the Electronic volume offset (EOF), Resistance ratio (ROF) value and ID2 into the EEPROM.
ISS 1 1 Inst / Para EPWRIN Parameter D/!C !WR !RD 0 1 No Parameter D7 1 D6 1 D5 0 D4 0 D3 1 D2 1 D1 0 D0 1 (Code) (CDh)
6.2.36 EPWROUT: EEPROM Write End (CCh)

Write end the Electronic volume offset (EOF), Resistance ratio (ROF) value and ID2 into the EEPROM
ISS 1 1 Inst / Para EPWROUT Parameter D/!C !WR !RD 0 1 No Parameter D7 1 D6 1 D5 0 D4 0 D3 1 D2 1 D1 0 D0 0 (Code) (CCh)
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6.2.37 RDEV: Read Electrical Volume Value (7Ch)

This read byte returns 7-bit Electrical Volume Value. The 1st parameter is dummy data The 2nd parameter (EV6 to EV0): Internal Electrical Volume Value.
ISS 1 1 1 Inst / Para RDEV Dummy read 2nd parameter D/!C 0 1 1 !WR 1 1 !RD 1 D7 0 D6 1 EV6 D5 1 EV5 D4 1 EV4 D3 1 EV3 D2 1 EV2 D1 0 EV1 D0 0 EV0 (Code) (7Ch) -
6.2.38 RDRR: Read Resistor Ratio Value (7Dh)

This read byte returns 3-bit Resistor Ratio Value. The 1st parameter is dummy data The 2nd parameter (RR2 to RR0): Internal Resistor Ratio Value.
ISS 1 1 1 Inst / Para RDRR Dummy read 2nd parameter D/!C 0 1 1 !WR 1 1 !RD 1 D7 0 D6 1 D5 1 D4 1 D3 1 D2 1 RR2 D1 0 RR1 D0 1 RR0 (Code) (7Dh) -
6.2.39 RDID1: Read ID1 Value (DAh)

This read byte returns 8-bit LCD modules manufacturer ID The 1st parameter is dummy data The 2nd parameter (ID17 to ID10): LCD modules manufacturer ID.
ISS 1 1 1 Inst / Para RDID1 Dummy read 2nd Parameter D/!C 0 1 1 !WR 1 1 !RD 1 D7 1 D6 1 D5 0 D4 1 D3 1 D2 0 D1 1 D0 0 (Code) (DAh) -
6.2.40 RDID2: Read ID2 Value (DBh)

This read byte returns 8-bit LCD module/driver version ID The 1st parameter is dummy data The 2nd parameter (ID26 to ID20): LCD module/driver version ID
ISS 1 1 1 Inst / Para RDID2 Dummy read 2nd Parameter D/!C 0 1 1 !WR 1 1 !RD 1 D7 1 1 D6 1 D5 0 D4 1 D3 1 D2 0 D1 1 D0 1 (Code) (DBh) -
ID26 ID25 ID24 ID23 ID22 ID21 ID20
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6.2.41 RDID3: Read ID3 Value (DCh)

This read byte returns 8-bit LCD module/driver ID. The 1st parameter is dummy data The 2nd parameter (ID37 to ID30): LCD module/driver ID.
ISS 1 1 1 Inst / Para RDID3 Dummy read 2nd Parameter D/!C 0 1 1 !WR 1 1 !RD 1 D7 1 D6 1 D5 0 D4 1 D3 1 D2 1 D1 0 D0 0 (Code) (DCh) -
6.2.42 IDMOFF: Idle Mode Off (38h)

This command is used to recover from Idle mode on. There will be no abnormal visible effect on the display mode change transition. In the idle off mode LCD can display maximum 4096 colors and normal frame frequency is applied.
ISS 1 1 Inst / Para IDMOFF Parameter D/!C !WR !RD 0 1 No Parameter D7 0 D6 0 D5 1 D4 1 D3 1 D2 0 D1 0 D0 0 (Code) (38h)
6.2.43 IDMON: Idle Mode On (39h)

This command is used to enter into Idle mode on. There will be no abnormal visible effect on the display mode change transition. ISS Inst / Para D/!C !WR !RD D7 D6 D5 D4 D3 D2 D1 D0 (Code) 1 IDMON 0 1 0 0 1 1 1 0 0 1 (39h) 1 Parameter No Parameter In the idle on mode, 1. Color expression is reduced. The primary and the secondary colors using MSB of each RMG and B in the Frame Memory, 8 color depth data is displayed. 2. 8-Color mode frame frequency is applied. 3. Exit from IDMON by Idle Mode Off (38h) command
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6.2.44 TEOFF: Tearing Effect Line OFF (34h)

This command is used to turn OFF (Active Low) the Tearing Effect output signal from the TE signal line.
ISS 1 1 Inst / Para TEOFF Parameter D/!C !WR !RD 0 1 No Parameter D7 0 D6 0 D5 1 D4 1 D3 0 D2 1 D1 0 D0 0 (Code) (34h)
6.2.45 TEON: Tearing Effect Line ON (35h)

This command is used to turn ON the Tearing Effect output signal from the TE signal line. This output is not affected by changing MADCTL bit ML.
ISS 1 1 Inst / Para TEON Parameter D/!C 0 1 !WR !RD 1 1 D7 0 D6 0 D5 1 D4 1 D3 0 D2 1 D1 0 D0 1 M (Code) (35h) -
6.2.46 TEST1: Test Command1 (6-h)

ISS 1 Inst / Para TEST1 D/!C 0 !WR !RD 1 D7 0 D6 1 D5 1 D4 0 D3 D2 D1 D0 (Code) (6-h)
6.2.47 TEST2: Test Command2 (0-h)

ISS 1 Inst / Para TEST2 D/!C 0 !WR !RD 1 D7 0 D6 0 D5 0 D4 0 D3 D2 D1 D0 (Code) (0-h)
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6.3 RESET TABLE (DEFAULT VALUE)

6.3.1 Instruction Code0 (ISS=0)
After Power On Random In Off Normal Off Off 3Fh Off 01h 82h 01h 82h All 0h 00h 80h 00h 84h 00h 00h Off 0 (Mode1) 0/0/0/0/0 After Hardware Reset No Change In Off Normal Off Off 3Fh Off 01h 82h 01h 82h All 0h 00h 80h 00h 84h 00h 00h Off 0 (Mode1) 0/0/0/0/0 After Software Reset No Change In Off Normal Off Off 3Fh Off 01h 82h 01h 82h No Change 00h 80h 00h 84h 00h 00h Off 0 (Mode1) No Change Off No Change Internal 03h/07h/07h/07h 03h/07h/07h/07h 2Dh/7Fh/7Fh 05h 07h (field) 15h 45h 80h ~ FFh 03h Item Frame memory Sleep In/Out Booster On/Off Display mode (normal/partial) Display Inversion On/Off All Pixel On/Off Contrast (EV) Display On/Off Column: Start Address (XS) Column: End Address (XE) Row: Start Address (YS) Row: End Address (YE) RGB for 4k and 256 Color Mode (R/G/B) Partial: Start Address (PSL) Partial: End Address (PEL) Scroll: Top Fixed Area (TFA) Scroll: Scroll Area (VSA) Scroll: Bottom Fixed Area (BFA) Scroll Start Address (SSA) Tearing: On/Off Tearing Mode Memory Data Access Control (MY/MX/MV/ML/RGB) Idle Mode On/Off Interface Pixel Color Format (P) Clock Internal/External Frame Frequency in Normal Color (FA/FB/FC/FD) Frame Frequency in 8-Color (Idle) (F8A/F8B/F8C/F8D) Temperature Range (TA/TB/TC) Temperature Hysteresis (TH) Display Control: F1/F2 Switching (FS) Display Control: N-Line Inversion (FINV/NL) ID1 ID2 ID3
Off Off 3 (12-Bit/Pixel Type A) 3 (12-Bit/Pixel Type A) Internal Internal 03h/07h/07h/07h 03h/07h/07h/07h 2Dh/7Fh/7Fh 05h 07h (field) 15h 45h 80h ~ FFh 03h 03h/07h/07h/07h 03h/07h/07h/07h 2Dh/7Fh/7Fh 05h 07h (field) 15h 45h 80h ~ FFh 03h
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6.3.2
Instruction Code1 (ISS=1)

After Power On Random In Off 00h (All Off) 00h 83h Off Off 00h 83h 00h 83h All 0h 00h 00h 00h 3 (Whole Scroll) 00h 0/0/0/0 2 (12-Bit/Pixel Type A) Out 20h 07h (field) 15h 03h/07h/07h/07h 03h/07h/07h/07h 2Dh/7Fh/7Fh 05h Off Off 45h 80h ~ FFh 03h After Hardware Reset No Change In Off 00h (All Off) 00h 83h Off Off 00h 83h 00h 83h All 0h 00h 00h 00h 3 (Whole Scroll) 00h 0/0/0/0 2 (12-Bit/Pixel Type A) Out 20h 07h (field) 15h 03h/07h/07h/07h 03h/07h/07h/07h 2Dh/7Fh/7Fh 05h Off Off 45h 80h ~ FFh 03h
Item Frame memory Sleep In/Out Oscillator On/Off Power Control (PW) Partial: Start Line (PSB) Partial: End Line (PEB) Display Inversion On/Off Display On/Off Column: Start Address (XS) Column: End Address (XE) Row: Start Address (YS) Row: End Address (YE) RGB for 4k and 256 Color Mode (R/G/B) Scroll: Top Scroll Block (SSL) Scroll: Bottom Scroll Block (SEL) Scroll: Specified Block (SFL) Scroll: Scroll Mode (SMD) Scroll Start Address (SSA) Data Access Control (MV/MX/MY/RGB) Data Access Control (GS) Read Modify Write In/Out Volume Control: (EV) Display Control: F1/F2 Switching (FS) Display Control: N-Line Inversion (FINV/NL) Frame Frequency in Normal Color (FA/FB/FC/FD) Frame Frequency in 8-Color (Idle) (F8A/F8B/F8C/F8D) Temperature Range (TA/TB/TC) Temperature Hysteresis (TH) Idle Mode On/Off Tearing: On/Off ID1 ID2 ID3
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6.4 INSTRUCTION SETUP FLOW

6.4.1 Initializing with the Built-in Power Supply Circuits
Initializing Start (Power ON)
H/W Reset
Power Input: VSS, VDD1 VDD2 (order should be kept) Wait Until Power Stabilization !RES = L Wait for more than 10s !RES = H
DISCTR (Display Control) - F1/F2 switching period set - Line inversion set OSCON (Oscillator ON) SLPOUT (Sleep mode OFF)
Display Environment Set1
VOLCTR (Electronic Volume Control) - Electronic volume (EV) / Built-in resistance ratio (RR) set PWRCTR (Power Control) - PW [3:0] set
Power Supply Set
DISNOR / DISINV (Display Normal / Inversion Set) PATIN / PATOUT (Partial Mode Set) - Partial start/end block set (PSB, PEB) ASCSET (Area Scroll Set) - Scroll start block, specified block, scroll end block set (SSL, SFL, SEL) - Scroll mode set (SMD) VSCSAD (Scroll Start Address set) - Scroll start address by block unit (SSB) DATCTR (Data Control) - Address direction (V), column direction (MX), row direction (MY) - RGB order (RGB) / Gray scale (GS) set RGBSET (256-Color position set) - Red/green/blue mapping data set
Display Environment Set2
RASET / CASET (Row/Column Address Set) - Start/end row address set (YS, YE), Start/end column address set (XS, XE) RAMWR (Memory Data Write) Wait for more than 120ms after power control command DISPON (Display ON)
Display Data Write & Display On
Initializing End
Fig. 6.4.1 Initializing with the built-in power supply circuits (Only for Instruction Code1: ISS=High)
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Initializing Start (Power ON)

H/W Reset
Power Input: VSS, VDD1 VDD2 (order should be kept) Wait Until Power Stabilization !RES = L Wait for more than 10s !RES = H
WRCNTR (Electronic Volume Control) - Electronic volume (EV) set SLPOUT (Sleep mode OFF & OSC/Booster On)
Power Supply Set
INVON / INVOFF (Display Inversion / Normal Set) IDMON / IDMOFF (Idle Mode On/Off) PTLAR / PTLON / PTLOFF (Partial Area Set & Partial On/Off) - Partial start/end line set (PSB, PEB) SCRLAR (Area Scroll Set) - Top fixed area, scroll area and bottom fixed area set (TFA, VSA, BFA) VSCSAD (Scroll Start Address Set) - Scroll start address (SSA) MADCTR (Memory Data Access Control) - Row direction (MY), column direction (MX), address direction (V), scan direction (ML) and RGB order COLMOD (Interface Pixel Format Set) RGBSET (4k and 256-Color position set) - Red/green/blue mapping data set
Display Environment Set
RASET / CASET (Row/Column Address Set) - Start/end row address set (YS, YE), Start/end column address set (XS, XE) RAMWR (Memory Data Write) Wait for more than 120ms after power control command DISPON (Display ON)
Display Data Write & Display On
Initializing End
Fig. 6.4.2
Initializing with the built-in power supply circuits (Only for Instruction Code0: ISS=Low)
The initializing sequence does not have any effect on the display. The display is in its normal background color during the initialization.
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6.4.2
Power OFF Sequence
Power OFF Start (Without H/W Reset)

DISPOFF (Display OFF) All of the common & segment pins become VC potential. PWRCTR (Power Control) All the liquid crystal power supply circuits become OFF. OSCOFF (Oscillator OFF) SLPIN (Sleep IN) Stop the Power Supply: VDD2 stop VDD1 stop (order should be kept)
Power OFF End
Power OFF Start (With H/W Reset)

H/W Reset
!RES = L Wait for more than 10s !RES = H
Stop the Power Supply: VDD2 stop VDD1 stop (order should be kept))
Power OFF End
Fig. 6.4.3
Power OFF sequence (Only for Instruction Code1: ISS=High)
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Power OFF Start (Without H/W Reset)

DISPOFF (Display OFF) All of the common & segment pins become VC potential. SLPIN (Sleep IN) All the liquid crystal power supply circuits and oscillator circuit become OFF.
Stop the Power Supply: VDD2 and VDD1 stop
Power OFF End
Power OFF Start (With H/W Reset)

H/W Reset
!RES = L Wait for more than 10s !RES = H
Stop the Power Supply: VDD2 and VDD1 stop
Power OFF End
Fig. 6.4.4
Power OFF sequence (Only for Instruction Code0: ISS=Low)
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6.4.3
EEPROM Program Sequence

Start
EXTB = VSS RESET * EPVOL command EVOF[5:0] = (000000)b ROF[2:0] = (000)b * WRID2 command: ID2[6:0] = (0000000)b Apply 13.0V~ 15.0V at VH pad * EPWRIN command Wait for more than 1.5sec * EPWROUT command Remove VH external power * SLPOUT command * RAMWR command Pattern Data Write * DISPON command
EEPROM Initialize (Clear data)
ID bit assignment
Bit ID1 ID2 ID3 D7 D6 D5 D4 D3 D2 D1 D0 ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30
* ID17 to ID10, ID27, ID37 to ID30: Fixed by Metal Layer * ID26 to ID20: Programmed to EEPROM
* WRCNTR command No
Optimum Display? Yes * EPVOL command EVOF[4:0] = |EV-63| EVOF[5] = 1 (EV<63), 0 (EV63) ROF[2:0] = value * WRID2 command: ID2[6:0]
* SLPOUT command * DISPON command No

EVOF program fail
Optimum Display? Yes
EEPROM Program Confirm
EEPROM Programming
* SLPIN command Apply 13.0V~ 15.0V at VH pad * EPWRIN command Wait for more than 1.5sec * EPWROUT command Remove VH external power
* RDDID command No
ID2 program fail
ID2 OK? Yes
End
Fig. 6.4.5
EEPROM write/read sequence (For both Instruction Code0 and Code1)
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SPECIFICATIONS
(VSS = 0V)
7.1 ABSOLUTE MAXIMUM RATINGS

Item Supply voltage (1) Supply voltage (2) Supply voltage (3) Input voltage range Output voltage range Operating temperature range Symbol VDD1, VDD2 VLCD (VH-VL) VMAX (VH-VOUTL) VIN VO TOPR Value - 0.3 ~ + 4.0 - 0.3 ~ + 20.0 - 0.3 ~ + 20.0 - 0.3 ~ VDD + 0.3 - 0.3 ~ VDD + 0.3 - 40 ~ + 85 - 55 ~ + 125 Unit V V V V V C C
Storage temperature range TSTG NOTE: 1. Voltages are all based on VSS = 0V.
2. Voltage relationship: VH VXH2 VXH1 VC VXL1 VXL2 (VSS) VL VOUTL must always be satisfied.
7.2 ESD PROTECTION LEVEL

Table 7.2.1 ESD models.
Model Human Body Model Machine Model
Test Condition C = 100 pF, R = 1.5 k C = 200 pF, R = 0.0
Protection Level > 2000 > 200
Unit V V
7.3 LATCH-UP PROTECTION LEVEL

The device will not latch up at trigger current levels less than 100 mA.
7.4 LIGHT SENSITIVITY

The operation of the IC will not be materially altered by incident light.
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7.5 MAXIMUM SERIES RESISTANCE

The driver will operate in Chip on Glass applications with series resistances (due to ITO track resistance). Voltages are specified at module I/O assuming maximum values as in Table 7.5.1.
Table 7.5.1 Maximum series resistance on module.
Name VDD1 VDD2 VSS VSS1 *1) VH *1) VXH2 *1) VXH1 *1) VC *1) VXL1 *1) VXL2 *1) VL OSC, TEST3, TEST4, TEST5, EXTB SRGB, SMX, SMY, ROWM ISS PS0, PS1 !RES !CS (!SCE) D/!C (SCL) !WR !RD TE D7 to D0(SDA) CX1P, CX2P CX1M, CX2M VOUT VOUT2 C1P, C2P C1M to C3M VOUTL C5M C5P
Type Power supply Power supply Power supply Power supply Capacitor connection Capacitor connection Capacitor connection Capacitor connection Capacitor connection Capacitor connection Capacitor connection Input
Maximum Series Resistance 100 50 50 1000 100 100 100 100 100 100 100 1000
Unit

Input Input Input Input Input Input Input Input Output Input / Output Capacitor connection Capacitor connection Capacitor connection Capacitor connection Capacitor connection Capacitor connection Capacitor connection Capacitor connection Capacitor connection
1000 1000 1000 200 200 200 200 200 1000 200 100 100 100 100 100 100 100 100 100
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7.6 DC CHARACTERISTICS
7.6.1 Basic Characteristics
(VSS=0V, VDD1=1.65V to 1.95V, VDD2=2.6V to 2.9V,Ta = -30 to 70C)
Parameter Symbol Conditions Related Pins MIN TYP MAX Unit
Logic Operating voltage Analog Operating voltage Driving voltage input High level input voltage Low level input voltage High level output voltage Low level output voltage Input leakage current Driver on resistance (SEG) Driver on resistance (COM) External oscillator frequency Booster1 output voltage range Booster1 output efficiency Reference voltage Voltage follower output voltage Booster2 output voltage range Booster2 output efficiency Booster3 output efficiency
VDD1 VDD2 VLCD VMAX VIH VIL VOH VOL IIL RONSEG RONCOM fOSC VOUT VOUT2 VOUTEF VOUT2EF VREG VXH1 VC VXL1 VOUTL VOUTLEF VHEF
VH - VL VH - VOUTL IOH = -0.5mA IOL = +0.5mA VXH2 = 5.0V VH = 10.0V DFCL=32 X3, No load X2, No load X3, No load X2, No load Ta = 25C VXH2 = 6.0V
VDD1 VDD2 VH, VL VH, VOUTL *1) *1) D7 to D0, TE, TEST1 *2) S0 to S395 *2) C0 to C131 OSC VOUT VOUT2 VOUT VOUT2 VXH1 VC VXL1
1.65 2.6 0.7VDD1 VSS 0.8VDD1 VSS -1.0 200.0 7.8 5.2 95.0 95.0 1.55 4.28 2.85 1.43 -5.2 95.0 95,0
1.8 2.75 3.5 0.4 211.0 99.0 99.0 1.60 4.50 3.00 1.50 99.0 99.0
1.95 2.9 18.0 18.0 VDD1 0.3VDD1 VDD1 0.2VDD1 +1.0 10 1.0 222.0 8.7 5.8 1.65 4.73 3.15 1.73 -5.8 -
VIN = VDD1 or VSS *1)
k kHz V V % % V V
X3, No load X3, No load X2, No load
VOUTL VOUTL VH
% %
NOTE: *1) Applies to EXTB, ROWM, OSC, TEST3 to TEST5, ISS, PS0, PS1, !CS, !RES, D/!C(SCL), !WR, !RD, and D7 to D0(SDA) pins *2) Resistance value when -0.1[mA] is applied during the ON status of the output pin S0 to S395 and C0 to C131. RON [K] = V[V] / 0.1[mA] (V : Voltage change when 0.1[mA] is applied in the on status.)
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7.6.2
Host I/F
Current Consumption
Mode of operation Frame Frequency Inversion Mode Image Note 1 Note 2 Note 3 Note 4 Note 5 Note 5 Interface Pixel (P[2:0]) X;X;X X;X;X X;X;X X;X;X X;X;X X;X;X Current consumption Typical Worst case (9) (10) VDD2 VDD1 VDD2 VDD1 (mA) (mA) (mA) (mA)
- Normal Mode On - Partial Mode Off - Idle Mode Off - Sleep Out Mode
Host interface NOT active
65Hz
- Normal Mode On - Partial Mode Off - Idle Mode On - Sleep Out Mode - Normal Mode Off - Partial Mode On (32 lines) - Idle Mode Off - Sleep Out Mode - Normal Mode Off - Partial Mode On (32 lines) - Idle Mode On - Sleep Out Mode - Sleep In Mode
65Hz
65Hz
Grey Levels
X;X;X
Note 6 65Hz Note 7 N/A N/A N/A 4k Colours
X;X;X X;X;X X;X;X 0;0;0 0;0;1 0;1;0 0;1;1 1;0;0 1;0;1 1;1;0 1;1;1 0.002 0.010
Host interface active
- Normal Mode On - Partial Mode Off - Idle Mode Off - Sleep Out Mode
Full screen
Checker board one by one CPU Access @ 10fps
NOTE: X 1. 2. 3. 4. 5. 6. 7.
Typical Case: TA = 25C Do not care VDD2 = 2.75V All pixels black VDD1 = 1.8V Checker board one by one Checker board 4 by 4 Worst Case: TA = -30 to70C Grey-scale from top to bottom VDD2 = 2.6V to 2.9V 20% Black, 80%White VDD1 = 1.65V to 1.95V Black & White Checker board 8 by 8. Includes Process Variance. Absolute Worst Case Patterns: - Black & White Horizontal Stripe 1 by 1 - Black & White Checker board 1pixel by 1pixel - Black & White Checker board 1dot by 1dot 8. Absolute worst case VDD2 current is less than 0.8mA in the case of Normal Mode On, Partial Mode Off, Idle Mode Off, Sleep Out mode (CPU access is inactive).
9.
Absolute worst case VDD1 current is less than 2.0A in the case of Normal Mode On, Partial Mode Off, Idle Mode Off, Sleep Out mode (Host interface not active). 10. Inrush currents are not included in current consumption values
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7.7 AC CHARACTERISTICS
7.7.1 Parallel Interface Characteristics (8080-series MPU)
tCHW
!CS
VIH VIL tCSW tCSF
VIH VIL
D/!C
VIH VIL tAS tPWLW tAH tCYW VIH VIL tCSR tCYR tPWLR VIH tPWHR tDS tDH VIL tDOA VOH VOL tDOD VOH VOL tCSF VIH VIL tPWHW
!WR
!RD
D7 to D0
VIH VIL
Fig. 7.7.1
Parallel Interface characteristics (8080-series MPU)

Symbol tCSW, tCSR tCSF tCHW tAS tAH tCYW tPWHW tPWLW tCYR tPWHR tPWLR tCYR tPWHR tPWLR tDS tDH tDOA tDOD Parameter Chip select setup time Chip select hold time Chip select high pulse width Address setup time Address hold time Write cycle time Write High Time Write Low Time Read cycle time (Parameter read) Read High (Parameter read) Read Low (Parameter read) Read cycle time (Data read) Read High (Data read) Read Low (Data read) Data setup time Data hold time Data output access time Data output disable time Conditions Related Pins MIN 40 10 45 10 10 160 90 40 160 90 40 450 90 355 10 10 20 TYP MAX Unit
!CS D/!C !WR
ns ns ns
!RD
ns
!RD
40 80
ns ns ns
D7 to D0 CL = 30pF
NOTE: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less.
Input Signal Slope tr
VIH=0.7*VDDI VIL=0.3*VDDI
Output Signal Slope tf tr

VOH=0.8*VDDI VOL=0.2*VDDI
tf
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7.7.2
Parallel Interface Characteristics (6800-series MPU)
!CS
VIH VIL tCSW68 tCSF68
D/!C
VIH VIL
R/!W
VIH VIL
tAS68
tAH68
tCYR68 tCYW68 VIH VIL tPWHW68 tDS68 tDH68 tPWLW68 tPWLR68 VIL VIH tPWHR68 tDOA68 tDOD68
D7 to D0
VIH VIL
Fig. 7.7.2
Parallel Interface characteristics (6800-series MPU)

Symbol tCSW68 tCSF68 tAS68 tAH68 tCYW68 tPWHW68 tPWLW68 tCYR68 tPWHR68 tPWLR68 tCYR68 tPWHR68 tPWLR68 tDS68 tDH68 tDOA68 tDOD68 Parameter Chip select setup time Chip select hold time Address setup time Address hold time Write cycle time Write High Time Write Low Time Read cycle time (Parameter read) Read High (Parameter read) Read Low (Parameter read) Read cycle time (Data read) Read High (Data read) Read Low (Data read) Data setup time Data hold time Data output access time Data output disable time Conditions Related Pins
!CS D/!C R/!W E
D7 to D0 CL = 30pF
MIN 40 10 10 10 160 40 90 160 40 90 450 355 90 10 10 20
TYP -
MAX -
Unit
ns ns ns
ns
40 80
ns ns ns
NOTE: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less.

tf
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7.7.3
Serial Interface Characteristics
!SCE
tCSS tCYS tPWL tSCC VIH VIL tDSS tDHS tPWH tCHS tCHW
SCL
SDA (SDI)
tACC tODE
SDA (SDO)
Fig. 7.7.3
Serial interface characteristics
VSS=0V, VDD1=1.65V to 1.95V, VDD2=2.6V to 2.9V,Ta = -30 to 70C)

Symbol
tCYS tPWH tPWL tDSS tDHS tCSS tCHS tCHW tSCC tACC tODE
Parameter Serial clock cycle Low pulse width High pulse width Data setup time Data hold time Chip select setup time Chip select hold time Chip select high pulse width SCL to Chip select SDO access time SDO disable time
Conditions
Related Pins
SCL SDA (SDI)
*1)
!SCE SCL, !SCE SDA (SDO)
MIN 150 60 60 60 60 60 65 45 20 10 15
TYP
MAX
Unit
50 50
ns ns ns ns ns
NOTE:*1) tACC condition: Load = 30pF, tODE condition: Load = 5pF and R = 3kOhm The input signal rise time and fall time (tr, tf) is specified at 15 ns or less.

tf
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7.7.4
Reset Input Timing
Shorter than 5s
tRESW
!RES
tREST
Internal Status
Normal Operation
Reset Processing
Initial Condition (Default for H/W reset)
Fig. 7.7.4
Reset input timing
VSS=0V, VDD1=1.65V to 1.95V, VDD2=2.6V to 2.9V,Ta = -30 to 70C)

Symbol Parameter Related Pins MIN TYP MAX Note Unit s
tRESW tREST
*1) Reset low pulse width *2) Reset complete time
!RES -
10 -
ms
NOTE: 1) Spike due to an electrostatic discharge on !RES line does not cause irregular system reset according to the table below.
!RES Pulse Shorter than 5s Longer than 10s Between 5s and 10s Action Reset Rejected Reset Not Determined
2) During the resetting period, the display will be blanked and then return to Default condition for H/W reset. (ID2 value in OTP will be latched to internal register during this period) 3) Spike Rejection also applies during a valid reset pulse as shown below:
10s
Reset is accepted 10s
1usec
Less than 1usec width positive spike will be rejected.
4) It is necessary to wait 10sec after releasing !RES before sending commands. After reset complete, Sleep Out command can be sent to start internal power circuit.
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7.7.5
Measurement Conditions for Parallel and Serial Interfaces
Measurement Condition Set-up for Parallel and Serial Interaces
Data Generator
Oscilloscope See NOTE Connector
LCD Panel
FPC
External components for test condition (pull-down and pull-up cases) which are removed after test: Resistor: 3kOhm 5% Capacitor: 8 or 30pF 10%
Connector Pin / Measurement
NOTE: Capacitances and resistances of the oscilloscopes probe must be included externals components in these measurements 7.7.5.1 tDOA, tDOD Measurement Condition
Minimum Value Measurement
70%
!RD
tDOD
D(n) [n=0..7]
(pulled up)
D(n) [n=0..7]
(pulled down) Measurement circuit pulled down
External components on the connector pin
0% 100%
Measurement circuit pulled Up

VDD1 3kOhm
D(n) [n=0..7]
(pulled down)
Measurement point on the connector pin
3kOhm 8pF
D(n) [n=0..7]
(pulled down)
8pF
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Maximum Value Measurement
70%
!RD
tDOA tDOD
D(n) [n=0..7]
(pulled up)
20% 80%
D(n) [n=0..7]
0% 100%

VDD1
D(n) [n=0..7]
(pulled down)
3kOhm 30pF
3kOhm
D(n) [n=0..7]
(pulled down)
30pF
7.7.5.2
tACC, tODE Measurement Condition
Minimum Value Measurement
70%
SCL SDA
(pulled up)
30% 100% tODE
tACC
SDA
0%
0% 100%

VDD1 3kOhm
SDA (DOUT)
(pulled down)
3kOhm 8pF
SDA (DOUT)
(pulled down)
8pF
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Maximum Value Measurement
70%
SCL SDA
(pulled up)
30% tODE 100% 20% tACC 80% 0% 0% 100%
SDA

VDD1 3kOhm
SDA (DOUT)
(pulled down)
3kOhm 30pF
SDA (DOUT)
(pulled down)
30pF
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REFERENCE APPLICATIONS
Interfacing with 8080-series MPU 8-Bit Bus (PS0 = "H", PS1 = "H")
8.1 MICROPROCESSOR INTERFACE 8.1.1
VDD1 PS0
LDS176
PS1
8 0 8 0 - S e r ie s MPU
CSB D /C /R D /W R D 7 to D 0 RESB TE
!C S D /! C !R D !W R D 7 to D 0 !R E S TE
Fig. 8.1.1
Interfacing with 8-bit 8080-series
8.1.2
Interfacing with 6800-series MPU 8-Bit Bus (PS0 = "H", PS1 = "L)
VDD1 PS0
LDS176
PS1
6 8 0 0 - S e r ie s MPU
CSB RS E R /W
VSS !C S D /! C E R /! W D 7 to D 0 !R E S TE
D 7 to D 0 RESB TE
Fig. 8.1.2
Interfacing with 8-bit 6800-series
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8.1.3
3-Line Serial mode (PS0 = "L", PS1 = "L" or "H")
MPU
V DD1, V SS CSB VSS !S C E !W R !R D PS0 PS1
LDS176
VDD1 or VSS VDD1 or VSS V DD1, V SS or O pen SCL S D I/S D O TE
D 7 to D 1 S C L ( D /! C ) S D A (D 0 ) TE
Fig. 8.1.3
3-Line serial interface (PS0 = "L")
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8.2 CONNECTIONS WITH LCD PANEL

Case 1
C0 C67 S0 C0
LDS176
C68 C131 S395
Bumps up
G B B
MADCTR Command MX = 0 MY = 0 RGB = 0 S0 = Filter R S1 = Filter G S2 = Filter B
C67
G
C68
R
C131
Case2
C68 C131 S395
LDS176
C0 C67 S0
Bumps down
G B B G
C0
MADCTR Command MX = 1 MY = 0 RGB = 1 S0 = Filter B S1 = Filter G S2 = Filter R
C67
C68
R
C131
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CHIP INFORMATION
9.1 CHIP OVERVIEW

1,590.0 um (25+2-1)*41=1,066.0 193.0 41.0 150.0 1 90.0 C68 457.0 130.0 150.0 (72+2-1)*90 = 6,570.0 89.0 111.0 C131 (39+8-1)*41 = 1,886.0 457.0 80.0 130.0 80.0 C92 C93 331.0 143.5 41.0
156.0
Top Metal
69.0 46.0 (26-1)*46 = 1,150.0 69.0 20,500.0 um 85.0 S395
Input pad area = 20,186.0
(396+2-1)*41 = 16,277.0
(136+2-1)*90 = 12,330.0
S0
Unit: m : Dummy pad : COM output pad : SEG output pad
C67
(43+8-1)*41 = 2,050.0 457.0 130.0 457.0 C0 156.0 C24 C25 143.5 80.0
Top Metal
80.0 130.0
LDS176 Bumps Up
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NOTE: * Chip Size = 20,500 x 1,590 (Excluding Scribe Lane 200 x 200) * Chip Thickness = 500 12 m * Bump height = 17 3 m (chip to chip), less than 2 m (pad to pad in one chip)
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9.2 BUMP INFORMATION

9.2.1 COM/SEG Output Pad Format
Symbol A B C D I H G E1 E2 F1 F2 A+B C*H J Size 31m 10 m 27 m 7 m 74 m 130 m 50 m 10 m 7 m 2 m 5 m 41 m 3,510 m2 85 m Item AL width AL to AL gap Bump width Pad open width AL height Bump height Pad open height Pad open to Bump gap Bump to AL gap Pad pitch Bump area Chip boundary to Bump edge
Chip boundary
A C
F2
B J
D E1 F1
E2+F2
I H
E2
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9.2.2
Input Pad Format

Symbol A B C D I H G E1 E2 F1 F2 A+B C*H J Size 80 m 10 m 70 m 56 m 62 m 58 m 38 m 7 m 10 m 5 m 2 m 90 m 4,060 m2 86 m Size (TESTF) 36 m 10 m 26 m 12 m 62 m 58 m 38 m 7 m 10 m 5 m 2 m 46 m 1,508 m2 86 m
Item AL width AL to AL gap Bump width Pad open width AL height Bump height Pad open height Pad open to Bump gap Bump to AL gap Pad pitch Bump area Chip boundary to Bump edge
E2
F2
A C D
E1
F1
Chip boundary
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9.3 PAD COORDINATES

Table 9.3.1 Pad Center Coordinates
No
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Name
DUMMY DUMMY VH VH VH VH VXH2 VXH2 VXH2 VXH2 VXH1 VXH1 VXH1 VXH1 VC VC VC VC VXL1 VXL1 VXL1 VXL1 VXL2 VXL2 VXL2 VXL2 DUMMY VLL VLL VLL VLL DUMMY CX2M CX2M CX2M CX1M CX1M CX1M CX1P CX1P CX1P VOUT2 VOUT2 VOUT2 VOUT2 CX2P CX2P CX2P VOUT VOUT
X
-10094.0 -10004.0 -9914.0 -9824.0 -9734.0 -9644.0 -9554.0 -9464.0 -9374.0 -9284.0 -9194.0 -9104.0 -9014.0 -8924.0 -8834.0 -8744.0 -8654.0 -8564.0 -8474.0 -8384.0 -8294.0 -8204.0 -8114.0 -8024.0 -7934.0 -7844.0 -7754.0 -7664.0 -7574.0 -7484.0 -7394.0 -7304.0 -7214.0 -7124.0 -7034.0 -6944.0 -6854.0 -6764.0 -6674.0 -6584.0 -6494.0 -6404.0 -6314.0 -6224.0 -6134.0 -6044.0 -5954.0 -5864.0 -5774.0 -5684.0
Y
-680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0
No
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Name
VOUT VOUT EXTB EXTB !RES !RES !CS !CS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS1 VSS1 TE TE TESTF1 TESTF2 TESTF3 TESTF4 TESTF5 TESTF6 TESTF7 TESTF8 TESTF9 TESTF10 TESTF11 TESTF12 TESTF13 TESTF14 TESTF15 TESTF16 TESTF17 TESTF18 TESTF19 TESTF20 TESTF21 TESTF22 TESTF23 TESTF24 TESTF25 TESTF26
X
-5594.0 -5504.0 -5414.0 -5324.0 -5234.0 -5144.0 -5054.0 -4964.0 -4874.0 -4784.0 -4694.0 -4604.0 -4514.0 -4424.0 -4334.0 -4244.0 -4154.0 -4064.0 -3974.0 -3884.0 -3794.0 -3704.0 -3614.0 -3524.0 -3455.0 -3409.0 -3363.0 -3317.0 -3271.0 -3225.0 -3179.0 -3133.0 -3087.0 -3041.0 -2995.0 -2949.0 -2903.0 -2857.0 -2811.0 -2765.0 -2719.0 -2673.0 -2627.0 -2581.0 -2535.0 -2489.0 -2443.0 -2397.0 -2351.0 -2305.0
Y
-680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0
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Table 9.3.2
Pad Center Coordinates (Continued)
No
101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150
Name
OSC OSC TEST7 TEST7 TEST7 TEST7 TEST7 TEST7 ISS ISS PS0 PS0 PS1 PS1 TEST6 TEST6 TEST8 TEST8 TEST8 TEST8 TEST8 TEST8 !RD !RD !WR !WR TEST1 TEST1 DB7 DB7 DB6 DB6 DB5 DB5 DB4 DB4 DB3 DB3 DB2 DB2 DB1 DB1 VCAP2 VCAP2 VCAP2 VCAP2 VCAP2 VCAP2 VCAP2 VCAP2
X
-2236.0 -2146.0 -2056.0 -1966.0 -1876.0 -1786.0 -1696.0 -1606.0 -1516.0 -1426.0 -1336.0 -1246.0 -1156.0 -1066.0 -976.0 -886.0 -796.0 -706.0 -616.0 -526.0 -436.0 -346.0 -256.0 -166.0 -76.0 14.0 104.0 194.0 284.0 374.0 464.0 554.0 644.0 734.0 824.0 914.0 1004.0 1094.0 1184.0 1274.0 1364.0 1454.0 1544.0 1634.0 1724.0 1814.0 1904.0 1994.0 2084.0 2174.0
Y
-680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0
No
151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200
Name
VCAP2 VCAP2 VCAP2 VCAP1 VCAP1 VCAP1 VCAP1 VCAP1 VCAP1 VCAP1 VCAP1 VCAP1 VCAP1 VCAP1 C3M C3M C3M DB0 DB0 D/!C D/!C VDD1 VDD1 VDD1 VDD1 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 C2P C2P C2P C1P C1P C1P C2M C2M C2M C1M C1M C1M C5M C5M C5M
X
2264.0 2354.0 2444.0 2534.0 2624.0 2714.0 2804.0 2894.0 2984.0 3074.0 3164.0 3254.0 3344.0 3434.0 3524.0 3614.0 3704.0 3794.0 3884.0 3974.0 4064.0 4154.0 4244.0 4334.0 4424.0 4514.0 4604.0 4694.0 4784.0 4874.0 4964.0 5054.0 5144.0 5234.0 5324.0 5414.0 5504.0 5594.0 5684.0 5774.0 5864.0 5954.0 6044.0 6134.0 6224.0 6314.0 6404.0 6494.0 6584.0 6674.0
Y
-680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0
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Table 9.3.3
No
201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250
Name
VOUTL VOUTL VOUTL VLR VLR VLR VLR DUMMY VXL2 VXL2 VXL2 VXL2 VXL1 VXL1 VXL1 VXL1 VC VC VC VC VXH1 VXH1 VXH1 VXH1 VXH2 VXH2 VXH2 VXH2 VH VH VH VH C5P C5P C5P C5P DUMMY DUMMY DUMMY COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10
X
6764.0 6854.0 6944.0 7034.0 7124.0 7214.0 7304.0 7394.0 7484.0 7574.0 7664.0 7754.0 7844.0 7934.0 8024.0 8114.0 8204.0 8294.0 8384.0 8474.0 8564.0 8654.0 8744.0 8834.0 8924.0 9014.0 9104.0 9194.0 9284.0 9374.0 9464.0 9554.0 9644.0 9734.0 9824.0 9914.0 10004.0 10094.0 10100.0 10100.0 10100.0 10100.0 10100.0 10100.0 10100.0 10100.0 10100.0 10100.0 10100.0 10100.0
Y
-680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -680.0 -602.0 -561.0 -520.0 -479.0 -438.0 -397.0 -356.0 -315.0 -274.0 -233.0 -192.0 -151.0
No
251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300
Name
COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 DUMMY DUMMY DUMMY COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57
X
10100.0 10100.0 10100.0 10100.0 10100.0 10100.0 10100.0 10100.0 10100.0 10100.0 10100.0 10100.0 10100.0 10100.0 10100.0 10106.5 10065.5 10024.5 9983.5 9942.5 9901.5 9860.5 9819.5 9778.5 9737.5 9696.5 9655.5 9614.5 9573.5 9532.5 9491.5 9450.5 9409.5 9368.5 9327.5 9286.5 9245.5 9204.5 9163.5 9122.5 9081.5 9040.5 8999.5 8958.5 8917.5 8876.5 8835.5 8794.5 8753.5 8712.5
Y
-110.0 -69.0 -28.0 13.0 54.0 95.0 136.0 177.0 218.0 259.0 300.0 341.0 382.0 423.0 464.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0
LEADIS Technology
CONFIDENTIAL
158
LDS176
Version 0.10
Table 9.3.4
No
301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350
Name
COM58 COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66 COM67 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33
X
8671.5 8630.5 8589.5 8548.5 8507.5 8466.5 8425.5 8384.5 8343.5 8302.5 8261.5 8220.5 8179.5 8138.5 8097.5 8056.5 8015.5 7974.5 7933.5 7892.5 7851.5 7810.5 7769.5 7728.5 7687.5 7646.5 7605.5 7564.5 7523.5 7482.5 7441.5 7400.5 7359.5 7318.5 7277.5 7236.5 7195.5 7154.5 7113.5 7072.5 7031.5 6990.5 6949.5 6908.5 6867.5 6826.5 6785.5 6744.5 6703.5 6662.5
Y
645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0
No
351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400
Name
SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83
X
6621.5 6580.5 6539.5 6498.5 6457.5 6416.5 6375.5 6334.5 6293.5 6252.5 6211.5 6170.5 6129.5 6088.5 6047.5 6006.5 5965.5 5924.5 5883.5 5842.5 5801.5 5760.5 5719.5 5678.5 5637.5 5596.5 5555.5 5514.5 5473.5 5432.5 5391.5 5350.5 5309.5 5268.5 5227.5 5186.5 5145.5 5104.5 5063.5 5022.5 4981.5 4940.5 4899.5 4858.5 4817.5 4776.5 4735.5 4694.5 4653.5 4612.5
Y
645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0
LEADIS Technology
CONFIDENTIAL
159
LDS176
Version 0.10
Table 9.3.5
No
401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450
Name
X
4571.5 4530.5 4489.5 4448.5 4407.5 4366.5 4325.5 4284.5 4243.5 4202.5 4161.5 4120.5 4079.5 4038.5 3997.5 3956.5 3915.5 3874.5 3833.5 3792.5 3751.5 3710.5 3669.5 3628.5 3587.5 3546.5 3505.5 3464.5 3423.5 3382.5 3341.5 3300.5 3259.5 3218.5 3177.5 3136.5 3095.5 3054.5 3013.5 2972.5 2931.5 2890.5 2849.5 2808.5 2767.5 2726.5 2685.5 2644.5 2603.5 2562.5
Y
645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0
No
451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500
Name
X
2521.5 2480.5 2439.5 2398.5 2357.5 2316.5 2275.5 2234.5 2193.5 2152.5 2111.5 2070.5 2029.5 1988.5 1947.5 1906.5 1865.5 1824.5 1783.5 1742.5 1701.5 1660.5 1619.5 1578.5 1537.5 1496.5 1455.5 1414.5 1373.5 1332.5 1291.5 1250.5 1209.5 1168.5 1127.5 1086.5 1045.5 1004.5 963.5 922.5 881.5 840.5 799.5 758.5 717.5 676.5 635.5 594.5 553.5 512.5
Y
645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0
LEADIS Technology
CONFIDENTIAL
160
LDS176
Version 0.10
Table 9.3.6
No
501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550
Name
X
471.5 430.5 389.5 348.5 307.5 266.5 225.5 184.5 143.5 102.5 61.5 20.5 -20.5 -61.5 -102.5 -143.5 -184.5 -225.5 -266.5 -307.5 -348.5 -389.5 -430.5 -471.5 -512.5 -553.5 -594.5 -635.5 -676.5 -717.5 -758.5 -799.5 -840.5 -881.5 -922.5 -963.5 -1004.5 -1045.5 -1086.5 -1127.5 -1168.5 -1209.5 -1250.5 -1291.5 -1332.5 -1373.5 -1414.5 -1455.5 -1496.5 -1537.5
Y
645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0
No
551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600
Name
X
-1578.5 -1619.5 -1660.5 -1701.5 -1742.5 -1783.5 -1824.5 -1865.5 -1906.5 -1947.5 -1988.5 -2029.5 -2070.5 -2111.5 -2152.5 -2193.5 -2234.5 -2275.5 -2316.5 -2357.5 -2398.5 -2439.5 -2480.5 -2521.5 -2562.5 -2603.5 -2644.5 -2685.5 -2726.5 -2767.5 -2808.5 -2849.5 -2890.5 -2931.5 -2972.5 -3013.5 -3054.5 -3095.5 -3136.5 -3177.5 -3218.5 -3259.5 -3300.5 -3341.5 -3382.5 -3423.5 -3464.5 -3505.5 -3546.5 -3587.5
Y
645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0
LEADIS Technology
CONFIDENTIAL
161
LDS176
Version 0.10
Table 9.3.7
No
601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650
Name
X
-3628.5 -3669.5 -3710.5 -3751.5 -3792.5 -3833.5 -3874.5 -3915.5 -3956.5 -3997.5 -4038.5 -4079.5 -4120.5 -4161.5 -4202.5 -4243.5 -4284.5 -4325.5 -4366.5 -4407.5 -4448.5 -4489.5 -4530.5 -4571.5 -4612.5 -4653.5 -4694.5 -4735.5 -4776.5 -4817.5 -4858.5 -4899.5 -4940.5 -4981.5 -5022.5 -5063.5 -5104.5 -5145.5 -5186.5 -5227.5 -5268.5 -5309.5 -5350.5 -5391.5 -5432.5 -5473.5 -5514.5 -5555.5 -5596.5 -5637.5
Y
645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0
No
651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700
Name
X
-5678.5 -5719.5 -5760.5 -5801.5 -5842.5 -5883.5 -5924.5 -5965.5 -6006.5 -6047.5 -6088.5 -6129.5 -6170.5 -6211.5 -6252.5 -6293.5 -6334.5 -6375.5 -6416.5 -6457.5 -6498.5 -6539.5 -6580.5 -6621.5 -6662.5 -6703.5 -6744.5 -6785.5 -6826.5 -6867.5 -6908.5 -6949.5 -6990.5 -7031.5 -7072.5 -7113.5 -7154.5 -7195.5 -7236.5 -7277.5 -7318.5 -7359.5 -7400.5 -7441.5 -7482.5 -7523.5 -7564.5 -7605.5 -7646.5 -7687.5
Y
645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0
LEADIS Technology
CONFIDENTIAL
162
LDS176
Version 0.10
Table 9.3.8
No
701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750
Name
SEG384 SEG385 SEG386 SEG387 SEG388 SEG389 SEG390 SEG391 SEG392 SEG393 SEG394 SEG395 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY COM131 COM130 COM129 COM128 COM127 COM126 COM125 COM124 COM123 COM122 COM121 COM120 COM119 COM118 COM117 COM116 COM115 COM114 COM113 COM112 COM111 COM110 COM109 COM108 COM107 COM106 COM105 COM104 COM103 COM102 COM101 COM100
X
-7728.5 -7769.5 -7810.5 -7851.5 -7892.5 -7933.5 -7974.5 -8015.5 -8056.5 -8097.5 -8138.5 -8179.5 -8220.5 -8261.5 -8302.5 -8343.5 -8384.5 -8425.5 -8466.5 -8507.5 -8548.5 -8589.5 -8630.5 -8671.5 -8712.5 -8753.5 -8794.5 -8835.5 -8876.5 -8917.5 -8958.5 -8999.5 -9040.5 -9081.5 -9122.5 -9163.5 -9204.5 -9245.5 -9286.5 -9327.5 -9368.5 -9409.5 -9450.5 -9491.5 -9532.5 -9573.5 -9614.5 -9655.5 -9696.5 -9737.5
Y
645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0
No
751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786
Name
COM99 COM98 COM97 COM96 COM95 COM94 COM93 DUMMY DUMMY DUMMY COM92 COM91 COM90 COM89 COM88 COM87 COM86 COM85 COM84 COM83 COM82 COM81 COM80 COM79 COM78 COM77 COM76 COM75 COM74 COM73 COM72 COM71 COM70 COM69 COM68 DUMMY
X
-9778.5 -9819.5 -9860.5 -9901.5 -9942.5 -9983.5 -10024.5 -10065.5 -10106.5 -10100.0 -10100.0 -10100.0 -10100.0 -10100.0 -10100.0 -10100.0 -10100.0 -10100.0 -10100.0 -10100.0 -10100.0 -10100.0 -10100.0 -10100.0 -10100.0 -10100.0 -10100.0 -10100.0 -10100.0 -10100.0 -10100.0 -10100.0 -10100.0 -10100.0 -10100.0 -10100.0
Y
645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 645.0 464.0 423.0 382.0 341.0 300.0 259.0 218.0 177.0 136.0 95.0 54.0 13.0 -28.0 -69.0 -110.0 -151.0 -192.0 -233.0 -274.0 -315.0 -356.0 -397.0 -438.0 -479.0 -520.0 -561.0 -602.0
KEY_L KEY_R
-9793.0 9793.0
338.0 338.0
LEADIS Technology
CONFIDENTIAL
163

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LDS176

Feb. 15, 2005

132 x 132 (RGB), 4k-Color STN Driver

MPU INTERFACE ........................................................................................................................................ 5

Display Module Data Transfer Modes ............................................................................................................. 15

DISPLAY DATA RAM (DDRAM)................................................................................................................16

Tearing Effect Output Line............................................................................................................................... 28

Colour Depth Conversion Look Up Tables ...................................................................................................... 30

5.3 5.4 5.5 5.6 5.7

132 x 132 (RGB), 4k-Color STN Driver

SEGMENT DRIVER ...................................................................................................................................31 BLOCK COUNTER ....................................................................................................................................31

5.10 COMMON DRIVER ....................................................................................................................................31 5.11 LCD POWER GENERATION CIRCUIT.....................................................................................................32

5.12 POWER ON/OFF SEQUENCE..................................................................................................................42

INSTRUCTION CODE 0 (ISS=0, MESSI-8) ..............................................................................................45

132 x 132 (RGB), 4k-Color STN Driver

INSTRUCTION CODE 1 (ISS=1).............................................................................................................112

132 x 132 (RGB), 4k-Color STN Driver

6.2.5 6.2.6 6.2.7 6.2.8 6.2.9

132 x 132 (RGB), 4k-Color STN Driver

RESET TABLE (DEFAULT VALUE) ........................................................................................................131

INSTRUCTION SETUP FLOW ................................................................................................................133

CONNECTIONS WITH LCD PANEL .......................................................................................................151

CHIP OVERVIEW ....................................................................................................................................152 BUMP INFORMATION.............................................................................................................................154

132 x 132 (RGB), 4k-Color STN Driver

132 x 132 (RGB), 4k-Color STN Driver

Document No: LTT176DS-010

Prepared by: Ted Park

132 x 132 (RGB), 4k-Color STN Driver

132 x 132 (RGB), 4k-Color STN Driver

LCD Panel (4k-Color)

C0 - - - - - C131 VH VXH2 VXH1 VC VXL1 VXL2 VL FPC

396 Segment Drivers

132 Common Drivers

Column Address Counter RAM Data Generator (LUT) Gray Control

System Clock Generator

MPU I/F & Data Latch

132 x 132 (RGB), 4k-Color STN Driver

132 x 132 (RGB), 4k-Color STN Driver

Pin Description (continued)

Name Type Host interface pins ISS I PS0, PS1 I !RES I

!RD (E) TE D7 to D0(SDA) Mode Select

132 x 132 (RGB), 4k-Color STN Driver

5.1 MPU INTERFACE

Interface Type Selection

S: Start data tranamission P: Stop data tranamission TB: tranamission byte

Command1 code is interrupped by command2

Write interrupt sequence

132 x 132 (RGB), 4k-Color STN Driver

8080-Series Parallel Interface (PS0 = "High", PS1="High")

CMD: Write command code PA: Write parameter or RAM data

8080-Series parallel bus protocol, write to register or display RAM

132 x 132 (RGB), 4k-Color STN Driver

Read display RAM data

8080-Series parallel bus protocol, read from register

132 x 132 (RGB), 4k-Color STN Driver

6800-Series Parallel Interface (PS0 = "Low", PS1="Low")

CMD: Write command code PA: Write parameter or RAM data

6800-Series parallel bus protocol, write to register or display RAM

132 x 132 (RGB), 4k-Color STN Driver

Read display RAM data

6800-Series parallel bus protocol, read from register

132 x 132 (RGB), 4k-Color STN Driver