National Semiconductor

June 16, 2010 Rev 1.0

ADC16DV160HFEB Evaluation Board Users Guide

ADC16DV160 Dual 16-Bit, 160 MSPS A/D Converter

2009 National Semiconductor Corporation.

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Table of Contents
1.0 Introduction ......................................................................................................................................... 3 2.0 Board Assembly................................................................................................................................... 3 3.0 Quick Start ........................................................................................................................................... 4 4.0 Functional Description......................................................................................................................... 4 4.1 Analog Input .......................................................................................................................... 4 4.2 ADC reference circuitry ........................................................................................................ 4 4.3 ADC clock circuit .................................................................................................................. 5 4.4 Power Supply Connections .................................................................................................... 5 5.0 Installing the ADC16DV160 Evaluation Board .................................................................................. 5 6.0 Hardware Schematic ............................................................................................................................ 6 7.0 Evaluation Board Layout ..................................................................................................................... 7 8.0 Evaluation Board Bill of Materials ...................................................................................................... 10

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1.0 Introduction
This Evaluation Board may be used to evaluate the ADC16DV160. The ADC is a dual 16 bit analog to digital converters that provides data at rates of up to 160 MHz. The evaluation board is designed to be used with the WaveVision5 Data Capture Board which is connected to a personal computer through a USB port and running WaveVision5 software, operating under Microsoft Windows. The software can perform an FFT on the captured data upon command and, in addition to a frequency domain plot, shows dynamic performance in
J2 Input I

the form of SNR, SINAD, THD SFDR and ENOB. The latest WaveVision software is available through the National Semiconductor website: http://www.national.com/analog/adc/wavevision5

2.0 Board Assembly

The ADC16DV160 Evaluation Board comes preassembled. Refer to the Bill of Materials in Section 8 for a description of components, to Figure 1 for major component placement and to Section 6 for the Evaluation Board schematic.

U2 ADC16DV160

P3 1.8V

P2 1.8V

Wavevision Connector

J4 Clock Input

J3 Input Q

P1 3.0V

P4 3.0V

Figure 1. Major Component Locations

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Figure 2: Test Set Up

3.0 Quick Start Refer to Figure 1 for locations of jumpers, test points and major components. Refer to Figure 2 for the test set up. The latest WaveVision software is available through the National Semiconductor website: http://www.national.com/analog/adc/wavevision5. If a software CD is included with the evaluation board kit, then use the provided software and instructions to install WaveVision and ensure compatibility with this evaluation board. 1. Apply power to the WaveVision5 board and connect it to the computer using a USB cable. See the WaveVision5 User Guide for operation of that board. Connect the evaluation board to the WaveVision5 Data Capture Board. NOTE: power to the WaveVision5 Data Capture Board should be applied before power to the ADC16DV160 Evaluation Board to insure that the FPGA on the WaveVision5 Data Capture Board is not damaged. Connect a clean +3.0V power supply to Power Connectors P1 and P4. Connect a clean +1.8V power supply to Power Connectors P2 and P3. Connect a 160 MHz signal from a 50-Ohm source to connector J4 for the input Clock. Be sure to use a
4

4.

5.

bandpass filter before the Evaluation Board. Set the amplitude to 18 dBm. Connect a signal from a 50-Ohm source to connector J2 (I Channel) or J3 (Q-Channel). Be sure to use a bandpass filter before the Evaluation Board. For best results, also attach a 3dB 50 ohm attenuator right at the input SMA of the eval board. This will help match the impedance between the cables/signal source to the eval board input. Adjust the input signal amplitude as needed to ensure that the signal does not over-range by examinining a histogram of the output data with the WaveVision software.

4.0 Functional Description

The ADC16DV160 Evaluation Board schematic is shown in Section 6. A list of test points and jumper settings can be found in the Appendix. 4.1 Analog Input To obtain the best distortion results the analog input network must be optimized for the signal frequency being applied. The ADC16DV160 Evaluation Board comes configured for input frequencies greater than 70MHz. To accurately evaluate the dynamic performance of this converter, the input test signal will have to be passed through a high-quality bandpass filter. 4.2 ADC reference circuitry
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2.

3.

This Evaluation Board is configured to use the internal reference.

4.3 ADC clock circuit Care must be taken to provide a high quality low jitter clock source. The board is configured to accept a single ended sinusoidal. It converts the sine wave to a differential signal through transformer T4. Refer to the schematic for more detail. 4.4 Power Supply Connections Power is applied to the board through power connectors P1 P4. Care must be taken to observe the correct polarity.

5.0 Installing the ADC16DV160 Evaluation Board

The evaluation board requires a dual power supplies as described in Section 4.4. NOTE: power to the WaveVision5 Data Capture Board should be applied before power to the ADC16DV160 Evaluation Board to insure that the FPGA on the WaveVision5 Data Capture Board is not damaged. A low noise sinusoidal signal source should be connected to the Clock Input SMA connector J4. An appropriate signal source should be connected to the Signal Input SMA connector J2. When evaluating dynamic performance, an appropriate signal generator (such as R&S SMA-100A) with 50 Ohm source impedance should be connected to the Analog Input connector through an appropriate bandpass filter as even the best signal generator available can not produce a signal pure enough to evaluate the dynamic performance of an ADC. If this board is used in conjunction with the the WaveVision5 Data Capture Board and WaveVision5 software, a USB cable must be connected between the Data Capture Board and the host. See the WaveVision5 Data Capture Board manual for details.

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6.0 Hardware Schematic

VAD3.0 C9 1 1 1 1 1 1 C10 T1 BD0205F5050A00 2 J2 INPUT_I 5 4 3 2 R34 0 1 C88 1 2 0.1u 2 2 0.1u 8 7 1 6 2 R45 DNP GND4 GND5 R7 2 24.9 1 C92 1 2 0.1u C38 2 10uF 1 2 1 1 2 C13 10p R10 0 R21 10 1 2 VDR1.8 1 C3 0.1u R38 0 VA1.8 C34 VRPI C62 1 2 0.1u C63 1 TP21 1 1 + 10uF 1 1 1 C66 0.1u 2 2 C65 0.1u C75 0.1u 2 2 2 0.1u C64 2 1 1TP3 TP41 1 1 + 10uF 1 C74 0.1u VA3.0 2 C78 10uF C79 2 2 C83 1 1 1u C93 C47 0.1u 1 4 5 2 0.1u 1 1 1 1 0.1u + 1 1 1 C15 0.1u C16 0.01u VRNI VRPI VRPQ VRNQ 1 1 VRNI VRPQ C73 2 0.1u C71 2 0.1u C72 2 1 1TP5 1 C59 0.1u 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 VA3.0 VRNQ 2 2 C82 1 1 1 1 1 1 1u 2 C12 0.1u 2 C14 0.01u 0.1u 1 RN1 1 C4 0.01u C30 0.1u 2 C23 1 1 0.1u R3 0 9 1 GND9 R5 24.9 2 C7 10p 2 2 GND2 R35 0 1 1 C11 0.01u C19 0.1u C20 0.01u C36 0.1u C40 0.01u 1 0.1u 8 U3 1 2 3 6 7 A0 A1 A2 SCL WP

VCC

SDA

GND10

C17 1 1 1 0.1u R6 49.9 DNP 2 1 2 2

L1 2 DNP R36 DNP 2 1

VAD3.0

24C02-SO8

UNBALANCED NC GND/DIFF_IN

BALANCED_PORT_2 DC_BIAS/NC BALANCED_PORT_1

2 C89 DNP 3

1 2

GND

10

R37 DNP

C21 22p 2

VA3.0 1 C1 0.1u 1 C2 0.01u

GND2 SDA SCL VCC VAD3.0

+5V J1 A24 B24 C24 D24 A23 B23 C23 D23 A22 B22 C22 D22 A21 B21 C21 D21 A20 B20 C20 D20 A19 B19 C19 D19 A18 B18 C18 D18 A17 B17 C17 D17 A16 B16 C16 D16 A15 B15 C15 D15 A14 B14 C14 D14 A13 B13 C13 D13 A12 B12 C12 D12 A11 B11 C11 D11 A10 B10 C10 D10 A9 B9 C9 D9 A8 B8 C8 D8 A7 B7 C7 D7 A6 B6 C6 D6 A5 B5 C5 D5 A4 B4 C4 D4 A3 B3 C3 D3 A2 B2 C2 D2 A1 B1 C1 D1 A24 B24 C24 D24 A23 B23 C23 D23 A22 B22 C22 D22 A21 B21 C21 D21 A20 B20 C20 D20 A19 B19 C19 D19 A18 B18 C18 D18 A17 B17 C17 D17 A16 B16 C16 D16 A15 B15 C15 D15 A14 B14 C14 D14 A13 B13 C13 D13 A12 B12 C12 D12 A11 B11 C11 D11 A10 B10 C10 D10 A9 B9 C9 D9 A8 B8 C8 D8 A7 B7 C7 D7 A6 B6 C6 D6 A5 B5 C5 D5 A4 B4 C4 D4 A3 B3 C3 D3 A2 B2 C2 D2 A1 B1 C1 D1

C41 0.1u

C43 0.01u

C46 0.1u

C68 0.01u

C69 0.1u

C70 0.01u

C90 DNP

C91 DNP

GND2 2 U4 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 2 4 6 8 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

C24 0.1u

1 3 5 C86 0.1u C6 0.1u C84 0.1u C8 0.01u 7

2 4 6 8

RN_753-08

68_AGND VIN-I VIN+I 65_AGND 64_VA3.0 DRGND VDR1.8 D0/1-I DO/1+I D2/3-I D2/3+I D4/5-I D4/5+I D6/7-I D6/7+I D8/9-I D8/9+I

D14/15 JP1 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 1 2 1 2 1 3 5 7 RN_753-08 RN2

VBB GND2 EN34 RIN8RIN8+ RIN7+ RIN7RIN6RIN6+ R1N5+ RIN5EN VCC1 RIN4RIN4+ RIN3+ RIN3RIN2RIN2+ RIN1+ RIN1EN12 GND1 GND

VCC2 VCC3 EN56 DOUT8DOUT8+ DOUT7+ DOUT7DOUT6DOUT6+ DOUT5+ DOUT5GND3 GND4 DOUT4DOUT4+ DOUT3+ DOUT3DOUT2DOUT2+ DOUT1+ DOUT1EN78 VCC4 VCC5

R9 0

GND69 GND70

AGND_18 VIN-Q VIN+Q AGND_21 VA3.0_22 SCLK SDI CLKCLK+ CSB D0/1+Q D0/1-Q D2/3+Q D2/3-Q D4/5+Q D4/5-Q D6/7+Q

D0/1-I D0/1+I D2/3-I D2/3+I D4/5-I D4/5+I D6/7-I D6/7+I

D8/9-I D8/9+I D10/11-I D10/11+I D12/13-I D12/13+I D14/15-I D14/15+I OUTCLK+ OUTCLKD14/15-Q D14/15+Q

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

VA1.8_1 VRMI AGND_3 VA3.0_4 VRNI VRNI_6 VRPI VRPI_8 VREF VRPQ VRPQ_11 VRNQ VRNQ_13 VA3.0_14 AGND VRMQ VA1.8_17

U2 ADC16DV160

D10/11-I D10/11+I D12/13-I D12/13+I D14/15-I D14/15+I OUTCLKOUTCLK+ D14/15-Q D14/15+Q D12/13-Q D12/13+Q D10/11-Q D10/11+Q D8/9-Q D8/9+Q D6/7-Q

FIN1108MTD

GND2

R33 1

100 2 8 7 6 5

VAD3.0

GND4

GND5

1 2

1 2

R22 10 2 2 8 7 6 1 R44 DNP 2 2

C94 DNP

C95 DNP

U6 1 RIN+ 2 RINVCC 3 GND DOUT+ 4 EN GND1 DOUTFIN1101K8X 1 1 2 C67 GND2 2 0.1u

U5 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VBB GND2 EN34 RIN8RIN8+ RIN7+ RIN7RIN6RIN6+ R1N5+ RIN5EN VCC1 RIN4RIN4+ RIN3+ RIN3RIN2RIN2+ RIN1+ RIN1EN12 GND1 GND VCC2 VCC3 EN56 DOUT8DOUT8+ DOUT7+ DOUT7DOUT6DOUT6+ DOUT5+ DOUT5GND3 GND4 DOUT4DOUT4+ DOUT3+ DOUT3DOUT2DOUT2+ DOUT1+ DOUT1EN78 VCC4 VCC5 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 D12/13-Q D12/13+Q D10/11-Q D10/11+Q D8/9-Q D8/9+Q

R13 24.9 2

C52 10p VA1.8 2 C33 1 1 1 C87 22p 0.1u C25 0.1u C85 0.1u 1

18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

GND10

C58 0.1u 2

DNP 1 0 R41

GND9

R18 24.9 1

5 4 3

R20 49.9 DNP 1 1 1

2 1

UNBALANCED

BALANCED_PORT_1

L2

NC

DC_BIAS/NC

C26 0.01u

OUTCLK JP2

1 2

R39 DNP

3 R40 DNP

GND/DIFF_IN

BALANCED_PORT_2

69 70

VAD3.0

10

INPUT_Q J3

C96 DNP

C53 10p 1 1 R25 0 2 1 R43 0 2

1 R42 0 2 3 5 7

RN3

2 4 6 8

T2 BD0205F5050A00

C97 1 2 0.1u 1 1

D6/7-Q D6/7+Q D4/5-Q D4/5+Q

D2/3-Q D2/3+Q D0/1-Q D0/1+Q CSB VAD3.0

C56 0.1u 2 2

C31 0.1u

C27 0.1u

RN_753-08 C29 0.01u

C28 0.1u 1 2 3 J4 CLK_DIFF 5 4 1 3 2 C32 1 0.1u 2 1 6 ADT1_1WT 1 C37 0.1u 1 1TP1 TestPoint 1 R12 0 2 C35 33p 2 T4 4 5 2 1 R14 0 2 R31 100 1 1 2

VA3.0 1 3 5 7 1 2 RN4 2 4 6 8 RN_753-08 D0/1 CSB SDIO VA3.0 P1 VA3.0 GND_1 VA3.0 P3 VDR1.8 GND_3 VDR 1 1 1 2 C48 10uF 2 + 2 C49 0.1u P2 VA1.8 GND_2 VA1.8 VAD3.0 1 1 1 2 C60 10uF 2 + 2 C61 0.1u P4 VAD3.0 GND_4 VAD3.0 GND2 1 1 1 2 C54 10uF 2 + 2 C55 0.1u 1 GND2_TP1 1 GND2_TP2 1 1 1 2 C50 10uF 2 + 2 C51 0.1u GND_TP2 GND_TP3 GND_TP1 1 1 1 1 1 1 1 1 GND_TP4 VA1.8 SCLK VDR1.8 C81 2 1 0.1u 1 2 3 4 5 6 7 8 9 10 11 12 U8 VCCA VCCB1 DIR VCCB2 A1 OE A2 B1 A3 B2 A4 B3 A5 B4 A6 B5 A7 B6 A8 B7 GND1 B8 GND2 GND3 SN74AVC8T245 GND2 24 23 22 21 20 19 18 17 16 15 14 13 VAD3.0 C80 1 2 GND2 C76 0.1u 1

FIN1108MTD

VDR1.8 1 C77 0.1u

SDIO

U7 1 2 3 4 5 6 7 8 9 10 11 12 VCCA VCCB1 DIR VCCB2 A1 OE A2 B1 A3 B2 A4 B3 A5 B4 A6 B5 A7 B6 A8 B7 GND1 B8 GND2 GND3 SN74AVC8T245 24 23 22 21 20 19 18 17 16 15 14 13

GND2 SCLK

CLKCLK+

DIR

Connector Future Bus Header96

JP3

1 2

GND2

+3.3V GND2 SDIO

0.1u

VDR1.8

National Semiconductor
Title

ADC16DV160HFEB Evaluation Board

Size C Date: Document Number Wednesday, May 19, 2010 Sheet 1 of 1 Rev 1

GND2

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7.0 Evaluation Board Layout

Layer 1: Component Side

Layer 2: Ground

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Layer 3: Power

Layer 4: Ground, Clock

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Layer 5: Ground

Layer 6: Circuit Side

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8.0 Evaluation Board Bill of Materials

Item Quantity Reference ______________________________________________ 1 2 3 4 5 11 13 4 12 30 C1,C3,C6,C12,C15,C25,C27, C34,C79,C86,C87 C2,C4,C8,C11,C14,C16,C20, C26,C29,C40,C43,C68,C70 C7,C13,C52,C53 C9,C17,C23,C28,C31,C32, C37,C49,C51,C55,C58,C61 C10,C19,C24,C30,C36,C41, C46,C47,C56,C59,C62,C63, C65,C66,C67,C69,C71,C73, C74,C75,C76,C77,C80,C81, C84,C85,C88,C92,C93,C97 C21,C33 C35 C38,C64,C72,C78 C48,C50,C54,C60 C82,C83 GND_TP1,GND_TP2,GND_TP3, GND_TP4,GND2_TP1, GND2_TP2 J1 J2 J3 J4 P1 P2 P3 P4 RN1,RN2,RN3,RN4 R3,R9,R10,R25,R34,R35, R38,R41,R42,R43 R5,R7,R13,R18 R12,R14 R21,R22 R31,R33 T1,T2 T4 U2 U3 U4,U5 U6 U7,U8 Part Manufacturer Manufacturer P/N

0.1u 0.01u 10p 0.1u 0.1u

Murata Murata Murata Murata Murata

GRM033R60J104KE19D GRM155R71H103KA88D GRM1555C1H100JZ01D GRM188R71C104KA01D GRM155R61A104KA01D

6 7 8 9 10 13

2 1 4 4 2 6

22p 33p 10uF 10uF 1u TestPoint

Murata Murata Nichicon AVX Panasonic Keystone

GRM1555C1H220JZ01D GRM1555C1H330JZ01D F931A106MAA TAJC106K020R ECY-29RA105KV 5002

17 18 19 20 22 23 24 25 26 27 28 30 31 32 37 38 39 40 41 42 43

1 1 1 1 1 1 1 1 4 10 4 2 2 2 2 1 1 1 2 1 2

NSC

Connector Future Bus Header96 INPUT_I INPUT_Q CLK_DIFF VA3.0 VA1.8 VDR VAD3.0 RN_753-08 0 24.9 0 10 100 BD0205F5050A00 ADT1_1WT ADC16DV160 24C02-SO8 FIN1108MTD FIN1101K8X SN74AVC8T245

Tyco Electronics Johnson Johnson Johnson Phoenix Contacts Phoenix Contacts Phoenix Contacts Phoenix Contacts CTS Resistor Yageo Panasonic - ECG Yageo Panasonic - ECG Panasonic - ECG Anaren Mini-Circuits National Semiconductor Atmel Fairchild Fairchild Texas Instuments

5223514-3 142-0701-851 142-0701-851 142-0701-851 1759017 1759017 1759017 1759017 753083101GTR RC0402JR-070RL ERJ-2RKF24R9X RC0603JR-070RL ERJ-3EKF10R0V ERJ-2RKF1000X BD0205F5050A00 ADT1-1WT+ ADC16DV160 AT24HC02BN-SH-B FIN1108MTD FIN1101K8X SN74AVC8T245DGVR

NSC NSC

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BY USING THIS PRODUCT, YOU ARE AGREEING TO BE BOUND BY THE TERMS AND CONDITIONS OF NATIONAL SEMICONDUCTOR'S END USER LICENSE AGREEMENT. DO NOT USE THIS PRODUCT UNTIL YOU HAVE READ AND AGREED TO THE TERMS AND CONDITIONS OF THAT AGREEMENT. IF YOU DO NOT AGREE WITH THEM, CONTACT THE VENDOR WITHIN TEN (10) DAYS OF RECEIPT FOR INSTRUCTIONS ON RETURN OF THE UNUSED PRODUCT FOR A REFUND OF THE PURCHASE PRICE PAID, IF ANY.

The ADC16DV160 Evaluation Boards are intended for product evaluation purposes only and are not intended for resale to end consumers, is not authorized for such use and is not designed for compliance with European EMC Directive 89/336/EEC, or for compliance with any other electromagnetic compatibility requirements. National Semiconductor Corporation does not assume any responsibility for use of any circuitry or software supplied or described. No circuit patent licenses are implied. LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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National does not assume any responsibility for any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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