Clock Gating

Assignment #2 , ELEC6016 Digital Systems Synthesis

Manraj Singh Gujral, msg1g10

ELEC 6016 Digital Systems Synthesis Assignment #2 Clock Gating

Table of Contents
Introduction ................................................................................................................................................................. 2 Specifications & Design ................................................................................................................................................ 2 Simulations & Analysis ................................................................................................................................................. 4 Simulations ............................................................................................................................................................... 4 Simulation Analysis .................................................................................................................................................. 5 Synthesis................................................................................................................................................................... 5 Synthesis Analysis..................................................................................................................................................... 9 Observations & Conclusion ........................................................................................................................................ 10 Appendix .................................................................................................................................................................... 11 Simulation Reports ................................................................................................................................................. 11 Report for un-Clock gated Model....................................................................................................................... 11 Report for Clock gated Model- with nReset driving enables =0 (LOW) ............................................................. 12 Report for Clock gated Model- with nReset driving enables =1 (HIGH)............................................................. 13 TestBench for ModelSim simulation of the HDL models. ...................................................................................... 14

ELEC 6016 Digital Systems Synthesis Assignment #2 Clock Gating

Introduction
Clock gating is a technique used to reduce the power consumption of a digital system. This exercise shows the result obtained for the same HDL model one with clock gating and one without. The main observations are included in this report. Briefly, Dynamic Power of a digital system is given by:

Where,

VDD Power Supply f Clock Frequency CL Load Capacitance Activity Factor As can be judged by the equation there are many ways to reduce the dynamic power of a system. Clock gating, specifically, aims to reduce the power by reducing the activity factor. By completely switching off the clock the activity factor can be reduced and therefore the dynamic power is lowered. This is an important factor when designing low power systems. Although this technique seems straight forward, there are, however, few constraints that a designer needs to add in order to ensure that the system is efficiently modelled. There is an extra circuit that is added to the circuit logic that implements the clock gating, therefore if a piece of logic uses very few elements those work on clock , then addition of clock gating circuitry might not prove that useful.

Specifications & Design

This exercise asks us to analyse the clockgated and nonclockgated circuits of the same model. The block diagram of the given circuit is shown in figure 1

nready counter

3-bits

(3rd to 5th Counter Value)

wr_en_gen

rd_en_gen

8th to 10th Counter Value

wr_enable data_in (sequential) wr_data

16-bits 16-bits 16-bits 16-bits

rd_enable data_out (sequential) rd_data

16-bits

Fig.1: Block Diagram representation of the required system. Clock and nReset are not shown

The blocks highlighted in grey shade are the write-enable-generator and the read-enable-generator blocks which are required to be developed.

ELEC 6016 Digital Systems Synthesis Assignment #2 Clock Gating The VHDL codes for the two blocks are listed below:

//////////////////////////////////////// //rd_en_gen HDL

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; --------------------------entity rd_en_gen is port( clk : in std_logic; nreset: in std_logic; count_in: in std_logic_vector(3 downto 0); rd_enable : out std_logic ); end entity rd_en_gen; --------------------------

//////////////////////////////////////// //wr_en_gen HDL

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; --------------------------entity wr_en_gen is port( clk : in std_logic; nreset: in std_logic; count_in: in std_logic_vector(3 downto 0); wr_enable : out std_logic ); end entity wr_en_gen; -------------------------architecture wr_en_gen_arch of wr_en_gen is

architecture rd_en_gen_arch of rd_en_gen is

begin process (nreset, clk) is begin if (nreset = '0') then rd_enable <= '1'; elsif (rising_edge(clk)) then if ((count_in > 5) AND (count_in <9)) then rd_enable <= '0'; else rd_enable <= '1'; end if; end if; end process; end rd_en_gen_arch; //////////////////////////////////////////////// end if; end if; end process; end wr_en_gen_arch; //////////////////////////////////////////////// begin process (nreset, clk) is begin if (nreset = '0') then wr_enable <= '1'; elsif (rising_edge(clk)) then if (count_in >= 2 AND count_in <=4) then wr_enable <= '0'; else wr_enable <= '1';

There are 3 models which are analysed in this exercise.

ELEC 6016 Digital Systems Synthesis Assignment #2 Clock Gating 1. Un-Clockgated model: In this model the system as described by the HDL is simulated and then synthesized to find the timing and power analysis. 2. Clockgated model: In this model there are further two sub-models a. Enable HIGH: During nReset from the top module, the enable signals of rd_en_gen block and wr_en_gen block are driven HIGH. Since it is an active low signal the initial/reset condition is set to HIGH logic. i.e., the VHDL code for reset in rd_en_gen , for e.g., will look like :
begin process (nreset, clk) is begin if (nreset = '0') then rd_enable <= '1';

b. Enable LOW: In this model the enable signals of rd_en_gen block and wr_en_gen block are driven LOW, as per the conventional logic. . i.e., the VHDL code for reset in rd_en_gen , for e.g., will look like :
begin process (nreset, clk) is begin if (nreset = '0') then rd_enable <= '0';

We will attempt and see all the three conditions and analyze it for Power and Area factors.

Simulations & Analysis

Simulations
The HDL models are simulated in ModelSim (Linux environment) to check for the specifications. Testbench is attached in the Appendix. Figure 2 shows the waveforms obtained for Enable LOW model and its analysis. 3. Counter switched to 0 after 11

1. DataWrite for Counter Value 3 to 5

4. Enables LOW at nReset

2. Sampled Values reproduced in data_out

Fig.2: Waveform from the VHDL code for Enable LOW model satisfying the specifications

ELEC 6016 Digital Systems Synthesis Assignment #2 Clock Gating 2. Sampled Values reproduced in data_out

4. Enables HIGH at nReset

1. DataWrite for Counter Value 3 to 5

3. Counter switched to 0 after 11

Fig.3: Waveform from the VHDL code for Enable HIGH model satisfying the specifications

Simulation Analysis
1. The Input Data stream is saved at 3 consecutive counter values from 3 to 5. As seen from the Wave form shown in figure 2 & figure 3, input data 9011, 15155, and 13619 are sampled at Count = 3, 4, and 5 respectively. 2. The Sampled values are then available at the top modules output, data_out, during counter value 8, 9 and 10. 3. The counter after reaching 11 restarts from 0 and therefore this cycle continues. 4. The wr_enable and rd_enable are both driven LOW during nReset for enable LOW model and are both driven HIGH for enable HIGH model.

Synthesis
The simulated HDL model was extracted in the dc_shell, for two models one with Clockgating and one without to observe the differences:

Counter Block

wr_en_gen Block

rd_en_gen Block

rd_data Block

wr_data Block

Fig.4: Circuit Diagram for entire model

ELEC 6016 Digital Systems Synthesis Assignment #2 Clock Gating

(b) Fig.5: Circuit Diagram for wr_data. (a) ClockGated wr_data block (Clock gated elements highlighted). (b) UnclockGated rd_data block

(a)

ELEC 6016 Digital Systems Synthesis Assignment #2 Clock Gating

(a)

(b)

Fig.6: Circuit Diagram for rd_data block. (a) ClockGated rd_data block (Clock gated element highlighted). (b) UnclockGated rd_data block

Figure 5 & Figure 6 are for representational purpose only. This helps in analysing the relative sizes of each block which gives us an estimate of the combinational Area size, difference of which can be seen in the table 1 made after recording the Reports. The dotted-line shows the clockgating elements added to the system. Figure 7 presents a zoomed in view of the bottom clockgated element.

ELEC 6016 Digital Systems Synthesis Assignment #2 Clock Gating

Fig.7: Zoomed in view of the Clock Gating element, from figure6 (a)

Fig.8: Clock Gating circuit elements from figure 7

Fig.9: Circuit Diagram for the synthesized wr_en_gen block

Fig.10: Circuit Diagram for the synthesized rd_en_gen block

ELEC 6016 Digital Systems Synthesis Assignment #2 Clock Gating

Synthesis Analysis
Table 1: reported values of clockgated and unclockgated models Category Cell internal Power Switching Power Dynamic Power Leakage Power Total Power ClockGated Enable HIGH 334.5107 nW 129.7042 nW 464.215 nW 25.476 nW 25.94022 W Enable LOW 937.1408 nW 306.41 nW 1.2436 W 25.6095 W 26.8531 W Un-ClockGated 1.4106 W 132.1066 nW 1.5427 W 27.8057 W 29.3484 W

Combinational Non-combinational Total Area

968.25 units2 968.25 units2 3473.645 units2

968.25 units2 2505.362 units2 3473.645 units2

1395.9024 units2 2432.743 units2 3828.645 units2

Form the data available in the Table 1 the Power Reduction in the Clockgated and unclockgated models can be seen. Table 2 to Table 5 present relative differences between the models.
Table 2: Dynamic Power Reduction

ClockGated Dynamic Power (in W ) % reduction Overall % reduction Enable HIGH 0.464215 62.67% 69.91%
Table 3: Total Power Reduction

Enable LOW 1.2436

Un-ClockGated 1.5427 19.39%

ClockGated Total Power (in W ) % reduction Overall % reduction Enable HIGH 25.9402 3.40% 11.61%
Table 4: Combinational Area Reduction

Enable LOW 26.8531

Un-ClockGated 29.3484 8.50%

ClockGated Enable HIGH Combinational Area (units2 ) % reduction Overall % reduction 968.25 0.00% 30.64% Enable LOW 968.25

Un-ClockGated 1395.9024 30.64%

ELEC 6016 Digital Systems Synthesis Assignment #2 Clock Gating

Table 5: Total Area Reduction

ClockGated Enable HIGH 3473.645 0.00% 9.27% Enable LOW 3473.645 Un-ClockGated 3828.645 9.27%

Total Area (units2 ) % reduction Overall % reduction

Observations & Conclusion

This clock gating exercise has resulted in better understanding of the circuit and its behaviour with and without the constraint of clock gating. The main advantage of implementing it is the reduction in dynamic power. 1. In this exercise, the dynamic power reduction is about 69%. A reduction of 69% for bigger circuits would save a lot of power and it extremely suitable for low-power designs. 2. There were a total of 4 Clock gating elements, a Latch and AND gate (figure 8), added to the existing system. This is a small price to pay for a large amount of dynamic power reduction. In this exercise, however, the overall area is also reduced by about 9%. This has been achieved by addition of multiplexers in the combinational logic (Figure 5 & Figure 6). 3. As a designer, addition of 4 extra clockgating elements resulted in dynamic power reduced by in 69% and overall power by 11 %. This is very significant improvement in the performance and especially for Low-power designs.

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ELEC 6016 Digital Systems Synthesis Assignment #2 Clock Gating

Appendix
Simulation Reports
Report for un-Clock gated Model
**************************************** ****************************************

Report : power -analysis_effort high

Design : top Version: C-2009.06-SP4 Date : Sat May 28 16:19:06 2011 ****************************************

Report : area
Design : top Version: C-2009.06-SP4 Date : Sat May 28 16:15:24 2011 **************************************** Library(s) Used:

Library(s) Used: CORE9GPLL (File: /opt/esdcad/designkits/st/st12/v92/CORE9GPLL_SNPS_AVT _4.1/SNPS/bc_1.32V_0C_wc_1.08V_105C/PHS/CORE9GPLL_ Worst.db) CORE9GPLL (File: /opt/esdcad/designkits/st/st12/v92/CORE9GPLL_ SNPS_AVT_4.1/SNPS/bc_1.32V_0C_wc_1.08V_10 5C/PHS/CORE9GPLL_Worst.db) Number of ports: Number of nets: Number of cells: Number of references: 35 89 5 5

Operating Conditions: Worst Library: CORE9GPLL Wire Load Model Mode: top
Design Wire Load Model Library -----------------------------------------------top area_3Kto4K CORE9GPLL

Combinational area: 1395.902437 Noncombinational area: 2432.743233 Net Interconnect area: undefined (Wire load has zero net area) Total cell area: Total area: 3828.645669 undefined

Global Operating Voltage = 1.08 Power-specific unit information : Voltage Units = 1V Capacitance Units = 1.000000pf Time Units = 1ns Dynamic Power Units = 1mW (derived from V,C,T units) Leakage Power Units = 1pW

***** End Of Report *****

Cell Internal Power = 1.4106 uW (91%) Net Switching Power = 132.1066 nW (9%) --------Total Dynamic Power = 1.5427 uW (100%)

Cell Leakage Power

= 27.8057 uW

***** End Of Report *****

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ELEC 6016 Digital Systems Synthesis Assignment #2 Clock Gating

Report for Clock gated Model- with nReset driving enables =0 (LOW)
**************************************** Report : power -analysis_effort high Design : top Version: C-2009.06-SP4 Date : Mon May 30 13:09:58 2011 **************************************** *************************************** Report : area Design : top Version: C-2009.06-SP4 Date : Mon May 30 13:13:11 2011 *************************************** Library(s) Used: Library(s) Used: CORE9GPLL (File: /opt/esdcad/designkits/st/st12/v92/CORE9GPLL_SNPS_AVT _4.1/SNPS/bc_1.32V_0C_wc_1.08V_105C/PHS/CORE9GPLL_ Worst.db) CORE9GPLL (File: /opt/esdcad/designkits/st/st12/v92/CORE9GPLL _SNPS_AVT_4.1/SNPS/bc_1.32V_0C_wc_1.08V_ 105C/PHS/CORE9GPLL_Worst.db) Number of ports: Number of nets: Number of cells: Number of references: 35 89 5 5

Operating Conditions: Worst Library: CORE9GPLL Wire Load Model Mode: top
Design Wire Load Model Library -----------------------------------------------top area_3Kto4K CORE9GPLL

Combinational area: 968.256010 Noncombinational area: 2505.362434 Net Interconnect area: undefined (Wire load has zero net area) Total cell area: Total area: 3473.618444 undefined

Global Operating Voltage = 1.08 Power-specific unit information : Voltage Units = 1V Capacitance Units = 1.000000pf Time Units = 1ns Dynamic Power Units = 1mW (derived from V,C,T units) Leakage Power Units = 1pW

Cell Internal Power = 937.1408 nW (75%) Net Switching Power = 306.4100 nW (25%) --------Total Dynamic Power = 1.2436 uW (100%) Cell Leakage Power = 25.6095 uW

***** End Of Report *****

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ELEC 6016 Digital Systems Synthesis Assignment #2 Clock Gating Report for Clock gated Model- with nReset driving enables =1 (HIGH)
****************************************

Report : power

-analysis_effort high

Design : top Version: C-2009.06-SP4 Date : Tue May 31 10:06:20 2011 ****************************************

**************************************** Report : area Design : top Version: C-2009.06-SP4 Date : Tue May 31 10:06:02 2011 **************************************** Library(s) Used:

Library(s) Used: CORE9GPLL (File: /opt/esdcad/designkits/st/st12/v92/CORE9GPLL_SNPS_AVT _4.1/SNPS/bc_1.32V_0C_wc_1.08V_105C/PHS/CORE9GPLL_ Worst.db) CORE9GPLL (File: /opt/esdcad/designkits/st/st12/v92/CORE9GPLL_ SNPS_AVT_4.1/SNPS/bc_1.32V_0C_wc_1.08V_10 5C/PHS/CORE9GPLL_Worst.db) Number of ports: Number of nets: Number of cells: Number of references: 35 89 5 5

Operating Conditions: Worst Library: CORE9GPLL Wire Load Model Mode: top Design Wire Load Model Library -----------------------------------------------top area_3Kto4K CORE9GPLL

Combinational area: 968.256010 Noncombinational area: 2505.362434 Net Interconnect area: undefined (Wire load has zero net area) Total cell area: Total area: 3473.618444 undefined

Global Operating Voltage = 1.08 Power-specific unit information : Voltage Units = 1V Capacitance Units = 1.000000pf Time Units = 1ns Dynamic Power Units = 1mW (derived from V,C,T units) Leakage Power Units = 1pW

***** End Of Report *****

Cell Internal Power = 334.5107 nW (72%) Net Switching Power = 129.7042 nW (28%) --------Total Dynamic Power = 464.2149 nW (100%) Cell Leakage Power = 25.4760 uW

***** End Of Report *****

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ELEC 6016 Digital Systems Synthesis Assignment #2 Clock Gating

TestBench for ModelSim simulation of the HDL models.

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; entity tb_top is end entity tb_top; architecture tb_top_arch of tb_top is component top is port ( clk : in std_logic; nreset: in std_logic; nready : in std_logic; data_in: in std_logic_vector(15 downto 0); data_out: out std_logic_vector(15 downto 0) ); end component; --------------------------component ports-signal signal signal signal signal begin ---component instantiation---dut: top port map( clk => clk, nreset => nreset, nready => nready, data_in => data_in, data_out => data_out ); clk : std_logic := '1'; nreset : std_logic := '1'; nready : std_logic; data_in : std_logic_vector(15 downto 0):= (others=>'0'); data_out : std_logic_vector(15 downto 0);

--clock generation-clock_gen: process(clk) begin

-- clock generator and one shot clear signal

clk <= not clk after 500 ns;

-- 1000 ns period

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ELEC 6016 Digital Systems Synthesis Assignment #2 Clock Gating

end process clock_gen; wavegen_proc: process begin nreset <= '0'; nready <= '1'; wait for 1000 ns; nreset <= '1'; wait for 1000 ns; nready <= '0'; wait for 1000 ns; --count_in <= "000"; data_in <= "0111001100110011"; wait for 1000 ns; --count_in <= "001"; data_in <= "0001001100110011"; wait for 1000 ns; --count_in <= "010"; data_in <= "0010001100110011"; wait for 1000 ns; --count_in <= "011"; data_in <= "0011101100110011"; wait for 1000 ns; --count_in <= "100"; data_in <= "0011010100110011"; wait for 1000 ns; --count_in <= "101"; data_in <= "0011010000110011"; wait for 1000 ns; --count_in <= "110"; data_in <= "0011001111000011"; wait for 1000 ns; --count_in <= "111"; data_in <= "0011001100101111"; wait for 1000 ns; --count_in <= "000"; data_in <= "0011001100111111"; wait for 1000 ns; --count_in <= "001"; data_in <= "0011101101110011"; wait for 1000 ns; --count_in <= "010"; data_in <= "0111001100110011"; wait for 1000 ns; --count_in <= "011"; data_in <= "0011011100110011"; wait for 1000 ns; --count_in <= "100"; data_in <= "0011101100110011"; wait for 1000 ns; --count_in <= "101"; data_in <= "0011101100110011"; wait for 1000 ns;

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ELEC 6016 Digital Systems Synthesis Assignment #2 Clock Gating

--count_in <= "110"; data_in <= "0011111110110011"; wait for 1000 ns; --count_in <= "111"; data_in <= "0011001110110011"; wait for 1000 ns; --count_in <= "000"; data_in <= "0011001100110011"; wait for 1000 ns; --count_in <= "001"; data_in <= "0011001110110011"; wait for 1000 ns; --count_in <= "010"; data_in <= "0011001101110011"; wait for 1000 ns; --count_in <= "011"; data_in <= "0011001100111011"; wait for 1000 ns; --count_in <= "100"; data_in <= "0011001100110111"; wait for 1000 ns; --count_in <= "101"; data_in <= "0011101110111011"; wait for 1000 ns; --count_in <= "110"; data_in <= "0111011100110011"; wait for 1000 ns; --count_in <= "111"; data_in <= "0011001101110011"; wait for 2000 ns; end process wavegen_proc; end tb_top_arch;

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