321091

High Speed Digit al

Design Principles
January 2009













Whit e Paper
Sat hi sh
Venk at ar amani
Technical Market ing
Engineer
I nt el Corporat ion
High Speed Digit al Design Principles


2 321091
Cont ent s
Background. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Groundwork . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Get Me An Archit ect ! . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Schemat ic - ally Correct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
What s wit h t he Layout ?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
To Be t he Signal or Not To Be t he Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
I ll be back t he Terminat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
ShhhNo Noise Please! . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
The Scope of t he I ssue Debug Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
We Researched I t , We Designed I t , and I t Works! . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

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Back gr ound
All embedded I nt el

archit ect ure product s vary in t heir uses, but t hey have
one t hing in common: t he complexit y of t heir design. From an engineers
perspect ive t here are many new and unfamiliar challenges of get t ing large
amount s of elect rical, elect ronic hardware on generally a smaller piece of
board/ PCB in t he case of embedded design.
This whit e paper discusses some of t he maj or fact ors t hat need t o be
considered in designing an embedded product and t he various high speed
digit al design concept s t hat play a vit al role in t he funct ionalit y of t he
hardware/ product as a whole. This paper will help a designer underst and
why t he elect rical signals act so different ly on a high speed design, ident ify
t he various problems t hat may occur in t he design, and solve t hese problems.
Gr oundw or k
I n t he world of high speed digit al design and archit ect ure t he following
concept s play a maj or role in deciding t he success of a product .
First t he archit ect ure of a syst em forms an import ant part of t he design
equat ion. Next , designers must get t hrough t he schemat ics and layout of t he
design. During t he layout phase t he signal int egrit y fact ors such as
reflect ions, ground bounce, crosst alk, power supply noise and EMI fact ors
such as radiat ion and elect rost at ic discharge need t o be considered before t he
board is built . The guidelines necessary for t he opt imal schemat ic and layout
design of t he board are provided t hrough t he schemat ic and layout checklist s
in t he product Plat form Design Guideline ( here on referred t o as t he PDG) .
For a good design a lot of ground work is done before t he act ual board is
built . This is made up of syst em archit ect ure, schemat ics and layout of t he
design.
Get Me An Ar chi t ect !
The first st ep t owards a good design is t he syst em archit ect ure. Knowing t he
part s t hat make up your complet e syst em and laying t hem out on a board
using comput er aided soft ware will help visualize what t he board will end up
looking like. Be sure t o keep memory, CPU, MCH sect ions separat e from t he
I CH and I O sect ions. This will help creat e a clean design. This first st ep
ensures t hat t he designer will have a plan t o work wit h when doing
schemat ics and layout of devices. Figure 1 shows a sample board which
employs a clean design t echnique.
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Fi gur e 1. Sampl e Cust omer Boar d w i t h a cl ean desi gn


Figure 1 illust rat es a design which employs a good archit ect ure and layout
met hod by following t he product PDG.
Schemat i c - al l y Cor r ect
I t is import ant t o check t he schemat ics against t he guidelines provided for
various high speed busses ( Clock signals, DDR2, DDR3, PCI express et c) and
t o correct t he errors. I t is also imperat ive t hat all t he pull up/ pull down
resist ors are verified for t he value and t he volt ages provided t o t he devices
are checked. Addit ional informat ion on schemat ic design and t he process of
checking schemat ics is available in t he Embedded Design Cent er ( EDC) .
Schemat ics need t o be t horoughly checked since layout is direct ly cascaded
down from t he schemat ics. A small error in t he schemat ic will be harder t o
find in layout . Layout engineers do not check for t he right values; t hey layout
t he schemat ic report s.
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What s w i t h t he Lay out ?
High speed signal principles are put t o use in t he layout st age. This st age
defines how t he copper wires on t he PCB are cut int o t races of st ripline and
microst rip. All t he devices are also placed on t he board eit her on t he t op or
bot t om layer and int erconnect ions are made t hrough an int ensely woven
inner layer of signals.
Layout is anot her st age during t he design where t he principles play a vit al
role. Most of t he principles can be followed in a general manner in t he
archit ect ure and schemat ic st eps, but during layout t he high speed design
principles are used in every signal rout e.
Theor y
Theory: speculat ion, knowledge, met hodologies and mat hemat ical proof
( Source: Wikipedia)
The word t heory describes high speed design principles as t hey have
evolved t hough speculat ion, knowledge, furt hered by mat hemat ical proof and
t hen using syst emat ic st udy and met hodology.
Gordon Moore st at ed I t cant cont inue forever. The nat ure of exponent ials is
t hat you push t hem out and event ually disast er happens . We are seeing
more of t his happening as t he speed is pushed for many digit al int erfaces.
We are looking t o mult iply cores t o make devices use parallel processing
rat her t han brut e force speed. This in t urn has made t he devices more
complicat ed but has not changed t he principles on a syst em design level
drast ically.
That said, t he principles used in high speed digit al design are count less, and
many aut hors have put forward t heir t heories and findings about t he peculiar
way elect rical signals behave as t he frequency of operat ion get s closer t o t he
gigahert z range. The following sect ions will t ry t o shed light on a few of t he
maj or principles used in high speed design.
To Be t he Si gnal or Not To Be t he Si gnal
Signals in high speed design are elect rical in nat ure and consist of current
flowing t hrough t he wires. The following principles of mut ual induct ance,
mut ual capacit ance and crosst alk will affect t he response, qualit y of t he
elect rical signal when it flows t hrough a copper t race ( essent ially a
t ransmission line) .
The schemat ic only shows t he pat h t he signal pat h from a source t o a
dest inat ion. I t hides t he fact t hat when signal flows t here are t wo at t ribut es:
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The current forms loops in circuit . These loops are somet imes simple or can
be complex. Every loop of current has induct ance L associat ed wit h it . A
series induct or passes DC but blocks high frequency noise.
Given a value of L and also given t he frequency f, t hen for a sinusoidal input
t he equat ion t hat governs t hat effect ive impedance magnit ude is given by:
X
l
= 2 * ( pi) * f( frequency) * L ( Source: HSDD 2007 V. 13)
From t he equat ion we see t hat wit h t he increasing frequency of syst ems t he
effect ive impedance of t he given circuit increases. Thus a good high speed
design would need t o provide as lit t le of an induct ance value in t he circuit t o
provide a good signal qualit y.
Figure 2 shows t he effect of current loops causing mut ual induct ance.
Fi gur e 2. Mut ual I nduct ance ( Sour ce: Hi gh Speed Di gi t al Desi gn 2007 V . 13)










Two conduct ors in close proximit y t o each ot her, carrying a signal, share an
elect ric field and t his elect ric field causes an unint ent ional current flow
bet ween t hem. The coupling bet ween t hem act s like a shunt capacit or. A
capacit or blocks DC but passes high frequency signals. Given t he value of C
and frequency f, t hen for a sinusoidal input t he equat ion t hat governs t he
effect ive impedance is given by
X
c =
1 / 2 * pi * f * C ( Source: HSDD 2007 V. 13)
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The equat ion shows t hat t he effect ive capacit ive of t he circuit st art s t o
decrease as t he frequency of t he circuit get s higher. This means t hat
capacit ors st art becoming more like short circuit s at higher frequencies.
Figure 3 shows t he how mut ual capacit ance is creat ed in circuit s of close
proximit y.
Fi gur e 3. Mut ual Capaci t ance ( Sour ce: Hi gh Speed Di gi t al Desi gn 2007 V . 13)








These propert ies can help us find t he effect ive capacit ance or induct ance
present in a circuit due t o mut ual induct ance and capacit ance. These are t he
parasit ic element s involved in a circuit and t hey have t he abilit y t o dest roy a
good frequency response.
I t has already been st at ed t hat current flows in loops, t hese loops form t he
ret urn pat h. The problem wit h high speed digit al design is t hat current
bunches t oget her and forms very t ight loops t hat t ry t o follow t he pat h as
close as possible. Figure 4 shows t his propert y of current .
Fi gur e 4. Cur r ent Loops ( Sour ce: Hi gh Speed Di gi t al Desi gn 2007 V . 13)






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Figure 4 demonst rat es t hat t his poses a serious problem for a designer.
Unless t here is a proper ret urn pat h for high speed signals, t he ret urn current
will flow t hrough a longer ret urn pat h forming a larger loop and t his can
cause signal issues on t he signal and also ot her signals due t o t he mut ual
induct ance caused.
Experience shows t hat for a high speed digit al design t hat uses low
impedance devices and high current s in t he circuit designers need t o be
concerned about mut ual induct ance. A mut ual induct ance can cause eit her a
posit ive or negat ive edge crosst alk on anot her signal based on t he direct ion
of t he loop present and t he durat ion equal t o t he rise t ime of t he aggressive
signal. Mut ual capacit ance, not playing a maj or fact or in t he high speed
designs, generally causes a posit ive edge crosst alk wit h durat ion equal t o t he
rise t ime of t he aggressive signal.
I l l be back t he Ter mi nat i on
The signals on a board are t ransmit t ed using copper t races; t hese are
essent ially t ransmission lines. Charact erist ic impedance is one of t he
propert ies of t ransmission lines.
Charact erist ic impedance is t he rat io of volt age t o current in a t ransmission
line. The inst ant a signal propagat es t he t ransmission line, t he input
impedance of t he PCB t race looks resist ive. The PCB t race impedance is a
value t hat needs special at t ent ion from a designer. I t is difficult t o mat ch t he
load and t he source in complex designs. But in t heory a perfect ly mat ched
t ransmission line will be devoid of any reflect ions from t he far end and
t hereby will not have any reflect ed signal causing an addit ion or subt ract ion
t o t he original signal at t he near end and so on. Reflect ions can cause ringing
of t he signal. I f t he signal has enough t ime t o set t le t o it s final value aft er all
t he reflect ions before t he next t ransit ion t he design will not encount er issues.
I f t he t ime is not adequat e t hen t here might be an error t o t he value t hat is
found due t o t he reflect ions.
Reflect ions on a t ransmission line can be avoided by using t erminat ions t o t he
t ransmission line. The most popular t erminat ions used in t he digit al logic are
eit her end t erminat ion or series t erminat ion. End t erminat ions use a resist or
or split a pair of resist ors which connect t o VCC and ground respect ively wit h
t he line as t he reference point . Figure 5 shows t he end t erminat ion t opology
on a t ransmission line near t he load wit h a split resist or t erminat ion.




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Fi gur e 5. Spl i t Resi st or Ter mi nat i on ( Sour ce: Hi gh Speed Di gi t al Desi gn 2007
V . 13)
The second most common met hod of t erminat ions is t he one used in point t o
point signals. This is t he ser i es t er mi nat i on. A resist or of mat ched value t o
t he impedance of t he line is put in series t o t he source before t he
t ransmission line. The resist or accomplishes t he cancellat ion of reflect ions as
shown in Figure 6.
Fi gur e 6. Ser i es Ter mi nat i on ( Sour ce: Hi gh Speed Di gi t al Desi gn 2007 V . 13)

There are also ot her t ypes of t erminat ions:
1. AC wit h DC balance t erminat ions used wit h clock signals
2. AC wit hout Dc balance t erminat ions
3. Double series t erminat ion
For addit ional informat ion on t erminat ions, refer t o

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e f e r e n c e s .

ShhhNo Noi se Pl ease!
The biggest roadblock for any high speed design is noisy signals. Wit h added
noise comes t he problem of having more errors on a given bus. This
somet imes can be such a huge issue t hat t he syst em design might have t o go
t hrough a layout change t o get it resolved. This can cost a lot of money and
t ime.
As seen previously, t he concept s of mut ual induct ance and capacit ance cause
a maj orit y of t he crosst alk which result s in noise being inj ect ed on t he signal.
A few simple rules keep t he noise from becoming t he nemesis of t he design.
1. Provide ample spacing as required ( or as provided in t he PDG, PCI - sig
specs, Jedec specs) bet ween pairs of high speed signals.
2. Provide ample ground planes t o guarant ee a quick ret urn pat h for t he
high speed signal current s. This avoids t he unwant ed looping effect if
no ground planes are provided.
3. Provide ample st it ching capacit ors ( decoupling) for high speed signals
if t hey cross planes. These provide a ret urn pat h t o t he reference
plane.
4. Use t he right t erminat ion; t his kills t he reflect ions and crosst alk.
5. Avoid having slot s on t he ground plane. This causes unwant ed current
loops t o int eract wit h ot her sensit ive circuit s.
6. Wit h connect or pins make sure t o have enough clear ground cut out s
around t he pins t o provide a ret urn pat h.
7. Use a good st ack up for t he design, alt ernat e signal layers wit h ground
and power planes.
8. Provide a separat e region on your board t o house all t he sensit ive
analog circuit s away from t he high speed digit al circuit s.
The Scope of t he I ssue Debug Techni ques
One can expect t o go t hrough at least t wo revisions of a design before
product ion. Murphys Law st at es t hat What ever can go wrong will go wrong,
and at t he worst possible t ime, in t he worst possible way . Not going t hat far
we can safely assume t hat t here is always a chance t hat errors can occur and
would need t o be debugged in a high speed design. A favorit e t ool in t he lab
t hat any elect rical engineer will swear by is t he oscilloscope.
Many kinds of scopes and probes exist and most of t hem can measure an
elect rical signal. The problem is most engineers assume t hat t he pict ure on
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t he scope is t he way t he signal act ually is behaving. The following t ypes of
probes exist in t he realm of measurement equipment .

1. 10x 10- pF Passi v e Pr obe
The probe works on signals of about 300MHZ. This is t oo slow for most
high speed signals. Figure 7 shows t he int ernals of t his probe.
Fi gur e 7. Passi v e Pr obe ( Sour ce: Hi gh Speed Di gi t al Desi gn 2007 V . 13)

2. FET- I nput Pr obe
The FET amplifier separat es t he input circuit from t he cable effect s.
This probe has higher bandwidt h capabilit y of up t o 6GHz. The t ips do
get warm due t o t he power dissipat ion. Figure 8 shows t he FET
amplifier.
Fi gur e 8. FET- I nput Pr obe ( Sour ce: Hi gh Speed Di gi t al Desi gn 2007 V . 13)

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3. Di f f er ent i al Act i v e Pr obes.
They have high input impedance of almost up t o 250- 300 ohms and
higher bandwidt h.
4. Resi st i v e I nput Pr obes.
These are inexpensive and offer higher bandwidt h as t he different ial
probes. The problem is t his probe works only wit h low impedance circuit s.
A designer/ engineer should research t he t ype of probe t o be used based on
t he t ype of signal. I f a fast signal is measured using a passive probe t he rise
t imes report ed are different compared t o measuring it using t he right
bandwidt h probe.
The equat ion t hat defines a measurement set up is as follows
Tdi spl ay = ( Tpr obe
2
+ Tscope
2
)
1/ 2
For example a 5GHZ probe wit h a 5GHZ scope would yield a syst em capable
of measuring a 3. 5GHZ signal.
We Resear ched I t , We Desi gned I t ,
and I t Wor k s!
This paper is but a short int roduct ion t o t he world of high speed design. I t
at t empt s t o answer some of t he basic quest ions t hat come t o an engineers
mind when designing an embedded I nt el

archit ect ure product using high

speed principles.
For more informat ion on high speed digit al design principles, refer t o t he
publicat ions list ed in

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e f e r e n c e s .
For more informat ion on Embedded product s wit h I nt el

archit ect ure, go t o

t he Embedded Design Cent er ( EDC) webpage.

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Ref er ences
1. High Speed Digit al Design , Two Days of Black Magic wit h Dr. Howard
Johnson, present at ion manual, HSDD 2007 V . 13
2. High Speed Digit al Design: A Handbook of Black Magic, Dr. Howard
Johnson, Prent ice Hall publicat ions
3. High- Speed Digit al Syst em Design: A Handbook of I nt erconnect
Theory and Design Pract ices, St ephen H. Hall,Garret t W. Hall ,James
A. McCall
4. Signal I nt egrit y - Simplified ( Prent ice Hall Modern Semiconduct or
Design Series' Sub Series: PH Signal I nt egrit y Library) ( Hardcover) ,
Eric Bogat in ( aut hor)
5. PCB Design for Real- World EMI Cont rol ( The Springer I nt ernat ional
Series in Engineering and Comput er Science) , Bruce R. Archambeault ,
James Drewniak



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Aut hor s
Sat hish Venkat aramani is a Technical Market ing Engineer wit h
ECG at I nt el Corporat ion.


Acr ony ms/ Key w or ds
AC Alt ernat ing Current
DC Direct Current
FET Field Effect Transist or
Ghz Giga hert z
PDG Plat form Design Guide
pF Pico Farad
VCC Power source
Xl Effect ive induct ance of t he circuit
Xc Effect ive capacit ance of t he circuit
Zo Charact erist ic impedance of t he t ransmission line

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