OUTCOME 2

ELECTRONIC COMPONENT DESIGN PARAMETERS

Design Rules & Failure Modes

Introduction

Integrated circuits: many transistors on one chip. Very Large Scale Integration (VLSI)

What is Design Rules?

Provide a set of guidelines for constructing the various masks needed in the patterning process. Consist of minimum width and minimum spacing constraints and requirement between object on the same or on different layer.

Why need Design Rules?

Represent a compromise between performance and yield Manufacturing processes have inherent limitations in accuracy. Design rules specify geometry of masks which will provide reasonable yields. Design rules are determined by experience. To build functional circuit in as small area as possible

Design Rules?
In 1975 Gordon Moore, cofounder of Intel, predicted that the number of transistors that could be placed on a chip would double every two years [Moore65]. Chip manufacturers have relied on the continued scaling down of the transistor size, but the scaling will soon end. Three obstacles stand in the way: the rising costs of fabrication, the limits of lithography, and the size of the transistor.

Design Rules?
For example, parts of the latest transistors are only a few atoms thick, and shrink with the scaling of transistors. Thus, when these reach the limit of 1-2 atoms thick, the scaling will have to cease and a new technology will have to be adopted. One possible to lithography based integrated circuits is nanotechnology and the nano-scale electrical devices.

Design Rules?
Process scaling is fundamental to most of the benefits achieved by modern electronics. For some applications, scaling allows for more devices to be integrated on a single die, and thus provide greater functionality per chip.

Design Rules?
Scaling also allows the same circuit to be smaller, cheaper, faster, and consume less power.

Unfortunately, the scaling down of lithographically patterned transistors cannot continue forever, but nano-electronics may be able to continue the scaling when transistors hit their limit.

Design Rules?
Typical Rules

Minimum size Minimum spacing Alignment / overlap

Design Rules?
Scalable Design Rules (e.g. SCMOS) Based on scalable coarse grid (lambda) Idea: reduce value for each new process, but keep rules the same advantage: portable layout disadvantage: not everything scales the same Absolute Design Rules Based on absolute distances (e.g. 0.75m) Tuned to a specific process (details usually proprietary) Complex, especially for deep submicron Layouts not portable

LAYOUT DESIGN RULES

The physical mask layout of any circuit to be manufactured using a particular process generally called layout design rules. Usually specify # minimum allowable line widths for physical objects on-chip such as metal and polysilicon Interconnects # diffusion areas, # minimum feature dimensions # minimum allowable separations between two such features. If a metal line width is made too small, for example, it is possible for the line to break during the fabrication process or afterwards, resulting in an open circuit.

LAYOUT DESIGN RULES

If two lines are placed too close to each other in the layout, they may form an unwanted short circuit by merging during or after the fabrication process. The main objective of design rules is to achieve a high overall yield and reliability while using the smallest possible silicon area, for any circuit to be manufactured with a particular process.

LAYOUT DESIGN RULES

The design rules are usually described in two ways : (i) Micron rules, in which the layout constraints such as minimum feature sizes and minimum allowable feature separations, are stated in terms of absolute dimensions in micrometers, or, (ii) Lambda rules, which specify the layout constraints in terms of a single parameter Lambda-based layout design rules were originally devised to simplify the industry- standard micron-based design rules and to allow scaling capability for various processes.

LAYOUT
Chips are specified with set of masks Minimum dimensions of masks determine transistor size (and hence speed, cost, and power) Feature size f = distance between source and drain Set by minimum width of polysilicon Feature size improves 30% every 3 years or so Normalize for feature size when describing design rules Express rules in terms of = f/2 E.g. = 0.3 m in 0.6 m process

CMOS DIAGRAM

SCMOS DIAGRAM RULES SUMMARY

Metal and diffusion have minimum width & spacing of 4 Contact are 2 x 2 and must be surrounded by 1 on the layers above and below Polysilicon uses a width of 2 Polysilicon overlaps diffusion by 2 where transistor is desired and has a spacing of 1 away where no transistor is desired. Polysilicon and contacts have spacing of 3 from other polysilicon or contacts. N-well surrounds pMOS by 6 and avoids nMOS transistors by 6

SIMPLIFIED DESIGN RULES SIMPLIFIED DESIGN RULES

WHAT IS DESIGN FOR RELIABILITY?

When a product performs the functions for which it is designed then the product is said to be reliable. When it does not, it is said to be unreliable. To ensure that the electronic system packaging will be reliable over an extended period of time, two approaches need to follow (i) design the system packaging up-front for reliability (ii) conduct and accelerated test on the system packaging for reliability after the system is designed, fabricated and assembled.

WHAT IS DESIGN FOR RELIABILITY?

1st approached pre determine various potential failure mechanisms that could result in product failure. Create designs and select material and processes that would minimize or eliminate the chances for the failure. 2nd approached after built and assembled, the system is subject to accelerated test conditions such as thermal cycling, temperature and humidity cycling and power cycling for short periods of time by applying higher temperature, voltage humidity pressure and more to accelerate the failure process

THERMOMECHANICAL DESIGN
Thermomechanically failure cause by stresses and strains generated within electronic package (thermal loading from the environment or internal heating in service) Due to # mismatch in the coefficient of thermal expansion among different materials # thermal gradients in system, # geometric constrains, # thermally-induced stresses and strains are generated in various parts of the system

ETCHING
is the process in which material is removed from selected regions of the substrate

ETCHING
WET ETCHING DRY ETCHING

Liquid etchants are used to remove material Wafer are immersed in a tank of reactants Makes large volumes of waste

Done by a plasma No liquid are used

ETCH PROFILE : TYPES

The shape of the feature that is etched is called etch profile
WET ETCHING DRY ETCHING

Etched equally in all directions Wet etches give isotropic profiles

Etched in the preferred direction only Only dry gives anisotropic profiles Anisotropic are needed to transfer lithographic patterns for small features

ETCH - SELECTIVITY
A process is selective if the desired film is removed quickly compared to other films which are exposed to the plasma Selectivity is controlled by the chemistry of the process

WET ETCH
Oxide Etch
#Recipe : H2O/HF #Remove : Oxide (SiO2) # HF reacts with SiO2 to make liquid products SiO2 + 6HF - H2SiF6 + 2H2O

Silicon Etch
#2 step process : first oxidize with HNO3 Si + 2HNO3 - SiO2 + 2HNO2

OTHER WET ETCHANTS

WET ETCH REACTION RATES

Etch rate depends on temperature, reaction chemistry and concentration

Effect of shrinkage lambda value in term of performance of transistor

The Gain

Decrease in gate capacitance per unit length as fabrication processes have scaled
Increased the performance of logic gates & amount of power consumed per unit area As transistor decrease, supply voltage also decrease Technology could go a long way toward satisfying consumers demands longer battery life, portable computer & additional capabilities in wireless telephones

Effect of shrinkage lambda value in term of performance of transistor

Losses

The minimum size of each region on the chip is limited by the wavelength of light that is used due to optical effects. Early chip fabrication = visible light Current = ultraviolet Future = x-ray (big problem dont have good lenses to focus, use reflective optics cost barriers) CAD tools need to be made some additions and changes to existing parts for nano-electronics.

Effect of shrinkage lambda value in term of performance of transistor

Losses

transient faults will be a problem with nano-electronics due to their small size and low current levels. (to handle this fault a redundancy method are use detect & repair the faults)

Effect of altering polysilicon gate width on transistor speed

The channel length is defined as the distance between source and drain. The shorter the channel length, shorter the electrons travel faster device. less space consumes less power. The higher temperature or the longer time in the thermal steps, more the source/drain dopants will diffuse under the gate, creating a shorter channel length.

Effect of plasma deposition to the thin gate oxide

Fabrication processes such as plasma deposition of materials can generate huge amounts of electrical charges Extent these thin gate oxides can be ruptured, destroying the active device or transistors that are critical to the function of the circuit or design. This process of making the chip actually destroys the chip.

Effect of scaled down wiring dimension (metallization) to the circuit or devices operation.
As wiring dimensions (metallization) shrink with advance technologies, the amount of current that the wires can carry is reduced. Fundamental physics tells us that when too much current passes through a thin wire, the wire can fuse or destroy itself Such an occurrence can destroy the circuit operation and make the device useless.

Limitation of using visible light when photomask become slit

The minimum size of each region on the chip is limited by the wavelength of light that is used due to optical effects. Early chip fabrication = with visible light. Current fabrication = ultraviolet range, and future processes will need to operate in the X-Ray range The big problem with using radiation at these frequencies is that we dont have good lenses to focus X-Rays, so fabrication processes will have to use reflective optics instead, which creates both technical and cost barriers.

Purpose of using wider wires (aluminium metal width) in submicron technologies.

If wider wires are implementing the spacing between wires must also increase. This new design rules can completely invalidate any areas reserved for wiring and make the circuit too congested to be completely wired in the original size planned. The process have determined that when a contact between a wider or fat wires made a narrower or minimum width wire, more vias have to be implemented to make the connection to improve the manufacturing yields. Instead of implementing a single via connection, the place and route tool should insert an array or multiple vias to conform to the rules.

Goals of Manufacturing
To achieve finished products with ~ Low Cost ~ High quality ~ High reliability Cost most directly impact by yield and throughput. Yield is the proportion of products that meet the requirement Throughput refer to the number of products processed per unit time

Goals of Manufacturing
Quality is derived from a stable and well-controlled manufacturing process Reliability also impacted by manufacturing process. High reliability results from the minimization faults

Failure Modes
Todays electronic system become more complex and compact Concepts of quality and reliability are applied to products Failure causes disruption in the service and costly down time for repair, which affect the economy of the operation Failure analysis (FA) give valuable insight into the causes of failure and provide inputs for product improvement. Failure analysis identifies the causes of failure by analyzing stresses and other mechanism causing failure

Failure Mechanism
Design against failure can be achieve by one of the following # Reducing the stress that cause the failure # Increasing the strength of the component Reduction in stress and/or increasing strength can be achieve through # Selecting alternate material # Changing package geometry & dimensions # Introducing new protection or encapsulation # combination all of these

Failure Modes

(1) STATISTICAL FUNDAMENTALS (2) FAILURE MECHANISMS

STATISTICAL FUNDAMENTALS
basic statistics and problem solving methods can be used to improve the quality of microelectronics packaging manufacturing process. Statistic allow decision to be made regarding a process population, based on the analysis of a sample from that population Statistical methods provide the principle means by which products are sampled, tested, and evaluated in a manufacturing environment Several methodologies are introduced as tools for use in quality control and improvement.

STATISTICAL FUNDAMENTALS
For example 2 well known statistics ~ sample average ~ sample variance Suppose that x1, x2,xn are observations in a sample of size n The statistic used to estimate the mean value () of this population based on the sample, is the sample average (x) is given by (x) = x1+x2+xn/n = 1 n
1 The variance (2) can be estimated byi =the sample variance

x n

1 s = xi x n 1 i =1
2

STATISTICAL FUNDAMENTALS
Probability distributions ~ Discrete describe random variable that only take on certain specifics values, ex: no of defect ~ Continuous ex : line width in a sample of population Binomial distribution ~ process consists of n independent trials. ~ Each trial has two possible outcomes (success & failure) p = the probability of success for any given trial (thus, 0<p<1). If p is constant, then the probability of achieving x successes in n trial is

n x n x P ( x) = p (1 p ) x

x = 0,1..., n

EXAMPLE
Suppose a bonding process has an average of 1% defective bonds. Is an inspector selects a random sample of 100 bonds, what is the probability of more than two of the bonds being defective?

SOLUTION
In this case, n=100 and p=0.01. to find the probability of the greater than 2 defective bonds.
n P ( x) = p x (1 p ) n x x

Note that

100 P( x) = 0.01x (0.99)100 x x

P( x > 2) = 1 P( x 2) = P(0) + P(1) + P(2)

100 x 100 x = (0.01) (0.99) x =0 x
2

SOLUTION
= (0.99) + 100(0.01) (0.99) + 4950(0.01) (0.99) 0.92
100 1 99 2 98

Therefore, the probability of finding more than two defective bonds is 1-0.92=0.08@8%

Component of Failure Mechanism

Early Failure (infant mortality)

The Early Failure Rate (EFR), sometimes referred to as Infant Mortality Failures (IMF) or Early Life Failures (ELF) Represents this small fraction of the population of components which contain defects that do not immediately fail but will fail in a relatively short time interval. The infant mortality failures are due to # defects during manufacture # improper design or implementation of the component # freak failures that have not failed during screening.

Early Failure (infant mortality)

Usually, failures during this phase are caused by stresses such as high temperature (thermal overstress), high voltage/current (electrical overstress), humidity, vibration, mechanical or thermal shock. Out of spec part that quickly fail due to normal stress

Overstress Failures (intrinsic failure)

Caused by high level stress beyond normal usage Cause : stress outside of design Example : ESD, radiation, Interconnect melting, interfacial delamination This behavior is seen in large populations of mature components and is commonly referred to as the useful life of the product. The intrinsic failure rate is usually defined by the Failure-InTime (FIT)a FIT being 1 failure in 1 billion device hours of operation.

Wearout Failures
Occur after the useful life phase of the component has passed. Examples of wear-out failure are: corrosion, electrical leakage, insulation breakdown, migration of metallic ions in the direction of current flow, cracking of the encapsulating material due to deterioration of the material, and cracks in the bond wires due to repeated stresses

Failure Mechanism

Example of failure

Gate Pin Holes

Crack

Damage under bonding (bottom view)

No molding resin injected

Short circuit due to conductive particles in package

Gate Oxide Failure

Defects in the Gate Oxide are called Traps Breakdown/failure is defined as the time when there is a conduction path from the anode to the cathode through the gate oxide Traps allow for creation of conduction path Refers to the destruction of an oxide layer (usually silicon dioxide or SiO2) in a semiconductor device.

Gate Oxide Failure

Oxide layers are used in many parts of the device: as gate oxide between the metal and the semiconductor in MOS transistors, as dielectric layer in capacitors, as inter-layer dielectric to isolate conductors from each other, etc. Oxide breakdown is also referred to as 'oxide rupture' or 'oxide punch-through.

Gate Oxide Failure

Gate Oxide Failure

Oxide breakdown has always been of serious reliability concern in the semiconductor industry because of the continuous trek towards smaller and smaller devices. As other features of the device are scaled down, so must oxide thickness be reduced. Oxides become more vulnerable to the voltages fed into the device as they get thinner.

Electromigration Failure
Definition: Electromigration is the movement of metal ions in a conductor Sources and Failure Modes: Electromigration most commonly results in an open circuit condition. Electromigration is most commonly observed as a result of extended life tests (Burn-in Tests) The main factors of electromigration are; high temperature, small metal grain boundaries, and the activation energy of the interconnect material

Electromigration Failure
The metal atom (such as solders used to flip chip) connect the IC to the package under the influence of the electron wind of high current. They experience a mechanical force and get physically dislodged from their position Causes the formation of metal voids in the conductor Process continues, the resistance drop across the conductor is increased leading to electrical open

Electromigration Design guideliness

Mostly notice in aluminum and silver metallization. Copper traces are found more resistant Using shorter traces. But adds more routing layer and complexity to fabrication of product By controlling current density design rules based on electromigration data

Electromigration Failure
Prevention techniques :
Adding 2% copper to aluminum wiring Control of deposition parameters to decrease grain boundaries Covering aluminum with tungsten Maintaining lower current densities.

Corrosion Failure
Corrosion is chemically induced damage to a material that results in deterioration of the material and its properties. This may result in failure of the component. Several factors should be considered during a failure analysis to determine the affect corrosion played in a failure

Corrosion Failure
Consist of anodic reactions & cathodic reactions Anodic reaction is oxidation reactions in which a metal loses electrons Cathodic reaction is reductions in which the lost electrons combine with another species

Electrostatic Discharge (ESD)

Defined as the transfer of electrostatic charge between bodies at different potential Caused by direct contact or induced by an electrostatic field. When two bodies are rubbed each other, transfer of electron takes place rapidly

Electrostatic Discharge (ESD)

Body loses electron becomes +ve charged, receives electrons becomes ve charged Since electric charge is transferred, it can be said that electricity is generated Transfer of charge -> triboelectric effect Static electricity can also generated when two object in contact and suddenly separated each other

Electrostatic Discharge (ESD) Reduce the chances of ESD

Workstations can be provided with measures conductive tablemates, wristband, conductive flooring Air ionizers neutralize static charges on conductive material use in manufacture All test and soldering equipment should be provided with ground potential and should be checked periodically Antistatic foams used to protecting ESD sensitive devices

Electrostatic Discharge (ESD) Reduce the chances of ESD

Monitoring device like electrostatic alarms, electrostatis voltmeter can be used to measure and control static charge on materials