MC33178, MC33179 Low Power, Low Noise Operational Amplifiers

The MC33178/9 series is a family of high quality monolithic amplifiers employing Bipolar technology with innovative high performance concepts for quality audio and data signal processing applications. This device family incorporates the use of high frequency PNP input transistors to produce amplifiers exhibiting low input offset voltage, noise and distortion. In addition, the amplifier provides high output current drive capability while consuming only 420 mA of drain current per amplifier. The NPN output stage used, exhibits no deadband crossover distortion, large output voltage swing, excellent phase and gain margins, low openloop high frequency output impedance, symmetrical source and sink AC frequency performance. The MC33178/9 family offers both dual and quad amplifier versions, and is available in DIP and SOIC packages.
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DUAL PDIP8 P SUFFIX CASE 626 1

600 W Output Drive Capability Large Output Voltage Swing Low Offset Voltage: 0.15 mV (Mean) Low T.C. of Input Offset Voltage: 2.0 mV/C Low Total Harmonic Distortion: 0.0024% (@ 1.0 kHz w/600 W Load) High Gain Bandwidth: 5.0 MHz High Slew Rate: 2.0 V/ms Dual Supply Operation: 2.0 V to 18 V ESD Clamps on the Inputs Increase Ruggedness without Affecting Device Performance PbFree Package is Available

8 1

SOIC8 D SUFFIX CASE 751

QUAD PDIP14 P SUFFIX CASE 646 14 1 SOIC14 D SUFFIX CASE 751A

14 1

VCC

ORDERING INFORMATION
Iref Iref
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.

Vin

Vin +

CC VO CM

DEVICE MARKING INFORMATION

See general marking information in the device marking section on page 4 of this data sheet.

VEE

Figure 1. Representative Schematic Diagram (Each Amplifier)

Semiconductor Components Industries, LLC, 2004

February, 2004 Rev. 4

Publication Order Number: MC33178/D

MC33178, MC33179
MAXIMUM RATINGS
Rating Supply Voltage (VCC to VEE) Input Differential Voltage Range Input Voltage Range Output Short Circuit Duration (Note 2) Maximum Junction Temperature Storage Temperature Range Maximum Power Dissipation Operating Temperature Range Symbol VS VIDR VIR tSC TJ Tstg PD TA Value +36 Note 1 Note 1 Indefinite +150 60 to +150 Note 2 40 to +85 Unit V V V sec C C mW C

1. Either or both input voltages should not exceed VCC or VEE. 2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded. (See power dissipation performance characteristic, Figure 2.)

ORDERING INFORMATION
Device MC33178D MC33178DG MC33178DR2 MC33178P MC33179D MC33179DR2 MC33179P Package SOIC8 SOIC8 (PbFree) SOIC8 PDIP8 SOIC14 SOIC14 PDIP14 Shipping 98 Units / Rail 98 Units / Rail 2500 / Tape & Reel 1000 Units / Rail 55 Units / Rail 2500 / Tape & Reel 500 Units / Rail

For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

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MC33178, MC33179
MARKING DIAGRAMS

DUAL PDIP8 CASE 626 8 MC33178P AWL YYWW 1 1 8 33178 ALYW 1 SOIC8 CASE 751 14 MC33179P AWLYYWW PDIP14 CASE 646

QUAD SOIC14 CASE 751A 14 MC33179D AWLYWW 1

A WL, L YY, Y WW, W

= Assembly Location = Wafer Lot = Year = Work Week

PIN CONNECTIONS
DUAL CASE 626/751 Output 1 Inputs 1 VEE
1 2 3 4 8

QUAD CASE 646/751A Output 1 Inputs 1

3 1 2 + + 14 13

VCC Output 2 Inputs 2

Output 4 Inputs 4

+ 5

12 11

(Top View)

VCC Inputs 2

4 5 6 + +

VEE Inputs 3

10 9 8

Output 2

Output 3

(Top View)

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MC33178, MC33179
DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = 15 V, TA = 25C, unless otherwise noted.)
Characteristics Input Offset Voltage (RS = 50 W, VCM = 0 V, VO = 0 V) (VCC = +2.5 V, VEE = 2.5 V to VCC = +15 V, VEE = 15 V) TA = +25C TA = 40 to +85C Average Temperature Coefficient of Input Offset Voltage (RS = 50 W, VCM = 0 V, VO = 0 V) TA = 40 to +85C Input Bias Current (VCM = 0 V, VO = 0 V) TA = +25C TA = 40 to +85C Input Offset Current (VCM = 0 V, VO = 0 V) TA = +25C TA = 40 to +85C Common Mode Input Voltage Range (DVIO = 5.0 mV, VO = 0 V) Large Signal Voltage Gain (VO = 10 V to +10 V, RL = 600 W) TA = +25C TA = 40 to +85C Output Voltage Swing (VID = 1.0 V) (VCC = +15 V, VEE = 15 V) RL = 300 W RL = 300 W RL = 600 W RL = 600 W RL = 2.0 kW RL = 2.0 kW (VCC = +2.5 V, VEE = 2.5 V) RL = 600 W RL = 600 W Common Mode Rejection (Vin = 13 V) Power Supply Rejection VCC/VEE = +15 V/ 15 V, +5.0 V/ 15 V, +15 V/ 5.0 V Output Short Circuit Current (VID = 1.0 V, Output to Ground) Source (VCC = 2.5 V to 15 V) Sink (VEE = 2.5 V to 15 V) Power Supply Current (VO = 0 V) (VCC = 2.5 V, VEE = 2.5 V to VCC = +15 V, VEE = 15 V) MC33178 (Dual) TA = +25C TA = 40 to +85C MC33179 (Quad) TA = +25C TA = 40 to +85C 6 7, 8 Figure 3 Symbol |VIO| 3 DVIO/DT 4, 5 IIB |IIO| VICR AVOL 50 25 9, 10, 11 VO+ VO VO+ VO VO+ VO VO+ VO 12 13 14, 15 CMR PSR 80 ISC +50 50 16 ID +80 100 mA 110 mA +12 +13 1.1 80 +12 12 +13.6 13 +14 13.8 1.6 1.6 110 12 13 1.1 dB dB 200 V 13 5.0 14 +14 50 60 +13 V kV/V 100 500 600 nA 2.0 nA 0.15 3.0 4.0 mV/C Min Typ Max Unit mV

1.7

1.4 1.6 2.4 2.6

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MC33178, MC33179
AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = 15 V, TA = 25C, unless otherwise noted.)
Characteristics Slew Rate (Vin = 10 V to +10 V, RL = 2.0 kW, CL = 100 pF, AV = +1.0 V) Gain Bandwidth Product (f = 100 kHz) AC Voltage Gain (RL = 600 W, VO = 0 V, f = 20 kHz) Unity Gain Bandwidth (OpenLoop) (RL = 600 W, CL = 0 pF) Gain Margin (RL = 600 W, CL = 0 pF) Phase Margin (RL = 600 W, CL = 0 pF) Channel Separation (f = 100 Hz to 20 kHz) Power Bandwidth (VO = 20 Vpp, RL = 600 W, THD 1.0%) Total Harmonic Distortion (RL = 600 W,, VO = 2.0 Vpp, AV = +1.0 V) (f = 1.0 kHz) (f = 10 kHz) (f = 20 kHz) Open Loop Output Impedance (VO = 0 V, f = 3.0 MHz, AV = 10 V) Differential Input Resistance (VCM = 0 V) Differential Input Capacitance (VCM = 0 V) Equivalent Input Noise Voltage (RS = 100 W,) f = 10 Hz f = 1.0 kHz Equivalent Input Noise Current f = 10 Hz f = 1.0 kHz 28 26 21, 23, 24 22, 23, 24 25 Figure 17, 32 18 19, 20 Symbol SR 1.2 GBW AVO BW Am fm CS BWp THD 27 |ZO| Rin Cin en 29 in 0.33 0.15 8.0 7.5 pA/ Hz 150 200 10 kW pF nV/ Hz 0.0024 0.014 0.024 W 2.5 2.0 5.0 50 3.0 15 60 120 32 MHz dB MHz dB Deg dB kHz % Min Typ Max Unit V/ms

PD (MAX), MAXIMUM POWER DISSIPATION (mW)

2400 V IO , INPUT OFFSET VOLTAGE (mV) 2000 1600 MC33179D 1200 800 MC33178D 400 0 60 40 20 MC33178P/9P

4.0 3.0 2.0 1.0 0 1.0 2.0 3.0 4.0 55 25 0 25 50 75 100 125 Unit 2 Unit 3 Unit 1 VCC = +15 V VEE = 15 V RS = 10 W VCM = 0 V

20

40

60

80 100 120 140 160 180

TA, AMBIENT TEMPERATURE (C)

TA, AMBIENT TEMPERATURE (C)

Figure 2. Maximum Power Dissipation versus Temperature

Figure 3. Input Offset Voltage versus Temperature for 3 Typical Units

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MC33178, MC33179
160 I IB , INPUT BIAS CURRENT (nA) I IB , INPUT BIAS CURRENT (nA) 140 120 100 80 60 40 20 0 15 10 5.0 0 5.0 VCM, COMMON MODE VOLTAGE (V) 10 15 VCC = +15 V VEE = 15 V TA = 25C 120 110 100 90 80 70 60 55 VCC = +15 V VEE = 15 V VCM = 0 V

25

0 25 50 75 TA, AMBIENT TEMPERATURE (C)

100

125

Figure 4. Input Bias Current versus Common Mode Voltage

V ICR , INPUT COMMON MODE VOLTAGE RANGE (V)

Figure 5. Input Bias Current versus Temperature

VCC 0.5 V VCC 1.0 V VCC 1.5 V VCC 2.0 V VCC = +5.0 V to +18 V VEE = 5.0 V to 18 V DVIO = 5.0 mV

AVOL, OPEN LOOP VOLTAGE GAIN (kV/V)

VCC

250 200 150 100 50 0 55 VCC = +15 V VEE = 15 V f = 10 Hz DVO = 10 V to +10 V RL = 600 W

VEE +1.0 V VEE +0.5 V VEE 55 25 0 25 50 75 100 125

25

25

50

75

100

125

TA, AMBIENT TEMPERATURE (C)

TA, AMBIENT TEMPERATURE (C)

Figure 6. Input Common Mode Voltage Range versus Temperature

Figure 7. Open Loop Voltage Gain versus Temperature

A VOL, OPEN LOOP VOLTAGE GAIN (dB)

50 40 30 20 10 0 10 20 1A 1B VCC = +15 V VEE = 15 V VO = 0 V TA = 25C

80 , EXCESS PHASE (DEGREES) 100 120 140 160 180 200 220 240 260 20 280 VO, OUTPUT VOLTAGE (Vpp )

40 35 30 25 20 15 10 5.0 0 0 5.0 10 15 VCC, |VEE|, SUPPLY VOLTAGE (V) 20 TA = 25C RL = 10 kW RL = 600 W

1A) Phase (RL = 600 W) 2B 30 2A) Phase (RL = 600 W, CL = 300 pF) 2A 40 1B) Gain (RL = 600 W) 2B) Gain (RL = 600 W, CL = 300 pF) 50 2 3 4 5 6 7 8 9 10 f, FREQUENCY (Hz)

Figure 8. Voltage Gain and Phase versus Frequency

Figure 9. Output Voltage Swing versus Supply Voltage

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MC33178, MC33179
V sat , OUTPUT SATURATION VOLTAGE (V) VCC TA = +125C VCC 1.0 V TA = 55C VCC 2.0 V VEE +2.0 V VEE +1.0 V TA = +125C VEE 0 5.0 10 IL, LOAD CURRENT (mA) VCC = +5.0 V to +18 V VEE = 5.0 V to 18 V 15 20 Sink TA = 55C Source VO, OUTPUT VOLTAGE (Vpp ) 28 24 20 16 12 8.0 4.0 0 1.0 k VCC = +15 V VEE = 15 V RL = 600 W AV = +1.0 V THD = 1.0% TA = 25C 10 k 100 k 1.0 M

f, FREQUENCY (Hz)

Figure 10. Output Saturation Voltage versus Load Current

Figure 11. Output Voltage versus Frequency

120 CMR, COMMON MODE REJECTION (dB) PSR, POWER SUPPLY REJECTION (dB) 100 80 60 40 20
CMR = 20 Log DVCM ADM + DVCM DVO DVO

120 VCC = +15 V VEE = 15 V VCM = 0 V DVCM = 1.5 V TA = 55 to +125C 100 80 60 40 20

PSR = 20 Log ADM + VCC DVO VEE DVO/ADM DVCC

+PSR PSR

TA = 55 to +125C VCC = +15 V VEE = 15 V DVCC = 1.5 V

x ADM

0 10

100

1.0 k 10 k f, FREQUENCY (Hz)

100 k

1.0 M

0 10

100

1.0 k 10 k f, FREQUENCY (Hz)

100 k

1.0 M

Figure 12. Common Mode Rejection versus Frequency Over Temperature

Figure 13. Power Supply Rejection versus Frequency Over Temperature

I SC , OUTPUT SHORT CIRCUIT CURRENT (mA)

100 Source 80 Sink 60 40 20 0 15

I SC , OUTPUT SHORT CIRCUIT CURRENT (mA)

100 90 Sink 80 Source 70 60 50 55 VCC = +15 V VEE = 15 V VID = 1.0 V RL < 10 W

VCC = +15 V VEE = 15 V VID = 1.0 V

9.0

3.0 0 3.0 VO, OUTPUT VOLTAGE (V)

9.0

15

25

25

50

75

100

125

TA, AMBIENT TEMPERATURE (C)

Figure 14. Output Short Circuit Current versus Output Voltage

Figure 15. Output Short Circuit Current versus Temperature

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MC33178, MC33179
I CC, SUPPLY CURRENT/AMPLIFIER ( A) 625 SR, SLEW RATE (NORMALIZED) 500 375 250 125 0 TA = +125C TA = +25C TA = 55C 1.15 1.10 1.05 1.00 0.95 0.90

VCC = +15 V VEE = 15 V DVin = 20 Vpp

0.85 0.80 0.75 55 25 0 25

DVin

VO + 600 W 100 pF

2.0

4.0

6.0

8.0

10

12

14

16

18

50

75

100

125

VCC, |VEE| , SUPPLY VOLTAGE (V)

TA, AMBIENT TEMPERATURE (C)

Figure 16. Supply Current versus Supply Voltage with No Load

Figure 17. Normalized Slew Rate versus Temperature

GBW, GAIN BANDWIDTH PRODUCT (MHz)

10 8.0 6.0 4.0 2.0 0 55 VCC = +15 V VEE = 15 V f = 100 kHz RL = 600 W CL = 0 pF

50 40 A V , VOLTAGE GAIN (dB) 30 20 10 0 10 20 30 40 100 125 50 100 k 1.0 M 10 M f, FREQUENCY (Hz) VCC = +15 V VEE = 15 V RL = 600 W TA = 25C CL = 0 pF Gain Phase

80 120 140 160 180 200 220 240 260 280 100 M , EXCESS PHASE (DEGREES) 125 100

25

0 25 50 75 TA, AMBIENT TEMPERATURE (C)

Figure 18. Gain Bandwidth Product versus Temperature

Figure 19. Voltage Gain and Phase versus Frequency

50 40 A V , VOLTAGE GAIN (dB) 30 20 10 0 10 1B 2B 2A 1A TA = 25C RL = CL = 0 pF

80 Am, OPEN LOOP GAIN MARGIN (dB) 100 140 160 180 200 220 240 260 10 M 280 100 M , PHASE (DEGREES) 120

15 CL = 10 pF 12 CL = 100 pF 9.0 CL = 300 pF 6.0 3.0 0 55 VCC = +15 V VEE = 15 V RL = 600 W

20 1A) Phase V =18 V, V = 18 V CC EE 30 2A) Phase VCC 1.5 V, VEE = 1.5 V 1B) Gain V = 18 V, VEE = 18 V 40 2B) Gain VCC = 1.5 V, V = 1.5 V CC EE 50 100 k 1.0 M

25

25

50

75

100

f, FREQUENCY (Hz)

TA, AMBIENT TEMPERATURE (C)

Figure 20. Voltage Gain and Phase versus Frequency

Figure 21. Open Loop Gain Margin versus Temperature

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MC33178, MC33179
60 m , PHASE MARGIN (DEGREES) 50 40 30 20 10 0 55 VCC = +15 V VEE = 15 V RL = 600 W 25 0 25 50 75 100 125 CL = 10 pF A m , GAIN MARGIN (dB) CL = 100 pF 12 10 8.0 6.0 4.0 2.0
Vin R2

60 50 VCC = +15 V VEE = 15 V RT = R1+R2 VO = 0 V TA = 25C

R1

Gain Margin 40 30 20 + 1.0 k 10 k Phase Margin

VO

CL = 300 pF

10 0 100 k

0 100

TA, AMBIENT TEMPERATURE (C)

RT, DIFFERENTIAL SOURCE RESISTANCE (W)

Figure 22. Phase Margin versus Temperature

Figure 23. Phase Margin and Gain Margin versus Differential Source Resistance

18 A m , OPEN LOOP GAIN MARGIN (dB) Phase Margin 15 12 Gain Margin VCC = +15 V VEE = 15 V VO = 0 V

60 m, PHASE MARGIN (DEGREES) CS, CHANNEL SEPARATION (dB) 50 40 30

Vin VO + 600 W CL

150 140 130 120 110 100 100 Drive Channel VCC = +15 V CEE = 15 V RL = 600 W TA = 25C

9.0 6.0 3.0 0 10 100 CL, OUTPUT LOAD CAPACITANCE (pF)

20 10 0 1.0 k

1.0 k

10 k f, FREQUENCY (Hz)

100 k

1.0 M

Figure 24. Open Loop Gain Margin and Phase Margin versus Output Load Capacitance

Figure 25. Channel Separation versus Frequency

THD, TOTAL HARMONIC DISTORTION (%)

10 |Z O |, OUTPUT IMPEDANCE ( ) VCC = +15 V VO = 2.0 Vpp VEE = 15 V TA = 25C RL = 600 W 1.0 AV = 100 0.1 AV = 10 AV = 1.0 10 k 100 k

500 AV = 1000 400 300 200 100 0 1.0 k 3 4 100 1.0 k f, FREQUENCY (Hz) 10 k 100 k f, FREQUENCY (Hz) 1.0 M 10 M 1. AV = 1.0 2. AV = 10 3. AV = 100 4. AV = 1000 VCC = +15 V VEE = 15 V VO = 0 V TA = 25C

0.01 10

Figure 26. Total Harmonic Distortion versus Frequency

Figure 27. Output Impedance versus Frequency

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m , PHASE MARGIN (DEGREES)

MC33178, MC33179
e n , INPUT REFERRED NOISE VOLTAGE ( nV/ Hz ) 20 18 16 14 12 10 8.0 6.0 4.0 2.0 0 10 VCC = +15 V VEE = 15 V TA = 25C 100 1.0 k f, FREQUENCY (Hz) 10 k 10 k i n , INPUT REFERRED NOISE CURRENT (pA/ Hz ) 0.5
Input Noise Current Test Circuit

Input Noise Voltage Test Circuit + VO

0.4 0.3 0.2 0.1 0 10 VCC = +15 V VEE = 15 V TA = 25C 100

RS

+ VO

(RS = 10 kW)

1.0 k f, FREQUENCY (Hz)

10 k

100 k

Figure 28. Input Referred Noise Voltage versus Frequency

Figure 29. Input Referred Noise Current versus Frequency

100 80 70 60 50 40 30 20 10 0 10 100 1.0 k 10 k RL = 600 W RL = 2.0 kW V O, OUTPUT VOLTAGE (5.0 V/DIV) 90 PERCENT OVERSHOOT (%) VCC = +15 V VEE = 15 V TA = 25C VCC = +15 V VEE = 15 V AV = +1.0 RL = 600 W CL = 100 pF TA = 25C

t, TIME (2.0 ms/DIV)

CL, LOAD CAPACITANCE (pF)

Figure 30. Percent Overshoot versus Load Capacitance

Figure 31. Noninverting Amplifier Slew Rate

V O, OUTPUT VOLTAGE (50 mV/DIV)

V O, OUTPUT VOLTAGE (5.0 V/DIV)

VCC = +15 V VEE = 15 V AV = +1.0 RL = 600 W CL = 100 pF TA = 25C

VCC = +15 V VEE = 15 V AV = +1.0 RL = 600 W CL = 100 pF TA = 25C

t, TIME (2.0 ns/DIV)

t, TIME (5.0 ms/DIV)

Figure 32. Small Signal Transient Response

Figure 33. Large Signal Transient Response

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MC33178, MC33179
10 k To Receiver A1 + 10 k 1.0 mF 200 k 120 k From Microphone 2.0 k A2 300 820 0.05 mF

10 k

+ VR

Tip

1N4678 10 k

Phone Line

Ring 10 k + A3

VR

Figure 34. Telephone Line Interface Circuit

APPLICATION INFORMATION This unique device uses a boosted output stage to combine a high output current with a drain current lower than similar bipolar input op amps. Its 60 phase margin and 15 dB gain margin ensure stability with up to 1000 pF of load capacitance (see Figure 24). The ability to drive a minimum 600 W load makes it particularly suitable for telecom applications. Note that in the sample circuit in Figure 34 both A2 and A3 are driving equivalent loads of approximately 600 W . The low input offset voltage and moderately high slew rate and gain bandwidth product make it attractive for a variety of other applications. For example, although it is not single supply (the common mode input range does not include ground), it is specified at +5.0 V with a typical common mode rejection of 110 dB. This makes it an excellent choice for use with digital circuits. The high common mode rejection, which is stable over temperature, coupled with a low noise figure and low distortion, is an ideal op amp for audio circuits. The output stage of the op amp is current limited and therefore has a certain amount of protection in the event of a short circuit. However, because of its high current output, it is especially important not to allow the device to exceed the maximum junction temperature, particularly with the MC33179 (quad op amp). Shorting more than one amplifier could easily exceed the junction temperature to the extent of causing permanent damage.
Stability

As usual with most high frequency amplifiers, proper lead dress, component placement, and PC board layout should be exercised for optimum frequency performance. For example, long unshielded input or output leads may result in unwanted input/output coupling. In order to preserve the relatively low input capacitance associated with these amplifiers, resistors connected to the inputs should be immediately adjacent to the input pin to minimize additional stray input capacitance. This not only minimizes the input pole frequency for optimum frequency response, but also minimizes extraneous pick up at this node. Supplying decoupling with adequate capacitance immediately adjacent to the supply pin is also important, particularly over temperature, since many types of decoupling capacitors exhibit great impedance changes over temperature. Additional stability problems can be caused by high load capacitances and/or a high source resistance. Simple compensation schemes can be used to alleviate these effects.

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MC33178, MC33179
If a high source of resistance is used (R1 > 1.0 kW), a compensation capacitor equal to or greater than the input capacitance of the op amp (10 pF) placed across the feedback resistor (see Figure 35) can be used to neutralize that pole and prevent outer loop oscillation. Since the closed loop transient response will be a function of that capacitance, it is important to choose the optimum value for that capacitor. This can be determined by the following Equation:
CC + (1 ) [R1 R2])2 CL (ZO R2) (1)

For moderately high capacitive loads (500 pF < CL < 1500 pF) the addition of a compensation resistor on the order of 20 W between the output and the feedback loop will help to decrease miller loop oscillation (see Figure 36). For high capacitive loads (CL > 1500 pF), a combined compensation scheme should be used (see Figure 37). Both the compensation resistor and the compensation capacitor affect the transient response and can be calculated for optimum performance. The value of CC can be calculated using Equation 1. The Equation to calculate RC is as follows:
RC + ZO R1 R2 (2)

where: ZO is the output impedance of the op amp.

R2 CC R2

+ R1 ZL

RC

R1

CL

Figure 35. Compensation for High Source Impedance

Figure 36. Compensation Circuit for Moderate Capacitive Loads

R2

CC

RC

R1

CL

Figure 37. Compensation Circuit for High Capacitive Loads

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MC33178, MC33179
PACKAGE DIMENSIONS
PDIP8 P SUFFIX CASE 62605 ISSUE L
NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC 10_ 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC 10_ 0.030 0.040

B
1 4

F
NOTE 2

A L

C T
SEATING PLANE

J N D K
M

M T A B

G 0.13 (0.005)
M M

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MC33178, MC33179
SOIC8 D SUFFIX CASE 75107 ISSUE AB
X A
8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 75101 THRU 75106 ARE OBSOLETE. NEW STANDARD IS 75107. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244

B
1 4

0.25 (0.010)

Y G C Z H D 0.25 (0.010)
M SEATING PLANE

X 45 _

0.10 (0.004)

Z Y

DIM A B C D G H J K M N S

SOLDERING FOOTPRINT*

1.52 0.060 7.0 0.275 4.0 0.155

0.6 0.024

1.270 0.050
SCALE 6:1 mm inches

SOIC8
*For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

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MC33178, MC33179
PACKAGE DIMENSIONS
PDIP14 P SUFFIX CASE 64606 ISSUE M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 18.80 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 10_ 0.38 1.01

14

B
1 7

A F N T
SEATING PLANE

L C

K H G D 14 PL 0.13 (0.005)
M

J M

DIM A B C D F G H J K L M N

SOIC14 D SUFFIX CASE 751A03 ISSUE F

A
14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

B
1 7

P 7 PL 0.25 (0.010)
M

G C

R X 45 _

T
SEATING PLANE

D 14 PL 0.25 (0.010)

K
M

M
S

T B

DIM A B C D F G J K M P R

MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50

INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019

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MC33178, MC33179

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MC33178/D

This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components.