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Digital Control of a Three Phase 4 Wire PWM Inverter for PV Applications

Said El-Barbari and W. Hofmann CHEMNITZ UNIVERSITY OF TECHNOLOGY Department of Electrical Machines and Derives D-09107 Chemnitz, Germany Tel: ++49 371 531 3319 / Fax: ++49 371 531 3324 e-mail: said.el-barbari@e-technik.tu-chemnitz.de URL: http://www.infotech.tu-chemnitz.de/~ema/staff/el-barbari.html
Keywords: Control, Design, Harmonics, Simulation, Three phase system, Renewable energy system, Solar cell system, UPS

ABSTRACT
The Microcontroller based digital control of a three phase 4 wire PWM inverter for simultaneously supply of three phase and single phase load in transformerless stand alone photovoltaic application with battery energy storage (BES) and LC output filter is described. An observer is implemented to estimate the load current and to predict the space states for one step ahead. A control method based on the dead beat control algorithm is described to regulate the output voltage of the LC filter so that disturbance of the output voltage due to load unbalances is eliminated. Simulation results for various operation conditions are presented to verify the validity of the control method.
PV G e n e r a to r D C /D C 2 DC S DC DC AC Z in t B a ttery Storage D C /D C 1 DC DC L in k 3 4 W ire In v e r t e r DC LC F ilte r L oad O u tp u t F ilte r

Fig.1: stand alone photovoltaic system with 3 phase 4 wire PWM voltage source inverter

1. INTRODUCTION
Nowadays more attention is paid to PV systems and their related technology for domestic applications as well as in large central power stations. PV systems are advantageous because they are abundant, pollution free and distributed through the earth. The only draw back is that the initial installation cost is considerably high. Since the power generated by an array of PV panels is direct-current, it may be transformed, either into a power with constant voltage for dc applications or into ac power. In both cases it is important to draw as much energy as possible from the PV panel. The output power of PV generators vary extensively with the weather conditions such as solar insulation, temperature and cloudy skies. To obtain the maximum power from such an array under any weather condition, it is necessary to connect the PV array to a converter that can adapt itself to the changing V-I characteristic of the PV generator (MPPT).

In the system illustrated in figure 1 this is provided by the DC/DC2. In this way the battery will be always charged at the Maximum Power Point. The goal of the system illustrated in figure 1 is to supply three as well as single phase loads of any art with constant amplitude sinusoidal voltage and constant frequency. For this propose the neutral point of the LC output filter and load is connected to the midpoint of the DC link capacitor bank. Due to load unbalances an intruding current flows throw the impedance between the neutral point and midpoint and a voltage drop occurs which distorts the symmetrical output voltage. To solve this problem the following measurements were taken a zero sequence current and voltage control is implemented a DC/DC converter is used to control the DC link voltage according to load unbalances In this way the symmetry of the output voltage is achieved and the linear region of the PWM

modulator of the DC/AC VSI (Voltage Source Inverter) is extended. For three phase inverters the dead beat control based on space vector was discussed in [3]. In [4] the disturbance observer, state variable observer and the dead beat control were combined to improve the transient and overall behaviour of the system. The digital control of the current minor loop for UPS applications to achieve quick and exact current response and to provide low THD of the output voltage waveform was described in [5]. The decoupling dead beat control of three phase inverter in dq-frame was explained in [1] and [2]. In [1] the voltage and current equations were discretised separately, thus the final discrete inverter model is simplified whereas in [2] the voltage and current equations were combined during the discretisation and thus a precise full inverter discrete model is provided. In this paper the dead beat control in [1] and [2] is adopted and extended to match for three phase four wire VSI. In addition, an observer is also implemented. The observer has the following tasks. Estimation of the load currents which act as disturbance on the plant
One step ahead prediction of the VSI voltages and currents

ib

i d+ R
2C b
u v

iu

iLu

Rb

vd Vb
2Cb

Zw Zv Zu

C idvu vN 0
RN0

iN 0

vCu

Fig.2: main circuit


V = I IL dt C d dt I = IR + V VC v N 0 d

(2)

(3) (4)

where

vN 0 = RN 0 (iu + iv + iw )
iu R L

iLu

vu

C vN0

vCu

Fig.3: average model of three phase four wire inverter with output LC filter The block diagram of phase u is illustrated in figure 4. The block GPWM describes the nonlinear behaviour of the PWM modulators. As it can be seen from this figure, the reference voltages of all three phases must stay within the linear region. In the conventional three phase inverter with balanced load and without fourth wire neutral connection the linear region will never be exceeded because the average of vN 0 = (d u + d v + d w )vd / 6 is equal zero. Whereas in three phase four wire inverter with unbalanced load the average value of vN0 in equation (4) is not equal zero, therefore the control output du must increase to compensate this value.

2. SYSTEM MODELING
In system proposed the neutral point of the output LC filter and the load are connected directly to the midpoint of the capacitor bank. Figure 2 illustrates the basic circuit of the VSI. The reference vector to be synthesised by the SPWM (Sinus Pulse Width Modulation) is given by the output of the control loop. For three phase four wire PWM inverter, the voltages and currents can be obtained by using the average circuit model of fig. 2 shown in figure 3. In figure 3 the voltages and the currents are given by

d = [d u d v d w ]

I = [iu iv iw ] , I L = [iLu iLv iLw ] ,


T T T

V = [vu vv vw ] , VC = [vCu vCv vCw ] ,


T T

du
(1)

GPWM
Vd 2 Ad

vN0 vu
1 sL+R

iLu iu

1 Zu 1 sC

vCu

where V = vd / 2 d

Fig.4: block diagram of the sine PWM inverter This component is the main reason for the saturation of the PWM modulator and therefore it must stay within a certain region [9].

and du ,dv and dw are the line to neutral duty cycles. The voltages and currents equations of the inverter and the output filter are given by

3. OUTPUT FILTER DESIGN


The output filter has to be designed to provide a sinusoidal output voltage with low voltage ripple.

3.1 FILTER FREQUENCY f0


The output voltage of the converter vu consists of the fundamental harmonic which is proportional to the modulation function and high frequency harmonics. When the carrier function is a symmetrical sawtooth signal, the high frequency harmonics are odd multiples of the carrier frequency fs (that is, fs, 3fs, 5fs, and so on). The harmonics which are even multiples of the carrier frequency are zero. The waveform of the output voltage vu also contains sidebands centred around multiples of fs and given by

From the figure one can see that a low voltage ripple (ku<5%) can be reached if the modulation factor is kept as high as possible and the ratio fs/f0 greater than 10. Minimum ripple is reached at fs/f0=14.5. The switching frequency of the inverter is 6kHz, that means the resonance frequency f0 of the filter is 413.8Hz.

3.2 POWER LOSSES MINIMISATION


The second step in the design approach is to find an appropriate value of inductor L so that the power losses of the inverter at nominal load are minimised. For this analysis it is enough to consider one phase of the inverter because all three phases are identical. Assuming that the major power losses corresponds to the conduction losses of the transistor, diode and the power losses in the inductor, caused by the resistance of the windings, the power losses of the three phase VSI can be written as

f h = n f s m f1

(5)

where fh and f1 are the frequencies of the sidebands and fundamental harmonics (reference signal), respectively, in Hz. The most dominate harmonics occur at the carrier frequency fs and the first sideband harmonics fh=fs2f1. For this reason the resonance frequency

P = 6 Ptr + 6 PD + 3PL
where

(7)

f 0 = 1 / 2 LC of the LC output filter must


fulfill the following condition:

f1 < f 0 < f h = f s 2 f1
10
0

(6)

Ptr conduction losses of a transistor PD conduction losses of diode PL power losses of the inductive L due to the
resistance of the windings The objective function to be minimised is

10 10

-2 0

M = 0 .001

P min
M = 0 .5

(8)

ku
10 10
-2 0

3.2.1 SWITCH CONDUCTION LOSSES


M=1
0 2 4 6 8 10 12 14 16 18 20

10

-2

The phase current of a PWM VSI can be approximated by its first harmonic
f s /f 0

) ) iu iu sin (1t ) = iu sin ( )

(9)

Fig.5: normalised voltage ripple versus the

frequency ratio fs/f0 Figure 5 shows the normalised voltage ripple in dependence on the frequency ratio f s / f 0 where
2 2 ku = vu , vu ,1 =1

The pulse period of the transistor can be written as

Ton ,tr =

Ts (1 + M sin ( )) 2

(10)

v
=1

2 u ,

and vu ,1 = M

vd 2

where Ts = 1 / f s the PWM period. Assuming that the ratio between the carrier and fundamental frequency f s / f1 is very high, the

and M is the modulation factor.

voltage and current of the transistor during the pulse time Ton ,tr can be considered as constant. The energy losses within Ton ,tr is given by

and the modulation factor is

M =
(11)

) 2vu vd

(18)

Eon ,tr ( ) = vCE (iC ( )) iC ( ) Ton,tr ( )

The angle in equation (14) represents the angle between the inverter output voltage vu and current iu respectively.
2 2 2 LC 2 RL + L RL C = arctan R + R + 2C 2 R 2 R L L

Substituting (9) and (10) in (11) will result in

) Eon ,tr ( ) = (VCE 0 + RBT iu sin ( )) ) T iu sin ( ) s (1 + M sin ( )) 2

(12)

(19)

When the ratio f s / f1 is very high, equation (12) can be considered as a differential equation by substituting Ts with d . The conduction losses of the transistor can be written as

3.2.2 DIODE CONDUCTION LOSSES The pulse time of the freewheeling diode is given by

sin ( )[1 + M sin ( )] d


Solving equation (13) will yield

) iu PTr = 4

[V

CE 0

) + RBT iu sin ( )
(13)

Ton , D =

Ts (1 M sin ( )) 2

(20)

In the same manner as in (3.2.1) the conduction losses of the diode can be written as

1 M ) Ptr = + cos iuVCE 0 2 8 )2 1 M + + cos iu RBT 8 3

(14)

1 M ) PD = cos iuVF 0 2 8 )2 1 M + cos iu RBD 8 3

(21)

where VCE 0 is the forward voltage drop of the IGBT and RBT is the conduction resistant. For a constant output voltage vCu, constant frequency and nominal load RL the inverter current can be written as

where VF 0 is the forward voltage drop of the diode and RBD is the conduction resistance. 3.2.3 INDUCTOR LOSSES The inductance of a cylinder air inductor is given by

iu ( ) = vCu ( )

1 + jRLC RL

(15)

and its magnitude as

2D2 N 2 l R = RW N

(22) (23)

) ) 1 2 iu = vCu 1 + (1RLC ) RL

(16)

and its resistance where

The magnitude of the inverter output voltage is

L R ) ) + 2 vu = vCu 1 2 LC + R + CR RL L

(17)

D inductor diameter N turns number l = dN inductor length d wire diameter RW resistance per turn

The ratio between two inductance is

L N R L1 N1 R1
and the power losses of the inductor is

(24)

PL =

1 )2 1) R iu R = iu2 L 1 2 2 L1

(25)

where R1 and L1 are the parameter of a reference inductor. Figur 6 illustrates the total power losses of equation (7) as a function of the inductance L. The power losses are normalised to the inverter output power.
1.3 1.2 1.1 1 0.9 0 4 8 12 L [mH] 16 20
P % P out

For experimental purpose a 1200V, 10A IGBT intelligent power module (IPM) from MITSUBISHI of type PM10RSH120 was used. The PWM signal was generated with a microcontroller of the type 80C166 from SIEMENS. Figure 7 shows the frequency spectra of the inverter output voltage vu for a DC link voltage of 106V. The filter inductor was optimised as described in (3.2) where the IGBT and diode data are given in the manufacturer data sheet. The inductor parameters were directly measured. The filter inductance and capacitance were optimised to 4mH and 60F respectively. The carrier frequency was set to fs=6.25kHz and the filter resonance frequency to f0=324.8Hz. For the frequency ratio of fs/f019 and the modulation factor of M0.5 the ripple factor can be red from figure 5 (ku2%). The measured ripple factor of the output voltage in figure 8 is (ku2.5%).
30

Filter Output Voltage [V]

vCu

vCw

vCv

Fig.6: power losses in dependence of the inductance L

3.3 EXPERIMENTAL RESULTS


The filter design approach was proved experimentally as illustrated in figure 7 and 8.
1 0.8 0.6 0.4 0.2 0

-30 0 16 t [ms]12 Fig.8: inverter output voltages 4 8 20

2 vu vd

f1 = 50 Hz f s = 6250 Hz

4. PROPOSED CONTROL
The control proposed of the VSI is illustrated in Figure 9. The output currents and voltages of the VSI will be measured and then led to a sample and hold unit which is necessary to keep the measured quantities constant while the analogue to digital converter (ADC) is working. The ADC is integrated in the microcontroller and works in the proposed control in multiplex mode as it can be seen from the figure. The discrete values of the currents and the voltages behind the ADC will be stored in the microcontroller buffer. The stored values of the currents and voltages will be transformed in the synchronised dq0-frame which rotates with the electrical output

40

80

120

Fig.7: frequency spectra of the normalised inverter output voltage 2vu vd

frequency of 50Hz. In this way, when the load is balanced, all AC quantities become DC quantities and thus the feedback control will not suffer from phase shifts. As the load currents act as disturbance on the plant, they will be fed forward to voltage and current control loop. The load current will be estimated by the observer and will not be measured directly. To compensate the time delay caused by the multiplex operation of the ADC the voltages and currents at the instant k must be fed back instead of k-1. These are indicated by I (ok ) , V( o ) and k

y (k )

v C (k 1) C d 11 0 0 = i 0 C d 22 0 (k 1) i L (k 1)

(29)

The state space model of the VSI can be expressed as:


x (k +1) = Ax (k ) + Bu ( k ) y ( k ) = Cx ( k 1)

(30) (31)

o L(k )

in figure 9. The index o indicates observed

To predict the VSI currents and voltages v C (k +1) and i ( k +1) at the sampling instant k, the output

quantities.
vd
PWM VSI L

y ( k +1) will be substituted in the observer


equation (32) instead of y ( k ) .
I
C

VC
Multiplex
S&H A/D Buffer

3 dq0

x (ok +1) = Ax ok ) + Bu (k ) + H(y (k +1) y ok ) ) ( (


VC(k-1)

(32)

Io(k)
Current Control

I(k-1) *
Voltage Control

V* VoC(k)

3 3 dq0 dq0 Observer & Predictor

where H is 6x6 identity matrix of the observer. Assuming that


? (k +1) = x ok +1) Hy (k +1) (

(33)

IoL(k)

Fig.9: principle of the control method

and dissolving (32) and concerning (33), the observer equation will be
? (k +1) = (A HC )(? (k ) + Hy (k ) ) + Bu (k )

4.1 PLANT MODEL


The currents and voltages equations in the time domain were combined to one sixth order matrix state equation. Thereafter, the resulting matrix was discretised and then transformed to the rotating dq0-frame as shown in (26).
v C ( k +1) Ad 11 Ad 12 v C ( k ) Bd 11 Bd 12 d ( k ) + = i ( k +1) Ad 21 Ad 22 i ( k ) Bd 21 Bd 22 i L ( k ) (26) 0 v C( k 1) C (27) y ( k ) = d 11 0 Cd 22 i (k 1)

(34)

and the output


x (ok ) = ? (k ) + Hy (k )

(35)

Figure 10 illustrates the observer structure.


Plant u(k)
x(k+1)=Ax(k)+Bu(k) y(k)=Cx(k-1)

Observer y(k)
H
? (k )

A-HC

4.2 OBSERVER DESIGN


The observer is designed to estimate the load currents. That is why the load currents are handled as a space state quantities (28) and not as disturbance as in (26).
v C(k +1) Ad11 Ad 12 Bd 12 v C( k ) Bd 11 (28) i ( k +1) = Ad 21 Ad 22 Bd 22 i ( k ) + Bd 21 d ( k ) i 0 0 C i 0 L(k ) L(k +1)

? (k +1)
B

1/z

x ok ) (

Fig.10: principle of the observer

4.3 CURRENT CONTROL LOOP


From (26) the currents equation can be written as
i ( k +1) = Ad 21 v C ( k ) + Ad 22 i ( k ) + Bd 21d ( k ) + Bd 22 i L (k ) (26)

where id ( k ) iLd (k ) vCd (k ) , , i (k ) = iq (k ) i L (k ) = iLq (k ) v C (k ) = vCq ( k ) and i i v 0(k ) L 0(k ) C 0(k )


d d (k ) d (k ) = d q(k ) d 0(k ) The first and second column of equation (26) express the relation of the inverter currents without the 0-component and can be written as

The first and second column of equation (38) express the relation of the inverter voltages without the 0-component and can be expressed as: d v vCd ( k +1) = A V Cd ( k ) + B V d ( k ) d v v q(k ) Cq ( k ) Cq ( k +1) i i (39) + CV d ( k ) + DV Ld ( k ) iq ( k ) iLq ( k ) where A V , B V CV and DV are 2x2 matrices which correspond to the first and second column in equation (38). The duty cycles d d (k ) d q ( k )

vCd ( k ) id ( k ) id ( k +1) = AI i + BI v i Cq ( k ) q (k ) q ( k +1) i d + C I d ( k ) + D I Ld ( k ) d q (k ) iLq ( k )

(27)

and the load currents

[i

Ld ( k )

iLq ( k ) act as a

A I , B I C I and D I are 2x2 matrices which correspond to the first and second column in equation (25) )
B Id c DIdc

) IL
DI BI

VC

) I

) d
GIC AIdc C Idc CI

) I
1/z AI

Fig.11 principle of the current control loop with decouplings Figure 11 illustrates the decoupled dead beat control of the inverter currents in the dq-frame. From (37) one can see that the d and the q variables are coupled with each other. To enhance the performance of the control loop the capacitor voltage and the load currents are fed forward as seen from figure 11. To control id and iq separately the coupling elements in AI and CI are decoupled by the matrices AIdc and CIdc so that id and iq depend only on the diagonal matrix elements AI. After removing the couplings, the dead beat controller GIC is provided.

disturbance on the voltage control loop in the rotating dq-frame. These disturbance quantities were compensated by feeding them forward through the decoupling matrices BVdc, DVdc. Figure 12 illustrates the decoupled dead beat control of the inverter voltages in the dq-frame. The matrices AVdc and CVdc are decoupling matrices so that the voltage vector of the output ) filter VC depends only on the diagonal matrix elements of AV. After removing the couplings, the dead beat controller GVC is provided. The same dead beat control is also applied to the 0-sequence of currents and voltages except that, in the 0 control loop no decouplings are needed [9].
B Vdc D Vdc

) IL
DV

) d

) VC
GVC AVdc CVdc

) I
CV

BV 1/z AV

) VC

Fig.12: principle of the voltage control loop with decouplings The mathematical model of the DC/DC converter in the continuous conduction mode is established and linearised ([6], [7]). The digital control is implemented [8] so that the DC link voltage will follow a certain reference [9].

4.4 VOLTAGE CONTROL LOOP


The voltage major loop is constructed in the same manner as the current minor loop. From (26) the voltage equations can be written as
v C(k +1) = Ad 11 v C (k ) + Ad 12 i (k ) + Bd 11d (k ) + Bd 12 i L (k )

5. SIMULATION RESULTS
Figure 13-15 illustrates the simulation results of the decoupled dead beat control with an observer for the following load cycle:

(38)

0.000.02s balanced load (ILu=ILv=ILw=1A0) 0.020.04s balanced load (ILu=ILv=ILw=2A0) 0.120.2s unbalanced load (ILu=ILv=10.4A0, ILw=2A0) Figure 13 shows the simulation results when an observer is used to estimate the load current and to predict the space states for the k+1st instant. From the simulation results one can see the high dynamic performance of the introduced observer based control method as the disturbance of the output voltage is quickly compensated. Figure 14 and 15 shows the original load currents and the load current estimated by the observer. From the figure it can be seen the high performance of the observer as the original load current almost the same as the estimated current.
400 300

5. CONCLUSION
In this paper the observer based digital control method of the 3 phase four wire PWM inverter for stand alone photovoltaic systems with battery energy storage was presented. Using an observer, there is no need to measure the load currents directly as the load currents can be estimated by the observer and thus saving money because no additional measuring instruments (LEM) are necessary. The output LC filter design for low ripple sinusoidal voltage and low power dissipation was described in detail in this paper. The resonance frequency of the output filter must be chosen for minimal ripple. The filter inductor value was chosen so that the whole system losses are minimised. The filter design approach was proved experimentally to illustrate the validity of the proposed design strategy. The measured and simulated ripple factor are almost the same.

Output voltage [V]

200 100 0 -100 -200 -300 -400 0.00

References
[1] Takao Kawabata, Takeshi Miyashita and Yushin Yamamoto, "Digital Control of three-Phase Inverter with LC Filter", IEEE Transactions on Power Electronics, Vol. 6, No. 1, January 1991, pp. 62-72. [2] Takao Kawabata, Takeshi Miyashita and Yushin Yamamoto, "Dead Beat Control of three-Phase PWM Inverter", IEEE Transactions on Power Electronics, Vol. 5, No. 1, January 1990, pp. 2128. [3] Osman Kkrer, "Deadbeat Control of a ThreePhase Inverter with an Output LC Filter", IEEE Transactions on Power Electronics, Vol. 11, No. 1, January 1996, pp. 16-23.
0.06

0.01

0 .02

0.03

0 .04

0.05

0.06

T im e [s]

Fig.13: voltages of the output filter


Load currents in the dq frame [A]
6 4 2 0 -2 -4 -6 -8 -10 -12 -14 0.00

o i Ld

i Ld

o i Lq
0.01 0.02 0.03 0.04

i Lq
0.05

T im e [ s ]

Fig.14: load current and estimated load current with the observer
3

[4] Tomoki Yokoyama and Atsuo Kawamura, "Disturbance Observer Based Fully Digital Controlled PWM Inverter for CVCF Operation", IEEE Transactions on Power Electronics, Vol. 9, No. 5, September 1994, pp. 473-480. [5] Youichi Ito and Shoichi Kawauchi, "Microprocessor-Based Robust Digital Control for UPS with Three -Phase PWM Inverter", IEEE Transactions on Power Electronics, Vol. 10, No. 2, March 1995, pp. 196-204. [6] P. R. K. Chetty "Current Injected Equivalent Circuit Approach to Modeling and Analysis of Current Programmed Switching DC-DC Converters (Discontinuous Inductor Conduction Mode)", IEEE Transactions on Industrial Applications, Vol. IA-18, No. 3, May/June 1982, pp. 295-299.

o-sequence load current [A]

o iL 0

iL 0

-1

-2

-3

-4 0.00

0.01

0.02

0.03

0.04

0.05

0.06

T im e [ s ]

Fig.15: 0-sequence load current and estimated 0sequence load current with the observer

[7] Francisco Guinjoan, Javier Calvente, Alberto Poveda and Luis Martinez, "Large-Signal Modeling and Simulation of Switching DC-DC Converter", IEEE Transactions on Power Electronics, Vol. 12, No. 3, May 1997, pp. 485494. [8] F. Al-Hosini, ABB Corporate Research, Sweden, "An Approximate Dead-Beat Control strategy for the design of functions regulators in DC/DC Converters", EPE Trondheim 1997, Vol. 3, pp. 155-160. [9] Said El-Barbari, W. Hofmann,Discrete Time Control of a Three Phase 4 Wire PWM Inverter with Variable DC Link Voltage and Battery Storage for PV Application,PCIM POWER QUALITY98 Nrnberg, proceedings, pp.183191.

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