Assembler Instructions

ASSEMBLER INSTRUCTIONS
Contents
DSECT - Dummy section or data section.............................................................................................................................................3 Definition Types (Formats)...............................................................................................................................................................4 Boundaries.........................................................................................................................................................................................4 ORG - Organize.....................................................................................................................................................................................5 EQU - Equates.......................................................................................................................................................................................6 Padding / Truncation.............................................................................................................................................................................7 Desk assembly.......................................................................................................................................................................................8 Desk assembly: coding......................................................................................................................................................................9 Desk assembly: 1st compiler run (location counter)......................................................................................................................10 Desk assembly: 2nd compiler run (translation to machine code)...................................................................................................11 Assembler instructions........................................................................................................................................................................12 A short introduction to the Assembler............................................................................................................................................12 A Add fullword........................................................................................................................................................................14 AH Add Halfword....................................................................................................................................................................15 AP Add packed decimal data...................................................................................................................................................16 AR Add register........................................................................................................................................................................17 BAS Branch and save...............................................................................................................................................................18 BASR Branch and save register...............................................................................................................................................19 BC Branch on condition...........................................................................................................................................................20 BCR Branch on condition register...........................................................................................................................................21 BCT Branch on count...............................................................................................................................................................22 BCTR Branch on count register...............................................................................................................................................23 BXLE Branch on index low or equal.......................................................................................................................................24 C Compare fullword.................................................................................................................................................................25 CH Compare Halfword.............................................................................................................................................................26 CL Compare logical fullword..................................................................................................................................................27 CLC Compare logical character...............................................................................................................................................28 CLCL Compare logical character long....................................................................................................................................29 CLI Compare logical immediate..............................................................................................................................................30 CLR Compare logical register.................................................................................................................................................31 CP Compare packed decimal data............................................................................................................................................32 CR Compare register................................................................................................................................................................33 CVB Convert to binary.............................................................................................................................................................34 CVD Convert to decimal..........................................................................................................................................................35 D Divide fullword....................................................................................................................................................................36 DC Define constant..................................................................................................................................................................37 DP Divide packed decimal data...............................................................................................................................................39 DR Divide register...................................................................................................................................................................40 DS Define storage....................................................................................................................................................................41 ED Edit.....................................................................................................................................................................................42 EDMK Edit and mark...............................................................................................................................................................43 EX Execute...............................................................................................................................................................................44 IC Insert character....................................................................................................................................................................45 ICM Insert character under mask.............................................................................................................................................46 L Load fullword........................................................................................................................................................................47 LA Load address......................................................................................................................................................................48 LCR Load complement register...............................................................................................................................................49 LH Load Halfword...................................................................................................................................................................50 LM Load multiple....................................................................................................................................................................51 LNR Load negative register.....................................................................................................................................................52 LPR Load positive register.......................................................................................................................................................53 LR Load register.......................................................................................................................................................................54 LTR Load and test register.......................................................................................................................................................55 M Multiply fullword................................................................................................................................................................56 MH Multiply Halfword............................................................................................................................................................57 MP Multiply packed decimal data...........................................................................................................................................58 MR Multiply register...............................................................................................................................................................59 MVC Move character...............................................................................................................................................................60 MVCL Move character long....................................................................................................................................................61 MVI Move immediate..............................................................................................................................................................62 MVN Move numeric................................................................................................................................................................63 MVO Move with offset............................................................................................................................................................64 MVZ Move zone......................................................................................................................................................................65
TPF Basic Course

Assembler Introduction
N And fullword........................................................................................................................................................................66 NC And character.....................................................................................................................................................................67 NI And immediate....................................................................................................................................................................68 NR And register........................................................................................................................................................................69 O Or fullword...........................................................................................................................................................................70 OC Or character........................................................................................................................................................................71 OI Or immediate......................................................................................................................................................................72 OR Or register..........................................................................................................................................................................73 PACK Pack...............................................................................................................................................................................74 S Subtract fullword..................................................................................................................................................................75 SH Subtract Halfword..............................................................................................................................................................76 SLA Shift left single arithmetic...............................................................................................................................................77 SLDA Shift left double arithmetic...........................................................................................................................................78 SLDL Shift left double logical.................................................................................................................................................79 SLL Shift left single logical.....................................................................................................................................................80 SP Subtract packed decimal data.............................................................................................................................................81 SR Subtract register..................................................................................................................................................................82 SRA Shift right single arithmetic.............................................................................................................................................83 SRDA Shift right double arithmetic.........................................................................................................................................84 SRDL Shift left double logical.................................................................................................................................................85 SRL Shift right single logical...................................................................................................................................................86 SRP Shift and round packed decimal data...............................................................................................................................87 ST Store fullword.....................................................................................................................................................................88 STC Store character.................................................................................................................................................................89 STCM Store character under mask..........................................................................................................................................90 STH Store Halfword.................................................................................................................................................................91 STM Store multiple..................................................................................................................................................................92 TM Test under mask................................................................................................................................................................93 TR Translate.............................................................................................................................................................................94 TRT Translate and test.............................................................................................................................................................95 UNPK Unpack..........................................................................................................................................................................96 X Exclusive or fullword...........................................................................................................................................................97 XC Exclusive or character........................................................................................................................................................98 XI Exclusive or immediate......................................................................................................................................................99 XR Exclusive or register........................................................................................................................................................100 ZAP Zero and add packed decimal data.................................................................................................................................101
1998 Atraxis AG, TPFDF Support , Zurich-Airport, Switzerland
Printed 29. Jul 2011
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TPF Basic Course

DSECT - Dummy section or data section
DSECTs are defined to avoid 'base-register and displacement'-coding and to make the source code more readable. Example: Address L80 Name & First Name L30 Name L14
06A 06C 000 000 000 00E 010 01E 01E 038 03C 03C 040 050 06A
Street & Nbr L30 Street L26

DS DSECT DS DS DS DS DS DS DS DS DS DS DS CSECT DS H 0CL80 0CL30 CL14 CL2 CL14 0CL30 CL26 CL4 0CL20 CL4 CL16 CL2
P-Code & Cityname L20 P-Code L4 Cityname L16
1st Name 2 L14
Nbr L4
LAST ADDRESS ADDR NA NAME FNAME STR STREET NBR CITY PCODE CITYNAME $IS$ NEW
label of the previous DSECT relative address is set to 000
relative addr. is reset to previous relative addr. label of the previous DSECT
a DSECT is a layout-definition of one or more a logical records (LRECs / Datasets). no storage is allocated !!! the end of a DSECT is marked by one of the macros CSECT, DSECT, END or FINIS. each used DSECT in a program has its own defined base-register done with USING, for example: USING R4,ADDRESS.
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Definition Types (Formats)
C X F H D A B P
Character format (EBCDIC, Extended Binary Coded - Decimal Interchange Code): 1 EBCDIC-character in 1 byte Hexadecimal format: 2 hex-digits in 1 byte Fullword format: Signed decimal number in a 4-byte field (on boundary) Halfword format: Signed decimal number in a 2-byte field (on boundary) Doubleword format: Signed decimal number in an 8-byte field (on boundary) Note: No DC possible with this type! Address-Constant format: Address-value in a 4-byte field (on boundary) Binary format: 8 binary digits in 1 byte Packed Decimal format: 2 decimal digits in 1 byte (signed)
Boundaries
There are 3 types of boundaries: Doubleword boundary (relative address is divisible by 8) Fullword boundary (relative address is divisible by 4) Halfword boundary (relative address is divisible by 2)
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ORG - Organize
000 050 000 01E 000 00E 010 01E 03C 01E 022 03C 050 03C 040 ADDRESS ADDR NAME LNAME FNAME STREET NUMBER STR CITY PCODE CITYN $IS$ 000 050 000 01E 03C 050 000 00E 010 01E 022 . . ADDRESS ADDR NAME STREET CITY LNAME FNAME NUMBER STR . . DSECT DS ORG DS ORG DS DS DS DS ORG DS DS DS ORG DS DS ORG CSECT DSECT DS ORG DS DS DS ORG DS DS DS DS DS . . CL80 ADDR CL30 NAME CL14 CL2 CL14 CL30 ADDR+30 CL4 CL26 CL20 STR+26 CL4 CL16 ADDR+80
CL80 ADDR CL30 CL30 CL20 ADDR CL14 CL2 CL14 CL4 CL26 . .
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EQU - Equates
Special Character Equates #CR Carriage Return #SP Blank #DOT Dot #EOM End of message #END Enditem (!,#) #FC Asterisk #HYPH Dash #SLASH Slash #SOM Start of message #CHA At-sign #APO Apostrophe X15 X40 X4B X4E X4F X5C X60 X61 X6E X7C X7D C C. C+ C! C* C- C/ C> C@ C
Equates are used to attach a value to a label. They are very often used for length calculations. Examples: VALUE1 FIELDA VALUE2 01E 022 03C 040 NBR STREET PCODE VALUE3 VALUE4 VALUE5 VALUE6 VALUE7 VALUE8
System
EQU DS EQU DS DS DS EQU EQU EQU EQU EQU EQU
20 CL40 LFIELDA CL4 CL26 CL4 * PCODE-NBR STREET+5 X44 CA B01111111
X14 / 2010 X28 / 4010
X40 / 6410 3C16-1E16 = 1E16 02216+516 = 2716 X44 / 6810 XC1 X7F / 12710
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Padding / Truncation
Padding Truncation FIELDA FIELDB FIELDC FIELDD FIELDE FIELDF FIELDG FIELDG = fill up / complete = cut off DC DC DC DC DC DC DC DC CL4ABCDEF
Truncation
C1C2C3C4 F1F2F3F44040
Padding
CL61234 XL289ABCDE
Truncation
BCDE 000567AB
Padding
XL4567AB P-1234 P324 PL21234 B11001

Truncation
01234D
Sign
324C 234C B00011001
Padding Sign
Padding
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TPF Basic Course

Desk assembly
Input + 30 XXX.XX
Input (L'=80)
1st step: copy

Output + 45 CCC.CC
Output (L'=133)
Output + 80 DDDD.DD
2nd step: duplicate
Input
XXX.XX
3 decimal digits followed by a dot and then again 2 decimal digits i.e. 123.45 EBCDIC: F1 F2 F3 4B F4 F5 075.01 EBCDIC: F0 F7 F5 4B F0 F1 999.99 EBCDIC: F9 F9 F9 4B F9 F9
Task Notes inserted
The input number is to be copied from the input line to the output line (1st step). As next the copied number is to be duplicated and the result is also placed on the output line (2nd step). Duplication is to be executed using binary arithmetics, i.e. the dot (X'4B') is to be removed for proper conversion and calculation. The same procedure us used the way back to put the result on the output line, i.e. the dot is to be at the correct location. DSECTs / fields and base registers see on next page. The binary value should be placed within register R5 for calculation. To duplicate the value use the Assembler instruction AR (Add register): i.e. AR R5,R5.
Steps
1. coding (after reviewing some solutions hand out of the course' coding solution 2. fill in the location counter (review of your solutions, hand out of 'our' solution) 3. translation of the source code into the machine code (review, hand out of the final solution)
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Desk assembly: coding
(Solution will be handed out; solution in ASSDesk.doc) Location counter 000 ... Machine code 8 bytes of macro coding 64 bytes of machine coding
Code (editor in TSO)

BEGIN some Assembler instructions MVC ...
152 bytes of machine code
some more Assembler instructions FINIS
DSECTs / field definitions WORK 000 ... CONVERT TASK1 ... ... INPUT OUTPUT $IS$ DSECT DS DSECT DS DS CSECT USING USING WORK,R7 TASK1,R3 CL80 CL133 D 268 bytes of previous definitions
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TPF Basic Course

Desk assembly: 1st compiler run (location counter)
(Solution will be handed out; solution in ASSDesk.doc)
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TPF Basic Course

Desk assembly: 2nd compiler run (translation to machine code)
(Solution will be handed out; solution in ASSDesk.doc)
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TPF Basic Course

Assembler instructions
A short introduction to the Assembler
It is not possible to communicate directly with a machine using a human language. Therefore we have to establish a code by which we can pass information to the machine or computer. The nature of this code is determined by the requirements and capabilities of the machine in question. If we use electric current, which creates tiny magnetic fields, the machine can distinguish between two states: positive and negative. If the magnetic fields (states) are lined up sequentially, we can define particular combinations of states to equate to a human alphabet. Thus it is possible to code our language in such a way that a machine can process it. The above kind of code is called machine code, and is based on the binary system. Thus each of "our" characters is defined as a particular combination of "ones" and "zeroes". The definitions are internationally standardised in code-tables. Large systems often use the EBCDIC code-table (Extended Binary-Coded Decimal Interchange Code): here "A" = "11000001". Personal Computers almost exclusively use the ASCII code-table (American Standard Code for Information Interchange): here "A" = "1000001". In the early days of data processing a programmer had to write his program in the machine code format, a sequence of states (bits) like this: 1101001000000001... . A little help here is the hexadecimal display of the machine code: D2015014F02E. But as you can see this 1st generation language is hard to understand and to learn. The hexadecimal string shown above is one instruction! Imagine the work involved and the possibilities of errors in a program with hundreds or thousands of instructions written in this machine language. To simplify the programmer's work, other programming languages were developed, which use mnemonic operation codes and symbolic addresses. The production or the maintenance of programs is much easier now. These alphanumeric symbols are more declarative and easier to understand than a hexadecimal string. The assembler language is the next-higher programming language of the machine language. It's a machine-orientated language of the 2nd generation, using symbolic instructions. 2nd-generation means that the conversion of one assembler instruction results in one machine-code instruction. (Example: MVC FIELDA,FIELDB == D2015014F02E ). Once again, each instruction in the source code is assembled to a single instruction in machine language. This conversion is done by a translation program, a compiler (here called assembler). After the conversion, there are two programs: one program still in source code, and one program in machine code. The other translation program is called an interpreter. This program also translates source code to machine code, but in a different way: after translation of a single 'source' instruction, the resulting 'machine' instruction will be executed immediately. In the end, there is no program in machine code. If the program starts again, it has to be translated (interpreted) again. Certainly a compiler-program is more complicated, but in the end it's faster and cheaper than an interpreter-program. The machine orientation and the lack of structured programming are reasons an assembler programmer uses or needs more time to code a program. But the product has the advantage of using the capabilities of the computer in a more direct and efficient way. The coding of a program in a language of the 3rd or a higher generation, for example COBOL, PASCAL, C or PL/1, is often simpler and faster. These languages are problem-orientated and their structures and symbolic conventions are closer to the human language. Therefore they are easier to learn. There are, then, three levels of computer languages: machine language, symbolic language (assembler), and high-level language. The computer only understands the bits comprising the machine language instruction.
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User
Writing the Source-Code
Software
Editor
Data
Source-Program
Assembly of the SourceProgram
Assembler
Object-Program in Machine-Code
Linking with other Programs
Linkage Editor / Binder
Processable Program
Page 13 of 101
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Add fullword
Operands
Mnemonic
A
Machine format (RX)
R1 , D2 (X2 , B2)
R1
8
5A
0
X2
12
B2
16 20
D2
31
A four byte field in storage containing a binary value has to be added to the binary value of a register. The A (Add fullword) instruction handles this problem. The data of the 2nd-operand field, a fullword (->> boundary!) in storage, is added to the contents of the 1st-operand register and the resulting sum is placed in the 1st-operand register. The operands and the result are treated as 32-bit signed binary integers. The 2nd-operand field remains unchanged. The calculation follows algebraic rules. The result is tested and a condition code is set. If the result does not fit into the 1st-operand register an overflow occurs and additionally the condition code is set to 3. The 2nd field, a fullword (->> boundary!) in storage, is left unchanged.
Condition codes 0 =0 result is zero 1 <0 result is negative 2 >0 result is positive 3 overflow result doesnt fit into the 1st operand register Graphical example
R15 00 07 E2 2F +
BINARY ADDITION
FIELDA 00 00 08 43
R15 00 07 EA 72 A R15,FIELDA
The First operand contains the RESULT of the calculation. The second operand remains unchanged !
Page 14 of 101
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AH
Mnemonic
Add Halfword
Operands
AH
Machine format (RX)
R1 , D2 (X2 , B2)
R1
8
4A
0
X2
12
B2
16 20
D2
31
A two byte field in storage containing a binary value has to be added to the binary value of a register. The problem can be solved by using the AH (Add Halfword) instruction. The data of the 2nd-operand field, a halfword (->> boundary!) in storage, is added to the contents of the 1st-operand register and the resulting sum is placed in the 1st-operand register. The 2nd-operand field is treated as a 16-bit signed binary integer. The 1st-operand register and the result are treated as 32-bit signed binary integers. The 2nd-operand field remains unchanged. The calculation follows algebraic rules. The result is tested and a condition code is set. If the result does not fit into the 1st-operand register an overflow occurs and additionally the condition code is set to 3. Condition codes 0 =0 result is zero 1 <0 result is negative 2 >0 result is positive 3 overflow result doesnt fit into the 1st operand register Graphical example
R3 00 00 00 07 +
BINARY ADDITION
FIELDB FF F6
R3 FF FF FF FD AH R3,FIELDB
Page 15 of 101
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AP
Mnemonic
Add packed decimal data

Operands
AP
Machine format (SS2)
D1 (L1 , B1) , D2 (L2 , B2)

L1
8
FA
0
L2
12
B1
16 20
D1
B2
32 36
D2
47
Two fields containing packed decimal data have to be added. The instruction AP (Add Packed decimal data) will do this in one step. The contents of the 2nd-operand field are added to the contents of the 1st-operand field and the resulting sum is placed in the 1st-operand field. The initial contents of both operand fields have to be in correct packed decimal format, otherwise the instruction results in a system error (Data Exception). The result is also in packed decimal format. The 2nd-operand field remains unchanged. The calculation follows algebraic rules. The result is tested and a condition code is set. In case of an overflow the overflow digits are ignored and additionally the condition code is set to 3.a condition code
Condition codes 0 =0 result is zero 1 <0 result is negative 2 >0 result is positive 3 overflow result doesnt fit into the 1st operand field Graphical example
FIELD1 00 07 02 93 2C +
DECIMAL ADDITION OF PACKED DATA
FIELD2 00 00 08 4C
FIELD1 00 07 03 01 6C AP FIELD1,FIELD2
Page 16 of 101
TPF Basic Course

AR
Mnemonic
Add register
Operands
AR
Machine format (RR)
R1 , R2
R1
8
1A
0
R2
12 15
To add the contents of two registers, the AR (Add Register) instruction is performed. The contents of the 2nd-operand register are added to the contents of the 1st-operand register and the resulting sum is placed in the 1st-operand register. The operands and the result are treated as 32-bit signed binary integers. The 2nd-operand register remains unchanged. The calculation follows algebraic rules. The result is tested and a condition code is set. If the result does not fit into the 1stoperand register an overflow occurs and additionally the condition code is set to 3.rmed. The contents of the 2nd-operand remain unchanged.
R5 FF FF FF FC +
BINARY ADDITION
R6 00 00 00 11
R5 00 00 00 0D AR R5,R6
Page 17 of 101
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BAS
Mnemonic
Branch and save

Operands
BAS
Machine format (RX)
R1 , D2 (X2 , B2)
R1
8
4D
0
X2
12
B2
16 20
D2
31
Unconditional branching within a program and the possibility to return to the branch-point is performed by the BAS (Branch And Save) instruction. The address of the next sequential instruction (NSI) is placed in the 1st-operand register. Subsequently a branch is made to the location given by a 2nd-operand label. The instruction(s) is commonly used to branch to a subroutine with an expected return. Now to return, the help of the unconditional BR (Branch Register) instruction is needed (see the BC instruction). See also the BASR instruction.
Condition codes Condition code remains unchanged! Graphical example
Instruction g Instruction h BAS Reg1,Branch-label

Main Processing
==>
Next Seq. Instr (NSI) Instruction j
The address of the NSI is saved in the 1st operand register !
Subroutine
Branch-label Instruction x Instruction y Instruction z BR Reg1 (Return) ==> Return to address saved in the 1st operand register !
Page 18 of 101
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BASR
Mnemonic
Branch and save register

Operands
BASR
Machine format (RR)
R1 , R2
R2
12 15 8
0D
0
R1
Unconditional branching within a program and the possibility to return to the branch-point is also performed by the BASR (Branch And Save Register) instruction. The address of the next sequential instruction (NSI) is placed in the 1st-operand register. Subsequently a branch is made to the location given by the address within the 2nd-operand register. The instruction(s) is commonly used to branch to a subroutine with an expected return. Now to return, the help of the unconditional BR (Branch Register) instruction is needed (see the BC instruction). See also the BAS instruction.
Main Processing
Instruction g Set up Branch-Reg2 BASR Reg1,Branch-Reg2 Next Seq. Instr (NSI) Instruction j ==> The address of the NSI is saved in the 1st operand register !
Subroutine
Branch-label Instruction x Instruction y Instruction z BR Reg1 (Return) ==> Return to address saved in the 1st operand register !
Page 19 of 101
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BC
Mnemonic
Branch on condition
Operands
BC
Machine format (RX)
M1 , D2 (X2 , B2)
M1
8
47
0
X2
12
B2
16 20
D2
31
To react on a condition code, which was previously set in the Program Status Word (PSW), the BC (Branch on Condition) instruction is performed. A 4-bit binary mask (1st operand) is used to test the condition code. If the condition is true, a branch is made to the target-location (2nd operand) given by a label; otherwise the next sequential instruction (NSI) is processed. Instead of coding the 1st-operand mask as in BC 8,LABEL , very often the extended mnemonic instructions are coded as in BZ LABEL . The full set of extended mnemonic branch-instructions is listed in the System/370 Extended Architecture Reference Summary. See also the BCR instruction.
Condition Code 0 (00) 1 (01) 2 (10) 3 (11)
Mask Position Value 8 4 2 1
Op. Code
M1
X2
B2
D2
Bit-Value (Mask Position Value)
Page 20 of 101
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BCR
Mnemonic
Branch on condition register

Operands
BCR
Machine format (RR)
R1 , R2
R1
8
07
0
R2
12 15
To react on a condition code, which was previously set in the Program Status Word (PSW), the BCR (Branch on Condition Register) instruction is performed. A 4-bit binary mask (1st operand) is used to test the condition code. If the condition is true, a branch is made to the target-location (2nd operand) given by the address within a register; otherwise the next sequential instruction (NSI) is processed. Instead of coding the 1st-operand mask as in BCR 11,R7 , very often the extended mnemonic instructions are coded as in BNMR R7 . The full set of extended mnemonic branch-instructions is listed in the System/370 Extended Architecture Reference Summary. See also the BC instruction.
Condition Code 0 (00) 1 (01) 2 (10) 3 (11)
Mask Position Value 8 4 2 1
Op. Code
M1
R2
Bit-Value (Mask Position Value)
Page 21 of 101
TPF Basic Course

BCT
Mnemonic
Branch on count
Operands
BCT
Machine format (RX)
R1 , D2 (X2 , B2)
R1
8
46
0
X2
12
B2
16 20
D2
31
One possibility to control a loop is the do times option. The instruction BCT (Branch on CounT) will handle this in following steps. First step: the contents of the 1st-operand register is subtracted by one. Second step: The result is checked for zero. Third step: If the result is not zero a branch is made to the location given by the 2nd-operand label; if the result is zero the next sequential instruction (NSI) is processed. See also the BCTR instruction.
Set up Loop-Count in Reg1 Label Start of Loop with instruction x Instruction y

If Reg1 not Zero ==> Branch to Label
BCT Reg1,Label Next Seq. Instr (NSI)
If Reg1 = Zero ==> NSI
Page 22 of 101
TPF Basic Course

BCTR
Mnemonic
Branch on count register

Operands
BCTR
Machine format (RR)
R1 , R2
R2
12 15 8
06
0
R1
One possibility to control a loop is the do times option. Also the instruction BCTR (Branch on CounT Register) will handle this in following steps. First step: the contents of the 1st-operand register is subtracted by one. Second step: The result is checked for zero. Third step: If the result is not zero a branch is made to the location given by the address within the 2nd-operand register; if the result is zero the next sequential instruction (NSI) is processed. See also the BCT instruction.
Set up Loop-Count in Reg1 Set up Branch-Address in Reg2 (Addr. of Label) Label Start of Loop with instruction x Instruction y
If Reg1 not Zero ==> Branch to Label
BCTR Reg1,Reg2 Next Seq. Instr (NSI)
If Reg1 = Zero ==> NSI
Page 23 of 101
TPF Basic Course

BXLE
Mnemonic
Branch on index low or equal

Operands
BXLE
Machine format (RS)
R1 , R3 , D2 (B2)
R3
12
87
0
R1
8
B2
16 20
D2
31
One possibility to control a loop is the do until option. The instruction BXLE (Branch on indeX Low or Equal) will handle this in the following steps. First step : An increment is added top the 1st operand index-register. Second step : The result is compared with a comparand. Third step : The result of the comparison determines if a branch occurs or not. If the value of the index-register is low or equal to the value of the comparand a branch is made to the location given by the 2nd operand label; if it is higher the next sequential instruction (NSI) is processed. The increment and the comparand values are designated by the 2nd operand even-odd register pair. See also the BXH instruction within the POP on page 7-13 ! Condition codes Condition code remains unchanged! Graphical example
2nd Operand (Branch Address) 1st Operand (register) 3rd Step : BRANCH to the 2nd-operand branch address if the index-register is lower or equal than the comparand-register 2nd Step : COMPARE
INDEX
1st Step : ADD
3rd Operand (Even / odd register pair) INCREMENT
COMPARAND
Page 24 of 101
TPF Basic Course

Compare fullword
Operands
Mnemonic
C
Machine format (RX)
R1 , D2 (X2 , B2)
R1
8
59
0
X2
12
B2
16 20
D2
31
To compare the arithmetic value of a register with the value of a four byte field in storage, the C (Compare fullword) instruction is performed. The data of the 1st-operand register is compared with the data of the 2nd-operand field, a fullword (->> boundary!) in storage. The result of the comparison is indicated in the condition code which may be checked subsequently. The operands are treated as 32-bit signed binary integers and remain unchanged.
Condition codes 0 1. = 2. operands are equal 1 1. < 2. 1st operand register is lower than the 2nd operand fullword 2 1. > 2. 1st operand register is greater than the 2nd operand fullword 3 not used! Graphical example
R1 00 02 F8 A3
FIELDE 00 02 01 40
COMPARISON The result is indicated in the CONDITION CODE ! Both operands remains unchanged !
C R1,FIELDE
Page 25 of 101
TPF Basic Course

CH
Mnemonic
Compare Halfword
Operands
CH
Machine format (RX)
R1 , D2 (X2 , B2)
R1
8
49
0
X2
12
B2
16 20
D2
31
To compare the arithmetic value of a register with the value of a two byte field in storage, the CH (Compare Halfword) instruction is performed. It will do this in two steps. First step: the data of the 2nd-operand field, a halfword (->> boundary!) in storage, is extended to a 32-bit interim field. The extension bits are the same as the high-order bit of the 2nd-operand field. Second step: The data of the 1st-operand register is compared with the data of the interim field. The result of the comparison is indicated in the condition code which may be checked subsequently. The 1st operand is treated as a 32-bit signed binary integer and the 2nd operand is treated as a 16-bit signed binary integer. Both operands remain unchanged.
Condition codes 0 1. = 2. operands are equal 1 1. < 2. 1st operand register is lower than the 2nd operand Halfword 2 1. > 2. 1st operand register is greater than the 2nd operand Halfword 3 not used! Graphical example
R1 FF A8 92 B7
FIELDE 92 B6
CH R1,FIELDE
Page 26 of 101
TPF Basic Course

CL
Mnemonic
Compare logical fullword

Operands
CL
Machine format (RX)
R1 , D2 (X2 , B2)
R1
8
55
0
X2
12
B2
16 20
D2
31
To compare logically the contents of a register with the contents of a four byte field in storage, the CL (Compare Logical fullword) instruction is performed. The data of the 1st-operand register is compared with the data of the 2nd-operand field, a fullword (->> boundary!) in storage. Execution proceeds from left to right, bit by bit, and stops as soon as an unequality is recognized or the end of the 1st-operand register is reached. The result is indicated in the condition code which may be checked subsequently. The sign of the operands does not affect the result of the comparison. Both operands remain unchanged.
Condition codes 0 1. = 2. operands are equal 1 1. < 2. 1st operand register is lower than the 2nd operand fullword 2 1. > 2. 1st operand register is greater than the 2nd operand fullword 3 not used! Graphical example
R3 00 05 FC 20
FIELDI 82 02 09 A1
CL R3,FIELDI
Page 27 of 101
TPF Basic Course

CLC
Mnemonic
Compare logical character

Operands
CLC
Machine format (SS1) 0
D1 (L1 , B1) , D2 (B2)

8
D5
L1
B1
16
20
D1
B2
32
36
D2
47
Logical data comparisons of two storage locations are performed by the CLC (Compare Logical Characters) instruction. The data of the 1st-operand field is compared with the data of the 2nd-operand field. Execution proceeds from left to right, bit by bit, and stops as soon as an unequality is recognized or the end of the 1st-operand field is reached. The length is defined by the 1stoperand field (see also the MVC instruction). The result is indicated in the condition code which may be checked subsequently. The sign of the operands does not affect the result of the comparison. Both operands remain unchanged.
Condition codes 0 1. = 2. operands are equal 1 1. < 2. 1st operand field is lower than the 2nd operand field 2 1. > 2. 1st operand field is greater than the 2nd operand field 3 not used! Graphical example
FIELDJ 00 05 FC
FIELDK 82 09 04 40 B8
CLC FIELDJ,FIELDK
Page 28 of 101
TPF Basic Course

CLCL
Mnemonic
Compare logical character long

Operands
CLCL
Machine format (RR)
R1 , R2
R2
12 15 8
0F
0
R1
Logical data comparisons of two large storage locations are performed by the CLCL (Compare Logical Characters Long) instruction. The data of the 1st-operand field (designated by the 1st-operand register-pair) is compared with the data of the 2ndoperand field (designated by the 2nd-operand register-pair). The maximum number which can be compared are 16777215 bytes of data. The instruction recommends even-odd pairs of registers. The shorter operand field is considered to be extended on the right with padding bytes. Execution proceeds from left to right, bit by bit, and stops as soon as an inequality is recognized or the end of the larger operand field is reached. The result is indicated in the condition code which may be checked subsequently. Both operands remain unchanged.
R4 storage address
R6 storage address
C3 C1 E3
..
C3 C1 E3
..
CLCL R4,R6
The number of bytes to be compared is in R5 (TOLENGTH) and R7 (FROM-LENGTH) ! The result of the comparison is indicated in the CONDITION CODE !
Page 29 of 101
TPF Basic Course

CLI
Mnemonic
Compare logical immediate

Operands
CLI
Machine format (SI) 0
D1 (B1) , I2
8
95
I2
B1
16
20
D1
31
To compare logically a single byte of data, defined at program coding, with the data of a storage location, the CLI (Compare Logical Immediate) instruction is performed. The data of the 1st-operand field is compared with the data of the 2nd-operand. The single byte of the 2nd operand is also called the immediate operand (format specifications see the MVI instruction). Execution proceeds from left to right, bit by bit, and stops as soon as an unequality is recognized or the end of the 1st-operand field is reached. The immediate data to be compared is contained within the instruction itself. The length of the 1st-operand field is not of interest. Only the 1st byte of the field is compared. The result is indicated in the condition code which may be checked subsequently. The sign of the operands does not affect the result of the comparison. The 1st-operand field remains unchanged.
Condition codes 0 1. = 2. operands are equal 1 1. < 2. 1st operand byte is lower than the 2nd operand immediate value 2 1. > 2. 1st operand byte is greater than the 2nd operand immediate value 3 not used! Graphical example
FIELDL 20
IMMEDIATE VALUE 6F
CLI FIELDL,X6F
Page 30 of 101
TPF Basic Course

CLR
Mnemonic
Compare logical register

Operands
CLR
Machine format (RR)
R1 , R2
R1
8
15
0
R2
12 15
Logical data comparisons of two registers are performed by the CLR (Compare Logical Register) instruction. The data of the 1stoperand register is compared with the data of the 2nd-operand register. Execution proceeds from left to right, bit by bit, and stops as soon as an unequality is recognized or the end of the 1st-operand register is reached. The result is indicated in the condition code which may be checked subsequently. The sign of the operands does not affect the result of the comparison. Both operands remain unchanged.
Condition codes 0 1. = 2. operands are equal 1 1. < 2. 1st operand register is lower than the 2nd operand register 2 1. > 2. 1st operand register is greater than the 2nd operand register 3 not used! Graphical example
R6 FF F8 20 9C
R7 FF F7 6F 11
CLR R6,R7
Page 31 of 101
TPF Basic Course

CP
Mnemonic
Compare packed decimal data

Operands
CP
D1 (L1 , B1) , D2 (L2 , B2)

L1
8
F9
0
L2
12
B1
16 20
D1
B2
32 36
D2
47
Two fields containing packed decimal data have to be compared. It will be done by the arithmetic compare instruction CP (Compare Packed decimal data). The contents of the 1st-operand field are compared with the contents of the 2nd-operand field. The result of the comparison is indicated in the condition code which may be checked subsequently. The contents of both fields have to be in correct packed decimal format, otherwise the instruction results in a system error (Data Exception). Both operands remain unchanged.nary integers and remain unchanged.
FIELDG 00 08 09 04 6C
FIELDH 90 75 5D
CP FIELDG,FIELDH
Page 32 of 101
TPF Basic Course

CR
Mnemonic
Compare register
Operands
CR
Machine format (RR)
R1 , R2
R1
8
19
0
R2
12 15
To compare the arithmetic values of two registers, the CR (Compare Register) instruction is performed. The data of the 1stoperand register is compared with the data of the 2nd-operand register. The result of the comparison is indicated in the condition code which may be checked subsequently. The operands are treated as 32-bit signed binary integers and remain unchanged.
Condition codes 0 1. = 2. operands are equal 1 1. < 2. 1st operand register is lower than the 2nd operand register 2 1. > 2. 1st operand register is greater than the 2nd operand register 3 not used! Graphical example
R0 00 00 00 2C
R14 FF FF FF D4
CR R0,R14
Page 33 of 101
TPF Basic Course

CVB
Mnemonic
Convert to binary
Operands
CVB
Machine format (RX)
R1 , D2 (X2 , B2)
R1
8
4F
0
X2
12
B2
16 20
D2
31
The conversion of packed decimal data to binary data is performed by the CVB (ConVert to Binary) instruction. It converts the packed data of the source-field (2nd operand) to binary data and places the result in the target-register (1st operand). The sourcefield has to be a doubleword (->> boundary!) in storage. The result is treated as a 32-bit signed binary integer. The maximum positive number that can be converted is 2,147,483,647 (->> X'7FFFFFFF'), the maximum negative number is -2,147,483,648 (->> X'80000000'). If the source-field does not contain packed decimal data, an error occurs (Data Exception). The source-field remains unchanged.
R1 00 00 07 CE FIELDD (DOUBLEWORD !) 00 00 00 00 00 01 99 8C CVB R1,FIELDD

SIGN DIGIT !
Page 34 of 101
TPF Basic Course

CVD
Mnemonic
Convert to decimal
Operands
CVD
Machine format (RX)
R1 , D2 (X2 , B2)
X2
12
4E
0
R1
8
B2
16 20
D2
31
The conversion of binary data to packed decimal data is performed by the CVD (ConVert to Decimal) instruction. It converts the binary data of the source-register (1st operand) to packed data and places the result at the target-field (2nd operand). The targetfield has to be a doubleword (->> boundary!) in storage. The source-data is treated as a 32-bit signed binary integer. The result has the format of packed decimal data (coded positive sign-digit is C ; coded negative sign-digit is D). The source-register remains unchanged.
R1 FF FD F5 8F FIELDF (DOUBLEWORD !) 00 00 00 00 01 33 74 5D CVD R1,FIELDF

SIGN DIGIT !
Page 35 of 101
TPF Basic Course

Divide fullword
Operands
Mnemonic
D
Machine format (RX)
R1 , D2 (X2 , B2)
R1
8
5D
0
X2
12
B2
16 20
D2
31
The binary value of a register-pair has to be divided by a four byte field in storage containing also a binary value. The D (Divide fullword) instruction handles this problem. Let's consider the divide instruction first (specially the size of the 1st operand): the problem here is that a division results in a quotient and a remainder. The assembler considers both. The instruction uses an evenodd register-pair to contain the quotient and the remainder. Also the dividend uses this register-pair. The contents of the 1st-operand register-pair (even-odd) are divided by the data of the 2nd-operand field, a fullword (->> boundary!) in storage. The quotient is placed in the 1st-operand odd-register and the remainder in the even-register. The 2nd-operand field (divisor), the quotient and the remainder are treated as 32-bit signed binary integers. The 1st-operand register-pair (dividend) is treated as a 64-bit signed binary integer. The remainder takes always the sign of the dividend. The 2ndoperand field remains unchanged. The calculation follows algebraic rules.
R4
R5
00 00 00 00 00 00 00 C8 :
BINARY DIVISION
R4
R5
FIELDW 00 00 00 06
00 00 00 02 00 00 00 21
The first operand register-pair contains the RESULT of the calculation.
D R4,FIELDW
The EVEN register contains the REMAINDER, the odd register contains the QUOTIENT ! The second operand remains unchanged !
Page 36 of 101
TPF Basic Course

DC
Mnemonic
Define constant
Operands
DC
Name; Storage type; Length; Value
Assembler Language instructions tell the computer what operations to perform. Assembler Instructions are also used to describe data. The DC (Define Constant) instruction is used to define the constants in a program. We must tell the computer everything about the constant: its length, its type, and, most important, its value. Is it 1 or 256 bytes long ? Is it a numeric or a non-numeric constant ? Is it a binary or a decimal constant ? What is the value of the constant ? The following table shows some examples of the instruction. Examples LABEL1 LABEL2 LABEL3 LABEL4 DC DC DC DC C'/' X'F9AB' H'100' F'-2' L' = 1 L' = 2 L' = 2 L' = 4 X'61' X'F9AB' X'0064' X'FFFFFFFE'
(Boundary !) (Boundary !)
Page 37 of 101
TPF Basic Course

LABEL5 LABEL6 LABEL7 LABEL8 LABEL9 LABEL10 LABEL11 LABEL12 LABEL13 LABEL14 LABEL15 LABEL16 DC DC DC DC DC DC DC DC DC DC DC DC 2CL2'GAG' CL5'NO' FL3'12' 3XL2'3A8' 3FL2'-3' A(22) P'35' AL2(-1) 2P'-4' BL2'01101' AL1(C'R',X'40',B'101' CL4'ADE' L' = 2 (2x !) L' = 5 L' = 3 L' = 2 (3x !) L' = 2 (3x !) L' = 4 L' = 2 L' = 2 L' = 1 (2x !) L' = 2 L' = 1 (3x !) L' = 5 X'C7C1C7C1' X'D5D6404040' X'00000C' X'03A803A803A8' X'FFFDFFFDFFFD' X'00000016' X'035C' X'FFFF' X'4D4D' X'000D' X'D94005' X'C1C4C54040' (No Boundary !) (No Boundary !) (Boundary !) (No Boundary !) (No Boundary !)
Page 38 of 101
TPF Basic Course

DP
Mnemonic
Divide packed decimal data

Operands
DP
D1 (L1 , B1) , D2 (L2 , B2)

L1
8
FD
0
L2
12
B1
16 20
D1
B2
32 36
D2
47
Two fields containing packed decimal data have to be divided by each other. The instruction DP (Divide Packed decimal data) will do this in one step. The contents of the 1st-operand field (dividend) is divided by the contents of the 2nd-operand field (divisor) and the result (quotient and remainder) is placed in the 1st-operand field. The initial contents of both operand fields have to be in correct packed decimal format, otherwise the instruction results in a system error (Data Exception). The results is also in packed decimal format. The 2nd-operand field remains unchanged. The quotient, in the length of the difference between dividend and divisor (L1-L2!), is placed leftmost in the 1st-operand field. The remainder, in the length of the divisor (L2!), is placed rightmost in the 1st-operand field. The calculation follows algebraic rules. Note: The divisor may not be greater than 15 digits plus sign (L2 << 8).
FIELDC 00 01 64 80 0C :
DECIMAL DIVISION OF PACKED DATA
FIELDD 30 0C
FIELDC 00 54 9C 10 0C DP FIELDC,FIELDD
The First operand field contains the RESULT of the calculation. The second operand remains unchanged !
Page 39 of 101
TPF Basic Course

DR
Mnemonic
Divide register
Operands
CR
Machine format (RR)
R1 , R2
R1
8
1D
0
R2
12 15
To divide the contents of a register-pair by the contents of another register, the DR (Divide Register) instruction is performed. The considerations about the format of the result and the 1st-operand register-pair are described in the D (Divide fullword) instruction. The contents of the 1st-operand register-pair (even-odd) are divided by the contents of the 2nd-operand register. The quotient is placed in the 1st-operand odd-register and the remainder in the even-register. The 2nd-operand register (divisor), the quotient and the remainder are treated as 32-bit signed binary integers. The 1st-operand register-pair (dividend) is treated as a 64-bit signed binary integer. The remainder takes always the sign of the dividend. The 2ndoperand register remains unchanged. The calculation follows algebraic rules.
R2
R3
FF FF FF FF FF FF FF 9C :
BINARY DIVISION
R2
R3
R14 00 00 00 07
FF FF FF FE FF FF FF F2
The first operand register-pair contains the RESULT of the calculation.
DR R2,R14
The EVEN register contains the REMAINDER, the odd register contains the QUOTIENT ! The second operand remains unchanged !
Page 40 of 101
TPF Basic Course

DS
Mnemonic
Define storage
Operands
DS
Name; Storage type; Length;
The DS (Define Storage) statement reserves storage without defining a value for that storage area. The following table shows some examples of the instruction. Examples LABEL1 LABEL2 LABEL3 LABEL4 LABEL5 LABEL6 LABEL7 LABEL8 LABEL9 LABEL10 LABEL11 LABEL12 LABEL13 DS DS DS DS DS DS DS DS DS DS DS DS DS C X B P H F A D 0CL8 FL3 3XL6 2HL3 5A Character Variable Hexadecimal Variable Binary Variable Packed Variable Decimal Variable Decimal Variable Address Variable Decimal Variable Character Variable, No Storage Reservation Decimal Variable, No Boundary Hexadecimal Variable, 3x ! Decimal Variable, No Boundary, 2x ! Address Variable, 5x ! Implicit L' = 1 Implicit L' = 1 Implicit L' = 1 Implicit L' = 1 Implicit L' = 2 Implicit L' = 4 Implicit L' = 4 Implicit L' = 8 Explicit L' = 8 Explicit L' = 3 Explicit L' = 6 Explicit L' = 3 Implicit L' = 4
Page 41 of 101
TPF Basic Course

ED
Mnemonic
Edit
Operands
ED
D1 (L1 , B1) , D2 (B2)

8
DE
L1
B1
16
20
D1
B2
32
36
D2
47
To edit a field containing packed decimal data to printable characters, the ED (EDit) instruction is performed. The packed data of the 2nd-operand field is changed to the zoned format and placed at right positions in the 1st-operand mask-field, which is also called as the pattern. That mask controls the operation (->> i.e. leading zeros in the 2nd-operand field are 'replaced' by the mask's fill charater). The result replaces the 1st-operand mask-field. The result of the instruction is also indicated in the condition code which may be checked subsequently. The contents of the 2nd-operand field has to be in correct packed decimal format, otherwise the instruction results in a system error (Data Exception). See also the EDMK instruction.
Condition codes 0 =0 Last Field Zero or Zero Length 1 <0 Last Field less than Zero 2 >0 Last Field greater than Zero 3 not used! Graphical example
1st Operand (Mask Field)

40 20 21 20 6B 20 20 6C
2nd Operand (Packed Data)

07 15 2C
Legend : 20 ==> 21 ==> 40 ==> Other ==>
Digit Selector Significance Starter Fill Character (1st Byte) Message byte

40 40 F7 F1 6B F5 F2 40
ED FIELDA,FIELDB
Page 42 of 101
TPF Basic Course

EDMK
Mnemonic
Edit and mark

Operands
EDMK
D1 (L1 , B1) , D2 (B2)

8
DF
L1
B1
16
20
D1
B2
32
36
D2
47
To edit a field containing packed decimal data to printable characters, the EDMK (EDit and MarK) instruction is performed. The packed data of the 2nd-operand field is changed to the zoned format and placed at right positions in the 1st-operand mask-field, which is also called as the pattern. That mask controls the operation (->> i.e. leading zeros in the 2nd-operand field are 'replaced' by the mask's fill charater). Additionally the address of the 1st significant result byte (1st digit unequal zero) is placed into the register R1. The result replaces the 1st-operand mask-field. The result of the instruction is also indicated in the condition code which may be checked subsequently. The contents of the 2nd-operand field has to be in correct packed decimal format, otherwise the instruction results in a system error (Data Exception). See also the ED instruction
Condition codes 0 =0 Last Field Zero or Zero Lenght 1 <0 Last Field less than Zero 2 >0 Last Field greater than Zero 3 not used! Graphical example

40 20 21 20 6B 20 20 6C
2nd Operand (Packed Data)

07 15 2C
Legend : 20 ==> 21 ==> 40 ==> Other ==>
Digit Selector Significance Starter Fill Character (1st Byte) Message byte

40 40 F7 F1 6B F5 F2 40
Register 1 points to this Address
EDMK FIELDA,FIELDB
Page 43 of 101
TPF Basic Course

EX
Mnemonic
Execute
Operands
EX
Machine format (RX)
R1 , D2 (X2 , B2)
R1
8
44
0
X2
12
B2
16 20
D2
31
To perform SS1 and SS2 instructions with a variable length, the EX (EXecute) instruction is recommended. First the 2nd byte of the instruction at the 2nd-operand address is modified by the rightmost byte of the 1st-operand register (that 2nd byte contains the length attributes!). Afterwards the resulting instruction, called as the target instruction, is executed. The modification will be done by an OR-connection (see also graphical example). Be careful using the EX instruction in connection with other instruction formats! Note: Do NOT use R0 as 1st-operand register ! In this case no OR-connection will be made.
R1 xx xx xx 1B
IN1 yy .. zz vv
EX R1,IN1
The 2nd byte of the TARGET INSTRUCTION will be ORED with the low order byte contents of the first operand register ! Possible use : MVC with a variable length ...
Page 44 of 101
TPF Basic Course

IC
Mnemonic
Insert character
Operands
IC
Machine format (RX)
R1 , D2 (X2 , B2)
R1
8
43
0
X2
12
B2
16 20
D2
31
To move one byte with binary data from a storage location into a register, the IC (Insert Character) instruction is performed. The data of the source-field (2nd operand), a single byte in storage, is inserted into the low-order byte of the target-register (1st operand). The source-field and the three high-order bytes of the target-register remain unchanged.
Condition codes Condition code remains unchanged!
R1 xx xx xx E3
FIELDA E3
IC R1,FIELDA
xx - remains UNCHANGED !
Graphical example
Page 45 of 101
TPF Basic Course

ICM
Mnemonic
Insert character under mask

Operands
ICM
Machine format (RS)
R1 , M3 , D2 (B2)
R1
8
BF
0
M3
12
B2
16 20
D2
31
The ICM (Insert Characters under Mask) instruction is an additional instruction to place one or more bytes of data in storage at wanted positions in a register. The data of the source-field (2nd operand), consecutive bytes in storage, are inserted into the target-register (1st operand) in the positions indicated by the 4-bit mask (3rd operand). The length of the source-field is given by the number of indicated bytes. The source-field and the non-affected bytes of the target-register remain unchanged. No boundary is wanted! See also the L, LH and IC instructions. 1)* all inserted bits are zeros or mask is zero 2)* leftmost inserted bit is one 3)* leftmost inserted bit is zero, but not all bits are zeros
Condition codes 0 all inserted bits are zero or mask is zero 1 leftmost inserted bit is one 2 leftmost inserted bit is zero, but not all bits are zero 3 not used! Graphical example
R6 C3 xx C1 E3
1 2 3
FIELDX C3 C1 E3
ICM R6,B1011,FIELDX
Controlled by the 3rd operand MASK : Here = 1011
Page 46 of 101
TPF Basic Course

Load fullword
Operands
Mnemonic
L
Machine format (RX)
R1 , D2 (X2 , B2)
R1
8
58
0
X2
12
B2
16 20
D2
31
To move four bytes with binary data from a storage location into a register, the L (Load fullword) instruction is performed. The data of the source-field (2nd operand), a fullword (->> boundary!) in storage, is loaded into the target-register (1st operand). The source-field remains unchanged.
R1 00 C1 4B E3
FIELDA 00 C1 4B E3
L R1,FIELDA
Page 47 of 101
TPF Basic Course

LA
Mnemonic
Load address
Operands
LA
Machine format (RX)
R1 , D2 (X2 , B2)
R1
8
41
0
X2
12
B2
16 20
D2
31
To place the address of a storage-location in a register, the LA (Load Address) instruction is performed. The effective address of the 2nd-operand field is loaded in the 1st-operand register. The address is placed right adjusted in the register and if nessesary left padded with zeros. Please note that the effective address of the 2nd-operand field is calculated adding up the values of the index-register, the baseregister and the displacement. The instruction may also be used to increment the contents of a register. The contents of register 5 are incremented by 8 with the coding: LA R5,8(0,R5)
R1 00 02 B7 8C
FIELDA D3 90 23
The ADDRESS is placed in REGISTER 1 !
Calculation - Rule :
X2 + B2 + D2 ==> R1
LA R1,FIELDA
Page 48 of 101
TPF Basic Course

LCR
Mnemonic
Load complement register

Operands
LCR
Machine format (RR)
R1 , R2
R1
8
13
0
R2
12 15
To change the binary data of a register to the two's complement of it, the LCR (Load Complement Register) instruction is performed. The contents of the source-register (2nd operand) are changed to the two's complement and the result is loaded into the target-register (1st operand). Afterwards the target-register is tested for sign and magnitude. The result of the test is indicated in the condition code. The source-registers and the result in the target-register are treated as 32-bit signed binary integers. The source-register remains unchanged.
R14 FF FF FC 3F
R6 00 00 03 C1
LCR R14,R6
The 1st operands sign bit will be tested !
Page 49 of 101
TPF Basic Course

LH
Mnemonic
Load Halfword
Operands
LH
Machine format (RX)
R1 , D2 (X2 , B2)
R1
8
48
0
X2
12
B2
16 20
D2
31
To move two bytes with binary data from a storage location into a register, the LH (Load Halfword) instruction is performed. It will do this in two steps. First step: the data of the source-field (2nd operand), a halfword (->> boundary!) in storage, is extended to a 32-bit signed binary integer. The extension bits are the same as the high-order bit of the source-field. Second step: the 32 bits are loaded into the target-register (1st operand). The source-field remains unchanged.
R1 00 00 4B E3
FIELDA 00 00 4B E3
R1 FF FF 8B E3
FIELDA FF FF 8B E3
LH R1,FIELDA
Page 50 of 101
TPF Basic Course

LM
Mnemonic
Load multiple
Operands
LM
Machine format (RS)
R1 , R3 , D2 (B2)
R1
8
98
0
R3
12
B2
16 20
D2
31
To move a sequence of four bytes of binary data from a storage location into adjacent registers, the LM (Load Multiple) instruction is performed. The data of the source-field (2nd operand), a sequence of fullwords (->> boundary!) in storage, is loaded into the adjacent target-registers, which are defined by the starting-register (1st operand) and the ending-register (3rd operand). The target-registers are loaded in the ascending order of their register numbers (with register R0 follows register R15). The number of target-registers defines the length of the source-field. The source-field remains unchanged.
R1 R2 R3 R4 .. .. .. ..
FA FB FC FD .. .. .. ..
LM R1,R4,FA
FA, FB, FC and FD are FULLWORDS !
Page 51 of 101
TPF Basic Course

LNR
Mnemonic
Load negative register

Operands
LNR
Machine format (RR)
R1 , R2
R1
8
11
0
R2
12 15
To transfer the two's complement of the absolute value between two registers, the LNR (Load Negative Register) instruction is performed. The binary data of the source-register (2nd operand) are changed into negative and the result is loaded into the targetregister (1st operand). If the binary data of the source-register is already negative or zero, the data is tranfered unchanged; otherwise the two's complement is loaded into the target-register. Afterwards the target-register is tested for magnitude. The result of the test is indicated in the condition code. The source-register and the result in the target-register are treated as 32-bit signed binary integers. The source-register remains unchanged. See also the LPR instruction.
Condition codes 0 =0 1st operand register is zero 1 <0 1st operand register is negative 2 not used! 3 not used! Graphical example
R1 FF FF FF F0
R7 00 00 00 10
R1 D3 90 23 BB
R7 D3 90 23 BB
LNR R1,R7
Page 52 of 101
TPF Basic Course

LPR
Mnemonic
Load positive register

Operands
LPR
Machine format (RR)
R1 , R2
R1
8
10
0
R2
12 15
To transfer the absolute value between two registers, the LPR (Load Positive Register) instruction is performed. The binary data of the source-register (2nd operand) are changed into positive and the result is loaded into the target-register (1st operand). If the binary data of the source-register is already positive or zero, the data is tranfered unchanged; otherwise the two's complement is loaded into the target-register. Afterwards the target-register is tested for magnitude. The result of the test is indicated in the condition code. The source-register and the result in the target-register are treated as 32-bit signed binary integers. The sourceregister remains unchanged.
Condition codes 0 =0 1st operand register is zero 1 not used! 2 >0 1st operand register is positive 3 not used! Graphical example
R2 00 00 00 06
R4 FF FF FF FA
R2 7A 50 1B 57
R4 7A 50 1B 57
LPR R2,R4
Page 53 of 101
TPF Basic Course

LR
Mnemonic
Load register
Operands
LR
Machine format (RR)
R1 , R2
R1
8
18
0
R2
12 15
Data transfers between two registers are performed by the LR (Load Register) instruction. The contents of the source-register (2nd operand) are loaded into the target-register (1st operand). The source-register remains unchanged.
R1 00 C1 4B E3
R6 00 C1 4B E3
LR R1,R6
Page 54 of 101
TPF Basic Course

LTR
Mnemonic
Load and test register

Operands
LTR
Machine format (RR)
R1 , R2
R1
8
12
0
R2
12 15
Data transfers between two registers may also performed by the LTR (Load and Test Register) instruction. The contents of the source-register (2nd operand) are loaded into the target-register (1st operand). Additionally the contents of the source-register, treated as a 32-bit signed binary integer, are tested for sign and magnitude. The result of the test is indicated in the condition code. The source-register remains unchanged. If the two operands are the same register as in LTR R3,R3 , no data is transfered, but the condition code is set!
Condition codes 0 =0 1st operand register is zero 1 <0 1st operand register is negative 2 >0 1st operand register is positive 3 not used! Graphical example
R14 82 09 04 40
Sign Bit will be tested
R7 82 09 04 40
LTR R14,R7
Page 55 of 101
TPF Basic Course

Multiply fullword
Operands
Mnemonic
M
Machine format (RX)
R1 , D2 (X2 , B2)
R1
8
5C
0
X2
12
B2
16 20
D2
31
The binary value of a register has to be multiplied by a four byte field in storage containing also a binary value. The M (Multiply fullword) instruction handles this problem. Let's consider the multiply instruction first (specially the size of the product): when two 32-bit operands are multiplied, the product requires 64-bits. Certainly the product cannot fit into the 1st-operand register! So it is not placed in a single register, but in a register-pair! The assembler requires that the register-pair has to be an even-odd pair! The contents of the 1st-operand odd-register (the contents of the even-register are ignored) are multiplied by the data of the 2ndoperand field, a fullword (->> boundary!) in storage and the resulting product is placed in the 1st-operand register-pair. The operands are treated as 32-bit signed binary integers and the result is treated as a 64-bit signed binary integer. The 2nd-operand field remains unchanged. The calculation follows algebraic rules.
R14 xx xx X
BINARY MULTIPLICATION
R15 xx xx 00 00 00 1A
R14
R15
FIELDM 00 00 00 21
00 00 00 00 00 00 03 5A M R14,FIELDM
The First operand register-pair contains the RESULT of the calculation. The second operand remains unchanged !
Page 56 of 101
TPF Basic Course

MH
Mnemonic
Multiply Halfword
Operands
MH
Machine format (RX)
R1 , D2 (X2 , B2)
R1
8
4C
0
X2
12
B2
16 20
D2
31
The binary value of a register has to be multiplied by a two byte field in storage containing also a binary value. The MH (Multiply Halfword) instruction handles this problem. The contents of the 1st-operand register are multiplied by the data of the 2nd-operand field, a halfword (->> boundary!) in storage and the resulting product is placed in the 1st-operand register. Now we are multiplying a 32-bit operand by a 16-bit operand. The product contains 48 bits, but only the low-order 32 bits of the product are placed in the 1st-operand register. If the product requires more than 31 bits and the sign bit, the high-order bits are lost and the result is invalid. No overflow occurs! The 2nd-operand field is treated as a 16-bit signed binary integer. The 1st-operand register and the result are treated as 32-bit signed binary integers. The 2nd-operand field remains unchanged. The calculation follows algebraic rules.
R15 00 00 00 02 X
FIELDH FF FA
R15 FF FF FF F4 MH R15,FIELDH
The First operand register contains the RESULT of the calculation. The second operand remains unchanged !
Page 57 of 101
TPF Basic Course

MP
Mnemonic
Multiply packed decimal data

Operands
MP
D1 (L1 , B1) , D2 (L2 , B2)

L1
8
FC
0
L2
12
B1
16 20
D1
B2
32 36
D2
47
Two fields containing packed decimal data have to be multiplied with each other. The instruction MP (Multiply Packed decimal data) will do this in one step. The contents of the 1st-operand field (multiplicand) is multiplied with the contents of the 2ndoperand field (multiplier) and the result is placed in the 1st-operand field. The initial contents of both operand fields have to be in correct packed decimal format, otherwise the instruction results in a system error (Data Exception). The result is also in packed decimal format. The 2nd-operand field remains unchanged. The multiplicand must have at least as many bytes of leading zeros as the number of bytes in the multiplier. The calculation follows algebraic rules. The result is tested and a condition code is set. In case of an overflow the overflow digits are ignored.
FIELDP 00 00 08 41 5F X
DECIMAL MULTIPLICATION OF PACKED DATA
FIELDQ 02 32 9C
FIELDP 00 00 10 74 4C MP FIELDP,FIELDQ
Page 58 of 101
TPF Basic Course

MR
Mnemonic
Multiply register
Operands
MR
Machine format (RR)
R1 , R2
R1
8
1C
0
R2
12 15
To multiply the contents of one register by another register, the MR (Multiply Register) instruction is performed. The considerations about the size of the product and the 1st-operand register-pair are described in the M (Multiply fullword) instruction. The contents of the 1st-operand odd-register (the contents of the even-register are ignored) are multiplied by the contents of the 2nd-operand register and the resulting product is placed in the 1st-operand register-pair. The operands are treated as 32-bit signed binary integers and the result is treated as a 64-bit signed binary integer. The 2nd-operand register remains unchanged. The calculation follows algebraic rules.
R2 xx xx X
R3 xx xx 00 00 00 2F
R2
R3
R4 00 00 00 13
00 00 00 00 00 00 03 7D MR R2,R4
The First operand register-pair contains the RESULT of the calculation. The second operand remains unchanged !
Page 59 of 101
TPF Basic Course

MVC
Mnemonic
Move character
Operands
MVC
D1 (L1 , B1) , D2 (B2)

8
D2
L1
B1
16
20
D1
B2
32
36
D2
47
Data transfers between two storage locations are performed by the MVC (MoVe Character) instruction. This is one of the most frequently-used assembler instructions. It moves data from the source-field (2nd operand) into the target-field (1st operand). The maximum length which can be moved is 256 bytes of data. The length is defined by the 1st-operand field, a): explicitly as in MVC FIELD1(14),FIELD2, or b): implicitly using the length defined at field definition. If the specified length is less than the length of the source-field (2nd operand), the low-order bytes of data are lost. The length of the source-field is not of interest. Data movement proceeds from left to right, byte by byte. The source-field remains unchanged.
FIELDA C3 C1 E3
1 2 3
FIELDB C3 C1 E3
MVC FIELDA,FIELDB
The number of bytes moved is determined by the length of the 1st operand !
Page 60 of 101
TPF Basic Course

MVCL
Mnemonic
Move character long

Operands
MVCL
Machine format (RR)
R1 , R2
R2
12 15 8
0E
0
R1
Data transfers between two large storage locations are performed by the MVCL (MoVe Character Long) instruction. It moves data from the source-field (designated by the 2nd-operand register-pair) into the target-field (designated by the 1st-operand register-pair). The maximum number which can be moved are 16777215 bytes of data. The instruction recommends even-odd pairs of registers. Data movement proceeds from left to right, byte by byte, and stops as soon as the end of the target-field is reached. If sourcefield is shorter than the target-field, the remaining rightmost byte positions of the target-field are filled with padding bytes. If the source-field is larger than the target-field, the remaining bytes of the source-field are ignored. The result is indicated in the condition code which may be checked subsequently. The source-field remains unchanged. 1)* operand lengths are equal 2)* 1st operand length is lower 3)* 1st operand length is higher 4)* destructive overlap, no movement performed
Condition codes 0 operand lengths are equal 1 1st operand length is lower than 2nd operand length 2 1st operand length is greater than 2nd operand length 3 destructive overlap, no movement performed Graphical example
R2 storage address
R4 storage address
C3 C1 E3
1 2 3
..
C3 C1 E3
..
MVCL R2,R4
The number of bytes to be moved is in R3 (TO-LENGTH) and R5 (FROM-LENGTH) !
Page 61 of 101
TPF Basic Course

MVI
Mnemonic
Move immediate
Operands
MVI
D1 (B1) , I2
8
92
I2
B1
16
20
D1
31
To move a single byte of data, defined at program coding, into a storage location the MVI (MoVe Immediate) instruction is performed. The source-data (2nd operand) is moved into the target-field (1st operand). The single byte of the 2nd operand is also called the immediate operand. The immediate data may be specified as a): a character (EBCDIC code) operand as in MVI FIELD,C'A', b): a hexadecimal operand as in MVI FIELD,X'C1', or c): a binary operand as in MVI FIELD,B'11000001'. The immediate data to be moved is contained within the instruction itself. The length of the target-field is not of interest. Only the 1st byte of the field will be overwritten.
FIELDA D4
Immediate Value C3
MVI FIELDA,CM
Page 62 of 101
TPF Basic Course

MVN
Mnemonic
Move numeric
Operands
MVN
D1 (L1 , B1) , D2 (B2)

8
D1
L1
B1
16
20
D1
B2
32
36
D2
47
To transfer the four low-order bits (numeric bits, numeric digit) between two storage locations the MVN (MoVe Numerics) instruction is performed. It moves the numeric data from the source-field (2nd operand) to the corresponding positions of the target-field (1st operand). The maximum length which can be handled is 256 bytes of data. The length is defined by the 1st operand, a): explicitly as in MVN FIELDX(24),FIELDZ, or b): implicitly using the length defined at field definition. If the specified length is less than the length of the source-field (2nd operand), the low-order bytes of data are lost. The length of the source-field is not of interest. Numeric digit movement proceeds from left to right, numeric digit by numeric digit. The sourcefield and the zone digits of the target-field remain unchanged. See also the MVZ instruction.
FIELDA D3 C1 E9
1 2 3
FIELDB C3 C1 D9
MVN FIELDA,FIELDB
The number of numeric digits moved is determined by the length of the 1st operand !
Page 63 of 101
TPF Basic Course

MVO
Mnemonic
Move with offset

Operands
MVO
D1 (L1 , B1) , D2 (L2 , B2)

L2
12
F1
0
L1
8
B1
16 20
D1
B2
32 36
D2
47
The last of the decimal move instructions, the MVO (MoVe with Offset) instruction, is the most complex. The data of the sourcefield (2nd operand) is moved and adjusted to the left of the low-order digit of the target-field (1st operand). The assembler must know the length of each operand field, which may be up to 16 (!) bytes long. If the length of the 1st-operand (receiving) field is too small, the leftmost positions of the 2nd-operand (sending) field are truncated. If the length of the 1st-operand field is too large, the field is padded with zeros. Data movement proceeds from right to left, digit by digit. The source-field and the low-order digit of the target-field remain unchanged.
FIELDA 39 11 93
3 2 1
FIELDB C3 C1 D9
MVO FIELDA,FIELDB
The last digit of the 1st operand remains unchanged !
Page 64 of 101
TPF Basic Course

MVZ
Mnemonic
Move zone
Operands
MVZ
D1 (L1 , B1) , D2 (B2)

8
D3
L1
B1
16
20
D1
B2
32
36
D2
47
To transfer the four high-order bits (zone bits, zone digit) between two storage locations the MVZ (MoVe Zones) instruction is performed. It moves the zone data from the source-field (2nd operand) to the corresponding positions of the target-field (1st operand). The maximum length which can be handled is 256 bytes of data. The length is defined by the 1st operand, a): explicitly as in MVZ FIELDA(15),FIELDB, or b): implicitly using the length defined at field definition. If the specified length is less than the length of the source-field (2nd operand), the low-order bytes of data are lost. The length of the source-field is not of interest. Zone digit movement proceeds from left to right, zone digit by zone digit. The source-field and the numeric digits of the target-field remain unchanged. See also the MVN instruction.
FIELDA D3 C1 E3
1 2 3
FIELDB D9 C1 E3
MVZ FIELDA,FIELDB
The number of zone digits moved is determined by the length of the 1st operand !
Page 65 of 101
TPF Basic Course

And fullword
Operands
Mnemonic
N
Machine format (RX)
R1 , D2 (X2 , B2)
R1
8
54
0
X2
12
B2
16 20
D2
31
To set single bits of a register to 'zero', the N (aNd fullword) instruction is performed. The 'one'-bits of the 1st-operand register are changed to 'zero', if the corresponding bits of the 2nd-operand field, a fullword (->> boundary!) in storage, are 'zero'. In all other cases the bits of the 1st-operand register remain unchanged. The result is indicated in the condition code which may be checked subsequently. See also the NR instruction.
Condition codes 0 =0 1st operand register is zero 1 != 0 1st operand register is not zero 2 not used! 3 not used! Graphical example
2nd Operand Field Bit in 2nd OP 0 0 1 1 0110 1011 1100 1110 0101 1110 1111 0111 1st Operand Register Bit in 1st OP 0 1 0 1 1101 1001 0011 0001 1101 0011 1101 0101 Result 1st Operand Register Result in 1st OP 0 0 0 1 0100 1001 0000 0000 0101 0010 1101 0101
Page 66 of 101
TPF Basic Course

NC
Mnemonic
And character
Operands
NC
D1 (L1 , B1) , D2 (B2)

8
D4
L1
B1
16
20
D1
B2
32
36
D2
47
To set single bits of a storage field to 'zero', the NC (aNd Character) instruction is performed. The 'one'-bits of the 1st-operand field are changed to 'zero', if the corresponding bits of the 2nd-operand field are 'zero'. In all other cases the bits of the 1stoperand field remain unchanged. The result is indicated in the condition code which may be checked subsequently.is indicated in the condition code which may be checked subsequently.
Condition codes 0 =0 1st operand field is zero 1 != 0 1st operand field is not zero 2 not used! 3 not used! Graphical example
2nd Operand Field Bit in 2nd OP 0 0 1 1 0110 1011 1100 1110 0101 1110 1st Operand Field Bit in 1st OP 0 1 0 1 1101 1001 0011 0001 1101 0011 Result 1st Operand Field Result in 1st OP 0 0 0 1 0100 1001 0000 0000 0101 0010
Page 67 of 101
TPF Basic Course

NI
Mnemonic
And immediate
Operands
NI
D1 (B1) , I2
8
94
I2
B1
16
20
D1
31
To set the bits of a single byte of data to 'zero', the NI (aNd Immediate) instruction is performed. The 'one'-bits of the 1st-operand field are changed to 'zero', if the corresponding bits of the 2nd-operand field are 'zero'. In all other cases the bits of the 1stoperand field remain unchanged. The 2nd operand is also called the immediate operand. The immediate data, defined at program coding, is contained within the instruction itself. The length of the 1st-operand field is not of interest. Only the 1st byte of the field is considered. The result is indicated in the condition code which may be checked subsequently.est. Only the 1st byte of the field is considered.
Condition codes 0 =0 1st operand byte is zero 1 != 0 1st operand byte is not zero 2 not used! 3 not used! Graphical example
Immediate Operand Bit in 2nd OP 0 0 1 1 1 1 1 1 0 0 0 0
1st Operand Bit in 1st OP 0 1 0 1 1 1 0 0 1 1 0 0
Result 1st Operand Result in 1st OP 0 0 0 1 1 1 0 0 0 0 0 0
Page 68 of 101
TPF Basic Course

NR
Mnemonic
And register
Operands
NR
Machine format (RR)
R1 , R2
R1
8
14
0
R2
12 15
To set single bits of a register to 'zero', the NR (aNd Register) instruction is performed. The 'one'-bits of the 1st-operand register are changed to 'zero', if the corresponding bits of the 2nd-operand register are 'zero'. In all other cases the bits of the 1st-operand register remain unchanged. The result is indicated in the condition code which may be checked subsequently. See also the N instruction.ain unchanged.
2nd Operand Register Bit in 2nd OP 0 0 1 1 0110 1011 1100 1110 0101 1110 1111 0111 1st Operand Register Bit in 1st OP 0 1 0 1 1101 1001 0011 0001 1101 0011 1101 0101 Result 1st Operand Register Result in 1st OP 0 0 0 1 0100 1001 0000 0000 0101 0010 1101 0101
Page 69 of 101
TPF Basic Course

Or fullword
Operands
Mnemonic
O
Machine format (RX)
R1 , D2 (X2 , B2)
R1
8
56
0
X2
12
B2
16 20
D2
31
To set single bits of a register to 'one', the O (Or fullword) instruction is performed. The 'zero'-bits of the 1st-operand register are changed to 'one', if the corresponding bits of the 2nd-operand field, a fullword (->> boundary!) in storage, are 'one'. In all other cases the bits of the 1st-operand register remain unchanged. The result is indicated in the condition code which may be checked subsequently. See also the OR instruction.
2nd Operand Field Bit in 2nd OP 0 0 1 1 0110 1011 1100 1110 0101 1110 1111 0111 1st Operand Register Bit in 1st OP 0 1 0 1 1101 1001 0011 0001 1101 0011 1101 0101 Result 1st Operand Register Result in 1st OP 0 1 1 1 1111 1011 1111 1111 1101 1111 1111 0111
Page 70 of 101
TPF Basic Course

OC
Mnemonic
Or character
Operands
OC
D1 (L1 , B1) , D2 (B2)

8
D6
L1
B1
16
20
D1
B2
32
36
D2
47
To set single bits of a storage field to 'one', the OC (Or Character) instruction is performed. The 'zero'-bits of the 1st-operand field are changed to 'one', if the corresponding bits of the 2nd-operand field are 'one'. In all other cases the bits of the 1st-operand field remain unchanged. The result is indicated in the condition code which may be checked subsequently.
2nd Operand Field Bit in 2nd OP 0 0 1 1 0110 1011 1100 1110 0101 1110 1111 0111 1st Operand Field Bit in 1st OP 0 1 0 1 1101 1001 0011 0001 1101 0011 1101 0101 Result 1st Operand Field Result in 1st OP 0 1 1 1 1111 1011 1111 1111 1101 1111 1111 0111
Page 71 of 101
TPF Basic Course

OI
Mnemonic
Or immediate
Operands
OI
D1 (B1) , I2
8
96
I2
B1
16
20
D1
31
To set the bits of a single byte of data to 'one', the OI (Or Immediate) instruction is performed. The 'zero'-bits of the 1st-operand field are changed to 'one', if the corresponding bits of the 2nd-operand field are 'one'. In all other cases the bits of the 1st-operand field remain unchanged. The 2nd operand is also called the immediate operand. The immediate data, defined at program coding, is contained within the instruction itself. The length of the 1st-operand field is not of interest. Only the 1st byte of the field is considered. The result is indicated in the condition code which may be checked subsequently.
Immediate Operand Bit in 2nd OP 0 0 1 1 0110 1011 1st Operand Field Bit in 1st OP 0 1 0 1 1011 1000 Result 1st Operand Field Result in 1st OP 0 1 1 1 1111 1011
Page 72 of 101
TPF Basic Course

OR
Mnemonic
Or register
Operands
OR
Machine format (RR)
R1 , R2
R1
8
16
0
R2
12 15
To set single bits of a register to 'one', the OR (Or Register) instruction is performed. The 'zero'-bits of the 1st-operand register are changed to 'one', if the corresponding bits of the 2nd-operand register are 'one'. In all other cases the bits of the 1st-operand register remain unchanged. The result is indicated in the condition code which may be checked subsequently. See also the O instruction.
Page 73 of 101
TPF Basic Course

PACK
Mnemonic
Pack
Operands
PACK
D1 (L1 , B1) , D2 (L2 , B2)

L2
12
F2
0
L1
8
B1
16 20
D1
B2
32 36
D2
47
The PACK instruction converts decimal data to packed format. The instruction takes the data from the source-field (2nd operand) and packs it to the target-field (1st operand). The assembler must know the length of each operand field, which may be up to 16 (!) bytes long. The instruction proceeds from right to left. If the length of the 1st-operand (receiving) field is too small, the leftmost positions of the 2nd-operand (sending) field are truncated. If the length of the 1st-operand field is too large, the field is padded with zeros. After execution, the low-order digit of the target-field signals the sign of the packed decimal value (Positive: A, C, E, F ; Negative: B, D). The source-field remains unchanged
FIELDA 00 42 5F
FIELDB F4 F2 F5
PACK FIELDA,FIELDB
The target field will be left padded with zeroes !
Page 74 of 101
TPF Basic Course

Subtract fullword
Operands
Mnemonic
S
Machine format (RX)
R1 , D2 (X2 , B2)
R1
8
5B
0
X2
12
B2
16 20
D2
31
A four byte field in storage containing a binary value has to be subtracted from the binary value of a register. The S (Subtract fullword) instruction handles this problem. The data of the 2nd-operand field, a fullword (->> boundary!) in storage, is subtracted from the contents of the 1st-operand register and the result is placed in the 1st-operand register. The operands and the result are treated as 32-bit signed binary integers. The 2nd-operand field remains unchanged. The calculation follows algebraic rules. The result is tested and a condition code is set. If the result does not fit into the 1stoperand register an overflow occurs and additionally the condition code is set to 3.
R4 00 03 E1 20 BINARY SUBTRACTION
FIELDS 00 00 06 A5
R4 00 03 DA 7B S R4,FIELDS
Page 75 of 101
TPF Basic Course

SH
Mnemonic
Subtract Halfword
Operands
SH
Machine format (RX)
R1 , D2 (X2 , B2)
R1
8
4B
0
X2
12
B2
16 20
D2
31
A two byte field in storage containing a binary value has to be subtracted from the binary value of a register. The problem can be solved by using the SH (Subtract Halfword) instruction. The data of the 2nd-operand field, a halfword (->> boundary!) in storage, is subtracted from the contents of the 1st-operand register and the result is placed in the 1st-operand register. The 2nd-operand field is treated as a 16-bit signed binary integer. The 1st-operand register and the result are treated as 32-bit signed binary integers. The 2nd-operand field remains unchanged. The calculation follows algebraic rules. The result is tested and a condition code is set. If the result does not fit into the 1stoperand register an overflow occurs and additionally the condition code is set to 3.
R2 00 00 00 15 BINARY SUBTRACTION
FIELDR 00 1A
R2 FF FF FF FB SH R2,FIELDR
Page 76 of 101
TPF Basic Course

SLA
Mnemonic
Shift left single arithmetic

Operands
SLA
Machine format (RS)
R1 , D2 (B2)
R1
8 12
8B
0
/////B2
16 20
D2
31
The data of a register has to be shifted to the left by a number of positions. The SLA (Shift Left single Arithmetic) instruction handles this problem. The number of positions (maximum 63) to be shifted is given in the immediate 2nd-operand, also called as shift value. The 1st-operand register is treated as a 32-bit signed binary integer. If the binary value of the 1st-operand register is shifted to the left by one position, the value is doubled. During the left-shift zeros are inserted on the right of the 1st-operand register. The sign bit is not shifted! The result is tested and a condition code is set. If one or more bits unlike the sign bit are shifted out of the leftmost position, an overflow occurs and additionally the condition code is set to 3. See also the SLL instruction.
Condition codes 0 =0 1st operand register is zero 1 <0 1st operand register is negative 2 >0 1st operand register is positive 3 overflow a bit unequal the sign bit is shifted out to the left Graphical example
R15 00 00 13 2E
2nd Operand
(immediate Value)
LEFTSHIFT : 5 Positions
R15 00 02 65 C0 SLA R15,5

The First operand contains the RESULT of the operation.
Page 77 of 101
TPF Basic Course

SLDA
Mnemonic
Shift left double arithmetic

Operands
SLDA
Machine format (RS)
R1 , D2 (B2)
/////B2
12 16 20
8F
0
R1
8
D2
31
The data of a register-pair has to be shifted to the left by a number of positions. The SLDA (Shift Left Double Arithmetic) instruction handles this problem. The number of positions (maximum 63) to be shifted is given in the immediate 2nd-operand, also called as shift value. The 1st-operand register-pair is treated as a 64-bit signed binary integer. The instruction recommends an even-odd pair of registers. If the binary value of the register-pair is shifted to the left by one position, the value is doubled. During the left-shift zeros are inserted on the right of the register-pair. The sign bit is not shifted! The result is tested and a condition code is set. If one or more bits unlike the sign bit are shifted out of the leftmost position, an overflow occurs and additionally the condition code is set to 3. See also the SLDL instruction.
Condition codes 0 =0 1st operand register pair is zero 1 <0 1st operand register pair is negative 2 >0 1st operand register pair is positive 3 overflow a bit unequal the sign bit is shifted out to the left Graphical example
R14 (Even/Odd Register Pair) 00 00 00 00 01 E0 00 00 2nd Operand

(immediate Value)
R14
The First operand REGISTER PAIR contains the RESULT of the operation.
00 00 00 03 C0 00 00 00 SLDA R14,9
Page 78 of 101
TPF Basic Course

SLDL
Mnemonic
Shift left double logical

Operands
SLDL
Machine format (RS)
R1 , D2 (B2)
/////B2
12 16 20
8D
0
R1
8
D2
31
The data of a register-pair has to be shifted to the left by a number of positions. The SLDL (Shift Left Double Logical) instruction handles this problem. The number of positions (maximum 63) to be shifted is given in the immediate 2nd-operand, also called as shift value. All 64 bits of the 1st-operand register-pair are included in the left-shift. The instruction recommends an even-odd pair of registers. If the binary value of the register-pair is shifted to the left by one position, the value is doubled. During the left-shift zeros are inserted on the right of the register-pair. Bits shifted out of the leftmost position are lost. See also the SLDA instruction.
R2 (Even/Odd Register Pair) 7A 00 00 00 00 00 00 19 2nd Operand

(immediate Value)
R2
00 00 00 00 00 00 0C 80 SLDL R2,7
Page 79 of 101
TPF Basic Course

SLL
Mnemonic
Shift left single logical

Operands
SLL
Machine format (RS)
R1 , D2 (B2)
R1
8 12
89
0
/////B2
16 20
D2
31
The data of a register has to be shifted to the left by a number of positions. The SLL (Shift Left single Logical) instruction handles this problem. The number of positions (maximum 63) to be shifted is given in the immediate 2nd-operand, also called as shift value. All 32 bits of the 1st-operand register are included in the left-shift. If the binary value of the 1st-operand register is shifted to the left by one position, the value is doubled. During the left-shift zeros are inserted on the right of the 1st-operand register. Bits shifted out of the leftmost position are lost. See also the SLA instruction.
R7 FF C0 14 09
2nd Operand
(immediate Value)
R7 F0 05 02 40 SLL R7,6
Page 80 of 101
TPF Basic Course

SP
Mnemonic
Subtract packed decimal data

Operands
SP
D1 (L1 , B1) , D2 (L2 , B2)

L1
8
FB
0
L2
12
B1
16 20
D1
B2
32 36
D2
47
Two fields containing packed decimal data have to be subtracted from each other. The instruction SP (Subtract Packed decimal data) will do this in one step. The contents of the 2nd-operand field are subtracted from the contents of the 1st-operand field and the result is placed in the 1st-operand field. The initial contents of both operand fields have to be in correct packed decimal format, otherwise the instruction results in a system error (Data Exception). The result is also in packed decimal format. The 2ndoperand field remains unchanged. The calculation follows algebraic rules. The result is tested and a condition code is set. In case of an overflow the overflow digits are ignored and additionally the condition code is set to 3.
FIELDS 00 00 00 75 5F DECIMAL SUBTRACTION OF PACKED DATA
FIELDR 00 92 1F
FIELDS 00 00 00 16 6D SP FIELDS,FIELDR
Page 81 of 101
TPF Basic Course

SR
Mnemonic
Subtract register
Operands
SR
Machine format (RR)
R1 , R2
R1
8
1B
0
R2
12 15
To subtract the contents of one register from another register, the SR (Subtract Register) instruction is performed. The contents of the 2nd-operand register are subtracted from the contents of the 1st-operand register and the result is placed in the 1st-operand register. The operands and the result are treated as 32-bit signed binary integers. The 2nd-operand register remains unchanged. The calculation follows algebraic rules. The result is tested and a condition code is set. If the result does not fit into the 1stoperand register an overflow occurs and additionally the condition code is set to 3.
R7 00 00 00 08 BINARY SUBTRACTION
R2 FF FF FF FD
R7 00 00 00 0B SR R7,R2
Page 82 of 101
TPF Basic Course

SRA
Mnemonic
Shift right single arithmetic

Operands
SRA
Machine format (RS)
R1 , D2 (B2)
R1
8 12
8A
0
/////B2
16 20
D2
31
The data of a register has to be shifted to the right by a number of positions. The SRA (Shift Right single Arithmetic) instruction handles this problem. The number of positions (maximum 63) to be shifted is given in the immediate 2nd-operand, also called as shift value. The 1st-operand register is treated as a 32-bit signed binary integer. If the binary value of the 1st-operand register is shifted to the right by one position, the value is cut in halve. During the rightshift, bits equal to the sign bit are inserted on the left of the 1st-operand register. Only the 31 rightmost bits are shifted. The sign bit (first bit) remains unchanged! The result is tested and a condition code is set. Bits shifted out of the rightmost position are lost. See also the SRL instruction.
Condition codes 0 =0 1st operand register is zero 1 <0 1st operand register is negative 2 >0 1st operand register is positive 3 not used! Graphical example
R3 00 00 13 2E
2nd Operand
(immediate Value)
RIGHTSHIFT : 7 Positions
R3 00 00 00 26 SRA R3,7
Page 83 of 101
TPF Basic Course

SRDA
Mnemonic
Shift right double arithmetic

Operands
SRDA
Machine format (RS)
R1 , D2 (B2)
/////B2
12 16 20
8E
0
R1
8
D2
31
The data of a register-pair has to be shifted to the right by a number of positions. The SRDA (Shift Right Double Arithmetic) instruction handles this problem. The number of positions (maximum 63) to be shifted is given in the immediate 2nd-operand, also called as shift value. The 1st-operand register-pair is treated as a 64-bit signed binary integer. The instruction recommends an even-odd pair of registers. If the binary value of the register-pair is shifted to the right by one position, the value is cut in halve. During the right-shift, bits equal to the sign bit are inserted on the left of the register-pair. Only the 63 rightmost bits are shifted. The sign bit (first bit of the even register) remains unchanged! The result is tested and a condition code is set. Bits shifted out of the rightmost position are lost. See also the SRDL instruction.
Condition codes 0 =0 1st operand register pair is zero 1 <0 1st operand register pair is negative 2 >0 1st operand register pair is positive 3 not used! Graphical example
R14 (Even/Odd Register Pair) 00 00 00 40 00 00 10 00 2nd Operand

(immediate Value)
R14
00 00 00 02 00 00 00 80 SRDA R14,5
Page 84 of 101
TPF Basic Course

SRDL
Mnemonic
Shift left double logical

Operands
SRDL
Machine format (RS)
R1 , D2 (B2)
/////B2
12 16 20
8C
0
R1
8
D2
31
The data of a register-pair has to be shifted to the right by a number of positions. The SRDL (Shift Right Double Logical) instruction handles this problem. The number of positions (maximum 63) to be shifted is given in the immediate 2nd-operand, also called as shift value. All 64 bits of the 1st-operand register-pair are included in the right-shift. The instruction recommends an even-odd pair of registers. If the binary value of the register-pair is shifted to the right by one position, the value is cut in halve. During the right-shift zeros are inserted on the left of the register-pair. Bits shifted out of the rightmost position are lost. See also the SRDA instruction.
R6 (Even/Odd Register Pair) 8E 00 00 00 00 00 03 01 2nd Operand

(immediate Value)
R6
02 38 00 00 00 00 00 0C SRDL R6,7
Page 85 of 101
TPF Basic Course

SRL
Mnemonic
Shift right single logical

Operands
SRL
Machine format (RS)
R1 , D2 (B2)
R1
8 12
88
0
/////B2
16 20
D2
31
The data of a register has to be shifted to the right by a number of positions. The SRL (Shift Right single Logical) instruction handles this problem. The number of positions (maximum 63) to be shifted is given in the immediate 2nd-operand, also called as shift value. All 32 bits of the 1st-operand register are included in the right-shift. If the binary value of the 1st-operand register is shifted to the right by one position, the value is cut in halve. During the rightshift zeros are inserted on the left of the 1st-operand register. Bits shifted out of the rightmost position are lost. See also the SRA instruction.ft of the 1st-operand register. The sign bit is not shifted!
R5 A0 88 14 F2
2nd Operand
(immediate Value)
R5 14 11 02 9E SRL R5,3
Page 86 of 101
TPF Basic Course

SRP
Mnemonic
Shift and round packed decimal data

Operands
SRP
Machine format (SS)
D1 (L1 , B1) , D2 (B2) , I3

L1
8
F0
0
I3
12
B1
16 20
D1
B2
32 36
D2
47
To cut and round a packed decimal value, the SRP (Shift and Round Packed decimal data) instruction is performed. The decimal digits of the 1st-operand field are shifted in the direction specified by the 2nd-operand address (only the 6 rightmost bits!). Additionaly, if shifting to the right is specified, the result value of the 1st-operand field is rounded by the rounding factor (I3). It is not used in the leftshift. The instruction can be used for left-shifting up to 31 positions (B'011111') and right-shifting up to 32 positions (B'100000'). The initial contents of the 1st-operand field has to be in correct packed decimal format, otherwise the instruction results in a system error (Data Exception). The result is also in packed decimal format. The result is tested and a condition code is set. In case of an overflow the overflow digits are ignored and additionally the condition code is set to 3.
Condition codes 0 =0 1st operand field is zero 1 <0 1st operand field is negative 2 >0 1st operand field is positive 3 overflow result doesnt fit into the 1st operand field Graphical example
FIELDE 00 00 73 4C
2nd Operand
(Immediate Value) Example : SRP 1st-OP,3,0
FIELDE 07 34 00 0C SRP FIELDE,3,0
If 0-31 ==> LEFTSHIFT; If 32-63==> RIGHTSHIFT
Page 87 of 101
TPF Basic Course

ST
Mnemonic
Store fullword
Operands
ST
Machine format (RX)
R1 , D2 (X2 , B2)
R1
8
50
0
X2
12
B2
16 20
D2
31
To move the four bytes of binary data from a register to a storage location, the ST (STore fullword) instruction is performed. The contents of the source-register (1st operand) are stored in the target-field (2nd operand). The target-field has to be a fullword (->> boundary!) in storage. The source-register remains unchanged.
R1 C7 D6 D6 C4
FIELDA C7 D6 D6 C4
ST R1,FIELDA
Page 88 of 101
TPF Basic Course

STC
Mnemonic
Store character
Operands
STC
Machine format (RX)
R1 , D2 (X2 , B2)
R1
8
42
0
X2
12
B2
16 20
D2
31
To move the low-order byte of binary data from a register to a storage location, the STC (STore Character) instruction is performed. The contents of the low-order byte of the source-register (1st operand) are stored in the target-field (2nd operand). The three high-order bytes of the source-register are ignored. The source-register remains unchanged.
R1 xx xx xx D8
FIELDA D8
STC R1,FIELDA
xx - these bytes are ignored !
Page 89 of 101
TPF Basic Course

STCM
Mnemonic
Store character under mask

Operands
STCM
Machine format (RS)
R1 , M3 , D2 (B2)
M3
12
B E R1
0 8
B2
16 20
D2
31
The STCM (STore Characters under Mask) instruction is an additional instruction to store one or more bytes of data from wanted positions in a register in a storage field. The data of the source-register (1st operand), bytes indicated by the 4-bit mask (3rd operand), are stored at the target-location (2nd operand). The length of the target-field is given by the number of indicated bytes. The source-register remains unchanged. No boundary is wanted! See also the ST, STH and STC instructions.
R2 61 xx 5C 4B
1 2 3
FIELDY 61 5C 4B
STCM R2,B1101,FIELDY
Controlled by the 3rd operand MASK : Here = 1101
Page 90 of 101
TPF Basic Course

STH
Mnemonic
Store Halfword
Operands
STH
Machine format (RX)
R1 , D2 (X2 , B2)
R1
8
40
0
X2
12
B2
16 20
D2
31
To move the two low-order bytes of binary data from a register to a storage location, the STH (STore Halfword) instruction is performed. The contents of the two low-order bytes of the source-register (1st operand) are stored in the target-field (2nd operand). The two high-order bytes of the source-register are ignored. The target-field has to be a halfword (->> boundary!) in storage. The source-register remains unchanged.
R1 FF FF 4B E3
FIELDA 8B E3
STH R1,FIELDA
Page 91 of 101
TPF Basic Course

STM
Mnemonic
Store multiple
Operands
STM
Machine format (RS)
R1 , R3 , D2 (B2)
R3
12
90
0
R1
8
B2
16 20
D2
31
To move the binary data from adjacent registers to a storage location, the STM (STore Multiple) instruction is performed. The contents of the source-registers, which are defined by the starting-register (1st operand) and the ending-register (3rd operand), are stored in the target-field (2nd operand). The source-registers are stored in the ascending order of their register numbers (with register R0 follows register R15). The target-field has to be a sequence of fullwords (->> boundary!) in storage. The number of source-registers defines the length of the target-field. The source-registers remain unchanged.
R3 R4 R5 R6 .. .. .. ..
FA FB FC FD .. .. .. ..
STM R3,R6,FA
FA, FB, FC and FD are FULLWORDS !
Page 92 of 101
TPF Basic Course

TM
Mnemonic
Test under mask

Operands
TM
D1 (B1) , I2
8
91
I2
B1
16
20
D1
31
To test the bits of a single byte of data, whether they are on or off, the TM (Test under Mask) instruction is performed. The bits of the 1st-operand field are selected and tested by an eight-bit mask, given by the 2nd-operand. A mask-bit of 'one' indicates, that the corresponding storage-bit is to be tested. If the mask-bit is zero, the storage-bit is ignored. The 2nd operand is also called the immediate operand. The immediate data (mask), defined at program coding, is contained within the instruction itself. The length of the 1st-operand field is not of interest. Only the 1st byte of the field is tested. The result is indicated in the condition code which may be checked subsequently. The 1st-operand field remains unchanged. 1)* all selected bits are zeros 2)* selected bits are mixed 3)* all selected bits are ones
Condition codes 0 all selected bits are zero 1 selected bits are mixed 2 not used! 3 all selected bits are one Graphical example
1001 1100
Immediate Operand (Mask)
FIELDA 1011 0110
ONLY the indicated bits (ones) are tested !
1st Operand (remains unchanged !)
TM FIELDA,B10011100
Page 93 of 101
TPF Basic Course

TR
Mnemonic
Translate
Operands
TR
D1 (L1 , B1) , D2 (B2)

8
DC
L1
B1
16
20
D1
B2
32
36
D2
47
To translate a hexadecimal value in a field to printable characters, the TR (TRanslate) instruction is performed. Each byte of the 1st-operand field is used as an eight-bit argument to reference a function byte within the 2nd-operand field. First the contents of the argument-byte is added to the initial 2nd-operand address to point at a function-byte. After that the found function-byte replaces the active argument-byte in the 1st-operand field. The instruction is processed from left to right, byte by byte. See also the TRT instruction.
FIELDA
REPLACE (2nd step) (E8) (C5) (E2) 02 05 01
FIELDF
D4
E2
E8
E6
C1
C5
REFERENCE (1st step): Argument added to the address of 2nd Operand field
TR FIELDA,FIELDF
Page 94 of 101
TPF Basic Course

TRT
Mnemonic
Translate and test

Operands
TRT
D1 (L1 , B1) , D2 (B2)

8
DD
L1
B1
16
20
D1
B2
32
36
D2
47
To check a numeric, an alpha or an alphanumeric field for right characters, the TRT (TRanslate and Test) instruction is performed. Each byte of the 1st-operand field is used as an eight-bit argument to reference a function byte within the 2nd-operand field. The contents of the argument-byte is added to the initial 2nd-operand address to point at a function-byte. The processing stops immediately if the found function-byte is not zero (X'00') or the end of the 1st-operand field is reached. The found non-zero function-byte is inserted in the rightmost byte of the register R2 and additionally the related argument-byte address (within the 1st-operand field) is placed into the register R1. If all found function-bytes are zero, the contents of registers R1 and R2 remain unchanged. The result of the instruction is also indicated in the condition code which may be checked subsequently. The instruction is processed from left to right, byte by byte. See also the TR instruction. 1)* all function bytes found are zero 2)* a nonzero function byte is found 3)* a nonzero function byte is found and last byte 1st opnd
Condition codes 0 all function bytes found are zero 1 a nonzero function byte is found 2 a nonzero function byte is found and its the last byte of the 1st operand field 3 not used! Graphical example
FIELDA
Register R1 points to this address ! (Result) 01 05 00 02 05
FIELDF
IGNORED 08 Function byte to Register R2 (Result) 08 00
00
00
08
00
REFERENCE (1st step): Argument added to the address of 2nd Operand field
TRT FIELDA,FIELDF
Page 95 of 101
TPF Basic Course

UNPK
Mnemonic
Unpack
Operands
UNPK
D1 (L1 , B1) , D2 (L2 , B2)

L2
12
F3
0
L1
8
B1
16 20
D1
B2
32 36
D2
47
The UNPK (UNPacK) instruction converts packed decimal data to zoned format. The packed decimal data of the source-field (2nd operand) is converted to zoned-format data and placed in the target-field (1st operand). The assembler must know the length of each operand field, which may be up to 16 (!) bytes long. Execution proceeds from right to left. If the length of the 1st-operand (receiving) field is too small, the leftmost positions of the 2nd-operand (sending) field are truncated. If the length of the receiving field is too large, decimal zeros are added. The source-field remains unchanged.
FIELDA F4 F2 F5
FIELDB 42 5F
UNPK FIELDA,FIELDB
The target field will be left padded with decimal zeroes !
Page 96 of 101
TPF Basic Course

Exclusive or fullword
Operands
Mnemonic
X
Machine format (RX)
R1 , D2 (X2 , B2)
R1
8
57
0
X2
12
B2
16 20
D2
31
To set single bits of a register to 'one' or to 'zero' in one step, the X (eXclusive or fullword) instruction is performed. The 'one'bits of the 1st-operand register are changed to 'zero', respectively the 'zero'-bits are changed to 'one', if the corresponding bits of the 2nd-operand field, a fullword (->> boundary!) in storage, are 'one'. In all other cases the bits of the 1st-operand register remain unchanged. The result is indicated in the condition code which may be checked subsequently. See also the XR instruction.ain unchanged.
Page 97 of 101
TPF Basic Course

XC
Mnemonic
Exclusive or character
Operands
XC
D1 (L1 , B1) , D2 (B2)

8
D7
L1
B1
16
20
D1
B2
32
36
D2
47
To set single bits of a storage field to 'one' or 'zero' in one step, the XC (eXclusive or Character) instruction is performed. The 'one'-bits of the 1st-operand field are changed to 'zero', respectively the 'zero'-bits are changed to 'one', if the corresponding bits of the 2nd-operand field are 'one'. In all other cases the bits of the 1st-operand field remain unchanged. The result is indicated in the condition code which may be checked subsequently.
Page 98 of 101
TPF Basic Course

XI
Mnemonic
Exclusive or immediate
Operands
XI
D1 (B1) , I2
8
97
I2
B1
16
20
D1
31
To set the bits of a single byte of data to 'one' or to 'zero' in one step, the XI (eXclusive or Immediate) instruction is performed. The 'one'-bits of the 1st-operand field are changed to 'zero', respectively the 'zero'-bits are changed to 'one', if the corresponding bits of the 2nd-operand field are 'one'. In all other cases the bits of the 1st-operand field remain unchanged. The 2nd operand is also called the immediate operand. The immediate data, defined at program coding, is contained within the instruction itself. The length of the 1st-operand field is not of interest. Only the 1st byte of the field is considered. The result is indicated in the condition code which may be checked subsequently.
Immediate Operand Bit in 2nd OP 0 0 1 1 0110 1011 1st Operand Field Bit in 1st OP 0 1 0 1 1011 1000 Result 1st Operand Field Result in 1st OP 0 1 1 0 1101 0011
Page 99 of 101
TPF Basic Course

XR
Mnemonic
Exclusive or register
Operands
XR
Machine format (RR)
R1 , R2
R1
8
17
0
R2
12 15
To set single bits of a register to 'one' or 'zero' in one step, the XR (eXclusive or Register) instruction is performed. The 'one'-bits of the 1st-operand register are changed to 'zero', respectively the 'zero'-bits are changed to 'one', if the corresponding bits of the 2nd-operand register are 'one'. In all other cases the bits of the 1st-operand register remain unchanged. The result is indicated in the condition code which may be checked subsequently. See also the X instruction.
Page 100 of 101
TPF Basic Course

ZAP
Mnemonic
Zero and add packed decimal data

Operands
ZAP
D1 (L1 , B1) , D2 (L2 , B2)

L1
8
F8
0
L2
12
B1
16 20
D1
B2
32 36
D2
47
To set up packed decimal data in an other field, the ZAP (Zero and Add Packed decimal data) instruction is performed. First the 1st-operand field is set to packed decimal zero. Then the contents of the 2nd-operand field is added to the 1st-operand zero value. The initial contents of the 2nd-operand field has to be in correct packed decimal format, otherwise the instruction results in a system error (Data Exception). The result is also in packed decimal format. The 2nd-operand field remains unchanged. The calculation follows algebraic rules. The result is tested and a condition code is set. In case of an overflow the overflow digits are ignored and additionally the condition code is set to 3
FIELDC C2 00 40 4A F5
1st Step : Operand is set to packed decimal zero
FIELDD 00 09 20 8C
+
DECIMAL ADDITION of packed data (2nd Step)
FIELDC 00 00 09 20 8C ZAP FIELDC,FIELDD
Page 101 of 101

Assembler Instructions

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Assembler Instructions

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ASSEMBLER INSTRUCTIONS

TPF Basic Course

1998 Atraxis AG, TPFDF Support , Zurich-Airport, Switzerland

Printed 29. Jul 2011

TPF Basic Course

Street & Nbr L30 Street L26

P-Code & Cityname L20 P-Code L4 Cityname L16

1st Name 2 L14

label of the previous DSECT relative address is set to 000

1998 Atraxis AG, TPFDF Support , Zurich-Airport, Switzerland

Printed 29. Jul 2011

TPF Basic Course

1998 Atraxis AG, TPFDF Support , Zurich-Airport, Switzerland

Printed 29. Jul 2011

TPF Basic Course

1998 Atraxis AG, TPFDF Support , Zurich-Airport, Switzerland

Printed 29. Jul 2011

TPF Basic Course

EQU DS EQU DS DS DS EQU EQU EQU EQU EQU EQU

20 CL40 LFIELDA CL4 CL26 CL4 * PCODE-NBR STREET+5 X44 CA B01111111

X14 / 2010 X28 / 4010

1998 Atraxis AG, TPFDF Support , Zurich-Airport, Switzerland

Printed 29. Jul 2011

TPF Basic Course

XL4567AB P-1234 P324 PL21234 B11001

324C 234C B00011001

1998 Atraxis AG, TPFDF Support , Zurich-Airport, Switzerland

Printed 29. Jul 2011

TPF Basic Course

1st step: copy

2nd step: duplicate

Task Notes inserted

1998 Atraxis AG, TPFDF Support , Zurich-Airport, Switzerland

Printed 29. Jul 2011

TPF Basic Course

Code (editor in TSO)

152 bytes of machine code

some more Assembler instructions FINIS

1998 Atraxis AG, TPFDF Support , Zurich-Airport, Switzerland

Printed 29. Jul 2011

TPF Basic Course

1998 Atraxis AG, TPFDF Support , Zurich-Airport, Switzerland

Printed 29. Jul 2011

TPF Basic Course

1998 Atraxis AG, TPFDF Support , Zurich-Airport, Switzerland

Printed 29. Jul 2011

TPF Basic Course

1998 Atraxis AG, TPFDF Support , Zurich-Airport, Switzerland

Printed 29. Jul 2011

TPF Basic Course

Assembly of the SourceProgram

Linking with other Programs

Linkage Editor / Binder

1998 Atraxis AG, TPFDF Support , Zurich-Airport, Switzerland

Printed 29. Jul 2011

TPF Basic Course

1998 Atraxis AG, TPFDF Support , Zurich-Airport, Switzerland

Printed 29. Jul 2011

TPF Basic Course

1998 Atraxis AG, TPFDF Support , Zurich-Airport, Switzerland

Printed 29. Jul 2011

TPF Basic Course

Add packed decimal data