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  • Reading Cell Library Information and Netlist For APR: 1. Design Import Design

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    kiranravoori
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    The document provides instructions for importing a design and setting up an APR flow in Cadence Encounter for timing analysis, clock tree synthesis, optimization, routing, and LVS checking. Key steps include importing the netlist and libraries, defining the floorplan and power structure, placing cells, connecting power and clocks, running optimizations pre- and post-CTS, adding I/O fillers, and using Nanoroute for detail routing while preventing antenna and crosstalk issues. The final step is to check the routing for LVS errors.

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    SoC Encounter

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    The document provides instructions for importing a design and setting up an APR flow in Cadence Encounter for timing analysis, clock tree synthesis, optimization, routing, and LVS checking. Key steps include importing the netlist and libraries, defining the floorplan and power structure, placing cells, connecting power and clocks, running optimizations pre- and post-CTS, adding I/O fillers, and using Nanoroute for detail routing while preventing antenna and crosstalk issues. The final step is to check the routing for LVS errors.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
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    343 views37 pages

    Reading Cell Library Information and Netlist For APR: 1. Design Import Design

    Uploaded by

    kiranravoori
    The document provides instructions for importing a design and setting up an APR flow in Cadence Encounter for timing analysis, clock tree synthesis, optimization, routing, and LVS checking. Key steps include importing the netlist and libraries, defining the floorplan and power structure, placing cells, connecting power and clocks, running optimizations pre- and post-CTS, adding I/O fillers, and using Nanoroute for detail routing while preventing antenna and crosstalk issues. The final step is to check the routing for LVS errors.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 37

    ReadingCellLibraryinformationandNetlistforAPR

    1. Design>ImportDesign

    2. IntheBasictab,fillthefollowingfield: Netlist Files:CHIP_unique.v TopCell: ByUser:CHIP TimingLibraries MaxTimingLibraries: slow.libtpz973gvwc.lib( SOCE/lib/) MinTimingLibraries: fast.libtpz973gvbc.lib( SOCE/lib/) PhysicalLibraries LEFFiles: tsmc18_6lm_cic.lef tsmc18_6lm_antenna_cic.lef tpz973gv_6lm_cic.lef antenna.lef ( SOCE/lef/) TimingConstraint TimingConstraintFile:CHIP.sdc IOAssignment IOAssignmentFiles:CHIP.io

    3. IntheAdvanced=>Powertab,fillthefollowingfield: Power/GroundNets PowerNets: VDD GroundNets: VSS

    4. IntheAdvanced=>RCExtractiontab,fillthefollowingfield: RCExtraction TypicalCapacitanceTableFile: tsmc018.capTbl (SOCE/) BestCapacitanceTableFile: tsmc018.capTbl (SOCE/) WorstCapacitanceTableFile: tsmc018.capTbl (SOCE/) QX(SignOffRCExtraction) QXTechFile: icecaps_5lm.tch(SOCE/FireIce)

    5. IntheAdvanced=>SIAnalysistab,fillthefollowingfield: CeltICLibraries Max.cdbFile: slow.cdB (SOCE/celtic) Min.cdbFile: fast.cdB (SOCE/celtic)

    6. Savecurrentsettings: ClickSavebutton Filename: CHIP.conf ( SOCE , /usr3/ce21/student/ ) ClickOKbutton

    SpecifyChipFloorplan
    1. Floorplan>SpecifyFloorplan

    2. Specifycoresize: SpecifyDimensionsby CoreSizeby: Dimension: Height: 800 Width: 800

    3. CoreMarginsby: CoretoIOBoundary CoretoLeft: 100 CoretoRight: 100 CoretoTop: 100 CoretoBottom: 100 4. Applythespecification: ClickOKbutton

    Connect/DefineGlobalNet
    1. Floorplan>ConnectGlobalNets

    2. AddallVDDpinstoConnectionList: Connect Pin:PinName(s):VDD Scope ApplyAll ToGlobalNets:VDD ClickAddtoListbutton 3. AddallVDDnetstoConnectionList: Connect NetBasename:VDD Scope ApplyAll ToGlobalNets:VDD ClickAddtoListbutton 4. AddallTieHighpinstoConnectionList: Connect TieHigh Scope ApplyAll ToGlobalNets:VDD ClickAddtoListbutton 5. AddallGNDpinstoConnectionList: Connect Pins:PinName(s):VSS Scope ApplyAll ToGlobalNets:VSS ClickAddtoListbutton 6. AddallGNDnetstoConnectionList: Connect NetBasename:VSS Scope ApplyAll ToGlobalNets:VSS ClickAddtoListbutton 7. AddallTieLowpinstoConnectionList: Connect TieLow Scope ApplyAll ToGlobalNets:VSS ClickAddtoListbutton 8. Applytheconnectionlistandcheck: ClickApplybutton ClickCheckbutton ClickClosebutton

    PowerPlanning(AddPowerRings)
    1. Power>PowerPlanning>AddRings

    2. IntheBasictab,fillthefollowingfield: Specifymetallayersandwidth TopLayer: metal3H Width:9 BottomLayer: metal3H Width:9 LeftLayer: metal2V Width:9

    RightLayer: metal2V Width:9 ClickUpdatebutton Specifyoffset Centerinchannel

    3. IntheAdvancedtab,fillthefollowingfield: Configurewiregroup Usewiregroup Interleaving Numberofbits:4 4. Applythespecification: ClickApplybutton Checkiftheringiscorrectlycreated.Ifnot,clickundobutton(inencounter toolbar)andrepeatstep2~4again. ClickCancelbutton

    PowerPlanning(AddStripes)
    1. Power>PowerPlanning>AddStripes

    2. Createverticalpowerstripes: Specifymetallayer,width,directionandspacing Layer: metal2 Direction: Vertical Width: 9 ClickUpdateButton Specifysettosetdistance Settosetdistance: 100 Specifylocationsby Relativefromcoreorselectedarea Xfromleft: 50 Xfromright:50 ClickApplybutton Checkifthestripesarecorrectlycreated.Ifnot,clickundobutton(in encountertoolbar)andrepeatstepsagain. 3. Createhorizontalpowerstripes: Specifymetallayer,width,directionandspacing Layer: metal3 Direction: Horizontal Width: 9 ClickUpdateButton Specifysettosetdistance Settosetdistance: 100 Specifylocationsby Relativefromcoreorselectedarea Yfromleft: 50 Yfromright:50

    ClickApplybutton Checkifthestripesarecorrectlycreated.Ifnot,clickundobutton(in encountertoolbar)andrepeatstepsagain. ClickCancelbutton

    ConnectCorePowerPin 1. Route>SpecialRoute

    2. Connectcorepower: Setthefollowingconfiguration Blockpins Padpins Padrings Standardcellpins Stripes(unconnected) ClickOKbutton


    3. InAdvancedtab>Padpins>NumberofConnectionstoMultipleGeometries: All

    PlaceStandardCells
    1. Place>Specify>PlacementBlockage

    2. Specifyplacementblockageforstripes Specifyplacementblockageundermetal1andmetal2andmetal3 M1 M2 M3 M4 M5 ClickOKbutton


    3. Place>StandardCellsAndBlocks

    ConnectStandardCellPowerLine
    1. Route>SpecialRoute 2. Connectcorepower: Setthefollowingconfiguration Blockpins Padpins Padrings Standardcellpins Stripes(unconnected) ClickOKbutton

    InPlaceOptimization(IPO)BeforeClockTreeSynthesis
    1. Timing>AnalysisTiming


    2. PerformFirstEncountertrialroutetomodeltheinterconnectionRCeffects DesignStage preCTS AnalysisType Setup ClickOKbutton

    WNS,TNSmust 0 ViolatingPathsmust=0

    Max_cap,Max_tran,Max_fanoutmustbezero(includeRealandTotal) 3. Ifthetimingslackisnegative,orthereareDRVs,openTiming>Optimizationin encountermenu

    OryoucantypeoptDesignpreCTStocorrectsetupviolationsanddesignrule violation Tofurtheroptimizeadesignafterabovecommandexecution optDesignpreCTSincr1orincr2orincr3( optimize 1)

    ClockTreeSynthesis(CTS)
    1. Clock>DesignClock


    2. CellList:ChooseCLKBUFX1~CLKINVXL Add OutputSpecificationFile:Clock.ctstch OK

    3. OK

    4. Clock>Display>DisplayClockTree


    ClickOKbutton

    5. Clock>Display>DisplayClockTree DisplayClockTree AllLevel


    6. Clock>Display>ClearClockTreeDisplay

    InPlaceOptimization(IPO)AfterClockTreeSynthesis
    1. Timing>AnalysisTiming

    2. AfterCTS,furthertimingoptimizationisperformedtomeettimingconstraintsif

    thereisnegativetimingslackorDRVs.OpenTiming>Optimizationinencounter menu WNS,TNSmust 0 Max_cap,Max_tran,Max_fanoutmustbezero(includeRealandTotal)

    OryoucantypeoptDesignpostCTStocorrectsetupviolationsanddesignrule violation Tofurtheroptimizeadesignafterabovecommandexecution optDesignpostCTSincr1orincr2orincr3( optimize 1) 3. Timing>AnalysisTiming

    4. AfterCTS,furthertimingoptimizationisperformedtomeettimingconstraintsif thereisnegativetimingslackorDRVs.OpenTiming>Optimizationinencounter menu WNS,TNSmust 0 Max_cap,Max_tran,Max_fanoutmustbezero(includeRealandTotal)

    OryoucantypeoptDesignpostCTSholdtocorrectsetupviolationsand designruleviolation Tofurtheroptimizeadesignafterabovecommandexecution optDesignpostCTSholdincr1orincr2orincr3( optimize 1)

    AddPADFiller
    1. Inencountercommandprompt,executethefollowingcommands: addIoFillercellPFILLER20prefixIOFILLER addIoFillercellPFILLER10prefixIOFILLER addIoFillercellPFILLER5prefixIOFILLER addIoFillercellPFILLER1prefixIOFILLER addIoFillercellPFILLER05prefixIOFILLER addIoFillercellPFILLER0005prefixIOFILLERfillAnyGap PADfillermustbeaddedbeforedetailroute,ortheremayhavesomeDRC/LVS violationsafterPADfillerinsertion

    SIPreventionDetailRoute(NanoRoute)
    1. Route>NanoRoute>Route

    2. Nanoroutecanpreventcrosstalkeffectsandfixantennaruleviolations,alsoit routesdesigntomeettimingconstraints. Configureroutingfeatures FixAntenna InsertDiodes DiodeCellName:ANTENNA TimingDriven Effort:10 SIDriven ClickOKbutton

    3. Verify>Connectivity(CheckroutingforLVSerror)

    ClickOKbutton Ifyouseeanyviolations,routingresultisnotcorrect.(LVSerror)

    4. Verify>Geometry(CheckroutingforDRCerror)

    Allow OverlapofPadFillerCells ClickOKbuttonIfyouseeanyviolations,routingresultisnotcorrect.(DRCerror)

    InPlaceOptimization(IPO)

    AfterCTS,furthertimingoptimizationisperformedtomeettimingconstraintsif thereisnegativetimingslackorDRVs.OpenTiming>Optimizationinencounter menu WNS,TNSmust 0 Max_cap,Max_tran,Max_fanoutmustbezero(includeRealandTotal)

    OryoucantypeoptDesignpostRoutetocorrectsetupviolationsanddesign ruleviolation Tofurtheroptimizeadesignafterabovecommandexecution optDesignpostRouteincr1orincr2orincr3( optimize 1)

    AfterCTS,furthertimingoptimizationisperformedtomeettimingconstraintsif thereisnegativetimingslackorDRVs.OpenTiming>Optimizationinencounter menu WNS,TNSmust 0 Max_cap,Max_tran,Max_fanoutmustbezero(includeRealandTotal)

    OryoucantypeoptDesignpostRouteholdtocorrectsetupviolationsand designruleviolation Tofurtheroptimizeadesignafterabovecommandexecution optDesignpostRouteholdincr1orincr2orincr3( optimize 1)

    InPlaceOptimization(considercrosstalkeffects)
    1. Timing>AnalysisTiming

    AfterCTS,furthertimingoptimizationisperformedtomeettimingconstraintsif thereisnegativetimingslackorDRVs.OpenTiming>Optimizationinencounter menu WNS,TNSmust 0 Max_cap,Max_tran,Max_fanoutmustbezero(includeRealandTotal) Glitchviolationmustbezero

    OryoucantypeoptDesignpostRoutesitocorrectsetupviolationsand designruleviolation Tofurtheroptimizeadesignafterabovecommandexecution optDesignpostRoutesiincr1orincr2orincr3( optimize 1)

    Ifholdtimeslackisnegative,openTiming>Optimizationinencountermenu

    OryoucantypeoptDesignpostRouteholdsitocorrectsetupviolationsand designruleviolation Tofurtheroptimizeadesignafterabovecommandexecution optDesignpostRouteholdsiincr1orincr2orincr3( optimize 1)

    AddCOREFillerCells
    1. Place>PhysicalCells>AddFiller

    2. AddcorefillertoimproveelectriceffectsofNWELLandPWELL: ClickSelectbutton Selectallcorefillercells ClickAddbutton ClickClosebutton ClickOKbutton

    StreamOutandWriteNetlist
    1. Timing>CalculateDelay IdealClock SDF Output File: CHIP.sdf Click OK button

    2.SavedesignnetlistCHIP.vforpostlayoutsimulation: Inencountermenu,openDesign>Save>Netlist NetlistFile:CHIP.v ClickOKbutton

    PostLayoutGateLevelSimulation
    1. Changetodirectory05_Post_Sim 2. PerformPostLayoutGatelevelsimulationofCHIP.v %lns../04_LAYOUT/CHIP.v %lns../04_LAYOUT/CHIP.sdf %lns../TESTBED.v %lns../PATTERN.v %ncverilogf01_run.f

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