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PLL Theory Tutorial

J P Silver E-mail: john@rfic.co.uk

1 ABSTRACT
This tutorials discusses the key areas of Phase Locked Loop (PLL) design, covering the main components of the loop ie the phase detector, divider, VCO & loop filter.

Overall transfer function =

G T ( s) 1 + G T ( s ).H(s)

3 LOOP COMPONENTS
3.1 PHASE DETECTOR Phase detectors can be either analogue eg mixer or digital eg D-type flip-flop. When a mixer is used the output consists of the sum and difference frequencies. The sum of the frequencies are filtered out by the loop filter and the remaining difference frequency (otherwise known as the beatnote) when both input frequencies are the same is the phase difference. This beatnote or phase error signal is filtered in the loop filter to produce a DC control voltage for the VCO. Most PLL circuits now use digital phase detectors as shown in Figure 2.

2 INTRODUCTION [ 1,2 &3]

A phase locked loop schematic is shown in Figure 1. Pi(s) represents the phase of the reference oscillator, while Pe(S) is the error phase signal which is filtered and used to drive a VCO. The transfer function of this section is represented by G(S). A Voltage Controlled Oscillator (VCO) can be swept over the frequency range of interest by a control voltage. Some of the VCO output is fed back and compared with a reference frequency in a Phase Detector (PD). The reference is usually a crystal oscillator but might be the output of another loop for example. The PD generates an error voltage, which steers the VCO to lock it to the same frequency as the reference. This simple system produces an output on the same frequency as the reference crystal oscillator. In a practical system it is necessary to add a programmable divider, a reference divider and a loop filter.
Reference MHz Phase Detector K0 V/Rad Loop FilterIntegrator G(s) Kd MHz/V Output

Vhigh

Current Source

D D type Flip-Flop Q1

F1

Clk

Vhigh

Clear

NAND

Pi(s)

Pe(s)

D type Flip-Flop Q2 C
Current Sink

F2

Clk

Prescalar/ Divider N
H(s)

Figure 2 D-Type Flip-Flop Phase Detector

Figure 1 Schematic of a phase locked loop

H(s) represents the feedback transfer function which in this case is formed by the divider with division ratio = H(s) = N. The forward transfer function GT(s) is the Loop filter transfer function G(s) * K0 * Kd.

Refering to Figure 3. Signal F1 arrives at the D-type flip-flop 1 first causing the output Q1 to go high (This will stay high until F1 is clocked high again). F2 arrives at D-type flip-flop 2 causing Q2 to go high, at this point there will be two ones on the NAND gate causing the output (the clear to the flip-flops) to go low and this will cause both flip-flops to reset with Q1 & Q2 going low again. Now Q2 only went high when F2 was

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high but was immediately reset due to the NAND hence we will see a pulse out of Q2. The spacing between these pulses or the duty cycle will give the time delay between F1 & F2. The clear is the inversion of Q2. If we now add a capacitor to the output the pulsed voltage will be smoothed to give an average voltage which, is highest when the frequencies F1 & F2 are 180 degrees apart.
F1 Input

F1 Input

F2 Input

Q1

Q2

F2 Input

Clear

Q1

Figure 5 Both F1 & F2 in phase

Q2

The phase response of the phase detector is shown in Figure 6, where the slope of the graph is the phase detector sensitivity in V/rad.

Clear
Vhigh

Figure 3 Phase detector Input & output signals. F1 leads F2

In the case where F2 leads F1 the Q1 & Q2 outputs are reversed as shown in Figure 4.
F1 Input

Vhigh/2

Phase detector Sensitivity (V/rad) = slope of graph

Output Voltage (V) 0

Input phase difference (rad)

F2 Input

Typically if Vhigh = 5V then Kd = 5/2 = 0.8V/rad

Q1

Figure 6 D-type flip-flop phase detector output characteristic.

Q2

The outputs Q1 & Q2 turn on the current sources, which either sink or source current. This will cause a voltage to ramp up or down (as the capacitor charges up and down, depending on the phase difference between F1 & F2) This circuit is known as the charge pump and is shown in Figure 8.

Clear

Figure 4 Phase Detector Outputs F2 leads F1

The third case is where the two inputs signals are in phase resulting in a low average voltage ~ 0V from Q1/Q2 as shown in Figure 5.

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3.2 SQUARER The signals from the VCO and reference may well be analogue (ie a sine wave) and if an analogue mixer is being used as a phase detector, then these signals will mixed to produce a DC control voltage on the IF port of the mixer. However if we are going to use a digital phase detector (as described in section 3.1) we need to ensure that the reference and RF signals are square waves. If the loop consists of a prescaler on the RF path then the output of the prescaler to the phase detector will be a square wave. But if the VCO RF and/or analogue reference signal is feed to the phase detector directly then a squarer circuit is required. A simple squarer circuit is shown in Figure 7.
Vcc

Vhigh

D D type Flip-Flop Q1
R Clear NAND R

F1

Clk

Vhigh

Rfilter

D type Flip-Flop

Q2 Cfilter

F2

Clk

Figure 8 Output connection of Phase Detector if not using a charge pump.

Vcc

Rc Rfeedback
Analogue Input

Squarewave Output

Q1
Q1
Rb Re Logic Inverter

Kd =

Vcc (V/rad) 2

Vcc *1000 R (mA/rad) Kd = 2

To loop filter

To loop filter

0V

0V

Figure 7 Squarer circuit. Ths common-emitter circuit uses series feedback to make the circuit broadband. The output logic inverter futher cleans up the squared signal from the bipolar amplifier.

Q2

3.3 CHARGE PUMP The charge pump consists of a push-pull current source, current sink arrangement that connects to a shunt capacitor (part of the loop filter) that effectively smooths the clock pulses to give a constant DC level dependant on the duty cycle of the phase detector pulsed output. This arrangement is used to allow the designer to set the value of the phase detector gain Kd. If using an op-amp loop filter the outputs of the phase detector can be connected together using two resistors as shown in Figure 8. If using a charge pump (and a VCO whose control voltage is the within the range offered by the charge pump) then a simple loop filter can be used, consists of the RC circuit, as shown in Figure 8.

Figure 9 Typical Charge Pump Arrangement, with equations for calculating Kd.

3.4 SIMPLE LOOP FILTER The simplest loop filter consists of a passive RC filter as shown in Figure 10. Using such a circuit is fine for VCOs that use the same voltage supplies as the charge pump. If the control voltage of the VCO exceeds that generated by the charge pump then an active op-amp based loop filter is required.

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N=

Maximum VCO frequency Phase Detector frequency

Icp = Charge pump current (mA/rad)

f - Ln a f step Settling time ts (s) = 2 * * fn Where fa = Settling frequency releative to the final frequency required in time ts. ts = Desired settling time. = Damping Factor fstep = Frequency change fn = loop cut - off frequency

Loop bandwidth

1 2 * fn + Hz 4 2

These equations allow us to calculate the loop filter requirements, knowing the required lock time ts, Damping Factor , Division ratio N, Kvco (MHz/V) and Kd (charge pump current mA/rad). 3.5 ACTIVE LOOP FILTER In situations where the control range of the VCO is covered by the output of the PLL a passive loop filter is ideal. However, in most systems the VCO may have a larger control range and in these situation active loopfilters using an op-amp are used. In particular a popular circuit is the differential type II op-amp loop filter as shown Figure 11. This effectively uses the Q1 & Q2 outputs of the phase detector directly (bypassing the charge pump) and has the added advantage of better noise reduction than a single-input op-amp loop filter.
R2

From charge pump

R2

To VCO

R1

C1

C3

C2

Figure 10 Basic passive loop filter (Type I)

Calculation of C2
C2 = Icp * Kvco N * (2 * fn) 2

C2
R1/2 R1/2

0V

Vin1 C1

V1

Calculation of R1
R1/2 R1/2

Vo

N R1 = 2 * * Icp * Kvco * C2
Vin2

Calculation of C1

C1

V2 R2

C1 =

C2 10

C2

Optional spurious breakthrough filter

Figure 11 Type II Active Differential loop filter

Let fspur = 10 * fn C3 = 1 2 * fspur * C3

The differential loop filter can be simplified for analysis as shown in Figure 12. The loop filter components can be found from the following formulae:

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R2

C2
R1/2 R1/2

R3 1 + Vo = R2 sC2.R2 1 1 Vin + sC1.R1 + R1 R2 sC2.R2.

x top & bottom by sC2.R2

Vin C1 V1

Vo

R3 sC2.R2 + R2 sC2.R2 = sC2.R2 sC2.R2 + sC2.R2.sC1.R1 + R1 R2 = sC2.R3 + 1 sC2.R2 + s 2 C2.R2.C1.R1 + sC2 R1 sC2.R3 + 1 R2 s C2.R2.C1.R1 + sC2 + 1 R1
2

Figure 12 Simplified Type II active loop filter

Vin - V1 V1 V1 = 0 1 R1 R2 sC1

Vo = Vin

Let C1 = C2 = Cx

; R1 = R2 = Rx ; CxRx = T1; CxR3 = T2

1 Vin 1 = V1 + sC1 + R2 R1 R1 R1 Vin = V11 + sC1.R1 + R2 V1 = R2 Vo R3 + 1 sC2

x by R1

Vo 1 + sT2 = G(s) = Vin (sT1)2 + 2sT1

The open-loop gain can now be found with reference to the block diagram shown in Figure 13.
Ko.Kd V/dB ATTENUATION 1/N

V1 = Vo.R2 Divide top & bottom by R2 1 R3 + sC2 Vo R3 1 + R 2 sC2.R2 Vo R3 1 + R 2 sC2.R2 R1 1 + sC1.R1 + R2

LOOP FILTER G(s)

Figure 13 Block diagram of the PLL Closed-loop

Vin = -

Open - Loop Gain LG(s) = Kd.Ko .G(s) N

Kd.Ko (1 + sT2 ) N LG(s) = (sT1 )2 + 2sT1

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Closed - Loop Gain Kd.Ko .G(s) 1 N H(s) = = Kd.Ko 1 1+ .G(s) 1+ Kd.Ko N .G(s) N H(s) = 1+ 1

For a range of damping factors we can calculate the predicted phase margin as shown in Table 1. Dampi Factor 0 0.5 0.707 1 Phase Margin (degrees)

(sT1 )2 + 2sT1
Kd.Ko .G(s)(1 + sT2 ) N

0 51.8 65.5 76.3

Table 1 Resulting phase margins from a given damping factor.

3.5.1 Loop Filter Calculation of R1

N= VCO frequency Phase detector frequency

If assume a damping factor of 0.707 to give us a phase margin of 65 degrees the value of R2 is given by:

n . 2 2

Loop bandwidth = 2 . n Kv = VCO sensitivity (MHz/V); K = Phase detector sensitivity (mA/rad) 1 = R1.C2

2 = R2.C2 = n .R2.C2 2
3.5.3 Loop filter calculation of C1
Assume that Fc = 10 * Fn c = 1 2Fc R1.C1 4 C1 = 4. c R1

n =

K v .K N.1 K v .K Rearrange to get R1 N.R1.Cc

n =

Assume a value for C2 R1 = K v .K

n 2 .N.C2

c =

3.5.2 Loop filter Calculation of R2 The value of R2 is determined by setting the phase margin of the loop and is related to the damping factor . The phase margin, being the difference between the argument of the loop gain and -180 at the frequency where the loop gain is unity is given by:-

2 -1 2 4 = tan -1 = tan 2 2 + 4 + 1 n

3.6 DIVIDER/PRESCALER In most designs the VCO (Voltage controlled oscillator) runs at a much higher frequency than the maximum frequency limit of the phase detector, which is limited by the speed of the logic employed. In these situations a small amount of VCO output power is coupled off to a prescaler. The prescaler is a high frequency divider but is fed by an analogue signal but outputs a divided square wave suitable for the phase detector circuits. Most prescalers consist of a differential amplifier connected to

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cascaded J-K flip-flop circuits and are usually built into the PLL chip.

PhaseNoiseMod MOD2 Fnom=fcentre Rout=50 Ohm Fcorner=30 MHz NF=5 dB QL=15

Phase Noise Mod

This simulates the open-loop phase noise of the VCO

The addition of the prescaler in the PLL will increase the noise contribution in the loop by: Noise floor of prescaler + 20*Log N Where N is the division ratio For example: Prescaler device: Agilent HMMC 3128 Division ratio: 200 Phase noise @ 10KHz offset: -143dBc/Hz Additional phase noise = 20 log 200 = 46dB Therefore, the prescaler phase noise contribution to the loop would be: -143 + 46 = -97dBc/Hz @ 10KHz 3.7 VOLTAGE CONTROLLED OSCILLATOR (VCO) [4] The VCO is the heart of the PLL and dominates the overall phase noise performance of the loop. As has been shown in other tutorials the phase noise performance of the VCO (free running) is dependant on several key design parameters including loaded Q factor, noise figure and output power of the VCO. To determine the approximate phase noise performance of the VCO these parameters can be used with Leesons equation to estimate the phase noise of the VCO. To verify hand calculations the key VCO parameters can be fed into the ADS simulation shown in Figure 14. In the ADS simulation a VCO has the following: VCO center frequency: 2GHz, Noise Figure: 5dB Loaded Q: 15 Flicker Corner frequency: 30MHz

P_1Tone PORT1 Num=1 Z=50 Ohm P=dbmtow(10) Freq=fcentre

PM_DemodTuned DEMOD2 Sensitivity=180/pi Fnom=fcentre Rout=50 Ohm

Var Eqn

VAR VAR3 fcentre=2000MHz

HARMONIC BALANCE
HarmonicBalance HB1 Freq[1]=fcentre Order[1]=7 NLNoiseStart=100 Hz NLNoiseStop=40 MHz NoiseOutputPort=2 NoiseNode[1]="PNoise_OL"
Meas Eqn

MeasEqn meas1 PNoise_OLout=real(PNoise_OL[0]) VCO_OLout=VCO_OL[2]

Figure 14 ADS simulation used to predict phase noise performance given the resonator loaded Q, NF, Flicker corner frequency, centre frequency and output power.
PhaseNoise

Phase noise prediction (Bipolar device) assumimg loaded Q of 15 @2000MHz

0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 -105 -110 -115 -120 -125 -130 -135 -140 -145 -150 -155 -160 -165 -170 -175 -180 1E2

m2

m2 indep(m2)=1.000E4 plot_vs(PhaseNoise, noisefreq)=-75.383

1E3

1E4 noisefreq, Hz

1E5

1E6

EqnPhaseNoise=10*log(0.5*VCO_phasenoise..PNoise_OL.noise**2)

Figure 15 Resulting simulation from Figure 14, showing the resulting phase noise prediction with a marker set to 10KHz frequency offset and VCO loaded Q to 15.

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4 SUMMARY
This tutorial described the basic operation of a Phase Locked loop (PLL). A description of each component within the loop (ie VCO, Squarer, Prescaler, Loop filter & phase detector) was given and where necessary the relevant design equations. Emphasis was given to the design of passive and mire commonly active loop filters that define the overall phase noise response of the closed loop and the switching time in multi-channel PLLs. Further tutorials with give an example of PLL switching time and PLL phase noise performance.

5 REFERENCES
[1] Microwave and Wireless Synthesiser Theory and Design Ulrich L Rohde, 1997, Wiley-Interscience, ISBN 0-471-52019-5 [2] RF and Microwave Circuit Design For Wireless communications, L E Larson, 1997, Artech House ISBN 0-89006-818-6, Chapter 6. [3] Radio Frequency Design Wes Hayward, 1994, The American Radio Relay League, ISBN 0-87259-492-0, Chapter 7. [4] Oscillator Design and Simulation, Randall W Rhea, 1995, Noble Publishing, ISBN 1-884932-30-4, p 35.