Sessions

CMOS Sigma-Delta Converters From Basics to State-of-the-Art
Basic Concepts and Architectures

Roco del Ro, Beln Prez-Verd and Jos M. de la Rosa Roc R Bel rez- Verd Jos
{rocio,belen,jrosa}@imse.cnm.es
KTH, Stockholm, April 23-27

IMSE-CNM Design Group
OUTLINE 1. Introduction 2. Fundamentals of ADCs

Oversampling Quantization noise shaping Basic architecture Classification of ADCs
3. Discrete-Time Modulators
Single-bit single-quantizer architectures Single- singleDual quantization Multi-bit quantization MultiBandpass modulators
4. Continuous-Time Modulators
Basic concepts and topologies
Synthesis methods
Introduction: Basic ADC process
Introduction: Basic ADC process
Sampling process
Limits the input signal frequency Speed of the ADC
Quantization process
Limits the input signal accuracy Resolution of the ADC
Introduction: Resolution vs. conversion rate

CMOS ADCs
ADCs Nyquist ADCs
Introduction: Quantization
Introduction: Quantization
Quantization input-output characteristic
Quantization error
White noise model - If x varies randomly from sample to sample - If the # of quantizer levels is high
[Enge99]
Introduction: Quantization - white noise model
Introduction: Sampling Oversampling
Classification of ADCs
Nyquist-rate ADCs (M~1) Oversampling ADCs (M>>1)
Fundamentals of ADCs: Oversampling

PSD of oversampled quantization noise
In-Band Noise power (IBN or PQ)
10
Fundamentals of ADCs: Performance Metrics
11
Fundamentals of ADCs: Performance Metrics
12
Fundamentals of ADCs: Quantization Noise Shaping

Processing of the quantization error
In-band noise power and effective resolution
13
Fundamentals of ADCs: Basic ADC architecture
14
Fundamentals of ADCs: Nyquist-rate vs. ADCs

Nyquist ADC
Sigma-Delta SigmaADC
HIGH-SELECTIVITY ANALOG FILTER HIGHfor anti-aliasing antiOverall resolution obtained using HIGH-ACCURACY ANALOG BLOCKS HIGH-
LOW-SELECTIVITY ANALOG FILTER LOWfor anti-aliasing (1st/2nd order) antiHigh overall resolution obtained using LOW/MODERATE-ACCURACY ANALOG BLOCKS LOW/MODERATEHIGH-SELECTIVITY DIGITAL FILTER HIGHEASIER AND MORE ROBUST IN MODERN CMOS
15
Fundamentals of ADCs: Basic M architecture

H(z) with large gain within the signal band
L th-order M thM
1st-order M 1stM
16
Fundamentals of ADCs: Classification of Ms

Nature of the signals being handled: Low-pass vs. Band-pass
Low-Pass M
Band-Pass M
Dynamics of the loop filter: Discrete-Time vs. Continuous-Time
DT M
CT M
Number of bits of the embedded quantizer: single-bit vs. multi-bit Number of quantizers employed: single-loop, cascade, etc.. Type of primitives available in the fabrication technology
17
Fundamentals of ADCs: Basic control parameters

L B
H(z) with large gain within the signal band
L th-order M thM
Oversampling, OSR Speed of analog circuitry Order of the shaping, L Stability of the M M Resolution of the internal quantizer, B Linearity of the DAC
18
DT-Ms: 1st-order LP Modulator
Using a linear model for the quantizer
19
Ramp input & 1-bit quantizer
Sinewave input & 3-bit quantizer
20
10

Noise pattern
21
DT-Ms: 2nd-order LP Modulator

1st-order Modulator
2nd-order Modulator
22
11
DT-Ms: 2nd-order LP Modulator
Linear analysis
Output spectrum and noise pattern
23
DT-Ms: High-order Single-loop Modulators

2nd-order M 2ndM
Stable for inputs in if
[Candy85]
L th-order M thM
pure-differentiator FIR NTF pureProne to instability
High-order loops are only conditionally stable [OptE90]
IIR NTFs (1)
[Lee87]
(1)
Zeros at z = 1 Butterworth/Chebyshev poles Gain adjusted to satisfy
24
12

OPTIMIZED IIR NTFs
[Schr93]
5th-order NTF 5th(OSR = 64)
(2)
Complex zeros at |z | = 1 with optimal positions within the signal band Butterworth/Chebyshev poles
IIR NTFs (1) (2)
[Lee87]
(1)
Zeros at z = 1 Butterworth/Chebyshev poles Gain adjusted to satisfy
25

(1)
Distributed feedback and distributed feedforward input
Complexity (many feedback/feedforward coeffs) Large spread of coeffs (area, power)
(2)
Feedforward summation + local resonators
(2)
26
13
DT-Ms: High-order Cascade Modulators

Error Cancellation Logic (ECL)
HIGH-ORDER STABLE OPERATION is ensured HIGHby cascading low-order stages (Li = 1, 2). Relationships among ECL and M to be fulfilled for perfect cancellation (NOISE LEAKAGE). NOISE LEAKAGE
d > 1, interstage
coupling
MASH Ms Ms
Each stage re-modulates a signal containing the quantization error in the previous one. Digital processing is used to cancel out all quantization errors, but that in the last stage.
Systematic loss of resolution, but: Smaller than for single loops Independent of OSR Small spread of analog coeffs ECL can be easily implemented Performance close to ideal Suited at low oversampling
27
DT-Ms: High-order Cascade Modulators
2-2 M [Kare90] M 4th-order 2-stage cascade 4th2-
Noise leakage precludes the cascading of a large number of stages to be practical
1-1-1 M M 2-1 M M 2-2-1 M M 2-1-1-1 M M 2-2-2 M M
[Mats87] [Longo88] [Vleu01] [Rio00] [Dedic94]
2-1-1 M M
[Yin94] 4th-order 3-stage cascade 4th3-
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14
DT-Ms: Multi-bit Modulators
Increased dynamic range B can trade for OSR (wideband) Better stability properties
More aggressive high-order NTFs
DAC non-linearities are directly nonadded to the input

The linearity of the M will be no better than that
FULL-PARALLEL ADC/DAC FULL(Typically B < 6)
DAC linearity limited by component mismatch
POSSIBLE APPROACHES Correcting DAC errors

Element Trimming Analog Calibration Digital Correction
Decorrelating DAC errors from the input

DEM techniques
Introducing DAC errors at a non-critical position nonDual quantization
29
DT-Ms: Multi-bit Modulators

ELEMENT SELECTION LOGIC
Increased dynamic range B can trade for OSR (wideband) Better stability properties
More aggressive high-order NTFs
DAC non-linearities are directly nonadded to the input

The linearity of the M will be no better than that
FULL-PARALLEL ADC/DAC FULL(Typically B < 6)
DAC linearity limited by component mismatch
Dynamic Element Matching (DEM)

Elements selected to make DAC errors independent of the input signal Algorithms that try to average the error in each DAC level to zero (to push DAC errors to high freq.) Randomization: Distortion transforms into white noise Rotation: Distortion moves out of band (CLA) Mismatch-shaping: 1st/2nd order (ILA, DWA, DDS)
30
15
DT-Ms: Dual-quantization Modulators

Dual Quantization
Combines 1-bit and multi-bit quantizers (linearity/reduced error) Concept applied to single-loop Ms [Hair91] singleMs Improved stability Noise leakage Leslie-Singh Lesliearchitecture
[Lesl90]
L-0 cascade M Suffers from noise leakage Multi-bit quantization does not improve stability
Concept applied to cascade Ms [Bran91] Ms Multi-bit quantization usually applied only in the last stage DAC errors shaped by L-LN Relaxes DAC requirements Noise leakage (inherent to cascades) 31
DT-Ms: Bandpass Modulators IF Digitization
32
16
DT-Ms: Bandpass Modulators
33
34
17
DT-Ms: Bandpass Ms Signal band location
35
DT-Ms: LP-to-BP Transformation Method
36
18
37
38
19

Other BP-M architectures
39
DT-Ms: Bandpass ADCs - Decimation

Bandpass decimation
Efficient decimation
40
20
CT-Ms: Basic Concepts Discrete-Time Ms

DT loop filter All internal signals are DT Sampling at the input
Continuous-Time Ms
CT front (loop filter) part DT back (quantizer) part Sampling inside the loop
41
CT-Ms: Basic Concepts
AA Filter
Pros of CT-Ms
Implicit anti-aliasing filter Less impact of sampling errors No input switches potentially better for low-voltage supply No settling error at the loop filter circuitry Potentially larger operation speed with less power consumption No sampling of the noise at the input capacitors Reduced digital noise coupling Very involved dynamic due to the combination of non-linearity, CT and DT larger impact of circuit non-linearities Time constant tuning is needed for correct loop filtering Large sensitive to time uncertainty (jitter)
Counters of CT-Ms
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21
CT-Ms: Basic Concepts

Linear analysis of CT-Ms, assuming [Bree01]:
Linear model for the quantizer DAC gain is unity in the signal bandwidth
Example: Lth-order, B-bit single-loop architecture
43
CT-Ms: Synthesis Methods

DT-to-CT synthesis method: pulse invariant transformation (freq. domain)
Find an equivalent DT M that fulfils the required specifications Based on a DT-to-CT equivalence [Cher00]
Open-loop configuration
44
22

Application of DT-to-CT method to cascade CT Ms
Every state variable and DAC output must be connected to the integrator input of the ulterior stages in the cascade [Ortm01] Increases the number of analog components (transconductors and amplifiers)
DT-to-CT
45

Direct synthesis method [Bree01]
Uses the desired NTF as a starting point, (as for the DT case) An Inverse Chevychev distribution of the NTF zeros has advantages in terms of SNR and stability
Application to cascade architectures [Tort06]

Optimum placement of poles/zeroes of the NTF Synthesis of both analog and digital part of the cascade CT Modulator Reduced number number of analog components
DT-to-CT Method
Direct Method
46
23

Direct synthesis of cascade architectures (I) [Tort06]
Sensitivity to mismatch (gm,C) A 2-1-1 example

18
14
SNR Loss (dB)
16
12 10
14
12
10
8 2.5 2
4 2.5
gm(%)
1.5 1 1
0.8
0.6
0.4
0.2
c(%)
gm(%)
1.5 1 1 0.8
0.6
0.4
0.2
c(%)
DT-to-CT synthesis method
Direct synthesis method
47

Direct synthesis of cascade architectures (II) [Tort06]
48
24

A case study: A 12-bit@20MHz, 4-b, 2-1-1 CT M for VDSL [Tort06]
49
General References
[Bree01] [Cherr00] [Enge99] [Geer02] [Mede99] [Nors97] [Pelu99] [Rabi99] [Rio06] [Rodr03] [Rosa02] [Shoa95] L. Breems and J.H. Huijsing, Continuous-Time Sigma-Delta Modulation for A/D Conversion in Radio Receivers. Kluwer Academic Publishers, 2001. J.A. Cherry and W.M. Snelgrove, Continuous-Time Delta-Sigma Modulators for High-Speed A/D Conversion. Kluwer Academic Publishers, 2000. J.V. Engelen and R. van de Plassche, BandPass Sigma-Delta Modulators: Stability Analysis, Performance and Design Aspects. Kluwer Academic Publishers, 1999. Y. Geerts, M. Steyaert and W. Sansen: Design of Multi-bit Delta-Sigma A/D Converters. Kluwer, 2002. F. Medeiro, B. Prez-Verd, and A. Rodrguez-Vzquez, Top-Down Design of High-Performance SigmaDelta Modulators. Kluwer Academic Publishers, 1999. S.R. Norsworthy, R. Schreier, and G.C. Temes (Editors), Delta-Sigma Data Converters: Theory, Design and Simulation. IEEE Press, New York 1997. V. Peluso, M. Steyaert, and W. Sansen, Design of Low-Voltage Low-Power CMOS Delta-Sigma A/D Converters. Kluwer Academic Publishers, 1999. S. Rabii and B.A. Wooley, The Design of Low-Voltage, Low-Power Sigma-Delta Modulators. Kluwer Academic Publishers, 1999. R. del Ro, F. Medeiro, B. Prez-Verd, J.M. de la Rosa and A. Rodrguez-Vzquez, CMOS Cascade SigmaDelta Modulators for Sensors and Telecom: Error Analysis and Practical Design. Springer, 2006. A. Rodrguez-Vzquez, F. Medeiro and E. Janssens, CMOS Telecom Data Converters. Kluwer Academic Publishers, 2003. J.M. de la Rosa, B. Prez-Verd, and A. Rodrguez-Vzquez, Systematic Design of CMOS Switched-Current Bandpass Sigma-Delta Modulators for Digital Communication Chips. Kluwer Academic Publishers, 2002. O. Shoaei, Continuous-Time Delta-Sigma A/D Converters for High Speed Applications. Ph.D. Dissertation, Carleton University, 1995.
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Advanced Architectures and State of the Art

Roco del Ro, Beln Prez-Verd and Jos M. de la Rosa Roc R Bel P rez- Verd Jos
OUTLINE
1. State of the Art on SC ADCs
2. State of the Art on CT ADCs
DT-LP-Ms: State of the Art

Low-Pass Single-loop Single-bit M ICs
Author [Kert94] [Kash99] [Wang03] [Yama94] [Brig04] [Brig02] [Snoe01] [Mede97] [Coba99] [Bran91b] [Grilo96] [Maul00] [Romb03] [Bose88] [Yao04] [Dess01] [Klem06] [Send97] [Burm96] [Burg01] [Nade94] [Goes06] [OptE91] [Than97] [Chen03] [Till01] [Saue03] [Bajd02] [Kesk02] [Pelu98] [Shim05] [Saue02] [Pelu97] [Au97] [Kesk02] [Saue03] [Chen03] [Shim05] [Burg01] [Gero03] [Wismar06] [Chen03] DR (bit) 21.00 20.00 18.50 18.00 17.20 17.10 16.70 16.40 16.00 16.00 15.30 15.30 15.30 14.50 14.40 14.40 14.37 14.30 14.20 14.00 13.80 13.50 13.50 13.40 13.10 13.00 13.00 13.00 13.00 12.50 12.37 12.20 12.00 12.00 12.00 11.00 9.90 8.87 8.70 8.50 8.35 8.10 DOR (S/s) 8.00E+02 8.00E+02 4.80E+04 2.00E+01 8.00E+02 8.00E+02 2.20E+04 9.60E+03 4.00E+04 5.00E+04 7.00E+03 5.00E+05 5.00E+05 1.60E+04 4.00E+04 5.00E+04 2.70E+05 6.00E+03 1.95E+04 4.00E+04 2.00E+03 2.00E+04 5.00E+05 1.95E+05 2.00E+05 1.60E+04 1.60E+04 2.20E+04 4.00E+04 3.20E+04 4.00E+05 1.60E+04 6.80E+03 1.60E+04 1.00E+05 3.20E+04 1.00E+06 1.00E+07 7.68E+06 5.00E+02 4.00E+04 2.00E+06 OSR Architecture 320 4th-ord 320 4th-ord --6th-ord 1600 4th-ord 320 4th-ord 320 4th-ord 64 4th-ord 256 2nd-ord 64 4th-ord 256 2nd-ord 286 2nd-ord 64 5th-ord 96 5th-ord 256 2nd-ord 100 3rd-ord 100 3rd-ord 48 4th-ord 128 2nd-ord 256 2nd-ord 192 3rd-ord (IF-to-BB) 250 3rd-ord 256 2nd-or 64 4th-ord (DFB) 128 2nd-ord 520 2nd-ord 64 2nd-ord 64 2nd-ord (SO) 64 4th-ord 256 2nd-ord (RO) 48 3rd-ord 16 3rd-ord 64 2nd-ord (SO) 74 2nd-ord 64 3rd-ord 102.4 2nd-ord (RO) 32 2nd-ord (SO) 104 2nd-ord 8 3rd-ord 24 3rd-ord (IF-to-BB) 16 3rd-ord (SWO, LR) 85 1st-order 52 2nd-ord Process Power (W) 3um MS / 10V 2.50E-02 0.6um MS / 5V 1.60E-02 0.35um MS / 5V-3.3V 2.30E-01 1.2um MS / 5V 1.30E-03 0.6um MS (2P) / 5V 5.00E-02 0.6um MS / 5V 5.00E-02 0.5um MS / 2.5V 2.50E-03 0.7um STD / 5V 1.71E-03 0.5um STD / 1.5V 1.00E-03 1um MS / 5V 1.38E-02 0.6um STD / 1.8V 2.00E-03 0.6um STD / 5V 2.10E-01 0.8um STD / 3.3V 4.30E-02 3um MS / 5V 1.20E-02 0.18um STD / 1V 1.30E-04 0.35um MS (2P) / 1V 9.50E-04 0.25um / 2.7V 2.84E-03 0.5um MS / 1.5V 5.50E-04 2um MS / 5V 1.30E-02 0.25um STD / 2.5V 1.15E-02 2um MS / 5V 9.40E-04 0.18um MS (MiM) / 0.9V 2.00E-04 1.5um MS (2P) / 5V 1.60E-01 1.2um MS / 5V 2.59E-02 0.13um STD / 1.5V 1.28E-03 0.25um STD / 1.8V 1.00E-03 0.18um MS (MiM) / 0.65V 4.55E-05 0.5um MS / 1.8V 1.70E-03 0.35um MS (2P) / 1V 5.60E-03 0.5um STD / 0.9V 4.00E-05 0.18um / 1.8V 4.00E-03 0.18um STD / 0.7V 8.00E-05 0.7um STD / 1.5V 1.01E-04 1.2um MS / 2V 3.40E-04 0.35um MS (2P) / 1V 5.60E-03 0.18um MS (MiM) / 0.65V 4.55E-05 0.13um STD / 1.5V 1.28E-03 0.18um / 1.8V 4.00E-03 0.25um STD / 2.5V 1.35E-02 0.8um MS (2P) / 1.8V 2.20E-06 90nm STD / 0.2V 4.40E-07 0.13um STD / 1.5V 1.28E-03 FOM1 14.90 19.07 12.93 247.96 415.11 444.90 1.07 2.06 0.38 4.21 7.08 10.41 2.13 32.37 0.15 0.88 0.50 4.54 35.37 17.55 32.95 0.86 27.62 12.27 0.73 7.63 0.35 9.43 17.09 0.22 1.89 1.06 3.63 5.19 13.67 0.69 1.33 0.85 4.23 12.15 0.03 2.32 FOM2x10 351.28 137.22 71.59 2.64 0.91 0.79 248.96 104.79 428.81 38.84 14.22 9.67 47.24 1.79 358.94 61.40 106.39 11.08 1.33 2.33 1.08 33.50 1.05 2.20 30.18 2.68 58.90 2.17 1.20 67.00 6.99 11.05 2.82 1.97 0.75 7.36 1.79 1.37 0.25 0.07 24.01 0.29
5
2nd-order loop ~ 40% 3rd-order loop ~ 20% 4th-order loop ~ 30%

Low-Pass Single-loop Multi-bit M ICs
Author [Bair96] [Chen95] [Geer00] [Geer00] [Hair94] [Leun97] [Nys97] [Pras04] [Yang03] [Lei06] [Fogl00] [Fogl01] [Grilo02] [Mille03] [Mille03] [Mille03] [Mille03] [Joha03] [Kuo02] [Kuo02] [Reut02] Balm04 [Gagg03] [Jiang02] [Kwon06] [Lee06] [Fuji06] [Fuji06] [Gagg04] [Gagg04] [Gomez02] [Gomez02] [Yu05] [Yu05] [Yu05b] [Gomez02] [Koh05] DR (bit) 13.66 15.65 15.80 12.00 16.00 19.30 19.00 18.04 18.70 15.99 16.22 16.70 13.00 15.32 13.50 12.83 11.67 16.00 13.70 13.00 14.00 13.70 13.80 13.80 14.00 13.90 12.75 11.83 14.37 13.37 12.83 8.01 9.37 10.70 12.50 12.00 10.70 DOR (S/s) 5.00E+05 4.00E+04 2.50E+06 1.25E+07 3.90E+04 9.60E+04 8.00E+02 4.00E+04 4.00E+04 4.80E+04 4.80E+04 4.00E+04 1.00E+06 3.60E+04 4.00E+05 1.25E+06 3.84E+06 9.00E+01 1.25E+06 2.00E+06 2.50E+06 2.50E+07 6.00E+05 4.00E+06 4.40E+06 2.20E+06 6.40E+06 8.00E+06 3.00E+05 1.10E+06 4.00E+05 4.00E+06 4.00E+06 2.00E+06 4.00E+05 4.00E+05 3.88E+06 OSR 16 64 24 24 128 64 512 153.6 128 128 64 64 32 639 57.5 18 12 512 12 12 32 8 96 8 32.7 60 12.5 12.5 350 47 65 12 10 20 50 65 19.79 Architecture 4th-ord(4b) 2nd-ord(3b) 3rd-ord(4b) 3rd-ord(4b) 3rd-ord(1b, 5b) (dual) 7th-ord(1.5b) 2nd-ord(3b) 5th-ord (17level) 5th-ord(17level) 3rd-order(10level) 2nd-ord(5b) 2nd-ord(5b) 2nd-ord(4b) 2nd-ord(6b) 2nd-ord(6b) 2nd-ord(6b) 2nd-ord(6b) 1st-ord (3b) 4th-ord(4b) 4th-ord(4b) 5th-ord(1.5b) 4th-ord(4b) 2nd-ord (3b) 5th-ord(4b) 2nd-ord (4b) 2nd-ord (5level) 4th-ord(4b) 2S 4th-ord(4b) 2S 2nd-ord (3b) 2nd-ord (3b) 2nd-ord(5b) 2nd-ord(5b) 2nd-ord(4b-dual) 2nd-ord(4b-dual) 2nd-ord(4b-dual) 2nd-ord(5b) 2nd-ord(5level) Process Power (W) 1.2um MS / 5V 5.80E-02 1.2um MS / 5V 6.75E-02 0.65um MS / 5V 2.95E-01 0.65um MS / 5V 3.80E-01 2um MS (2P) / 5V 8.50E-02 0.8um MS / 5V 7.60E-01 2um MS / 5V 2.18E-03 0.35um MS / 5V 3.00E-01 0.35um MS (2P) / 5V-3.3V 6.80E-02 0.25um / 5V 1.25E-02 0.5um STD / 3.3V 6.86E-02 0.5um STD / 3.3V 7.04E-02 0.35um BiCMOS / 2.7V 1.19E-02 0.18um MS / 2.7V 3.00E-02 0.18um MS / 2.7V 3.00E-02 0.18um MS / 2.7V 3.00E-02 0.18um MS / 2.7V 5.00E-02 0.35um MS / 2.6V 6.00E-05 0.25um STD / 2.5V 1.00E-01 0.25um STD / 2.5V 1.05E-01 0.25um STD / 2.5V 2.40E-02 0.18um MS / 1.8V 2.00E-01 0.18um MS / 1.8V 1.50E-02 0.18um STD / 1.8V 1.49E-01 0.18um STD / 1.8V 1.38E-02 0.18um STD / 1.8V 5.40E-03 0.18um MS / 1.8V 2.38E-02 0.18um MS / 1.8V 3.44E-02 0.13um MS / 1.5V 8.00E-03 0.13um MS / 1.5V 7.00E-03 0.13um STD / 1.5V 2.40E-03 0.13um STD / 1.5V 2.90E-03 90nm STD / 1.3V 2.10E-03 90nm STD / 1.3V 2.10E-03 90nm STD / 1.3V 2.10E-03 0.13um STD / 1.2V 1.40E-03 90nm STD / 1.2V 1.20E-03 FOM1 8.96 32.82 2.07 7.42 33.26 12.26 5.19 27.83 3.99 4.01 18.72 16.53 1.45 20.37 6.47 3.30 4.00 10.17 6.01 6.41 0.59 0.60 1.75 2.61 0.19 0.16 0.54 1.18 1.26 0.60 0.82 2.81 0.79 0.63 0.91 0.85 0.19 FOM2x10 3.61 3.91 68.85 1.38 4.92 131.36 252.36 24.17 266.27 40.41 10.18 16.07 14.10 5.01 4.47 5.51 2.04 16.08 5.53 3.19 69.79 55.26 20.31 13.63 213.63 237.63 31.85 7.69 41.96 43.96 22.07 0.23 2.08 6.58 15.95 11.96 22.33
5
Loop order:
2nd-order ~ 50%
+ 2nd-order loop ~ 50%
(easier to stabilize w/ multi-bit)
Multi-bit resolution:
3 or 4 bits ~ 70%

Low-Pass Cascade Single-bit M ICs
Author [Yoon98] [Fuji97] [Marq98a] [Miao98] [Rebe90] [Rito94] [Wang01] [Will94] [Yin93] [Yin94] [Davi03] [Geer99] [Mori00] [Gome00] [Lee03] [Lee03] [Olia02] [Rabi97] [Saue03] [Saue03] [Ahn05b] DR (bit) 15.30 18.15 14.80 14.82 15.00 16.15 18.10 17.00 15.70 15.82 13.00 15.00 14.00 16.65 14.16 12.00 13.50 16.10 13.00 12.17 12.70 DOR (S/s) 6.40E+04 4.80E+04 2.00E+06 5.00E+04 1.80E+05 4.40E+04 2.50E+04 5.00E+04 3.20E+05 1.50E+06 1.00E+03 2.20E+06 2.20E+06 4.40E+04 1.00E+06 2.00E+06 3.60E+05 5.00E+04 1.60E+04 3.20E+04 4.80E+04 OSR 16 128 24 64 64 64 64 128 64 64 256 24 24 128 64 32 36 80 64 32 64 Architecture 2-1-1-2 2-2 2-1-1 2-2 1-1-1 2-2 2-2 2-1 2-1 2-1-1 2-1 2-1-1 2-2-2 2-1 2-2 2-2 2.2 2-1 2-1 2-1 2-2 (switched-RC int.) Process 2um MS / 6.6V 0.7um MS / 5V 1um MS / 5V 3um MS / 5V 1.5um MS / 5V 1.2um BiCMOS / 5V 0.6um MS / 5V 1um MS / 5V 1.2um STD / 5V 2um BiCMOS / 5V 1.5um MS / 5V 0.5um MS / 3.3V 0.35um MS / 3.3V 0.6um MS / 3V 0.35um MS (2P) / 1.8V-2.4V 0.35um MS (2P) / 1.8V 0.4um MS / 1.8V 0.8um MS / 1.8V 0.18um MS (MiM) / 0.65V 0.18um MS (MiM) / 0.65V 0.35um MS / 0.6V Power (W) 7.90E-02 5.00E-01 2.30E-01 7.40E-02 7.60E-02 1.02E-01 7.50E-02 4.70E-02 6.50E-02 1.80E-01 --2.00E-01 1.50E-01 2.20E-02 1.50E-01 1.50E-01 5.00E-03 2.50E-03 6.18E-05 6.18E-05 1.00E-03 FOM1 30.60 35.91 4.03 51.03 12.89 31.82 10.68 7.17 3.82 2.07 --2.77 4.16 4.86 8.20 18.31 1.20 0.71 0.47 0.42 3.13 FOM2x10 3.29 20.17 17.66 1.42 6.35 5.72 65.68 45.62 34.82 69.61 --29.48 9.83 52.88 5.57 0.56 24.12 246.29 43.37 27.45 5.30
5
Most-common cascades: 2-1 2-2 2-1-1 3rd order, 2 stage 4th order, 2 stage 4th order, 3 stage

Low-Pass Cascade Multi-bit M ICs
Author [Broo97] [Bran91a] [Mede99] [Fuji00] [Dedi94] [Mori00] [Gupta02] [Feld98] [Rio01b] [Rio01b] [Bosi05] [Lamp01] [Rio02b] [Rio02b] [Vleu01] [Rio03] [Rio03] [Para06] [Taba03] [Dezz03] [Dezz03] [Reve03] [Ahn05] [Brew05] DR (bit) 14.50 12.00 13.00 15.00 14.25 13.00 14.60 13.00 13.00 12.00 12.20 13.00 13.70 13.00 15.00 13.80 12.70 10.8 8.50 13.40 10.40 13.33 13.40 16.40 DOR (S/s) 2.50E+06 2.10E+06 2.20E+06 2.50E+06 2.00E+05 2.20E+06 2.20E+06 1.40E+06 2.20E+06 4.00E+06 2.00E+07 1.56E+06 2.20E+06 4.40E+06 4.00E+06 2.20E+06 4.40E+06 4.00E+07 8.00E+07 2.00E+05 3.84E+06 2.00E+04 4.00E+04 2.00E+06 OSR Architecture 8 2-0(5b) 24 2-1(3b) 16 2-1-1(3b) 8 2(4b)-1(4b)-1(4b) 16 2(1.5b)-2(1.5b)-2(1.5b) 24 2-2(5b) 29 2-1-1(2b) 16 2-2-2(1.5b) 16 2-1-1(4b) 16 2-1-1(4b) 4 2(4b)-pipeline(9b) 32 2-2(3b) 32 2-1-1(3b) 16 2-1-1(3b) 16 2(5b)-2(3b)-1(3b) 32 2-1-1(3b) 16 2-1-1(3b) 8 2-2 (4b) 4 2(LP1.5b)-2(BP4b) 195 2-1 (5-level) 100 2-1 (5-level) 64 2-1(1.5b) (2S) 64 2-2(1.5b) 8 2-2-0(dual) Process 0.6um MS / 5V 1um STD / 5V 0.7um STD / 5V 0.5um MS / 5V 1.2um MS / 5V 0.35um MS / 3.3V 0.35um STD / 3.3V 0.7um MS / 3.3V 0.35um STD /3.3V 0.35um STD / 3.3V 0.18um MS/ 3.3V-1.8V 0.35um MS / 2.5V 0.25um STD / 2.5V 0.25um STD / 2.5V 0.5um MS / 2.5V 0.25um MS (MiM) / 2.5V 0.25um MS (MiM) / 2.5V 90nm STD / 1.4V 0.13um MS / 1.2V 0.13um MS / 1.2V 0.13um MS / 1.2V 0.35um MS (2P, low-Vt) / 0.8V 0.35um MS / 0.6V 0.25um MS (2P) / ?V Power (W) 5.50E-01 4.10E-02 5.50E-02 1.05E-01 4.00E-02 9.90E-02 1.80E-01 8.10E-02 7.37E-02 7.83E-02 2.40E-01 5.00E-02 7.17E-02 7.17E-02 1.50E-01 6.58E-02 6.58E-02 7.80E-02 1.75E-01 2.40E-03 4.30E-03 6.00E-05 1.00E-03 4.75E-01 FOM1 9.49 4.77 3.05 1.28 10.26 5.49 3.29 7.06 4.09 4.78 2.55 3.91 2.45 1.99 1.14 2.10 2.25 1.09 6.04 1.11 0.83 0.29 2.31 2.75 FOM2x10 6.09 2.14 6.70 63.81 4.74 3.72 18.81 2.90 5.00 2.14 4.60 5.23 13.56 10.28 71.47 16.98 7.39 4.07 0.15 24.30 4.07 88.09 11.67 78.59
5
Multi-bit quantization is mostly used in the last modulator stage

DT LPSDMs organized per architecture
22.0 21.0 20.0 19.0 18.0 17.0 16.0 15.0 14.0 13.0 12.0 11.0 10.0 9.0 8.0 7.0 1.0E+01 1.0E+02 1.0E+03 1.0E+04 1.0E+05
CDMA UMTS
PRECISION MEASUREMENT VOICE
AUDIO BROADBAND WIRELINE COM

GSM EDGE ADSL
DR (bit)
VDSL
WIRELESS COMMUNICATIONS
1.0E+06 1.0E+07
WLAN
1.0E+08
DOR (Hz)
Single-loop Single-bit Single-loop Multi-bit Cascade Single-bit Cascade Multi-bit

[Good96] FOM 1 = DR (bit ) DT LPSDMs organized per 10 architecture
12
Power(W) 2 DOR(S/s)
The lower, the better
1.0E+03
1.0E+02
FOM1
1.0E+01
1.0E+00
1.0E-01
1.0E-02 1.0E+01
1.0E+02
1.0E+03
1.0E+04
1.0E+05
1.0E+06
1.0E+07
1.0E+08
DOR (Hz)

3 22 DR (bit ) DOR (S/s) [Rabi97] FOLPSDMs organized per architecture M 2 = 2kT DT Power(W)
1.0E+03
The larger, the better
1.0E+02
FOM2 x 1E+05
1.0E+01
1.0E+00
1.0E-01
1.0E-02 1.0E+01
1.0E+02
1.0E+03
1.0E+04
1.0E+05
1.0E+06
1.0E+07
1.0E+08
DOR (Hz)

DT LPSDMs organized per supply
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 1.0E+01
>5V 5V 3V-3.3V 2.4V-2.7V 1.2V-2.0V <=1.0V
DR (bit)
1.0E+02
1.0E+03
1.0E+04
1.0E+05
1.0E+06
1.0E+07
1.0E+08
DOR (S/s)
DT-LP-Ms: State of the Art / Precision Apps

Digitization of seismic signals [Kash99]
Fourth-order feedforward summation architecture Dynamic biasing of 1st amplifier for power saving 0.6m CMOS tech (2P) 122-dB DR within 400Hz bandwidth 256kHz sampling rate (OSR=320) 16mW, 5V
Slew Settle Hold
Resonation around the two last integs Chopper at the front-end in order to reduce 1/f noise
Front-end integ
DT-LP-Ms: State of the Art / Voice codecs

Voice-band conversion [Send97]
Second-order loop
Double-sampling 2x effective OSR Modified NTF Bootstrapped switches
0.5m CMOS tech (2P2M) 88dB DR within 3kHz bandwidth 1MHz clock rate (2MHz effective sampling) 0.55mW, 1.5V
DT-LP-Ms: State of the Art / Audio codecs

Audio conversion [Rabi97]
2-1 cascade topology Resolution limited by kT/C noise Rail-to-rail operation Two-stage class A/AB amplifiers Bootstrapping of switches 0.8m CMOS tech (1P3M) 99dB DR within 25kHz bandwidth 4MHz sampling rate (OSR=80) 2.5mW, 1.8V
Thermal noise Quantization noise

First modulator stage:
Low input commonmode voltage (400mV) CMOS switches only required for sampling large swing signals CMOS switches
Class A/AB amplifiers:

1/f noise relies on pMOS input sizing
nMOS switches
Regenerative comparator

Audio conversion [Coba99]
Fourth-order single-loop mixed topology
Feedforward and feedback paths Resonation around two last integs () Input cap based on kT/C noise Remaining caps based on matching
Capacitor sizing:
Bootstrapping of switches 0.5m CMOS tech (1P3M) 98.2dB DR within 20kHz bandwidth 2.82MHz sampling rate (OSR=64) 1mW, 1.5V
Power dissipation issues: 1st-integ gain is fixed to 1/3 Clock duty-cycle is not 50%: More time for integration (larger Ceq) 1st-integ consumes 72% of power Aggressive cap scaling in rest of integs
1st integrator
2nd to 4th integrators
Two-stage Miller amplifier pMOS input pair with non-minimal

lengths to reduce 1/f noise Large DC gain
Folded-cascode amps 55-dB DC gain
DT-LP-Ms: State of the Art / Mobile com

Wireless communications, GSM/BT/WCDMA [Chen03]
Passive 2nd-order modulator w/o amplifiers
Capacitive voltage dividers reduce the input range Loading effects between passive stages
Functionality critically relies in the comparator
H1*H2 is limited to unity at DC (passive) Eq suppressed within baseband by comparator gain Noise from comparator adds to the input signal Switching power dominates (104MHz clock) 30% from comparator DC biasing
80.5/61.5/50.3dB DR within 0.1/1/2MHz BW 1.3mW, 1.5V, 0.13m CMOS tech
3 amplifying stages + regen. latch
DT-LP-Ms: State of the Art / Mobile com

Wireless communications, GSM/GPRS/EDGE [Klem06]
Fourth-order distributed feedback topology Single-stage amplifiers:
Inverse Chebyshev approximation NTF w/ two optimized zeros (b1)
Telescopic OTAs w/ dynamic biasing Constant slew-rate for power saving under process variations
Capacitor scaling 8:2:1:1 (20pF integrating cap at input) 0.25m CMOS tech 88dB DR within 270kHz bandwidth 26MHz sampling rate (OSR=48) 2.8mW, 2.7V
Telescopic OTA
DT-LP-Ms: State of the Art / Broadband com

Broadband communications, ADSL [Vleu01]
2-2-1 cascade topology w/ multi-bit quantization
Limited by kT/C noise Multi-bit quantization in all stages to reduce noise leakage Linearization of 1st-stage DAC partitioned DWA (DEM) Double-sampling [Send97] OSR=2x8
150mW, 2.5V, 0.5m CMOS tech (2P3M) 32MHz clock rate (64MHz effective sampling) 95dB DR within 2MHz bandwidth
2nd-order(5b) DAC w/ DEM
2nd-order(3b) DAC w/o DEM
1st-order(3b) DAC w/o DEM

1st integrator
Front-end amplifier w/ gain boosting (120dB DC gain, 40mW)
Double-sampling
DEM
Chip -photo:
Multi-bit quantization in the 1st modulator stage saves power but penalizes area 10mm2 w/o pads
10

Broadband communications, ADSL [Lee06]
2nd-order topology w/ multi-bit quantization 2 channels w/ time interleaving, but only 2 opamps Reduced complexity Linearization of 5-level feedback to 1st integ ILA (DEM) 0.18m CMOS tech (MiM caps) 66MHz clock rate (132MHz effective sampling, OSR=60) 85dB DR within 1.1MHz bandwidth 5.4mW, 1.8V 1.1mm2
TI approach w/ reduced path complexity
Conventional approach
DEM
DT-LP-Ms: State of the Art / Wireless com

Wireless communications, WLAN [Para06]
2-2 cascade topology with 4-bit internal quantizers
Linearization of all multi-bit DACs
rotational DWA (DEM)
Two-stage amplifiers pMOS telescopic + nMOS common-source stage 90nm CMOS tech (1P7M) metal-metal caps 330MHz sampling rate OSR=8 67dB DR within 20MHz bandwidth 78mW, 1.4V
Metal-metal comb caps:

Thick oxide M3 to M6 arrangement Area + lateral + fringing 75fF/m2, 3.5% parasitic
11
DT-LP-Ms: State of the Art / Wireless com

Wireless communications, WLAN [Taba03]
Fourth-order multi-bit cascade topology
1st stage: 2nd-order LP (1.5b) 2nd stage: 2nd-order BP (4b) local resonation () and DAC w/o DEM
0.13m 1.2V CMOS tech (1P6M) 0.25m 2.5V I/O MOST, MiM caps Folded-cascode amplifiers with 0.13m input pMOS for fast settling 160MHz sampling rate OSR=4! 53dB DR within 40MHz bandwidth 175mW power consumption
DT-BP-Ms: State of the Art

Band-Pass M ICs
Based on z-1 -> -z-2 transformation
Author [Corm97] [Long93] [Rosa00] [Baza98] [Park99] [Song95] [Andr96] [Haira96] [Baza99] [Salo02] [Salo02] [Salo03] [Salo03] [Taba99] [Ueno02] [Cheu01] [Cheu02] [Kuo04] [Kuo04] [Kuo04] [Kuo04] DR (bit) 9.5 15 11.5 6.7 12.2 9 8 11.7 9.4 11.7 6.7 13.3 11.7 13 12.6 6.7 6.8 10 12.04 12.7 13.37 fs (Hz) 1.25E+06 7.20E+06 6.52E+06 4.00E+07 2.00E+07 8.00E+06 8.00E+06 1.30E+07 6.80E+07 8.00E+07 8.00E+07 8.00E+07 8.00E+07 8.00E+07 1.00E+07 4.28E+07 4.28E+07 7.13E+00 7.13E+00 7.13E+00 7.13E+00 fn (Hz) 2.50E+05 1.80E+06 1.63E+06 2.00E+07 5.00E+06 2.00E+06 2.00E+06 3.25E+06 1.70E+07 2.00E+07 2.00E+07 2.00E+07 2.00E+07 2.00E+07 5.66E+05 1.07E+07 1.07E+07 1.07E+07 1.07E+07 1.07E+07 1.07E+07 Bw (Hz) 6.25E+03 3.00E+04 1.00E+04 1.25E+06 2.00E+05 3.00E+04 6.40E+04 2.00E+05 1.25E+06 2.70E+05 3.84E+06 1.25E+06 1.76E+06 1.25E+06 2.50E+05 2.00E+05 2.00E+05 2.00E+05 1.00E+05 6.00E+04 6.00E+04 Architecture 4th-ord 4th-ord 4th-ord 2nd-ord 4th-ord 4th-ord 6th-ord 4-2 4-4 4th-ord 4th-ord 4-4 4-4 6th-ord 2-2(3b) 2nd-ord 2nd-ord 4th-ord 4th-ord 4th-ord 4th-ord Process 2um MS / 5V 1um MS / 5V 0.8um STD / 5V 0.5um MS / 5V 0.65um STD / 4V 2um MS / 3.3V 0.5um MS (2P) / 3.3V 0.8um MS (2P) / 3V 0.6um MS (2P) / 3V 0.35um / 3V 0.35um / 3V 0.35um / 3V 0.35um / 3V 0.25um MS / 2.5V 0.25um MS (2P) / 2.5V 0.35um STD / 1V 0.35um MS (2P) / 1V 0.25um MS / 1V 0.25um MS / 1V 0.25um MS / 1V 0.25um MS / -1 1V Power (W) ----6.00E-02 6.50E-02 1.80E-01 8.00E-04 8.00E-03 1.44E-02 4.80E-02 5.60E-02 5.60E-02 3.70E-02 3.70E-02 9.00E-02 7.70E-02 1.20E-02 1.20E-02 8.45E-03 8.45E-03 8.45E-03 -2 8.45E-03 FOM1 ----12.67 30.31 7.50 0.78 15.38 1.29 4.03 0.84 24.57 0.18 0.53 0.53 17.95 10.69 9.97 0.76 0.19 0.12 0.07 FOM2x10 ----5.71 0.09 15.66 16.48 0.42 64.27 4.18 99.34 0.11 1415.26 155.92 383.86 8.63 0.24 0.28 33.45 563.12 1403.30 3552.46
6
6
Synthesis method: z
-z (~50%)
--388.96 18.94 --2.62 0.76 1.11 6.71 29.37 1.58 0.11 0.17
Other BPSDM ICs

Author [Chua98] [Jant93] [Jant97] [Liu97] [Cusi01] [Ong97] [Toni99] [Chen05] [Andr98] [Taba00] [Maur05] [Ying04] DR (bit) 13 10.2 10.8 11.8 12 12.2 12.7 9.7 9.2 12 13.2 14.4 fs (Hz) 5.00E+05 1.83E+06 1.00E+07 8.27E+05 3.71E+07 8.00E+07 4.28E+07 1.28E+07 4.00E+06 6.40E+07 1.31E+07 6.00E+07 fn (Hz) 1.25E+05 4.55E+05 3.75E+06 4.13E+05 1.07E+07 2.00E+07 1.07E+07 3.25E+06 1.00E+06 1.60E+07 1.00E+07 4.00E+07 Bw (Hz) 5.00E+02 8.00E+03 2.00E+05 2.00E+03 2.00E+05 2.00E+05 2.00E+05 2.00E+05 2.00E+05 2.00E+06 2.00E+05 2.50E+06
Architecture 6th Opt NTF 4th Opt NTF 4th Quadrature 4th Opt NTF 6th Opt NTF 4th-ord 6th Opt NTF 3rd Quadrature 3rd(3b) Opt NTF 6th 2-path 2-0 Quadrature 4th Quadrature
fs/4 (~80%) Passband location: fn = Power (W) FOM1 Process

2um MS (2P) / 5V 3um MS (2P) / 5V 0.8um STD / 5V 2um MS (2P) / 5V 0.35um STD / 3.3V 0.6um STD / 3.3V 0.35um STD / 3.3V 0.35um STD / 3.3V 0.5um MS (2P) / 3V 0.25um STD / 2.5V 0.25um STD / 2.1V 0.18um STD / 1.8V --2.10E-01 1.30E-01 --1.16E-01 7.20E-02 8.00E-02 1.87E-02 1.90E-02 1.10E-01 1.00E-02 1.50E-01
FOM2x10 --0.08 2.35 --38.99 154.26 149.19 3.09 0.50 64.72 2232.33 3208.05
12

DT BPSDMs
16.0 15.0 14.0 13.0
FM GSM PCS
DR (bit)
12.0 11.0 10.0 9.0 8.0 7.0 6.0 1.0E+02
AM IS-54
UMTS IS-95 Bluetooth
1.0E+03
1.0E+04
1.0E+05
1.0E+06
1.0E+07
Bandwidth (Hz)
z-1 --> -z-2 transformation Other implementations

FOM 1 =
1.0E+03
DR ( bit )
Power(W) 1012 DT BPSDMs ( f n + BW / 2 ) (Hz)
The lower, the better Similar to the LP case, but considering fn
1.0E+02
FOM1
1.0E+01
1.0E+00
1.0E-01
1.0E-02 1.0E+02
1.0E+03
1.0E+04
1.0E+05
1.0E+06
1.0E+07
Bandwidth (Hz)
13

FOM 2 = 2kT
1.0E+04
3 22 DR (bit ) ( f n + BW / 2 ) (Hz) DT BPSDMs Power(W)
The larger, the better Similar to the LP case, but considering fn
1.0E+03
FOM2 x 1E+06
1.0E+02
1.0E+01
1.0E+00
1.0E-01
1.0E-02 1.0E+02
1.0E+03
1.0E+04
1.0E+05
1.0E+06
1.0E+07
Bandwidth (Hz)

DT BPSDMs organized per supply
16 15 14 13 DR (bit) 12 11 10 9 8 7 6 1.0E+02
5V 3V-4V 1.8V-2.5V 1.0V
1.0E+03
1.0E+04
1.0E+05
1.0E+06
1.0E+07
Bandwidth (Hz)
14
DT-BP-Ms: State of the Art / Wireless com

Digital IF receivers, IS-95/DECT [Salo03]
Eighth-order bandpass cascade topology
4-4 cascade BP M Equivalent to 2-2 LP M z-1 -z-2 transformation fn = fs/4 = 80MHz/4 = 20MHz Double-delay (DD) resonators using only one amplifier Based on single-amplifier 4th-order BP M
Only two amplifiers required Folded-cascode topology 82/72dB DR within 1.25/1.762MHz bandwidth 0.35m CMOS tech 37mW, 3.0V

4-4 cascade BP M
w/ only two amplifiers
Double-delay resonator
Single-amplifier 4th-order BP stage
18 clock signals required
15

Digital IF receivers, FM [Cusi01]
Sixth-order single-loop bandpass M
Limited by kT/C and amplifier noise 74dB DR within 200kHz bandwidth 0.35m CMOS tech 76mW, 3.3V
10.7MHz 200kHz
Distributed feedback and distributed feedforward topology Optimized NTF and STF NTF w/ spread zeros, STF w/ interferer filtering fn = fs/4 = 42.8MHz/4 = 10.7MHz
NTF STF
CT-Ms: State of the Art

Low-Pass Single-bit
Author [Badj02] [Bree00] [Gerf02] [Gerf03] [Lin99] [Luh00] [Luh98a] [Luh98b] [Putt04] [Veld02] [Zwan96] [Zwan99] [Ortm03] [Sami03] [Phil03] [Phil04] [Blan02] [Dagh04] [Das05] [Muo05] [Naga05] [Naga05] [Pun07] DR (bit) DOR (S/s) 10,00 2,20E+04 13,3 2,00E+05 11,3 5,00E+04 11,8 5,00E+04 10,5 5,00E+06 10 6,20E+06 8 2,00E+06 9,6 2,00E+06 12,5 2,00E+06 11,3 4,00E+06 13 8,00E+03 10,4 1,00E+06 10 5,00E+04 9,4 1,00E+05 12,3 1,00E+06 14,5 2,00E+06 11,30 1,60E+04 12,40 2,46E+06 14,00 1,20E+06 14,60 2,00E+06 11,37 8,56E+05 10,37 2,60E+06 12,00 5,00E+04 OSR 64 65 48 48 16 64 25 25 140 38,4 64 10 48 32 64 32 62,5 813 213 32 150 50 64 Architecture 4th-ord 4th-ord 3rd-ord 3rd-ord 2nd-ord 5th-ord 2nd-ord 2nd-ord 2nd-ord 4th-ord 4th-ord 2nd-ord 3rd-ord 3rd-ord 5th-ord 4th-ord 4th-ord 2nd-ord 4th-ord 4th-ord 4th-ord 4th-ord 3rd-ord Process Power (W) 0.5um CMOS 1.8V 1,70E-03 0.35um CMOS 2.5V 1,80E-03 0.5um CMOS 1.5V 2,50E-04 0.5um CMOS 1.5V 1,35E-04 1.2um CMOS 3V 1,20E-02 0.6um CMOS 3.3V 1,60E-02 2um CMOS 5V 1,50E-02 2um CMOS 5V 1,66E-02 0.18um CMOS / 1.8V 6,00E-03 0.18um CMOS 1.8V 6,60E-03 0.5um CMOS 2.2V 2,00E-04 0.5um CMOS 5V 7,20E-03 0.5um CMOS 1.5V 7,50E-04 0.5um CMOS 1.5V 7,50E-05 0.18um CMOS 4,40E-03 0.18um ST 1.8V 2,00E-03 0.35um STD/2.5V 7,50E-05 0.18um CMOS / 1.8V 1,80E-02 90nm CMOS /1.3V 5,40E-03 0.18um CMOS / 1.8V 4,70E-03 0.11um CMOS / 1.2V 3,42E-03 0.11um CMOS / 1.2V 3,42E-03 0.18um CMOS / 0.5V 3,70E-04
16

Low-Pass Multi-bit
DR (bit) 10 11 11 14 14,4 13 14 12 12,5 16,7 15,9 8,9 8,70 13 10,87 10,87 Author [Dorr03] [Gian03] [Pato04] [Yan03] [Yan04] [Moya03] [Schi04] [Dorr05] [Font05] [Morr05] [Nguy05] [Cald05] [Aria06] [Mitt06] Bree04 Bree04 DOR (S/s) 4,00E+06 3,00E+07 3,00E+07 2,00E+06 2,00E+06 2,40E+07 2,40E+05 4,00E+06 1,20E+06 4,00E+04 9,60E+04 4,00E+07 4,00E+07 4,00E+07 2,00E+07 4,00E+07 OSR Architecture 26 3rd-ord (3b) - DEM 10 4th-ord (4b) 10 4th-ord (4b) - DEM 16 3rd-ord (5b) 16 3rd-ord (5b) - Calib. 10 3rd-ord (6b) - Calib. 54 4th-ord (3b) - ?? 26 3rd-ord (4b) - Tracking quant 42 3rd-ord (2b) 128 2nd-ord(4b) - DEM 128 4th-ord (4b) - DEM 5 3rd-orde (4b) - time-interleav 16 2nd-order (3b) - Complex 16 3rd-order (4b) 8 2-2 (4b) 8 2-2 (4b) I/Q Process Power (W) 0.13um CMOS 1.2V 3,00E-03 0.13um CMOS 1.5V 7,50E-02 0.13um CMOS 1.5V 7,00E-02 0.5um CMOS MS / 6,20E-02 0.5um CMOS MS / 6,20E-02 0.5um CMOS MS/2.5V 7,50E-02 0.13um CMOS /1.25V 3,00E-03 0.13um CMOS /1.5V 3,00E-03 90nm CMOS / 1.5V 6,00E-03 0.18um CMOS /3.3V 3,73E-02 0.35um (2P) /3.3V 1,80E-02 0.18um CMOS /1.8V 1,03E-01 0.25um CMOS /2.5V 3,20E-02 0.13um CMOS / 1.2V 2,00E-02 0.18um ST/1.8V 1,22E-01 0.18um ST/1.8V 2,16E-01
Band-Pass
Author [Copp02] [Enge99] [Hsu00] [Tao99] [Zwan00] [Veld03b] [Veld03b] [Veld03b] [Schr06] DR (bit) 10 10,8 6,7 7,2 13,3 15 13,5 12 14,7 fs (Hz) fn (Hz) Bw (Hz) DOR(Hz) Architecture Process Power (W) 1,28E+08 4,00E+06 2,00E+06 4,00E+06 2nd-ord (Complex) 0.25um CMOS 2V 1,42E-02 4,00E+07 1,07E+07 2,00E+05 4,00E+05 6th-ord 0.5um CMOS 5V 6,00E-02 2,80E+08 7,00E+07 2,00E+05 4,00E+05 2nd-ord 0.5um CMOS 2.5V 3,90E-02 4,00E+08 1,00E+08 2,00E+05 4,00E+05 4th-ord 0.35um CMOS 3.3V 1,65E-01 2,11E+07 1,07E+07 2,00E+05 4,00E+05 5th-ord 0.25um CMOS 2.5V 1,10E-02 2,60E+07 1,00E+05 2,00E+04 4,00E+04 5th-ord (Quadrat) 0.18um CMOS ST/ 2.9V 9,10E-03 7,88E+07 1,23E+06 2,46E+06 5th-ord (Quadrat) 0.18um CMOS ST/ 2.9V 1,31E-02 1,54E+08 3,84E+06 7,68E+06 5th-ord (Quadrat) 0.18um CMOS ST/ 2.9V 1,41E-02 2,64E+08 4,40E+07 8,50E+06 1,70E+07 4th-ord (Quadrat) 0.18um CMOS ST/ 2.9V 3,75E-01

A Large number of different topologies and applications
Broadband (15-20MHz) telecom Wireless telecom
18 16
IF-to-BaseBand Quadrature Bandpass Multi-mode / multi-standard
D R (b its)
14 Low voltage / low power Hybrid architectures 12 10 8 6 1,E+03
Continuous-time / Discrete-time Active-passive implementations

Single-loop, Single-bit Single-loop, Multi-bit Cascade Bandpass
1,E+04
1,E+05
1,E+06
1,E+07
1,E+08
DOR (Hz)
17
CT-Ms: State of the Art / Broadband

Gm-C 5th-order single-loop [Luh00]
Fifth-order feedforward loop filter
Butterworth approximation Gm-C implementation Cross-coupled asymmetric differential pairs Tunable transconductance gain (controlled by Vc)
0.6m CMOS technology 62-dB DR within 3.1MHz bandwidth 400MHz sampling rate 16mW, 3.3V

Gm-C 2nd-order single-loop for CDMA [Dagh04]
Second-order loop filter Off-chip inductor
Choke for the mixer Resonator in the M
0.18m CMOS technology 79-dB SNR, 1.23-MHz band. 2-GHz sampling freq. 18mW, 1.8-V
Additional latches to reduce metastability
18

RC-active 4th-order (4-b) single-loop (I) [Pato04]
4th-order loop filter, 4-bit internal quantizer (+DEM) Direct synthesis method to optimize NTF
NTF-zero optimized to achieve the largest bandwidth Robustness (stability) against process variations
DAC2 used to compensate the excess loop delay 0.13m CMOS technology 67-dB DR within 15-MHz bandwidth 300-MHz sampling rate 70mW, 1.5V

RC-active 3rd-order (4-b) single-loop [Mitt06]
3rd-order 4-bit Active-RC integrators Trimming of time-constants 0.13-m CMOS 12-bit ENOB within 20-MHz band 640-MHz sampling rate 20mW, 1.2V
19

Complex architecture for WLAN (IEEE 802.11 a/b/g) [Aria06]
First Complex (2x2nd-order) 3-bit NTF poles for ZIF and LIF modes Gm-C integrators 0.25m CMOS standard technology (MOS caps) 8.7-bit ENOB within 20-MHz bandwidth 320-MHz sampling rate 32mW, 2.5V

Time-Interleaved architecture [Cald06]
Time-interleaved (2x3rd-order M) 0.18-m CMOS 8.7-bit ENOB within 20-MHz 200-MHz sampling rate 103mW, 1.8V
Equivalence for integrator reduction
20

Cascade architecture [Bree04] 2-2 cascade topology Each stage with 4-bit quantizer DT-to-CT synthesis method 0.18m CMOS technology 67-dB DR, 10-MHz bandwidth Quadrature configuration, 20-MHz 120mA, 1.8-V supply Digital calibration of NCF
CT-Ms: State of the Art / Wireless telecom

IF-to-BaseBand, GSM [Bree00]
Fifth-order feedforward loop filter Quadrature configuration Integrated mixer+active-RC front-end integrator 0.35m CMOS technology 82-dB DR within, 100-kHz band, IF=50MHz (GSM) 13-MHz sampling rate 1.8mW, 2.5V
Mixer+ Front-end integrator
21

Quadrature architecture (I) [Veld02]
Quadrature 4th-order, 1.5-bit topology Double loop to minimize internal signal swings 0.18m CMOS technology 70-dB DR within 2-MHz bandwidth (per channel) 153.6MHz sampling rate 11.5mW, 1.8V

Programmable-gain, Merged filtering architecture [Phil04]
Fourth-order loop filter Programmable gain functionality
1st integrator 2nd-4th integrator
Switchable input resistors (1,10,100k)
Compensating high-pass filtering Telescopic cascode opamps 0.18m CMOS technology 89-dB DR, 1-MHz bandwidth 46-59 dB SNR-peak 64MHz sampling rate 2mW, 1.8V
22

BP modulator + input mixer [Copp02] 1-bit, quadrature bandpass modulator
Second-order complex BP filter Input mixing stage

Downconversion of RF signals (0.3-1.6GHz) 0.25m CMOS technology 62-dB DR, 2-MHz bandwidth, 4MHz IF 128-MHz sampling rate 14mW, 2-V

MultiMode/MultiStandard applications [Veld03] 1-bit, complex fifth-order loop filter
SC DAC to reduce sensitivity to clock jitter NMOS in NWELL (switchable) capacitors Active RC 1st stage (regulated-cascode opamp) Gm-C integrators for the remaining stages
0.18m CMOS technology GSM/CDMA2000/UMTS modes
92/83/72-dB DR, 200/1228/3840-kHz 26/76.8/153.6-MHz sampling rate 3.8/4.1/4.5mW, 1.8-V
23
CT-Ms: State of the Art / Low-power, low-voltage

Low-power Modulator [Gerf03]
Third-order loop filter
RC-active implementation Folded-cascode opamps (40W)
CMFB
0.5m CMOS technology 80-dB DR within 25-kHz bandwidth 2.4MHz sampling rate 135W, 1.5V
CT-Ms: State of the Art / Low-power, low-voltage

Low-power/Low-Voltage (0.5V) [Pun07]
Third-order loop filter
RC-active integrators Body-input OTAs and comparators
Return-to-Open DAC 0.18m CMOS technology 74-dB DR within 25-kHz bandwidth 300W, 0.5V
24
CT-Ms: State of the Art / Hybrid architectures

Active-passive implementations (I) [Das05]
4th-order loop filter Two (folded-cascode) amplifiers plus passive components
N-well resistors PMOS capacitors
Double loop to minimize internal signal swings 90nm CMOS technology 86-dB SNR-peak within 600-kHz bandwidth 256MHz sampling rate 5.4mW, 1.3V
1-bit SC DACs

Active-passive implementations (II) [Naga05]
4th-order loop filter Passive current-summing network in the feedforward path
Phase compensation Reduce power consumption
0.11m, dual-Vt CMOS technology Variable gain implemented by varying the DAC output power 57-dB DR within 1.3-MHz bandwidth 132-MHz sampling rate 3.42mW, 1.2V
25

Hybrid lowpass (CT-DT) architectures [Morr05][Nguy05]
CT front-end integrator
Potentially faster with less power

consuption
Anti-aliasing filtering Avoids the use of bootstrapping

Problems
Sensitivity to clock jitter Chopper stabilization techniques with CT

filters
[Morr05]
0.18m CMOS technology 102-dB DR, 20-kHz signal bandwidth 11.3mA, 3.3-V
Hybrid tuning circuit required
[Nguy05]
0.35m CMOS technology 106-dB DR, 192-kHz 36mW

Hybrid BP (CT-DT) architecture [Tao99b]
Fourth-order loop filter
IF=100MHz CT front-end resonator In-loop mixer+DT integrator

50-dB DR, 200-kHz band 0.35m CMOS technology 330mW, 2.7/3.3V
26
DT-Ms: References
[Chen03] [Coba99] [Cusi01] F. Chen, S. Ramaswamy, and B. Bakkaloglu, A 1.5V 1mA 80dB Passive ADC in 0.13m Digital CMOS Process. Proc. of the IEEE International Solid-State Circuits Conference (ISSCC), 2003. A.L. Coban and P.E. Allen, A 1.5V 1.0mW Audio Delta Sigma Modulator with 98dB Dynamic Range. Proc. of the IEEE International Solid-State Circuits Conference (ISSCC), pp. 50-51, 1999. P. Cusinato, D. Tonietto, F. Stefani, and A. Baschirotto, A 3.3-V CMOS 10.7-MHz Sixth-Order Bandpass Modulator with 74-dB Dynamic Range. IEEE Journal of Solid-State Circuits, vol. 36, pp. 629-638, April 2001. F. Goodenough, Analog Techniques of all Varieties Dominate ISSCC. Electronic Design, vol. 44, pp. 96-111, February 1996. D.B. Kasha, W.L. Lee, and A. Thomsen, A 16-mW, 120-dB Linear Switched-Capacitor DeltaSigma Modulator with Dynamic Biasing. IEEE Journal of Solid-State Circuits, vol. 34, pp. 921-926, December 1999. N. Klemmer and E. Hegazi, A DLL-Biased, 14-Bit Analog-to-Digital Converter for GSM/GPRS/EDGE Handsets. IEEE Journal of Solid-State Circuits, vol. 41, pp. 330-338, February 2006. K.-S. Lee, S. Kwon, and F. Maloberti, A 5.4mW 2-Channel Time-Interleaved Multi-bit Modulator with 80dB SNR and 85dB DR for ADSL. Proc. of the IEEE International Solid-State Circuits Conference (ISSCC), 2006. J. Paramesh, R. Bishop, K. Soumyanath, and D. Allstot, An 11-bit 330MHz 8X OSR Modulator for NextGeneration WLAN. Proc. of the Symposium on VLSI Circuits, pp. 166-167, 2006. S. Rabii and B.A. Wooley, A 1.8V Digital-Audio Sigma-Delta Modulator in 0.8m CMOS. IEEE Journal of Solid-State Circuits, vol. 32, pp. 783-796, June 1997. T.O. Salo, S.J. Lindfors, T.M. Hollman, J.A.M. Jrvinen, and K.A.I. Halonen, 80-MHz Bandpass Modulators for Multimode Digital IF Receivers. IEEE Journal of Solid-State Circuits, vol. 38, pp. 464-474, March 2003.
[Good96] [Kash99]
[Klem06] [Lee06]
[Para06] [Rabi97] [Salo03]
DT-Ms: References
[Send97] [Taba03] [Vleu01] D. Senderowicz, G. Nicollini, S. Pernici, A. Nagari, P. Confalonieri, and C. Dallavalle, Low-Voltage DoubleSampled Converters. IEEE Journal of Solid-State Circuits, vol. 32, pp. 1907-1919, December 1997. A. Tabatabaei, K. Onodera, M. Zargari, H. Samavati, and D.K. Su, A Dual Channel ADC with 40MHz Aggregate Signal Bandwidth. Proc. of the IEEE International Solid-State Circuits Conference (ISSCC), 2003. K. Vleugels, S. Rabii, and B. Wooley, A 2.5-V Sigma-Delta Modulator for Broadband Communications Applications. IEEE Journal of Solid-State Circuits, vol. 36, pp. 1887-1899, December 2001.
27
CT-Ms: References
[Aria06] J. Arias, P. Kiss, V. Prodanov, V. Boccuzzi, M. Banu, D. Bisbal, J. San Pablo, L. Quintanilla and J. Barbosa: A 32-mW 320-MHz Continuous-Time Complex Delta-Sigma ADC for Multi-Mode Wireless-LAN Receivers. IEEE J. of Solid-State Circuits, pp. 339-351, Feb. 2006 L.J. Breems, E.J. Van der Zwan and J. Huijsing, A 1.8-mW CMOS Modulator with Integrated Mixer for A/D Conversion of IF Signals. IEEE Journal of Solid-State Circuits, Vol. 35, pp. 468-475, April 2000. L. Breems and J.H. Huijsing, Continuous-Time Sigma-Delta Modulation for A/D Conversion in Radio Receivers. Kluwer Academic Publishers, 2001. L.J. Breems, R. Rutten and G. Wetzker, A Cascaded Continuous-Time Modulator with 67-dB Dynamic Range in 10-MHz Bandwidth. IEEE Journal of Solid-State Circuits, Vol. 39, pp. 2152-2160, December 2004. T. C. Caldwell and D. A. Johns: A Time-Interleaved Continuous-Time DS Modulator With 20-MHz Signal Bandwidth. IEEE Journal of Solid-State Circuits, Vol. 41, pp. 1578-1588, July 2006. J.A. Cherry and W.M. Snelgrove, Continuous-Time Delta-Sigma Modulators for High-Speed A/D Conversion. Kluwer Academic Publishers, 2000. P. Coppejans, P. Vancorenland, W. de Cock and M. Steyaert, Continuous-Time Quadrature Bandpass Modulator With Input Mixers. IEE Pro. Circuits and Devices Syst. , Vol. 149, pp. 331-336, Oct/Dec 2002. E.H. Dagher, P. A. Stubberud, W. K. Masenten, M. Conta and T. Victor Dinh, A 2-GHz Analog-to-Digital DeltaSigma Modulator for CDMA Receivers With 79-dB Signal-to-Noise Ratio in 1.23-MHz Bandwidth. IEEE Journal of Solid-State Circuits, Vol. 39, pp. 1819-1828, November 2004. A. Das, R. Hezar, R. Byrd, G. Gomez and Baher Haroun, A 4th-order 86-dB CT ADC with Two Amplifiers in 90nm CMOS. Proc. of the 2005 IEEE Int. Solid-State Circuits Conf., pp. 496-497, 2005. L. Drrer, F. Kuttner, A. Wiesbauer, A. Di Giandomenico and T. Hartig, A 10-Bit, 3-mW Continuous-Time Sigma-Delta ADC for UMTS in a 0.12m CMOS Process. Proc. of ESSCIRC03, Sept. 2003. L. Drrer, F. Kuttner, P. Greco and S. Derksen, A 3mW 74 SNR 2-MHz CT ADC with a Tracking-ADCQuantizer in 0.13m CMOS. Proc. of the 2005 IEEE Int. Solid-State Circuits Conf., pp. 492-493, 2005.
[Bree00] [Bree01] [Bree04]
[Cald06] [Cher00] [Copp02] [Dagh04]
[Das05] [Drr03] [Drr05]
CT-Ms: References
[Font05] [Gerf03] [Luh00] [Mitt06] P. Fontaine, A. N. Mohieldin and A. Bellaourar, A Low-Noise Low-Voltage CT DS Modulator with Digital Compensation of Excess Loop Delay. Proc. of the 2005 IEEE ISSCC., pp. 498-499, 2005. F. Gerfers, M. Ortmanns and Y. Manoli, A 1.5-V 12-bit Power-Efficient Continuous-Time Third-Order Modulator. IEEE Journal of Solid-State Circuits, Vol. 38, pp. 1343-1352, August 2003. L. Luh, J. Choma and J. Draper, A 400-MHz 5th-Order Continuous-Time Switched-Current Modulator. Proc. of the 2000 European Conf. on Solid-State Circuits, pp. 72-75, September 2000. G. Mitteregger, C. Ebner, S. Mechnig, T. Blon, C. Holuigue and E. Romani: A 20-mW 640-MHz CMOS Continuous-Time SD ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB. IEEE Journal of Solid-State Circuits, Vol. 41, pp. 2641-2649, December 2006. M. Moyal, M. Groepl, H. Werker, G. Mitteregger and J. Schambacher, A 700/900mW/Channel CMOS Dual Analog Front-End IC for VDSL with Integrated 11.5/14.5dBm Line Drivers. Proc. Of ISSCC03, Feb. 2003. P. Morrow, M. Chamarro, C. Lyden, P. Ventura, A. Abo, A. Matamura, M. Keane, R. OBrien, P. Minogue, J. Mansson, N. McGuinness, M. McGranaghan and I. Ryan, A 0.18m 102dB-SNR Mixed CT SC Audio-Band ADC. Proc. of the 2005 IEEE Int. Solid-State Circuits Conf., pp. 178-179, 2005. T. Nagai, H. Satou, H. Yamazaki and Y. Watanabe, A 1.2 3.5mW Modulator with a Passive Current Summing Network and a Variable Gain Function. Proc. of the 2005 IEEE Int. Solid-State Circuits Conf., pp. 494-495, 2005. K. Nguyen, B. Adams, K. Sweetland, H. Chen and K. McLaughlin, A 106dB SNR Hybrid Oversampling ADC for Digital Audio. Proc. of the 2005 IEEE Int. Solid-State Circuits Conf., pp. 176-177, 2005. O. Olieai, State-Space Analysis of Clock Jitter in Continuous-Time Oversampling Data Converters. IEEE Transactions on Circuits and Systems I, Vol. 50, pp. 31-37, January 2003. O. Olieai, Design of Continuous-Time Sigma-Delta Modulators With Arbitrary Feedback Waveform. IEEE Transactions on Circuits and Systems II, Vol. 50, pp. 437-444, August 2003. M. Ortmanns, F. Gerfers, and Y. Manoli, On the synthesis of cascaded continuous-time Sigma-Delta modulators. Proc. of the 2001 IEEE Int. Symp. on Circuits and Systems, Vol. 5, pp. 419-422, May 2001.
[Moya03]
[Morr05]
[Naga05]
[Nguy05] [Olia03a] [Olia03b] [Ortm01]
28
CT-Ms: References
[Ortm04] M. Ortmanns, F. Gerfers and Y. Manoli, Compensation of Finite Gain-Bandwidth Induced Errors in Continuous-Time Sigma-Delta Modulators. IEEE Transactions on Circuits and Systems I, Vol. 51, pp. 10881099, June 2004. S. Patn, A. D. Giandomenico, L. Hernndez, A. Wiesbauer, T. Ptscher and M. Clara, A 70-mW 300-MHz CMOS Continuous-Time ADC With 15-MHz Bandwidth and 11 Bits of Resolution. IEEE Journal of Solid-State Circuits, Vol. 39, pp. 1056-1063, July 2004. K. Philips, P. A.C.M. Nuijten, R. L. J. Roovers, A. H.M. van Roermund, F. Muoz-Chavero, M. Tejero Pallars and A. Torralba, A Continuous-Time ADC With Increased Immunity to Interferers. IEEE Journal of SolidState Circuits, Vol. 39, pp. 1056-1063, July 2004. K. Pun, S. Chatterjee and P. R. Kinget: A 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator With a Return-to-Open DAC. IEEE Journal of Solid-State Circuits, Vol. 42, pp. 406-507, March 2007. J. Ruiz-Amaya, J.M. de la Rosa, F.V. Fernndez, F. Medeiro, R. del Ro, B. Prez-Verd and A. RodrguezVzquez, High-Level Synthesis of Switched-Capacitor, Switched-Current and Continuous-Time Modulators Using SIMULINK-Based Time-Domain Behavioral Models. IEEE Trans. on Circuits and Systems-I, Vol. 52, pp. 1785-1810, September 2005. L. Samid and Y. Manoli, A Micro Power Continuous-Time Modulator. Proc. of ESSCIRC03, Sept. 2003. M. Schimper, L. Drrer, E. Riccio and G. Panov, A 3mW Continuous-Time -Modulator for EDGE/GSM With High Adjacent Channel Tolerance. Proc. of ESSCIRC04, Sept. 2004. H. Tao, L. Toth and M. Khoury, Analysis of Timing Jitter in Bandpass Sigma-Delta Modulators. IEEE Transactions on Circuits and Systems I, Vol. 46, pp. 991-1001, August 1999. H. Tao and J.M. Khoury, A 400MS/s Frequency Translating BandPass Delta-Sigma Modulator. IEEE Journal of Solid-State Circuits, Vol. 34, pp. 1741-1752, December 1999. R. Tortosa, J.M. de la Rosa, A. Rodrguez-Vzquez and F.V. Fernndez, Analysis of Clock Jitter Error in Multibit Continuous-Time Modulators with NRZ Feedback Waveform. Proc. of ISCAS, May 2005.
[Pato04]
[Phil04]
[Pun07]
[Ruiz05]
[Sami03] [Schi04] [Tao99a] [Tao99b] [Tort05a]
CT-Ms: References
[Tort06] R. Tortosa, J.M. de la Rosa, F.V. Fernndez and A. Rodrguez-Vzquez: A New High-Level Synthesis Methodology of Cascaded Continuous-Time Sigma-Delta modulators. IEEE Trans. On Circuits and Systems II: Express Briefs, pp. 739-743, August 2006. R.H.M. van Veldhoven, B.J. Minnis, H.A. Hegt and A.H.M. Roermund, A 3.3-mW Modulator for UMTS in 0.18-m CMOS With 70-dB Dynamic Range in 2-MHz Bandwidth. IEEE Journal of Solid-State Circuits, Vol. 37, pp. 1645-1652, December 2002. R.H.M. van Veldhoven, A Triple-Mode Continous-Time Modulator With Switched-Capacitor Feedback DAC for a GSM-EDGE/CDMA2000/UMTS Receiver. IEEE Journal of Solid-State Circuits, Vol. 37, pp. 2069-2076, December 2003. S. Yan and E. Snchez-Sinencio, A Continuous-Time Modulator With 88-dB Dynamic Range and 1.1MHz Signal Bandwidth. IEEE Journal of Solid-State Circuits, pp. 75-86, January 2004. E.J. van der Zwan and E.C. Dijkmans, A 0.2mW CMOS Modulator for Speech Coding with 80dB Dynamic Range. IEEE Journal of Solid-State Circuits, pp. 1873-1880, December 1996. E.J. van der Zwan, K. Philips and C. A. A. Bastiaansen, A 10.7-MHz IF-to-Baseband A/D Conversion System for AM/FM Radio Receivers. IEEE Journal of Solid-State Circuits, pp. 1810-1819, December 2000.
[Veld02]
[Veld03]
[Yan04] [Zwan96] [Zwan00]
29
Circuits and Errors

Roco del Ro, Beln Prez-Verd and Jos M. de la Rosa Roc R Bel P rez- Verd Jos

OUTLINE 1. Circuits and Errors in DT Modulators

Errors degrading NTF Additive noise sources Harmonic distortion Case study
2. Circuits and Errors in CT Modulators

CT M subcircuits M Building-block errors BuildingArchitectural timing errors Case study
3. Layout & Prototyping

Layout floorplanning Chip package
Test PCB and Set-up Set-
DT-Ms: Overview of Non-idealities

- Ideal In-Band Error Power:
PQ =
1 2L 12 2 B 1 (2L +1)OSR 2 L +1
- Actual In-Band Error Power:
PT = PQ + PQ + PTH + PJ + PHD + ...

Finite Amplifier Gain Non-linearities Thermal Noise Comparator hysteresis
Capacitor Mismatch
Settling Errors
Clock Jitter
DAC Non-linearity
among others

Depending on the building-block:
Fully-diff SC schematic of a 2nd-order M
Clock: - Jitter Amplifiers:

Output swing DC gain Dynamic limitations (GB, SR) Thermal and 1/f noise Gain non-linearity
Switches:
Finite on-resistance Thermal noise Charge injection Clock feedthrough Non-linearity
References:
- Thermal and 1/f noise - Output impedance
Multi-bit ADCs & DACs:

- Gain error - Offset error - Non-linearity
4
Capacitors:
- Mismatch - Non-linearity
Comparators:
- Hysteresis - Offset

Depending on their effect:
ERRORS DEGRADING NTF
AMPLIFIER DC GAIN CAPACITOR MISMATCH INTEGRATOR SETTLING Amplifier GB Amplifier SR Switch Ron
Impact depends on topology SINGLE-LOOP Ms Low sensitivity CASCADE Ms Noise leakages

Imperfect cancellation of low-order quantization errors
Output PSD 4th order 3rd order 2nd order 1st order
0.5/OSR
0.5
f/fs (log)
5

Depending on their effect:
ERRORS DEGRADING NTF
AMPLIFIER DC GAIN CAPACITOR MISMATCH INTEGRATOR SETTLING Amplifier GB Amplifier SR Switch Ron
MODELED AS ADDITIVE ERRORS

CIRCUIT NOISE Thermal noise (switches, opamps, refs) 1/f noise (opamps, refs) CLOCK JITTER DISTORTION Non-linear Non-linear Non-linear Non-linear amplifier gain capacitors settling switches
Impact depends on topology SINGLE-LOOP Ms Low sensitivity CASCADE Ms Noise leakages

Imperfect cancellation of low-order quantization errors
Front-end dominates Similar impact on different topologies
DT-Ms: Integrator Leakage

Effect of amplifier gain on the integrator transfer function:
Ideal SC integrator SC integrator considering amplifier finite gain
g=
C1 C2
Amplifier gain
Shift of the pole from DC (z = 1)


Effect on single-loop Ms:
- Ideally:
- In practice:
2nd-order M
Lth-order M:
Quite insensitive to leakages (2, L-1 shaping)


Effect on cascade Ms:
2-1-1 M
Mismatch between analog and digital filtering - Ideally: - In practice:
low-order leakages (L1-1, L2-1, )


Comparison of integrator leakage effect on 4th-order Ms
(ideal)
Sensitivity to integ leakages of cascades increases with OSR and L 1st-stage leakages dominate (L1-1 shaping)
10
DT-Ms: Capacitor Mismatch

Circuit primitive: Physical implementations:
MOS cap Digital CMOS Mixed CMOS
Analog CMOS
11

Local and global errors in: Area Capacitance per Unit Area
SC integrator
g=
C1 nCu = C2 mCu
g
g
1 1 Cu + n m Cu
C ~ 0.05% - 0.1% using good quality caps and adequate layout strategies
Centroid techniques
12

Effect on single-loop Ms:
- Ideally:
2nd-order M - In practice:
Slight increase of error, but shaping is preserved
13

2-1-1 M
Mismatch between analog and digital coeffs - Ideally: - In practice:
low-order leakages (L1, L2, )

14

C = 0.5%
C = 0.1%
2-1-1 M
(OSR = 32)
2-1-1 M
(OSR = 32)
15

Required C for 1-bit loss in DR
Sensitivity to mismatch rapidly increases with: - Oversampling ratio (OSR) - Cascade order (L) 1st-stage leakages dominate (L1 shaping)
16
DT-Ms: Integrator Incomplete Settling

If only amplifier gain is considered, the relation between vo and virtual ground is assumed to be independent on time In practice, this relation depends is non-linear on time
Settling error
ADC
GB, SR
Integrator temporal evolution

error due to amplifier finite bandwidth slew-rate limitation
Modulator output spectrum

increase on the noise floor harmonic distortion due to slewing
SNDR degradation
17

Integrator temporal evolution: [Rio00]
Both integration and sampling dynamics considered 1 pole model + SR limitation in amplifiers All parasitic caps taken into account
18

Linear response Partial slew Full slew

GBi
SRi
19

GBi
GBs
SRi
SRs
20
10

21

Effect of the amplifier GB:
If only amplifier GB is considered (assuming no SR limitation)
Can be viewed as a systematic error in the integrator weight Effect on Ms similar to a mismatch between analog and digital coeffs It causes low-order noise leakages in cascade Ms
22
11

Additional effect of the amplifier SR (+ GB):
Dominant linear dynamics are not mandatory in order to fulfill specs SR can trade for GB It can be used to optimize the power consumption of amplifiers
Non-linear dynamics cause distortion! SR at the front-end integ must be carefully tackled
23

Additional effect of the switches Ron (+ GB + SR):
= 1
Input is sampled with an error
Linear dynamics are slowed down
Slew time shortens

24
12
DT-Ms: Circuit Noise

Main noise sources in SC integrators:
Switches Amplifiers References Sampling: Thermal noise Thermal and flicker noise Thermal and flicker noise Integration:
Noise contribution of the switches (input-referred):

Switches for sampling
Aliased component [Fisc82]

CS = 0.66pF fs = 70MHz
25

Main noise sources in SC integrators:
Switches Amplifiers References Sampling: Thermal noise Thermal and flicker noise Thermal and flicker noise Integration:
Noise contribution of the switches (input-referred):

Switches for sampling Switches for integration
26
13

Noise contribution of the amplifier (input-referred):
Thermal + Flicker
Thermal component
corner freq.
Aliased component
Flicker component
Low-pass filtered version at the integ input:
Folded tails are submerged into the aliased thermal noise
Similar treatment for the references

27

Total noise PSD for the front-end integ:
switches
amplifier
references
Switches:
kT/C is the ultimate limitation on the converter resolution It can only be decreased by increasing Cs and/or fs (it does not depend on Ron!) x2 in fully-diff implementations (3-dB increase, but signal power is 6dB larger!)
Amplifiers & References:

GBs should be as low as settling errors allow (reduces folding!) 1/f contributions decrease with the corner frequency Adequate techniques can be applied in low-freq apps: CDS, chopper, [Enz96]
In-band error power due to circuit noise in the M

28
14

Effect of noise leakages and thermal noise on a 2-1 cascade
3rd-order shaping
2nd-order shaping w/ Thermal noise no shaping w/ Integ leakage Ideal
29

Effect of 1/f and thermal noise on the spectra of a 4th-order M (silicon results for several fs)
Thermal components
Flicker component (1/f) Be careful with Flicker models for transistors! Front-end amplifier needed redesign!
30
15
DT-Ms: Clock Jitter

Sampling time uncertainty [Boser88]:
Non-uniform sampling of the input
If jitter is modeled as random:
Ideal J = 0.1ns, fx = 125kHz J = 0.1ns, fx = 500kHz
Error is larger, the larger input freq (wideband apps!)

31
DT-Ms: Non-linearity of Capacitors

In an ideal capacitor: dq = Cdv In practice: dq = C(v)dv, with C being voltage-dependent
vi
Considering the effect of the sampling cap only [Bran97]:
a1 = 500ppm/V, a2 = 500ppm/V2
HD3 = -94.0dB HD3 = -89.9dB HD3 = -89.8dB
Even-order distortion cancels w/ fully-diff Non-linearity of sampling cap dominates Valid for weak non-linearities (MOS caps are very non-linear!)
32
16
DT-Ms: Non-linear Amplifier Gain

Actual amplifier gain depends on output voltage:
Amplifier gain, dB
ADC
Output voltage, V
ADC = 500, 1 = 10%/V (single-ended M)
[Yin94]
Increasing ADC helps a lot! ADC at the front-end larger than noise leakages require
33
DT-Ms: Non-linear Settling

SR can trade for GB in the integrator settling, but non-linear dynamics cause distortion:
SR at the front-end larger than settling requires

34
17
DT-Ms: Non-linear Switch Resistance

Switches exhibit a finite RON which is also non-linear:
RON, p RON,n
RON,n = 1 W k'n (VDD vI VTn ) L n 1 = W k' p (vI | VTp |) L p
RON, p
RON ,eq
0 | VTp |
VDD VTn
VDD
vI
RON,eq = RON,n // RON, p
Non-linear sampling [Geer02]:
Alternative switch sizings
Numerically solved
Distortion is dynamic (increases with input freq!) Front-end switch dominates RON at the front-end smaller than settling requires Very important in low-voltage!
Most suited sizing depends on parasitics, Vref/Vsupply,
35
DT-Ms: Comparators and Multi-bit Quantizers

Single-bit Ms:
Comparator:
Offset Attenuated by the integrator DC gain Hysteresis Shaped similarly to quantization error [Boser88]
1-bit DAC
Inherently linear
Ph = 4h 2
2L (2L +1)OSR 2 L +1
Multi-bit Ms:
Effect of DAC errors on a 2nd-order 3-bit M
Multi-bit ADC Multi-bit DAC
Errors attenuated/shaped Non-linearity directly added to the input!

2
[Mede99]:
1 2 = B INL2LSB D 2 2 1
DEM techniques Dual quantization

36
18
DT-Ms: Case Study

A case study: A 2.5-V Cascade M in CMOS 0.25um for ADSL/ADSL+
2-1-1 w/ dual quantization

Two different amplifiers: 2-stage OA in the 1st stage, and 1-stage OA in 2nd and 3rd stages. Standard CMOS switches (no clock-boosting). Only 2-branch integrators and 2x16 unit capacitors (MiM). Comparators: regenerative latch + preamplification stage. 3-bit quantizer in the last stage: Resistive-ladder DAC (no calibration). Flash ADC: Static differential input stage + latched comparators. Power-down control.
37
DT-Ms: Case Study

Blocks Specs
EQUATION DATABASE
Typical Quantization noise Ideal Corner analysis: -88.1dB Worst Case -86.2dB
FRONT-END INTEGRATOR MODULATOR
Topology Oversampling ratio Reference voltage Clock frequency Clock jitter Sampling capacitor Cap. sigma (MiM, 1pF) Cap. tolerance Bottom parasitic cap. Switch on-resistance DC gain
2-1-1(3b) 16 1.5V 70.4MHz 15ps (0.1%) 0.66pF 0.05% 20% 1% 150 3000 (70dB) 265MHz 800V/s 1.8V 6nV/sqrt(Hz) 20mV 10mV 3ns 0.5%FS
-90.3dB
Fast and slow devices models DC gain leakage -99.8dB Temperature Cap. mismatch leakage range: [-40C, +110C] -95.4dB -89.4dB 5% variation in the 2.5-V supply (C = 0.05% | 0.1%)
DAC error Thermal noise kT/C noise Amplifier noise Clock jitter In-band error power Dynamic range -96.4dB -84.8dB -88.1dB -87.5dB -82.2dB -86.0dB -84.5dB
GB (1.5pF)
AMPLIFIER
Slew rate (1.5pF) Output swing Input equivalent noise Hysteresis
-90.1dB -82.3dB 82.8dB (13.5bit) -80.3dB 80.8dB (13.1bit)

COMPARATORS
Offset Resolution time DAC INL
3-bit QUANTIZER
38
19
DT-Ms: Case Study

Topology Oversampling ratio
MODULATOR
2-1-1(3b) 16 1.5V 70.4MHz 15ps (0.1%) 0.66pF 0.05% 20% 1% 150 3000 (70dB) 265MHz 800V/s 1.8V 6nV/sqrt(Hz) 20mV 10mV 3ns 0.5%FS
Reference voltage Clock frequency Clock jitter Sampling capacitor Cap. sigma (MiM, 1pF) Cap. tolerance Bottom parasitic cap. Switch on-resistance DC gain
Typical Quantization noise Ideal DC gain leakage Cap. mismatch leakage (C = 0.05% | 0.1%) DAC error Thermal noise kT/C noise Amplifier noise Clock jitter In-band error power Dynamic range -88.1dB
Worst Case -86.2dB

FRONT-END INTEGRATOR
-90.3dB -99.8dB -95.4dB -89.4dB
-96.4dB -84.8dB -88.1dB -87.5dB -82.2dB -86.0dB -84.5dB

AMPLIFIER
GB (1.5pF)
Slew rate (1.5pF) Output swing Input equivalent noise Hysteresis
COMPARATORS
-90.1dB -82.3dB 82.8dB (13.5bit) -80.3dB 80.8dB (13.1bit)
Offset Resolution time DAC INL
3-bit QUANTIZER
39
DT-Ms: Case Study

Integrator Dynamics
GB > 2.5fs is ideally enough to limit settling errors (this architecture w/ OSR = 16).
Switch on-resistance slows down the effective amplifier response:
Ron ~ 150 requires just GB > 3.2fs
Standard switches GB = 265MHz (no clock-boosting) (assuming that 85% of the clock cycle is useful)
Slew rate must be large enough to let the linear dynamic to correctly settle.
6.5
SR = 800V/s
Partially slew-rate limited operation of the front-end integrator introduces distortion. 40
20
DT-Ms: Case Study

Amplifiers
INTEG. 1 1 INTEG. 2 INTEG. Unit capacitor DC gain 0.66pF 0.66pF 0.45pF 30003000 (70dB) (70dB) 265MHz 265MHz 800V/s 800V/s 1.80V 1.80V 6nV/sqrt(Hz) 6nV/sqrt(Hz) INTEG. 3 INTEG. 4 0.45pF 600 (56dB) 210MHz 350V/s 1.60V 50nV/sqrt(Hz)
SC CMFB nets pMOS input scheme

Cancelled body effect (substrate noise coupling) Smaller 1/f noise
GB (1.5pF)
Slew rate (1.5pF) Output swing Input equivalent noise
OPA
OPB
41
DT-Ms: Case Study

Amplifiers
INTEG. 1 Unit capacitor DC gain 0.66pF INTEG. 2 0.45pF INTEG. 3 INTEG. 4 0.45pF 600 (56dB) 210MHz 350V/s 1.60V 50nV/sqrt(Hz)

3000 (70dB) 265MHz 800V/s 1.80V 6nV/sqrt(Hz)
GB (1.5pF)
OPA
2-stage amplifier Telescopic 1st stage

2-path compensation
Typical Worst Case 73.5dB 331.5MHz 57.9 883V/s 1.86V 5.5nV/sqrt(Hz) 129fF 19.4mW
DC gain
78.6dB 446.8MHz 64.0 1059V/s 2.09V 5.1nV/sqrt(Hz) 126fF 17.2mW
GB (1.5pF) PM (1.5pF) SR (1.5pF)

Output swing Input eq. noise Input capacitance Power consumption
42
21
DT-Ms: Case Study

Amplifiers
INTEG. 1 Unit capacitor DC gain 0.66pF INTEG. 2 0.45pF INTEG. 3 INTEG. 4 0.45pF 600 (56dB) 210MHz 350V/s 1.60V 50nV/sqrt(Hz)

3000 (70dB) 265MHz 800V/s 1.80V 6nV/sqrt(Hz)
GB (1.5pF)
OPB
Typical DC gain 58.0dB 393.5MHz 70.3 377V/s 1.97V 4.1nV/sqrt(Hz) 300fF 6.6mW Worst Case 56.8dB 331.7MHz 67.7 373V/s 1.72V 5.1nV/sqrt(Hz) 343fF 6.9mW
folded-cascode amplifier folded-
GB (1.5pF) PM (1.5pF) SR (1.5pF)

Output swing Input eq. noise Input capacitance Power consumption
43
DT-Ms: Case Study

Switch on-resistance onSlow-down of the integrators dynamics Incomplete sampling (RC time constant) Dynamic distortion (front-end integrator)
Ron ~ 150
Standard CMOS switches
nMOS: 8.5/0.25 pMOS: 36.5/0.25
No clock-boosting No low-Vt transistors
44
22
DT-Ms: Case Study

Switch on-resistance onDynamic distortion evaluated through electrical simulation
0.85Vpd @ 366kHz
Sinewave input
DMT input
45
DT-Ms: Case Study

MiM capacitors
CMOS tech with mixed-signal facilities Thin oxide between metal 4 and metal 5 M3 TOP M5
thin oxide
M4 BOTTOM
Cap. matching Bottom plate parasitic Cap. spread
0.05% (1pF) 1% 20%
Very good matching (0.1% assumed for 6- design) Helps to limit the capacitive load to integrators
Integrators weights:
Front-end integ, 0.66pF: 27m x 27m Remaining integs, 0.45pF: 22m x 22m Also MiM caps in OPA, in the SC CMFB nets, and in the anti-aliasing filter anti-
46
23
DT-Ms: Case Study

Comparator
Pre-amp + Regenerative latch + SR latch Pre(Different supplies) Hysteresis Resolution time, LH Input capacitance 127.5V Offset 3.9ns 100fF Resolution time, HL 6.3mV 2.8ns
Power consumption 0.3mW
3-bit Quantizer
Resistive-ladder DAC Resistive700- ladder between references +2V/+0.5V (14x50, 3.21mW) Unsalicided n+ poly used in resistors References obtained from the on-chip analog supply
Flash ADC
Static input scheme (no caps)
Reduces capacitive load to 4th integrator Saves silicon area
Extra differential pair in comparators

47
DT-Ms: Case Study

Layout & Prototyping
2.78mm2 w/o pads
CMOS 0.25m
44-pin plastic QFP 44-
4-layer PCB
Dedicated analog, mixed, and digital supplies Guard rings with dedicated pad/pin Increased distance among analog and digital blocks Layout symmetry and common-centroid techniques
Shielded bus for distributing the clock signals Extensive on-chip decoupling Pad ring divided blocking cells Multiple bonding techniques
48
24
DT-Ms: Case Study

Experimental results
-6dBV @ 160kHz
THD = -87dB SFDR = 90dB
Part of a commercial modem In mass production (STMicroelectronics)

49
CT-Ms : Overview of CT-M Non-idealities
CT-M Non-Idealities
Building-block Errors
Opamp finite (non-linear) DC gain Integrator transient response Element tolerances Time-constant error Non-linearity (Front-end V-I and DAC) Noise
Architectural Timing Errors
Quantizer metastability Excess loop delay Clock jitter
50
25
CT-Ms: Basic building blocks

Basic building blocks CT Integrators
A Gm-MC implementation - 2nd-order single-loop M - 1-bit switched-current DAC - 1-bit (latch) comparator
51
CT-Ms: Non-ideal Integrator Transfer Function

Integrator Transfer Function (ITF) degraded by circuit non-idealities
52
26
CT-Ms: Effect of finite DC gain error

Opamp finite DC gain (I)
RC integrators [Gerf03]
- Same IBN degradation as in SC Ms
53
CT-Ms: Effect of finite DC gain error

Opamp finite DC gain (II) Gm-C integrators
Power Spectral Density of an Lth-order M
Relative increase of PQ in a 2nd-order M
54
27
CT-Ms: Integrator transient response

Integrator transient response (I)
Less critical than in DT Ms Need to be taken into account, specially in broadband applications
Influence of GBW [Gerf03]
3rd-order single-loop RC CT-M
Other dynamic effects

2nd-order poles Slew-rate
Complex analysis Simulation-based study [Ruiz03] 55
CT-Ms: Integrator transient response

Model of GBW for RC-active based CT-Ms [Ortm04]
Modeled as a gain error (GE) and extra loop delay Each delay is different for each feeback path
56
28
CT-Ms: Circuit element tolerances

Element tolerances
Scaling coefficients accuracy limited by random errors in resistors/capacitors
Especially critical in:
High-order single-loop architectures (instability) Cascade architectures (analog/digital coefficient ratios) Absolute tolerances: variations from chip to chip (10-20%) Relative mismatches: variations from device to device on one chip (0.5-1%)
System-level optimization and synthesis method
14
Two types of random errors:
Electrical control of frequency tuning
12
10 8
4 2.5 2
gm (%)
1.5 1 1 0.8
0.6
0.4
0.2
c (%)
57

Direct synthesis method of CT cascade architectures [Tort06]:
Optimum placement of poles/zeroes of the NTF Synthesis of both analog and digital part of the cascade CT Modulator Reduced number number of analog components Reduced sensitivity to element tolerances
DT-to-CT Method
Direct Method
58
29

Direct synthesis of cascade architectures (I) [Tort06]
Sensitivity to mismatch (gm,C) A 2-1-1 example

18
14
SNR Loss (dB)
16
12 10
14
12
10
8 2.5 2
4 2.5
gm(%)
1.5 1 1
0.8
0.6
0.4
0.2
c(%)
gm(%)
1.5 1 1 0.8
0.6
0.4
0.2
c(%)
DT-to-CT synthesis method
59

Direct synthesis of cascade architectures (II) [Tort06]
60
30

Synthesized cascaded CT Ms to cope with 12-bit@20-MHz
2-1-1-1 CTM 2-2-1 CTM
3-2 CTM
61

A case study: A 12-bit@20MHz, 4-b, 2-1-1 CT M (RC/Gm Integrators)
62
31
CT-Ms: Integrator time-constant error

Integrator time-constant error (I)
63
CT-Ms: Integrator time-constant error

Integrator time-constant error (II)
Optimum SNR for:
64
32
CT-Ms: Non-linear errors

Non-linearity (I): Causes
Intrinsic non-linearity of the resistor material Modulation of thickness of the conductive layer with resistor voltage
V-I transformation in RC integrators
V-I transformation in Gm-C integrators
65

Non-linearity (II): Effect on Gm-C CT-Ms [Bree01]
Linearization strategies
66
33

Non-linearity (III) Commonplace architecture
RC-active front-end integrator Gm-C subsequent integrators
Other sources of non-linearity

Multi-bit DACs Linearity must be the same or lower than the required resolution Corrected by same techniques as those employed in SC Ms
DEM Calibration
Circuit noise
Dominated by noise sources from the front-end integrator and DAC Flicker noise reduced by proper sizing and/or chopper techniques Unsampled noise effect of sampling reduced by the loop gain
67
CT-Ms: Comparator metastability

Comparator metastability
Signal-dependent Delay
Can be cancelled by using additiona latches [Dagh04]
Modeled as a jitter noise [Cher00]
68
34
CT-Ms: Excess loop delay

Excess loop delay (I)
DAC transient response delay
Adds additional poles to STF/NTF Causes instability Stability condition:
2nd-order Lth-order
69

Excess loop delay (II) an example of instability
70
35

Excess loop delay (III) cancellation techniques
Extra feedback paths (DACs) with tunable gains [Cher00] Additional DAC and two latches [Yan04]
Y(n) (without DAC_B and latches)
DAC_B output Edge trigered Y(n)
Level trigered
71

Excess loop delay (IV) - Digital compensation [Font05]
Implemented in a 3rd-order single loop architecture with 5-level quantizer
90nm CMOS 74-dB SNDR-peak, 600kHz bandwidth 6.0mW, 1.5V

Excess loop delay compensated in the digital domain Half-a-clock-cycle delay
Relax comparators speed Provide maximum isolation between quantizer and DAC switch events
72
36
CT-Ms: Clock jitter error

Clock jitter (I)
S/H
Shaped by the modulator NTF Can be neglected

DAC
Directly adds with the input Increases the in-band noise power
DT DAC waveform CT DAC waveform
CT Ms are more sensitive to clock jitter than DT Ms
White noise model approximation (NRZ DAC) [Cher00][Zwan96]

Standard deviation of jitter error: SNR degradation:
73

Clock Jitter (II) White noise model approximation (NRZ/RZ DAC) [Tao99a]
Lowpass CT-Ms
Bandpass CT-Ms
74
37

Clock Jitter (III) lingering effect [Olia03a]
Jitter-induced noise includes both white and shaped components State-space analysis of CT-Ms with RZ DAC shows that:
Multi-bit NRZ DACs

Commonly used in CT-Ms for brodband telecom applications Less sensitive to clock jitter RZ DAC NRZ DAC
75

Clock Jitter (IV) Multi-bit NRZ DACs [Tort05] [Ris94]
- Using state-space formulation of NTF:
76
38

Clock Jitter (V): Comparison of [Tort05] with previous approaches
Assuming that SNRjitter is dominated by the signal-dependent term: [Boser, JSSC, 1988]
If the modulator-dependent term dominates (single-bit quantization):
[Van der Zwan, JSSC, 1996]
77

Clock Jitter (VI) Multi-bit NRZ DACs [Tort05]
Two cases: - CTM1: B=2bit, fs=400MHz - CTM2: B=5bit, fs=160MHz
CTM1
CTM2
78
39

Clock Jitter (VII) Compensation techniques
Multi-bit quantization (non-linear DAC) Switched-capacitor DAC [Veld03]
Voltage-mode operation (proper for active RC integrators) Slower than switched-current (current steering) DAC
FIRDAC to generate a multilevel signal [Putt04]
79
CT-Ms: Case Study

A case study: A Gm-C 12-bit@20MHz, 4-b, 3-2 CT M
130nm mixed-signal CMOS, 1P8M Cascade 3-2 multi-bit (4b) CT M Gm-C loop-filter implementation Current-steering feedback DACs + DEM 12-bit effective resolution 40MS/s output rate (20MHz bandwidth) 240MHz clock frequency 1.2V 10% analog/digital power supply On-chip tuning of analog components Estimated power consumption is 45mW
Building-block specifications
Loop-filter coefficients
80
40
CT-Ms: Case Study

Transconductors
Resistive source degenerated front-end transconductor Loop-filter transconductors based on quadratic term cancellation
Transistor-level performance
81
CT-Ms: Case Study

Current-steering DACs
2 360-A P-type gain-boosted current sources 15 N-type regulated-cascode current cells
Worst-Case Transistor-level performance
82
41
CT-Ms: Case Study

Chip implementation
Front-End Transconductors
M-i-M Capacitors
DAC1s
Transimpedance s
Clock Latches & DEM
DAC2s
Loop-Filter Transconductors
Quantizers
83
CT-Ms: Case Study

Transistor-level simulation results
SNDR = 75.3 dB (12.2 bits) @ 20-MHz bandwidth
84
42
Circuits & Errors: Layout & Prototyping Low-resistive bulk

Most Standard CMOS technologies
Epitaxial process with heavily-doped bulk
The deep-substrate is a low-impedance path for injected disturbances. Traditional layout techniques (guard rings, separation of blocks) have a limited effectiveness.
Impact of the on-chip switching activity
85
Circuits & Errors: Layout & Prototyping Typical M layout example
Dedicated analog and digital supplies: - Analog core - Digital core - Digital output buffers Open pad ring Common-centroid layout techniques Guard rings Increased distance among analog and digital blocks
86
43
Circuits & Errors: Layout & Prototyping
87
Circuits & Errors: Layout & Prototyping Example: A M in 0.25m for ADSL/ADSL+
2.78mm2 w/o pads
4-layer PCB
CMOS 0.25m
44-pin plastic QFP 44-
The chip also includes other blocks pertaining to the final application
PLL (2x, 4x) Decimation filter ( 8, 16, 32)
Test Set-Up Set-
PLL + M + Filter
88
44
Circuits & Errors: Test PCB
89
Circuits & Errors: Test PCB
90
45
Circuits & Errors: Chip Package
Double-bonding and multiple pins for supplies Different pin assignment for analog, mixed and digital
91
Circuits & Errors: Test Set-up

Two-layer PCB TwoSoldered samples (in order to avoid socket parasitics) Anti-aliasing filter (passive, 1st order) Independent control of amplifier bias currents Decoupling Impedance termination Novel tech (characterization not
yet confirmed by silicon results)
Workstation
Cancellation logic 64k-sample FFT
Test Set-Up
bit streams Digital test unit
Low-distortion signal generator
input
bit streams
PCB
clock supply, reference
92
46
DT-Ms: References
[Boser88] [Bran97] B.E. Boser and B.A. Wooley, The Design of Sigma-Delta Modulation Analog-to-Digital Converters. IEEE Journal of Solid-State Circuits, vol. 23. pp. 1298-1308, December 1988. B. Brandt, P.F. Ferguson, and M. Rebeschini, Analog Circuit Design of ADCs, Chapter 11 in Delta-Sigma Data Converters: Theory, Design and Simulation (S.R. Norsworthy, R. Schreier, and G.C. Temes, Editors). IEEE Press, 1997. C.C. Enz and G.C. Temes, Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: Autozeroing, Correlated Double Sampling, and Chopper Stabilization. Proceedings of the IEEE, vol. 84, no. 11, pp. 1584-1614, November 1996. J.H. Fischer, Noise Sources and Calculation Techniques for Switched Capacitor Filters. IEEE Journal of Solid-State Circuits, vol. 17, no. 4, pp. 742-752, August 1982. Y. Geerts, M. Steyaert, and W. Sansen, Design of Multi-Bit Delta-Sigma A/D Converters. Kluwer Academic Publishers, 2002. F. Medeiro, B. Prez-Verd, and A. Rodrguez-Vzquez, Top-Down Design of High-Performance Modulators. Kluwer Academic Publishers, 1999. R. del Ro, F. Medeiro, B. Prez-Verd, and A. Rodrguez-Vzquez, Reliable Analysis of Settling Errors in SC Integrators: Application to Modulators. IEE Electronics Letters, vol. 36, no. 6, pp. 503-504, March 2000. G. Yin and W. Sansen, A High-Frequency and High-Resolution Fourth-Order A/D Converter in BiCMOS Technology. IEEE Journal of Solid-State Circuits, vol. 29, pp. 857-865, August 1994.
[Enz96]
[Fisc82] [Geer02] [Mede99] [Rio00] [Yin94]
More details on errors and case study

[Rio06] R. del Ro, F. Medeiro, B. Prez-Verd, J.M. de la Rosa, and A. Rodrguez-Vzquez, CMOS Cascade SigmaDelta Modulators for Sensors and Telecom: Error Analysis and Practical Design. Springer, 2006. 93
CT-Ms: References
[Bree00] [Bree01] [Cher00] [Font05] L.J. Breems, E.J. Van der Zwan and J. Huijsing, A 1.8-mW CMOS Modulator with Integrated Mixer for A/D Conversion of IF Signals. IEEE Journal of Solid-State Circuits, Vol. 35, pp. 468-475, April 2000. L. Breems and J.H. Huijsing, Continuous-Time Sigma-Delta Modulation for A/D Conversion in Radio Receivers. Kluwer Academic Publishers, 2001. J.A. Cherry and W.M. Snelgrove, Continuous-Time Delta-Sigma Modulators for High-Speed A/D Conversion. Kluwer Academic Publishers, 2000. P. Fontaine, A. N. Mohieldin and A. Bellaourar, A Low-Noise Low-Voltage CT Modulator with Digital Compensation of Excess Loop Delay. Proc. of the 2005 IEEE Int. Solid-State Circuits Conf., pp. 498-499, 2005. F. Gerfers, M. Ortmanns and Y. Manoli, A 1.5-V 12-bit Power-Efficient Continuous-Time Third-Order Modulator. IEEE Journal of Solid-State Circuits, Vol. 38, pp. 1343-1352, August 2003. O. Olieai, State-Space Analysis of Clock Jitter in Continuous-Time Oversampling Data Converters. IEEE Transactions on Circuits and Systems I, Vol. 50, pp. 31-37, January 2003. O. Olieai, Design of Continuous-Time Sigma-Delta Modulators With Arbitrary Feedback Waveform. IEEE Transactions on Circuits and Systems II, Vol. 50, pp. 437-444, August 2003. M. Ortmanns, F. Gerfers, and Y. Manoli, On the synthesis of cascaded continuous-time Sigma-Delta modulators. Proc. of the 2001 IEEE Int. Symp. on Circuits and Systems, Vol. 5, pp. 419-422, May 2001. M. Ortmanns, F. Gerfers and Y. Manoli, Compensation of Finite Gain-Bandwidth Induced Errors in Continuous-Time Sigma-Delta Modulators. IEEE Transactions on Circuits and Systems I, Vol. 51, pp. 10881099, June 2004. M. Ortmanns, F. Gerfers and Y. Manoli: A Case Study on 2-1-1 Cascaded Continuous-Time Sigma-Delta Modulators. IEEE Transactions on Circuits and Systems I, Vol. 52, pp. 1515-1525, August 2005.
[Gerf03] [Olia03a] [Olia03b] [Ortm01] [Ortm04]
[Ortm05]
94
47
CT-Ms: References
[Tao99a] [Tao99b] [Tort05] H. Tao, L. Toth and M. Khoury, Analysis of Timing Jitter in Bandpass Sigma-Delta Modulators. IEEE Transactions on Circuits and Systems I, Vol. 46, pp. 991-1001, August 1999. H. Tao and J.M. Khoury, A 400MS/s Frequency Translating BandPass Delta-Sigma Modulator. IEEE Journal of Solid-State Circuits, Vol. 34, pp. 1741-1752, December 1999. R. Tortosa, J.M. de la Rosa, A. Rodrguez-Vzquez and F.V. Fernndez, Analysis of Clock Jitter Error in Multibit Continuous-Time Modulators with NRZ Feedback Waveform. Proc. Of the 2005 Int. Symposium on Circuits and Systems (ISCAS), May 2005. R. Tortosa, J.M. de la Rosa, F.V. Fernndez and A. Rodrguez-Vzquez: A New High-Level Synthesis Methodology of Cascaded Continuous-Time Sigma-Delta modulators. IEEE Trans. On Circuits and Systems II: Express Briefs, pp. 739-743, August 2006. R. Tortosa, A. Aceituno, J.M. de la Rosa, F.V. Fernndez and A. Rodrguez-Vzquez: A 12-bit@40Ms/s GmC Cascade 3-2 Continuous-Time Sigma-Delta Modulator. Proc. Of the 2007 Int. Symposium on Circuits and Systems (ISCAS), May 2007. S. Yan and E. Snchez-Sinencio, A Continuous-Time Modulator With 88-dB Dynamic Range and 1.1MHz Signal Bandwidth. IEEE Journal of Solid-State Circuits, pp. 75-86, January 2004.
[Tort06]
[Tort07]
[Yan04]
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48
Systematic Design Methodology

Roco del Ro, Beln Prez-Verd and Jos M. de la Rosa Roc R Bel rez- Verd Jos

OUTLINE 1. Introduction
Digital vs. Analog/Mixed-signal design Analog/MixedSimulation approaches Hierarchical synthesis approach
2. Top-down design methodology

Top-down/Bottom-up approach Top- down/BottomOptimization engine Behavioral simulation
3. Introduction to SIMSIDES
Description of the toolbox Behavioral modeling of building blocks
4. DEMO & Tutorial examples

Introduction: Tendency to System Integration

From PCB (Printed-on-Board) To SoC (Systems-on-Chip)
Portability and robustness increase Reduce cost Benefits from technology evolution Increase programability
To SiP (Systems-in-Package)
Introduction: Digital vs. Analog&Mixed-Signal design
Introduction: Digital vs. Analog&Mixed-Signal design
Introduction: Digital CAD tools
Introduction: Analog CAD tools
10
11
12
13
Introduction: Simulation approaches
14
Introduction: Simulation approaches
15
Introduction: Hierarchical synthesis approach
16
Introduction: Synthesis methods

Knowledge-based tools: capture the knowledge of experienced designers
Short execution times Not optimized: design procedures usually based on approximate equations and models Closed tools Limited to a reduced number of topologies Addition of new ones usually restricted to the tool developers
Optimization-based tools: based on an iterative optimization procedure
Cost function evaluation by numerical methods: equations or simulations Two main optimization techniques:
Deterministic: parameter updating needs information on the cost function and on their
derivatives o o Optimization process may be trapped in a local minimum of the cost function Useful for fine tuning of suboptimal designs
Statistical: parameters are changed randomly

o o o o Avoid local minima Appropriate for global optimization No good initial design point is needed Requires larger computational cost 17
Introduction: Optimization-based synthesis approach
18
Introduction
19
Design Methodology: Top-down & bottom-up approach

Circuit Technique SC, SI, CT Design Space Exploration
Modulator Specs.
Architecture Quantizer Resolution
V m v
ref
o
Performance evaluator Advanced Optimizer
Ci
Ron
HIGH-LEVEL SIZING
Electrical Simulator
Advanced Optimizer
CELL SIZING
LAYOUT
VERIFICATION
VERIFICATION
20
10
Design Methodology: Top-down & bottom-up approach
21
Design Methodology: Optimization

Modulator Topology
Design Space Discretization
BASIC FEATURES
Main Optimization Update design parameters End? Yes Local Optimization
Cost function evaluation
Combines adaptive statistical and deterministic optimization Cost function formulation very versatile Addition of knowledge is permitted
Performance evaluator
No

Update design parameters
Hundreths or thousands of iterations.
End?
No
Speed Requirements ~ s
22
11

OPTIMIZATION-BASED ENGINE (FRIDGE)
Interacts with any kind of performance evaluation approach Statistical + Deterministic techniques Designers expertise can be added through powerful tools (embedded C++) Between Optimization and Knowledgebased approaches, taking the best from both worlds Used both for spec transmission and for cell-level sizing In process of being complemented with Evolutionary Algorithms Intese internal use
23

ITERATIVE CYCLE
Unsized circuit Initial position x0 xn=xn-1+xn-1 Performance evaluation Specifications END yes Specs OK? no Generate new movement xn1
EXAMPLE OF A COST FUNCTION

Control of the tuning process
FORMULATION OF THE COST FUNCTION

Problem:
minimize y (x ) ,1 i P oi subjected to y (x ) Y or y (x ) Y ,1 k R rk rk rk rk Target Specification P design objectives R restrictions
Weights used to give priority to the fulfillment of their corresponding specifications

w ilog( y oi ) if x R A i ( x ) = y rk max w k log Y if x R A rk
Cost Function
24
12
Design Methodology: Simulation techniques
Simulation of Ms:
Strongly non-linear circuits Oversampling long time-domain simulation
Techniques
Accuracy Electrical Mixed-mode Behavioral Speed
days/weeks hours seconds
25
SIMSIDES: Implementation platform

MATLAB-SIMULINK is a widely spread platform. Direct access to very powerful tools for signal processing and data manipulation. Provides a high-level language to create custom functions, structures, Graphical User Interfaces (GUIs), etc.
Simulink block libraries

(Malcovati et al., IEEE Trans. CAS, 2003)
Limited to SC circuits. Limited accuracy:

Transient response in both clock-phases not considered. Non-linear opamp DC gain, nonlinear switch-on resistance, nonlinear capacitors not included.
Models based on MATLAB functions excessive CPU time.

26
13
SIMSIDES: Description of the toolbox

Graphical User Interface Collection of post-processing routines
Global and efficient optimization techniques
SC, SI and CT techniques
Precise behavioural models

27
28
14

IDEAL LIBRARIES REAL LIBRARIES
INTEGRATORS
QUANTIZERS
DACS
RESONATORS
INTEGRATORS
Continuous-Time
RESONATORS
Switched-Current
QUANTIZERS
Continuous-Time
DACs
Switched-Capacitor Switched-Current
Switched-Capacitor
Gm-C
FE
FE
Gm-MC
LD
LD
RC
MOSFET-C
29
SIMSIDES: Behavioral modeling using S-functions
S-functions
Cancellation Logic y
Precise models: All major non-idealities included

Time-domain models
65536 points All non-idealities

S-functions 3 s. M-functions 141 s.
Models based on C-code
fast!!
Initia e v iab liz ar les
C 1 v
1
AV = A 0
2 1 v
+
a
v2
vo
C p om ute
vo
C pute om
+
a
AV
AV v a AV = A 0( 1 + 1v o + 2v 2 + ) o
En d Y es C verg ce on en ? N o
Algorithm
Coding
#define S_FUNCTION_NAME intfescavnl ......................................... #define phi(S) ssGetSFcnParam(S,0) #define av(S) ssGetSFcnParam(S,4) #define avnl(S) ssGetSFcnParam(S,5) ......................................... static void mdlInitializeSampleTimes(SimStruct *S) { double TS; TS = *mxGetPr(ts(S)); ssSetSampleTime(S, 0, TS/2); ssSetOffsetTime(S, 0, 0); } .......................................... static void mdlOutputs(SimStruct *S, int_T tid) { .......................................... do{ temp = ((C1/C2)*(VC1ANT-VC1)* (AVNEW/(1+AVNEW+(C1/C2)))) + (VC2*((AVNEW+1)/(1+AVNEW+(C1/ C2)))); AVANT = AVNUE; VO2 = temp*temp;
BlockSymbol
Dialogue Box
S-function block
Compilation
30
15
SIMSIDES: Creating S-functions
31
SIMSIDES: Behavioral models included in the toolbox

Circuit Tec. Building Block Non-ideality
SC
Finite and non-linear open-loop DC gain Incomplete settling error (both clock phases considered) Opamps Output swing limit Thermal noise Thermal noise, switch-on (non-linear) Switches resistance Capacitors Mismatch, non-linearity Resonators Gain and integrator errors Linear and non-linear gain error Finite output-input conductance ratio error Charge injection error Incomplete settling error Gain and integrator errors Finite and non-linear DC gain Non-linear transconductance Thermal noise Output swing limit Transient response Gain and integrator errors Jitter Hysteresis and Offset Non-linearity, gain error, loop delay, offset
Integrators
SI
Integrators
Resonators
CT
Integrators
Resonators Clock Comparators Quantizers DACs IMSE-CNM Design Group
32
16
SIMSIDES: Behavioral modeling of SC FE Integrators

Input Voltages
v1 , v2
v1 v2 1 2 - v C1+ C1 2 1 + v o - v C2 + C2 1
vo
Yes
Sampling phase
No
Initialize variables
Transient Response
Calculate equivalent thermal noise v n Opamp finite and non-linear open-loop gain Non-linear capacitors Cnl = C( 1 + cnl1 v + cnl2v 2 ) Transient response
v 2
V o = f ( v1 , v2, Avn )
n
Memorized Voltage Input
Av n = Av ( 1 + 1 vo + 2 v2 ) Yes No
END
Convergence?
ro n
C2
vou t
Output Saturation End Convergence No
Cp
gm ( v + v -)
Io
gou t
o ut
33
SIMSIDES: Model accuracy

A 0.25m CMOS 2-1-1 cascade Modulator for ADSL
vs.
A 0.8m CMOS 4th-order bandpass SI Modulator for digital radio

fn --- 0.245 fs
0.240 0.25
vs.
0.235 0.230 0.225 0.220
SIMSIDES MEASURED
5 10
f s( MHz)
15
20
34
17
SIMSIDES: Simulating a CT 5th-order LP SL M
y Ideal_Comparator Sine Wave gmC-integrator gmC-integrator2 Ground gmC-integrator3 gmC-integrator4 Ground1 gmC-integrator5 T o Workspace
Real_DAC_Multibit_delay_jitter
7s. CPU time 65536 points P4@1.7GHz
95
-20 Relative Magnitude (dB) -40 -60 -80 signal-dependent delay fixed delay
90 SNR (dB) 85 80
-100 -120 -140 -160 10

4
Ideal
75
6 8
jitter = Ts
10
-5
10 Frequency (Hz)
10
70 -6 10
10
-4
10
-3
35
SIMSIDES: Sizing a SC 2-1-1 cascade M Specifications

13bits@4.4Ms/s Minimum area and power consumption
SPECIFICATIONS FOR: I Int. II Int. III Int. IV Int.
Cancellation Logic
Sampling frequency (MHz) Modulator Oversampling ratio Reference Voltage (V) Feed-back capacitor (pF) Cap. Non-linearity Integrators (ppm/V2) 2.64
70.4 16 1.5 0.9 15 150 81 65 54 54 0.9 0.45
Synthesis All non-idealities 40.8 minutes

Opamps
Switch on-resistance () DC-gain (dB)
Input noise PSD (nV/Hz) 1.6 1.5 2.9 2.9 Transconductance (mA/V) 6.4 7 3.4 3.4 Max. Output Current (mA) 1.5 2.2 1.6 1.6 Offset (mV) Hysteresis (mV) 10 20 3 0.5%FS
Comps.
Resolution (bits) A/D/A converter DAC INL IMSE-CNM Design Group
36
18
SIMSIDES: Sizing a SC 2-1-1 cascade M
-60
HSPICE MEASURED Synthesis Toolbox
Power Spectral Density (dB/Hz)
-80
Synthesis Toolbox Clock frequency (MHz) Digital output rate (Ms/s) Oversampling ratio 70.4 4.4 16 1.5
Measured
-100
-120
-140
-160
Reference voltage (V)

10
4
10
Frequency (Hz)
10
10
Technology Power consumption (mW) Area (mm2) Resolution (bits)
0.25m CMOS@2.5V 13.3 55 2.78 12.7
37
SIMSIDES: Conclusions
SIMSIDES is a M Synthesis Toolbox in the Matlab/Simulink environment.
It allows to efficiently map the modulator specifications into buildingblock specifications. It deals with the synthesis of Ms using both DT and CT circuit techniques.
The implementation platform brings numerous advantages with a relatively low penalty in computation time.
38
19
SIMSIDES: Conclusions
NGoran Tiempo de CPU CPU TIME

Precisin ACCURACY
ASIDES SIMSIDES TOSCA DAISY NGoran SDTOOLBOX
SDTOOLBOX TOSCA SIMSIDES ASIDES DAISY
Postprocesado
SDTOOLBOX DAISY ASIDES TOSCA NGoran
POSTPROCESSING
SIMSIDES Flexibilidad FLEXIBILITY
SIMSIDES SDTOOLBOX ASIDES TOSCA NGoran DAISY
39
DEMO & TUTORIAL EXAMPLES

40
20
References
[Dia92] V. F. Dias, V. Liberali and F. Maloberti: Design Tools for Oversampling Data Converters: Needs and Solutions, Microelectronics Journal, Vol. 23, pp. 641-650, 1992. G.G. E. Gielen and R.A. Rutenbar: Computer-Aided Design of Analog and Mixed-Signal Integrated Circuits, Proceedings of the IEEE, Vol. 88, pp. 1825-1852, December 2000.
[Giel00]
[Mede99] F. Medeiro, B. Prez-Verd and A. Rodrguez-Vzquez: Top-Down Design of High-Performance Modulators. Kluwer, 1999. [Ruiz05] J. Ruiz-Amaya, J.M. de la Rosa, F. V. Fernndez, F. Medeiro, R. del Ro, B. Prez-Verd and A. Rodrguez-Vzquez: High-Level Synthesis of Switched-Capacitor, Switched-Current and ContinuousTime Modulators Using SIMULINK-Based Time-Domain Behavioral Models. IEEE Trans. on Circuits and Systems-I: Regular Papers, Vol. 52, pp. 1795-1810, September 2005..
41
21

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CMOS Sigma-Delta Converters From Basics to State-of-the-Art

Basic Concepts and Architectures

KTH, Stockholm, April 23-27

OUTLINE 1. Introduction 2. Fundamentals of ADCs

Introduction: Basic ADC process

IMSE-CNM Design Group

Introduction: Basic ADC process

Introduction: Resolution vs. conversion rate

ADCs Nyquist ADCs

IMSE-CNM Design Group

IMSE-CNM Design Group

IMSE-CNM Design Group

Introduction: Quantization - white noise model

IMSE-CNM Design Group

Introduction: Sampling Oversampling

IMSE-CNM Design Group

Fundamentals of ADCs: Oversampling

In-Band Noise power (IBN or PQ)

IMSE-CNM Design Group

Fundamentals of ADCs: Performance Metrics

IMSE-CNM Design Group

Fundamentals of ADCs: Performance Metrics

IMSE-CNM Design Group

Fundamentals of ADCs: Quantization Noise Shaping

In-band noise power and effective resolution

IMSE-CNM Design Group

Fundamentals of ADCs: Basic ADC architecture

IMSE-CNM Design Group

Fundamentals of ADCs: Nyquist-rate vs. ADCs

IMSE-CNM Design Group

Fundamentals of ADCs: Basic M architecture

IMSE-CNM Design Group

Fundamentals of ADCs: Classification of Ms

Dynamics of the loop filter: Discrete-Time vs. Continuous-Time

Fundamentals of ADCs: Basic control parameters

IMSE-CNM Design Group

DT-Ms: 1st-order LP Modulator

Using a linear model for the quantizer

IMSE-CNM Design Group

DT-Ms: 1st-order LP Modulator

Ramp input & 1-bit quantizer

Sinewave input & 3-bit quantizer

IMSE-CNM Design Group

DT-Ms: 1st-order LP Modulator

IMSE-CNM Design Group

DT-Ms: 2nd-order LP Modulator

IMSE-CNM Design Group

DT-Ms: 2nd-order LP Modulator

Output spectrum and noise pattern

IMSE-CNM Design Group

DT-Ms: High-order Single-loop Modulators

IIR NTFs (1)

IMSE-CNM Design Group

DT-Ms: High-order Single-loop Modulators

5th-order NTF 5th(OSR = 64)

IIR NTFs (1) (2)

IMSE-CNM Design Group

DT-Ms: High-order Single-loop Modulators

Complexity (many feedback/feedforward coeffs) Large spread of coeffs (area, power)

Feedforward summation + local resonators

IMSE-CNM Design Group

DT-Ms: High-order Cascade Modulators

IMSE-CNM Design Group