Dien Tu 6937

TRNG I HC CN TH
KHOA CNG NGH

B MN IN T VIN THNG

LUN VN TT NGHIP
CHUYN NGNH IN T VIN THNG
THIT K
LCH VN NIN IN T
Gio vin hng dn:
Sinh vin thc hin:
TS.LNG VINH QUC DANH
NGUYN VN BNH
MSSV: 1071075
Lp: in T Vin Thng 2.K33
THIT K LCH VN NIN IN T

Cn Th 2010
NHN XT CA GIO VIN HNG DN
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Gio vin hng dn:

TS.Lng Vinh Quc Danh
II
Sinh vin thc hin:

Nguyn Vn Bnh
................................................................................................
Gio vin hng dn:

III
Sinh vin thc hin:

Nguyn Vn Bnh
LI CM T
u tin em xin gi li cm n n Ban Gim Hiu trng i Hc Cn Th
cho em mt mi trng hc tp tt, cng nh l to nhiu iu kin thun li
em c th pht huy c kh nng ca mnh.
Em xin chn thnh cm n n qu Thy/C, c bit l qu Thy/C trong
b mn in T -Vin Thng thuc khoa Cng Ngh trng i Hc Cn Th
tn tnh ch dy v truyn t nhng kin thc qu bu em c th hon thnh
lun n ny, ng thi cng l mt hnh trang ng qu em c th tip bc
trn con ng s nghip sau ny.
Em xin bi t lng bit n su sc i vi thy Lng Vinh Quc Danh l
ngi tn tnh hng dn v ng vin em trong sut thi gian em thc hin lun
vn tt nghip ny.
hon thnh lun vn tt nghip ny cng c s ng gp khng nh ca
cc bn. Ti xin c gi li cm n n tt c cc bn.
Ngoi ra ti cng xin gi li cm n n tt c nhng ngi thn xung quanh
gip v vt cht v tinh thn ti c th hon thnh xong lun vn tt
nghip ny.
Cn Th ngy
thng
nm 2010
Sinh vin thc hin
Nguyn Vn Bnh
Gio vin hng dn:

IV
Sinh vin thc hin:

Nguyn Vn Bnh
TM TT TI
Lch Vn Nin in T thit k da trn s kt hp gia IC thi gian
thc (DS1307) v vi iu khin 89S52 vi b iu khin s dng remote hng
ngoi. Ngoi ra mch cn s dng cm bin nhit (LM35) cng vi b bin i
t tng t sang s (ADC0804) o nhit xung quanh v hin th ra led 7 on.
Vi b iu khin dng remote hng ngoi, chng ta c th chn thi gian bo thc
hoc iu chnh gi, ngy, thng. rt d dng v thun tin (ging nh s dng
Romote iu khin mt chic TV vy!). Mch thit k thnh cng, hot ng
n nh vi chnh xc cao.
ABSTRACT
Electronic perpetual calendar designed based on a combination of realtime IC (DS1307) and 89S52 microcontroller with controller using infrared remote.
In addition, it uses a temperature sensor circuit ( LM35) with the transformation
from analog to digital (ADC0804) to measure ambient temperature and the LED 7
segment display. With the controller using infrared remote, we can select the alarm
time or adjust hours, days, months .... very easy and convenient (like Romote used
to control a TV too!). The circuit was successfully designed, stable operation with
high accuracy.
Key word: Infrared remote, measure temperature and calendar
Title: Electronic perpetual calendar
Gio vin hng dn:

Sinh vin thc hin:

Nguyn Vn Bnh
MC LC
TM TT TI...................................................................................................V
ABSTRACT.............................................................................................................V
MC LC...............................................................................................................VI
CHNG I: M U...........................................................................................X
I. KHI QUT VN .....................................................................................X
II. LCH S GII QUYT VN .................................................................X
III. MC CH YU CU CA TI.....................................................XI
CHNG II: C S L THUYT.....................................................................XII
A.O NHIT ..................................................................................................XII
I.GII THIU V VI IU KHIN 89S52......................................................XII
1. Tng quan v 89S52........................................................................................XII
XIII
2. M t chn 89S52............................................................................................XIV
2.1. S chn 89S52.............................................................................XIV
2.2. Chc nng ca cc chn 89S52.......................................................XIV
3. T chc b nh bn trong 89S52....................................................................XVI
3.1. RAM a dng.................................................................................XVIII
3.2. RAM c th nh a ch bit...........................................................XVIII
3.3. Cc bank thanh ghi.........................................................................XVIII
3.4. Cc thanh ghi c chc nng c bit..............................................XVIII
3.4.1. Thanh ghi trng thi chng trnh (PSW: Program Status Word)
..............................................................................................................XIX
3.4.2. Thanh ghi TIMER........................................................................XX
3.4.3. Thanh ghi ngt (INTERRUPT)...................................................XXI
II. S LC V CM BIN NHIT LM35D............................................XXIV
III. KHI QUT V ADC0804.....................................................................XXV
1. M t chn ADC0804...................................................................................XXV
2. T chc bn trong ADC0804......................................................................XXVII
...........................................................................................................XXVIII
2.1. Qu trnh chuyn i ca chip ADC0804.......................................XXIX
2.2. Qu trnh c d liu t chip ADC0804........................................XXIX
IV. GII THIU IC CHT 74HC374............................................................XXX
1. M t chn IC 74HC374................................................................................XXX
2. T chc bn trong IC74HC374.....................................................................XXX
B. NG H THI GIAN THC V B IU KHIN T XA DNG
REMOTE HNG NGOI...............................................................................XXXII
I. IU KHIN T XA DNG REMOTE HNG NGOI.......................XXXII
1. Hng ngoi l g?.......................................................................................XXXII
2. Cch to ra hng ngoi...............................................................................XXXII
3. Cach thu tin hiu hng ngoai.....................................................................XXXIII
4. Kho st tn hiu hng ngoi pht ra t Remote SONY............................XXXIV
Gio vin hng dn:
VI
Sinh vin thc hin:

Nguyn Vn Bnh

II. NG H THI GIAN THC............................................................XXXVI
1. Tng quan v DS1307..............................................................................XXXVI
1.1. S chn DS1307.....................................................................XXXVI
1.2. Cu to bn trong DS1307.........................................................XXXVII
XL
2. Khi qut giao din I2C ..................................................................................XLI
3. Mode (ch ) truyn d liu gia DS1307 v AT89S52............................XLIV
3.1. Mode Data Write (ch ghi d liu)............................................XLIV
3.2. Mode Data Read (ch dc d liu)............................................XLVI
XLVII
CHNG III: THIT K PHN CNG......................................................XLVIII
A. O NHIT ...........................................................................................XLVIII
I. S V CHC NNG TNG KHI...............................................XLVIII
1. S khi..................................................................................................XLVIII
2. Chc nng ca tng khi...........................................................................XLVIII
2.1. Cm bin nhit v khuch i......................................................XLVIII
2.2. Bin i ADC v khi x l trung tm (CPU_1).........................XLVIII
2.3. Khi hin th th 1 s dng LED 7 on........................................XLIX
2.4. Hiu ng dng LED n................................................................XLIX
II. S CHI TIT V NGUYN TT HOT NG............................XLIX
1. S chi tit................................................................................................XLIX
1.1. Cm bin nhit v b khuch i....................................................XLIX
1.2. Bin i ADC v khi x l trung tm (CPU_1)...................................L
1.3. Khi hin th th 1 s dng LED 7 on............................................LII
1.4. Hiu ng dng LED n...................................................................LIII
2. Nguyn tt hot ng......................................................................................LIV
REMOTE HNG NGOI....................................................................................LV
I. S V CHC NNG TNG KHI......................................................LV
1. S khi........................................................................................................LV
2. Chc nng ca tng khi..................................................................................LV
2.1. Khi thi gian thc.............................................................................LV
2.2. Khi pht hng ngoi.........................................................................LV
2.3. Khi thu hng ngoi..........................................................................LVI
2.4. Khi x l trung tm (CPU_2)..........................................................LVI
2.5. Khi m thanh v hin th th 2........................................................LVI
II.S CHI TIT V NGUYN TT HOT NG................................LVI
1. S chi tit...................................................................................................LVI
1.1. Khi thi gian thc (DS1307)...........................................................LVI
1.2. Khi thu hng ngoi.........................................................................LVII
LVII
1.3. Khi x l trung tm (CPU_2).........................................................LVII
1.4. Khi m thanh................................................................................LVIII
Gio vin hng dn:

VII
Sinh vin thc hin:

Nguyn Vn Bnh

LVIII
1.5. Khi hin th th 2..........................................................................LVIII
LIX
2. Nguyn tt hot ng.......................................................................................LX
CHNG III: THIT K PHN MM.............................................................LXI
A. O NHIT ...............................................................................................LXII
I. LU V GII THUT CHNG TRNH.........................................LXII
1. Gii thut.......................................................................................................LXII
1.1. Gii thut chng trnh chnh.........................................................LXII
1.2. Gii thut chng trnh con TRUY_CAP_ADC.........................LXII
2. Lu ...........................................................................................................LXII
2.1. Lu chng trnh chnh...............................................................LXII
2.2. Lu chng trnh con.................................................................LXIII
2.2.1. Lu chng trnh con TRUY_CAP_ADC...............LXIII
2.2.2. Lu chng trnh con HIENTHI_1.................................LXIV
II. PHN MM DO NHIT (CODE_1)..................................................LXV
I. LU V GII THUT CHNG TRNH........................................LXVI
1. Gii thut......................................................................................................LXVI
1.1. Gii thut chng trnh chnh..........................................................LXVI
1.2. Gii thut chng trnh ngt GIAI_MA_REMOTE_SONY........LXVI
1.3. Gii thut chng trnh con WRITE_CLOCK...........................LXVII
1.4. Gii thut chng trnh con READ_CLOCK........................LXVIII
2. Lu .......................................................................................................LXVIII
2.1. Lu chng trnh chnh...........................................................LXVIII
2.2. Lu chng trnh ngt GIAI_MA_REMOTE_SONY............LXIX
2.3. Lu chng trnh con ...............................................................LXXII
2.3.1. Lu chng trnh con WRITE_CLOCK.........................LXXII
2.3.2. Lu chng trnh con READ_CLOCK.........................LXXIII
2.3.3. Lu chng trnh con ghi 1 byte vo DS1307SEND_BYTE
.........................................................................................................LXXIV
2.3.4. Lu chng trnh con c 1 byte t DS1307READ_BYTE
..........................................................................................................LXXV
2.3.5. Lu chng trnh con ALARM_CLOCK_TEST..........LXXVI
2.3.6. Lu chng trnh con TAT_MO_CHUONG...............LXXVII
2.3.7. Lu chng trnh con HIEU_UNG_CHINH..............LXXVIII
2.3.8. Lu chng trnh con HIENTHI_2...............................LXXIX
II. PHN MM NG H THI GIAN THC V B IU KHIN T XA
DNG REMOTE HNG NGOI (CODE_2)............................................LXXX
CHNG IV: KT LUN V NGH....................................................LXXXI
I. KT LUN..........................................................................................LXXXI
LXXXIII
II. NGH............................................................................................LXXXIV
TI LIU THAM KHO.............................................................................LXXXV
Gio vin hng dn:

VIII
Sinh vin thc hin:

Nguyn Vn Bnh

PH LC.....................................................................................................LXXXVI
1. Phn mm o nhit (CODE_1)........................................................LXXXVI
2. Phn mm ng h thi gian thc v b iu khin t xa dng remote hng
ngoi (CODE_2)................................................................................................XC
4. Code word ca remote SONY......................................................................CIX
Gio vin hng dn:

IX
Sinh vin thc hin:

Nguyn Vn Bnh
CHNG I: M U
I. KHI QUT VN
Trong giai on hin nay vi s pht trin vt bt ca cng ngh Nano
hng lot IC mi c ch to. Nhng IC ny thng minh hn rt nhiu so vi cc
IC trc v c bit l chng ta c th ghi/xa d liu vo mt cch d dng. V th
n c s dng trong nhiu thit b in - in T v ngy cng th hin c
bn cht u vit ca mnh. in hnh l dng IC 8051/8052.
Vi s ra i ca dng IC mi lm thc y s pht trin ca nhng IC
thi gian thc nh DS1307, DS12887 Song song truyn d liu khng dy
cng bt pht trin vi nhiu kiu truyn khc nhau v phc tp, trong tt c cc
kiu truyn th truyn d liu bng tia hng ngoi c xem l n gin nht.
Cng vi s pht trin ca khoa hc k thut gp phn nng cao i sng
ca con ngi. Cng chnh v th m mi ngi cn phi bit chnh xc ngy, gi
thu xp vic lm cho hp l.
Xut pht t thc tin ny em i n quyt nh Thit k Lch Vn
Nin in T. Nhm p ng nhu cu ham mun hc hi ca bn thn, cng nh
l gp phn nng gi tr ca nhng mch in t trong i sng ca con ngi.
II. LCH S GII QUYT VN

ti ny trc khi ti thc hin c mt s sinh vin trng i hc
Bch Khoa Thnh Ph H Ch Minh thc hin nhng kt qu cha c nh
mong mun v mch chy khng n nh v thng hay b treo. Hn na h
ch Thit k Lch Vn Nin in T vi nhng cng tt iu chnh, khng
dng remote hng ngoi iu chnh. Chnh v th ti quyt nh chn ti ny
v kt hp thm b iu khin t xa dng remote hng ngoi. V ti mong mun
to ra mt thit b vi nhiu thun li hn cho ngi dng v tin cy cao.
Gio vin hng dn:

Sinh vin thc hin:

Nguyn Vn Bnh
III. MC CH YU CU CA TI
Trong lun n ny ti s dng mt con IC thi gian thc (DS1307) kt hp
vi vi iu khin 89S52 to thnh giao din I2C, 89S52 c nhim v c/ghi
(gi, pht, giy, th, ngy..thi gian bo thc) t chip DS1307. Khi thi gian bo
thc trng vi thi gian thc th loa s pht ra m thanh trong 1 pht, ng thi khi
c tn hiu pht ra t remote hng ngoi th 89S52 bt u gii m tn hiu ny, sau
khi gii m 89S52 ghi d liu nhn c vo DS1307. Ngoi ra mch cn s dng
cm bin nhit (LM35), ng ra ca cm bin ny c a qua b bin i tng t
sang s (ADC0804), d liu c 89S52 c ra t ADC0804 v hin th kt qu ra
led 7 on.
T y c th suy ra mc ch yu cu ca ti nh sau:
Mch hin th gi, pht, giy, th, ngy, thng, nm mt cch chnh
xc
o nhit v hin th ra led 7 on
B ci t thi gian c s dng bng remote hng ngoi, xc xut li
khi n remote l thp nht
Khi thi gian bo thc trng vi thi gian thc th loa phi pht ra m
thanh bo thc
Gi thnh sn phm khng qu c.
Da vo yu cu ca ti ti phn ra thnh 2 khi ln:
o Khi A: o nhit v hin th kt qu ra led 7 on
o Khi B: ng h thi gian thc v b iu khin t xa dng remote hng
ngoi
Gio vin hng dn:

XI
Sinh vin thc hin:

Nguyn Vn Bnh
CHNG II: C S L THUYT

A. O NHIT
I.GII THIU V VI IU KHIN 89S52
1. Tng quan v 89S52
AT89S52 l h IC vi iu khin do hng Intel sn xut. Cc sn phm
AT89S52 thch hp cho nhng ng dng iu khin. Vic x l trn byte v cc
ton s hc cu trc d liu nh c thc hin bng nhiu ch truy xut d
liu nhanh trn RAM ni. Tp lnh cung cp mt bng tin dng ca nhng lnh s
hc 8 bit gm c lnh nhn v lnh chia. N cung cp nhng h tr m rng trn
chip dng cho nhng bin mt bit nh l kiu d liu ring bit cho php qun l v
kim tra bit trc tip trong h thng iu khin.
AT89S52 cung cp nhng c tnh chun nh: 8 KByte b nh ch c c
th xa v lp trnh nhanh (EPROM), 128 Byte RAM, 32 ng I/O, 3
TIMER/COUNTER 16 Bit, 5 vect ngt c cu trc 2 mc ngt, mt Port ni tip
bn song cng, 1 mch dao ng to xung Clock v b dao ng ON-CHIP.
Cc c im ca chip AT89S52 c tm tt nh sau:
8 KByte b nh c th lp trnh nhanh, c kh nng ti 1000 chu k ghi/xo
Tn s hot ng t: 0Hz n 24 MHz
3 mc kha b nh lp trnh
3 b Timer/counter 16 Bit
128 Byte RAM ni.
4 Port xut /nhp I/O 8 bit.
Gio vin hng dn:

XII
Sinh vin thc hin:

Nguyn Vn Bnh

Giao tip ni tip.
64 KB vng nh m ngoi
64 KB vng nh d liu ngoi.
4 s cho hot ng nhn hoc chia
S khi ca AT89S52
Gio vin hng dn:

XIII
Sinh vin thc hin:

Nguyn Vn Bnh
2. M t chn 89S52
2.1. S chn 89S52
Mc d cc thnh vin ca h
8051(v d 8751, 89S52, 89C51,
DS5000) u c cc kiu ng v
AT89S52
khc nhau, chng hn nh hai hng

chn DIP (Dual In-Line Pakage),
dng v dt vung QPF (Quad Flat
Pakage) v dng chip khng c chn
LLC (Leadless Chip Carrier) th
chng u c 40 chn cho cc chc
nng khc nhau nh vo ra I/O, c
RD
, ghi
WR
, a ch, d liu v
ngt. Cn phi lu mt s hng

cung cp mt phin bn 8051 c 20 chn vi s cng vo ra t hn cho cc ng
dng yu cu thp hn. Tuy nhin v hu ht cc nh pht trin s dng chp ng
v 40 chn vi hai hng chn DIP nn ta ch tp trung m t phin bn ny.
2.2. Chc nng ca cc chn 89S52

Port 0: t chn 32 n chn 39 (P0.0 _P0.7). Port 0 c 2 chc nng: trong cc
thit k c nh khng dng b nh m rng n c chc nng nh cc ng IO, i
vi thit k ln c b nh m rng n c kt hp gia bus a ch v bus d liu.
Port 1: t chn 1 n chn 9 (P1.0 _ P1.7). Port 1 l port IO dng cho giao
tip vi thit b bn ngoi nu cn.
Port 2: t chn 21 n chn 28 (P2.0 _P2.7). Port 2 l mt port c tc dng
kp dng nh cc ng xut/nhp hoc l byte cao ca bus a ch i vi cc thit
b dng b nh m rng.
Gio vin hng dn:

XIV
Sinh vin thc hin:

Nguyn Vn Bnh

Port 3: t chn 10 n chn 17 (P3.0 _ P3.7). Port 3 l port c tc dng kp.
Cc chn ca port ny c nhiu chc nng, c cng dng chuyn i c lin h n
cc c tnh c bit ca 89S52 nh bng sau:
Bit
Tn
Chc nng chuyn i
P3.0
RXD
Ng vo d liu ni tip.
P3.1
TXD
Ng xut d liu ni tip.
P3.2
INT0
Ng vo ngt cng th 0.
P3.3
INT1
Ng vo ngt cng th 1.
P3.4
T0
Ng vo TIMER/ COUNTER th 0.
P3.5
T1
Ng vo ca TIMER/ COUNTER th 1.
P3.6
WR
Tn hiu ghi d liu ln b nh ngoi.
P3.7
RD
Tn hiu c b nh d liu ngoi.
PSEN (Program store enable):

PSEN l tn hiu ng ra c tc dng cho php c b nh chng trnh
m rng v thng c ni n chn OE ca Eprom cho php c cc byte
m lnh.
PSEN mc thp trong thi gian 89S52 ly lnh. Cc m lnh ca chng
trnh c c t Eprom qua bus d liu, c cht vo thanh ghi lnh bn trong
89S52 gii m lnh. Khi 89S52 thi hnh chng trnh trong ROM ni, PSEN
mc cao.
ALE (Address Latch Enable):
Khi 89S52 truy xut b nh bn ngoi, Port 0 c chc nng l bus a ch v
d liu do phi tch cc ng d liu v a ch. Tn hiu ra ALE chn th 30
dng lm tn hiu iu khin gii a hp cc ng a ch v d liu khi kt ni
chng vi IC cht.
Gio vin hng dn:
XV
Sinh vin thc hin:

Nguyn Vn Bnh

Tn hiu chn ALE l mt xung trong khong thi gian port 0 ng vai tr l
a ch thp nn cht a ch hon ton t ng.
EA (External Access): Tn hiu vo EA (chn 31) thng c mc ln mc 1
hoc mc 0. Nu mc 1, 89S52 thi hnh chng trnh t ROM ni. Nu mc 0,
89S52 thi hnh chng trnh t b nh m rng. Chn EA c ly lm chn cp
ngun 21V khi lp trnh cho Eprom trong 89S52.
RST (Reset): Khi ng vo tn hiu ny a ln
mc cao t nht 2 chu k my, cc thanh ghi bn
trong c np nhng gi tr thch hp khi
ng h thng. Khi cp in mch phi t ng
reset.
Cc gi tr t v in tr c chn l:
R1=10 , R2=220 , C=10 F.
Cc ng vo b dao ng X1, X2:
B to dao ng c tch hp bn trong
89S52. Khi s dng 89S52, ngi ta ch cn
ni thm thch anh v cc t. Tn s thch anh
ty thuc vo mc ch ca ngi s dng, gi
tr t thng c chn l 33p.
3. T chc b nh bn trong 89S52

B nh trong 89S52 bao gm ROM v RAM. RAM trong 89S52 bao gm
nhiu thnh phn: phn lu tr a dng, phn lu tr a ch ha tng bit, cc bank
thanh ghi v cc thanh ghi chc nng c bit.
AT89S52 c b nh c t chc theo cu trc Harvard: c nhng vng b
nh ring bit cho chng trnh v d liu. Chng trnh v d liu c th cha bn
trong 89S52 nhng 89S52 vn c th kt ni vi 64K byte b nh chng trnh v
64K byte d liu bn ngoi.
Gio vin hng dn:

XVI
Sinh vin thc hin:

Nguyn Vn Bnh

Bn b nh Data bn trong Chip 89S52 c t chc nh sau:
a ch
byte
a ch bit
Gio vin hng dn:

a ch
byte
XVII
a ch bit
Sinh vin thc hin:

Nguyn Vn Bnh

RAM bn trong AT89S52 c phn chia nh sau:
Cc bank thanh ghi c a ch t 00H n 1FH.
RAM a ch ha tng bit c a ch t 20H n 2FH.
RAM a dng t 30H n 7FH.
Cc thanh ghi chc nng c bit t 80H n FFH
3.1. RAM a dng

RAM a dng c a ch t 30h 7Fh c th truy xut mi ln 8 bit bng cch
dng ch nh a ch trc tip hay gin tip.
Cc vng a ch thp t 00h 2Fh cng c th s dng cho mc ch nh
trn, ngoi cc chc nng c bit c cp phn sau.
3.2. RAM c th nh a ch bit

Vng a ch t 20h -2Fh gm 16 byte c th thc hin nh vng RAM a
dng (truy xut mi ln 8 bit) hay thc hin truy xut mi ln 1 bit bng cc lnh x
l bit.
3.3. Cc bank thanh ghi

Vng a ch 00h 1Fh c chia thnh 4 bank thanh ghi: bank 0 t 00h
07h, bank 1 t 08h 0Fh, bank 2 t 10h 17h v bank 3 t 18h 1Fh. Cc bank
thanh ghi ny c i din bng cc thanh ghi t R0 n R7. Sau khi khi ng th
h thng bank 0 c chn s dng.
Do c 4 bank thanh ghi nn ti mt thi im ch c mt bank thanh ghi
c truy xut bi cc thanh ghi R0 n R7. Vic thay i bank thanh ghi c
thc hin thng qua thanh ghi t trng thi chng trnh (PSW).
3.4. Cc thanh ghi c chc nng c bit

Cc thanh ghi trong 89S52 c nh dng nh mt phn ca RAM trn chip
v vy mi thanh ghi s c mt a ch (ngoi tr thanh ghi b m chng trnh v
thanh ghi lnh v cc thanh ghi ny him khi b tc ng trc tip). Cng nh R0
Gio vin hng dn:
XVIII
Sinh vin thc hin:

Nguyn Vn Bnh

n R7, 89S52 c 21 thanh ghi c chc nng c bit (SFR: Special Function
Register) vng trn ca RAM ni t a ch 80H n 0FFH.
Sau y l mt vi thanh ghi c bit thng c s dng:
3.4.1. Thanh ghi trng thi chng trnh (PSW: Program Status
Word)
BIT
SYMBOL
ADDRESS
DESCRIPTION
PSW.7
CY
D7H
Cary Flag
PSW.6
AC
D6H
Auxiliary Cary Flag
PSW.5
F0
D5H
Flag 0
PSW4
RS1
D4H
Register Bank Select 1
PSW.3
RS0
D3H
Register Bank Select 0

00=Bank 0; address 00H 07H
01=Bank 1; address 08H 0FH
10=Bank 2; address 10H 17H
11=Bank 3; address 18H 1FH
PSW.2
OV
D2H
Overlow Flag
PSW.1
D1H
Reserved
PSW.0
DOH
Even Parity Flag
Chc nng tng bit trng thi chng trnh

- C Carry CY (Carry Flag):
C nh thng n c dng cho cc lnh ton hc: C =1 nu php ton
cng c s trn hoc php tr c mn v ngc li C = 0 nu php ton cng
khng trn v php tr khng c mn.
- C Carry ph AC (Auxiliary Carry Flag):
Khi cng nhng gi tr BCD (Binary Code Decimal), c nh ph AC c
set nu kt qu 4 bit thp nm trong phm vi iu khin 0AH - 0FH. Ngc li AC
=0
Gio vin hng dn:
XIX
Sinh vin thc hin:

Nguyn Vn Bnh

- C 0 (Flag 0):
C 0 (F0) l 1 bit c a dng dng cho cc ng dng ca ngi dng.
- Nhng bit chn bank thanh ghi truy xut:
RS1 v RS0 quyt nh dy thanh ghi tch cc. Chng c xa sau khi reset
h thng v c thay i bi phn mm khi cn thit.
Ty theo RS1, RS0 = 00, 01, 10, 11 s c chn Bank tch cc tng ng l
Bank 0, Bank1, Bank2 v Bank3.
RS1
RS0
BANK
- C trn OV (Over Flag):

C trn c set sau mt hot ng cng hoc tr nu c s trn ton hc.
- Bit Parity (P):
Bit t ng c set hay Clear mi chu k my lp Parity chn vi
thanh ghi A. S m cc bit 1 trong thanh ghi A cng vi bit Parity lun lun chn.
V d A cha 10101101B th bit P set ln mt tng s bit 1 trong A v P to
thnh s chn.
Bit Parity thng c dng trong s kt hp vi nhng th tc ca Port ni
tip to ra bit Parity trc khi pht i hoc kim tra bit Parity sau khi thu.
3.4.2. Thanh ghi TIMER
Gio vin hng dn:

XX
Sinh vin thc hin:

Nguyn Vn Bnh

Vi iu Khin 89S52 c 3 timer 16 bit, mi timer c bn cch lm vic.
Ngi ta s dng cc timer :
o nh khong thi gian.
o m s kin.
o
To tc baud cho port ni tip trong 89S52.
Trong cc ng dng nh khong thi gian, ngi ta lp trnh timer nhng

khong u n v t c trn timer. C c dng ng b ha chng trnh
thc hin mt tc ng nh kim tra trng thi ca cc ng vo hoc gi s kin ra
cc ng ra. Cc ng dng khc c th s dng vic to xung nhp u n ca timer
o thi gian tri qua gia hai s kin (v d o rng xung).
3.4.3. Thanh ghi ngt (INTERRUPT)
Mt ngt l s xy ra mt iu kin, mt s kin m n gy ra treo tm thi
thi chng trnh chnh trong khi iu kin c phc v bi mt chng trnh
khc.
Cc ngt ng mt vai tr quan trng trong thit k v ci t cc ng dng
vi iu khin. Chng cho php h thng p ng bt ng b vi mt s kin v
gii quyt s kin trong khi mt chng trnh khc ang thc thi.
- T chc ngt ca 89S52:
C 5 ngun ngt 89S52: 2 ngt ngoi, 2 ngt t timer v 1 ngt port
ni tip. Tt c cc ngt theo mc nhin u b cm sau khi reset h thng v c
cho php tng ci mt bng phn mm. Mc u tin ca cc ngt c lu trong
thanh ghi IP (Interrupt Priority) hay ni cch khc thanh ghi IP cho php chn mc
u tin cho cc ngt (gi tr thanh ghi IP khi reset l 00h).
Bit
K hiu
a ch bit
IP.7
Gio vin hng dn:

M t
Khng c m t
XXI
Sinh vin thc hin:

Nguyn Vn Bnh

IP.6
IP.5
ET2
BDH
Khng c m t
Chn mc u tin cao (=1) hay thp (=0) ti
timer 2
IP.4
ES
BCH

cng ni tip.
IP.3
ET1
BBH

timer 1
IP.2
EX1
BAH
Chn mc u tin cao (=1) hay thp (=0) ti ngt

ngoi 1
IP.1
ET0
B9H

timer 0
IP.0
EX0
B8H
Chn mc u tin cao (=1) hay thp (=0) ti ngt

ngoi 0
Tm tt thanh ghi IP
Nu 2 ngt xy ra ng thi th ngt no c no c mc u tin cao hn

s c phc v trc.
Nu 2 ngt xy ra ng thi c cng mc u tin th th t u tin c
thc hin t cao n thp nh sau: ngt ngoi 0 timer 0 ngt ngoi 1 timer 1
cng ni tip timer 2.
Nu chng trnh ca mt ngt c mc u tin thp ang chy m c mt
ngt xy ra vi mc u tin cao hn th chng trnh ny tm dng chy mt
chng trnh khc c mc u tin cao hn.
- Cho php v cm ngt:
Mi ngun ngt c cho php hoc cm ngt qua mt thanh ghi chc nng
t bit c nh a ch bit IE (Interrupt Enable: cho php ngt) a ch A8H.
Gio vin hng dn:
XXII
Sinh vin thc hin:

Nguyn Vn Bnh
Bit
K hiu
a ch bit
M t
IE.7
EA
AFH
Cho php / Cm ton b
IE.6
AEH
Khng c m t
IE.5
ET2
ADH
Cho php ngt t Timer 2 (8052)
IE.4
ES
ACH
Cho php ngt port ni tip
IE.3
ET1
ABH
Cho php ngt t Timer 1
IE.2
EX1
AAH
Cho php ngt ngoi 1
IE.1
ET0
A9H
Cho php ngt t Timer 0
IE.0
EX0
A8H
Cho php ngt ngoi 0
Tm tt thanh ghi IE
- Cc c ngt:
Khi iu kin ngt xy ra th ng vi tng loi ngt m loi c c t
ln mc cao xc nhn ngt.
Ngt
Thanh ghi SFR v v tr bit
Bn ngoi 0
IE0
TCON.1
Bn ngoi 1
IE1
TCON.3
Timer 1
TF1
TCON.7
Timer 0
TF0
TCON.5
Port ni tip
TI
SCON.1
Port ni tip
RI
SCON.0
Cc loi c ngt
Gio vin hng dn:

XXIII
Sinh vin thc hin:

Nguyn Vn Bnh

- Cc vect ngt:
Khi chp nhn ngt, gi tr c np vo PC gi l vector ngt. N l a ch
bt u ca ISR cho ngun to ngt, cc vector ngt c cho bng sau :
Ngt
a ch vector
Reset h thng
RST
0000H
Bn ngoi 0
IE0
0003H
Timer 0
TF0
000BH
Bn ngoi 1
IE1
0013H
Timer 1
TF1
001BH
Port ni tip
TI v RI
0023H
Timer 2
002BH
Vector reset h thng (RST a ch 0000H) c trong bng ny v theo

ngha ny, n ging ngt: n ngt chng trnh chnh v np cho PC gi tr mi.
II. S LC V CM BIN NHIT LM35D

Cm bin nhit LM35D l mt mch tch hp nhn tn
hiu nhit t mi trng bn ngoi sau chuyn thnh
tn hiu in di dng dng in hay in p. Da vo c
tnh rt nhy ca cc bn dn vi nhit , to ra in p
hoc dng in t l thun vi nhit tuyt i. o tn
hiu in ta bit c gi tr ca nhit cn o. S tc
ng ca nhit to ra in tch t do v cc l trng
trong cht bn dn. Bng s ph v cc phn t, bt cc
electron thnh dng t do di chuyn qua vng cu trc mng tinh th to s xut
hin cc l trng. Lm cho t l in t t do v l trng tng ln theo quy lut hm
m vi nhit .
Gio vin hng dn:

XXIV
Sinh vin thc hin:

Nguyn Vn Bnh

Ng ra ca LM35D l dng in p thay i theo nhit bn ngoi vi
nhy 10mv/10C
Sai s cc i 1.50C khi nhit ln hn 1000C.
Phm vi s dng: 00 C t0C 1000 C
III. KHI QUT V ADC0804

1. M t chn ADC0804
Chip ADC0804 l b chuyn i tng t- s thuc
h ADC800 ca hng National Semiconductor. Chip
ny cng c nhiu hng khc sn xut. Chip c in
p nui +3V v phn gii 8 bit. Ngoi phn gii
th thi gian chuyn i cng l mt thng s quan
trng nh gi b ADC. Thi gian chuyn i l
thi gian m b ADC cn chuyn mt u vo tng
t thnh mt s nh phn. i vi ADC0804 th thi
gian chuyn i ph thuc vo tn s ng h c cp ti chn CLK R (pin 19) v
CLK IN (pin 4) v khng b hn 110s. Cc chn khc c cc chc nng:
CS (Chip select):
Chn s 1 l chn chn chip, u vo tch cc mc thp c s dng kch
hot chip ADC 0804. truy cp chip ADC th chn ny phi mc thp.
RD (Read):
Chn s 2 l mt tn hiu vo, tch cc mc thp. Cc b chuyn i u vo
tng t thnh s nh phn v gi n vo mt thanh ghi bn trong. RD c s
dng xut d liu c chuyn i ti u ra ca ADC0804.
Khi CS = 0 nu c mt xung cao xung thp p n chn RD th d liu ra dng
s 8 bit c a ti chn d liu (DB0- DB7).
WR (Write):
Gio vin hng dn:

XXV
Sinh vin thc hin:

Nguyn Vn Bnh

Chn s 3 l chn vo tch cc mc thp c dng bo cho ADC bit bt
u qu trnh chuyn i. Khi vic chuyn i hon tt th chn INTR c ADC
h xung mc thp.
Khi CS = 0 nu c mt xung t thp ln cao p n chn WR th qu trnh
chuyn i c thc hin.
CLK IN v CLK R:
CLK IN l chn vo ni ti ng h ngoi c s dng to thi gian. Tuy
nhin ADC cng c mt b to xung ng h ring. dng ng h ring th cc
chn CLK IN v CLK R c ni ti mt t in v mt in tr. Khi tn s
c xc nh bng biu thc:
f =
1
1.1RC
y R=10K, C= 150pF suy ra tn s f = 606 kHz v thi gian chuyn i

l 110s.
Ngt INTR (Interupt):
Chn s 5 l chn tch cc mc thp. Bnh thng chn ny trng thi cao v
khi vic chuyn i hon tt th n xung thp bo cho CPU bit l d kiu
chuyn i sn sng ly i. Sau khi INTR xung thp, cn t CS = 0 v gi mt
xung cao xung thp ti chn RD a d liu ra.
Vin(+) v Vin(-):
Gio vin hng dn:

XXVI
Sinh vin thc hin:

Nguyn Vn Bnh

Chn s 6 v chn s 7 y l u vo tng t vi sai, trong V in = Vin(+) Vin(-). Thng thng Vin(-) c ni vi t v Vin(+) c dng lm u vo tng
t v s c chuyn i v dng s.
Vcc:
Chn s 20 l chn ngun +5V. Chn ny cn c dng lm in p tham
chiu khi u vo Vref/2 h.
Vref/2:
Chn s 9 l chn in p u vo c dng lm in p tham chiu. Nu chn
ny h th in p u vo tng t cho ADC nm trong di 0 +5V. Chn
Vref/2 c dng thc hin cc in p u ra khc 0 +5V.
Vref/2 (V)
H
2.0
1.5
1.28
1.0
0.5
Vin(V)
0-5
0-4
0-3
0-2.56
0-2
0-1
Kch thc bc (mV)

5/256=19.53
4/256=15.62
3/256=11.71
2.56/256=10
2/256=7.81
1/256=3.90
Ch : Do tn hiu ra ca cm bin nhit (LM35D) c phn gii l 10mV,

do ta cng phi chn phn gii ca b bin i sau cho ph hp. C nhiu
cch la chn cho ph hp, mch ny ti chn phn gii ca b bin i
ADC0804 l 19.53mV. Chnh v th trc khi a d liu qua b bin i ti phi
cho qua mch khuch i vi khuch i (chn K=1.97) m bo nhit
hin th ra tng i chnh xc.
D0- D7:
D0- D7 (chn 18- 11) l cc chn ra d liu s (D7 l bit cao nht MSB v
D0 l bit thp nht LSB). Cc chn ny c m 3 trng thi v d liu c
chuyn i ch c truy cp khi chn CS = 0 v chn RD a xung mc thp.
2. T chc bn trong ADC0804
Gio vin hng dn:

XXVII
Sinh vin thc hin:

Nguyn Vn Bnh
S khi bn trong ADC0804
Gio vin hng dn:

XXVIII
Sinh vin thc hin:

Nguyn Vn Bnh
2.1. Qu trnh chuyn i ca chip ADC0804

Chip ADC0804 bt u thc hin qu trnh chuyn i khi c mt s thay
i mc logic t thp ln cao (xung cnh ln) ti chn WR, trong khi chn CS
mc thp v chn RD mc cao. Sau khi thc hin xong qu trnh chuyn i th
chn INTR c ADC0804 ko xung mc thp (mc thp l 0, mc cao l 1).
Ton b qu trnh chuyn i c m t nh sau:
Qu trnh chuyn i ca chip ADC0804
2.2. Qu trnh c d liu t chip ADC0804

Qu trnh c d liu c thc hin khi c mt s thay i mc logic t cao
xung thp (xung cnh xung) ti chn RD, trong khi chn CS mc thp v chn
WR mc cao. Qu trnh ny cng c m t bng s sau:
Gio vin hng dn:

XXIX
Sinh vin thc hin:

Nguyn Vn Bnh

Qu trnh c d liu t chip ADC0804
IV. GII THIU IC CHT 74HC374

1. M t chn IC 74HC374
IC 74HC374 l IC cht 8 bit, hot ng tch cc
mc thp.
74HC
o D0 - D7: 8 bit d liu vo

o Q0 Q7: 8 bit d liu ra
o Vcc: ngun cung cp (5V)
o
OE
: ng vo cho php, IC hot ng th
phi clear ng vo cho php ny ( OE = 0).

o CP: ng vo xung clock tc ng mc cao.
2. T chc bn trong IC74HC374
S cu to ca 74HC374
Bng trng thi ca 74HC374
Ng vo cho
Ng vo xung
Data inputs
Data outputs
php ( OE )
L
Clock (CP)
D0 D7
L
Q0 Q7
L
Q0
Gio vin hng dn:

XXX
Sinh vin thc hin:

Nguyn Vn Bnh

H
Gio vin hng dn:

XXXI
Sinh vin thc hin:

Nguyn Vn Bnh
B. NG H THI GIAN THC V B IU KHIN T

XA DNG REMOTE HNG NGOI.
I. IU KHIN T XA DNG REMOTE HNG NGOI.
1. Hng ngoi l g?
Hng ngoi l s bc x nng lng vi tn s thp hn tn s m mt ta
nhn thy. V vy chng ta khng th nhn thy, cng nh l khng th nghe c
chng, nhng chng ta c th cm nhn c sc nng ca nhng tia hng ngoi
khi chng chiu vo da.
2. Cch to ra hng ngoi

Cach tao ra hng ngoai trong in t rt dang chi cn mt in tr va 1
led phat hng ngoai la u.
V
C
A
T _ H 2 2N 0
Tuy nhin nu tao ra hng ngoai nh trn thi khoang cach truyn la rt ngn.
cai thin vn nay ngi thit k thng tao ra tn s t 3060KHz, tt nht
l khong t 3638KHz truyn tin hiu hng ngoai ra bn ngoai. to ra tn
s 36 Khz l vic kh n gin chi cn tao mt xung vung co chu k xp x 27 s
a vo cc nn ca Transistor iu khin 1 LED hng ngoi truyn i.
Gio vin hng dn:

XXXII
Sinh vin thc hin:

Nguyn Vn Bnh
3. Cach thu tin hiu hng ngoai

thu tin hiu hng ngoai ta s dung mt
TSOP1338
thu hng ngoai, tuy thuc vao muc ich s dung

ma la chon phng phap thu cho phu hp.
Vai net v mt thu hng ngoai: Mt thu
hng ngoi l 1 IC tch hp c Photodiot thu hng
ngoi, b khuych i, b lc chng nhiu, b
iu ch. Mt thu hng ngoi c nhiu hnh dng kch thc khc nhau nhng c
bn l ng trong 1 v nha en ch cho tia hng ngoi i qua, c li bn ngoi
hoc bn trong chng nhiu. Mt thu hng ngoi (TSOP1338) gm c 3 chn:
chn 3 OUT, chn 2 ngun cp in p Vs v 1 chn ni mass.
S khi bn trong mt thu hng ngoi (TSOP1338)

Mt thu hot ng tn s iu ch 36 hoc 38Khz tuy nhin c th
dng ln 2 loi ny vi nhau.
Tm thu cho php khong 10m
Khi khng c sng ti, tn hiu ra mc cao.
Gio vin hng dn:

XXXIII
Sinh vin thc hin:

Nguyn Vn Bnh
4. Kho st tn hiu hng ngoi pht ra t Remote SONY
Remote Sony s dng m ha theo rng xung, y l kiu m ho n

gin. V vy vic gii m c thc hin kh d dng.
Gin thi gian ca tn hiu remote SONY

Tn hiu sng mang t LED hng ngoi ca remote SONY pht ra c
tn s khong t 36 Khz n 38 Khz. Sng mang ny chuyn ch tn hiu d
liu c m ha c dng nh sau:
Ta thy:
Bit 0 c m ha bng mt xung mc thp 600s v chuyn trng thi
sang mc cao 600s.
Bit 1 c m ha bng mt xung mc thp 600s v chuyn trng th
sang mc cao 1200s.
Gio vin hng dn:
XXXIV
Sinh vin thc hin:

Nguyn Vn Bnh

Khi ta bm mt phm no trn remote th remote s pht i mt lot tn hiu
xung c dng nh sau:
u tin xung Start s c pht i trc v c dng l mt tn hiu mc cao

trong khong thi gian 1800s. Tip theo l cc bit d liu. Tng cng c 12 bit d
liu v kt thc bng mt xung Stop mc thp trong thi gian 1800s. Tip theo
th tn hiu s c duy tr mc thp trong khong thi gian 20ms v xung Start
th 2 s c pht i bo hiu cho s tip tc ca mt khung d liu th 2.
Khung d liu ny hon ton ging vi khung d liu trc . V c nh th tip
tc cho n khi no ta bung phm remote ra th thi.
Lu : Bit u tin sau bit START l bit LSB, ta t tn n l bit B0, bit cui
cng s l bit MSB (B11).
B0---B6 : 7 bit m lnh
B7---B11 : 5 bit a ch
Nu s dng mt nhn hng ngoi c sn trn th trng th tt c dng sng
trn s b o li nh sau:
Gio vin hng dn:

XXXV
Sinh vin thc hin:

Nguyn Vn Bnh

thu v gii m c tn hiu hng ngoi t REMOTE SONY, thc t ta
khng cn thu ton b 12 bit m ho. Ta ch cn thu 7 bit COMMAND v c th b
qua 5 bit a ch, bi vi cng mt iu khin th tt c cc nt bm u pht ra m
a ch nh nhau, ch khc nhau m lnh. M Address c hng SONY s dng
phn bit gia cc MODEL REMOTE SONY khc nhau.
II. NG H THI GIAN THC

1. Tng quan v DS1307
1.1. S chn DS1307
DS1307 l chip ng h thi gian thc (RTC : Real-time clock), khi nim
thi gian thc y c dng vi ngha thi gian tuyt i m con ngi ang
s dng, tnh bng giy, pht, giDS1307 l mt sn phm ca Dallas
Semiconductor (mt cng ty thuc Maxim Integrated Products). Chip ny c 7
thanh ghi 8-bit cha thi gian l: giy, pht, gi, th (trong tun), ngy, thng, nm.
Ngoi ra DS1307 cn c 1 thanh ghi iu khin ng ra ph v 56 thanh ghi trng c
th dng nh RAM. DS1307 c c v ghi thng qua giao din ni tip I2C nn
cu to bn ngoi rt n gin. DS1307 xut hin 2 gi SOIC v DIP c 8 chn
nh trong hnh sau.
Hai gi cu to ca chip DS1307

Cc chn ca DS1307 c m t nh sau:
- X1 v X2: l 2 ng kt ni vi 1 thch anh 32.768KHz lm ngun to dao
ng cho chip
Gio vin hng dn:
XXXVI
Sinh vin thc hin:

Nguyn Vn Bnh

- VBAT: cc dng ca mt ngun pin 3V nui chip
- GND: chn mass chung cho c pin 3V v Vcc
- Vcc: ngun cho giao din I2C, thng l 5V v dng chung vi vi iu khin.
Ch : nu Vcc khng c cp ngun nhng VBAT c cp th DS1307 vn
ang hot ng (nhng khng ghi v c c).
- SQW/OUT: y l chn to ng ra xung vung ca DS1307 c 4 ch
1Hz, 4.096HZ, 8.192Hz, 32.768Hz... cc ch ny uc quy nh bi cc bit ca
thanh ghi Control Register (a ch 0x07).
- SCL v SDA l ng gi xung nhp v ng d liu ca giao din I2C m
chng ta s tm hiu sau.
1.2. Cu to bn trong DS1307
S khi bn trong chip DS1307
Gio vin hng dn:

XXXVII
Sinh vin thc hin:

Nguyn Vn Bnh

Cu to bn trong DS1307 bao gm mt s thnh phn nh mch ngun,
mch dao ng, mch iu khin logic, mch giao in I2C, con tr a ch v cc
thanh ghi (hay RAM). Do a s cc thnh phn bn trong DS1307 l thnh phn
cng nn chng ta khng c qu nhiu vic khi s dng DS1307. S dng
DS1307 ch yu l ghi v c cc thanh ghi ca chip ny. V th cn hiu r 2 vn
c bn l cu trc cc thanh ghi v cch truy xut cc thanh ghi ny thng qua
giao din I2C
Nh trnh by, b nh DS1307 c tt c 64 thanh ghi 8bit c nh a
ch t 0 n 63 (t 0x00h n 0x3Fh). Tuy nhin, thc cht ch c 8 thanh ghi u
l dng cho chc nng ng h, cn li 56 thanh ghi b trng c th c dng
cha bin tm nh RAM nu mun. By thanh ghi u tin cha thng tin v thi
gian ca ng h bao gm: giy (SECONDS), pht (MINUETS), gi (HOURS),
th (DAY), ngy (DATE), thng (MONTH) v nm (YEAR). Vic ghi gi tr vo 7
thanh ghi ny tng ng vi vic ci t thi gian khi ng cho RTC. Vic
c gi t 7 thanh ghi l qu trnh c thi gian thc m RTC to ra.
T chc b nh trong DS1307

V 8 thanh ghi u tin l quan trng nht trong hot ng ca DS1307,
chng ta s kho st cc thanh ghi ny mt cch chi tit. Trc ht hy quan st t
chc theo tng bit ca cc thanh ghi ny trong hnh sau:
Gio vin hng dn:
XXXVIII
Sinh vin thc hin:

Nguyn Vn Bnh
Ch l tt c cc gi tr thi gian lu trong cc thanh ghi theo dng BCD

(Binary-Coded Decimal).
Thanh ghi giy (SECONDS): thanh ghi ny l thanh ghi u tin trong b
nh ca DS1307, a ch ca n l 0x00. Bn bit thp ca thanh ghi ny cha m
BCD 4-bit ca ch s hng n v ca gi tr giy. Do gi tr cao nht ca ch s
hng chc l 5 nn ch cn 3 l . Bit cao nht (bit th 7) trong thanh ghi ny l 1
bit iu khin c tn CH (Clock halt treo ng h), nu bit ny c set bng 1 b
dao ng trong chip b v hiu ha, ng h khng hot ng. V vy, nht thit
phi reset bit ny xung 0 ngay t u.
Thanh ghi pht (MINUTES): c a ch 0x01h, cha gi tr pht ca ng
h. Tng t thanh ghi SECONDS, ch c 7 bit ca thanh ghi ny c dng lu
m BCD ca pht, bit th 7 lun lun bng 0.
Thanh ghi gi (HOURS): c th ni y l thanh ghi phc tp nht trong
chip DS1307. Thanh ghi ny c a ch 0x02h. Trc ht 4 bit thp ca thanh ghi
ny c dng cho ch s hng n v ca gi. Do DS1307 h tr 2 loi h thng
hin th gi l: 12h v 24h gi, v vy bit th 6 c dng xc lp h thng gi.
Nu bit th 6 = 0 th h thng 24h c chn, khi 2 bit th 5 v th 4 dng m
ha ch s hng chc ca gi tr gi. Do gi tr ln nht ca ch s hng chc trong
trng hp ny l 2 nn cn 2 bit m ha. Nu bit th 6 = 1 th h thng 12h
c chn. Vi trng hp ny ch c 1 bit th 4 dng m ha ch s hng chc
Gio vin hng dn:

XXXIX
Sinh vin thc hin:

Nguyn Vn Bnh

ca gi, bit th 5 ch bui trong ngy (AM hoc PM). Bit th 5 = 0 l AM v bit th
5 = 1 l PM. Bit th 7 lun bng 0.
Thanh ghi th (DAY ngy trong tun): nm a ch 0x03h. Thanh ghi
DAY ch mang gi tr t 1 n 7 tng ng t Ch nht n th 7 trong 1 tun. V
th, ch c 3 bit thp trong thanh ghi ny c ngha. Cc bit cn li lun bng 0.
Thanh ghi ngy (DATE ngy trong thng): nm a ch 0x04h. Thanh
ghi DATE mang gi tr t 1 n 31, ch c 5 bit u tin l c ngha. Cc bit cn li
lun bng 0.
Thanh ghi thng (MONTH): nm a ch 0x05h. Thanh ghi MONTH
mang gi tr t 1 n 12, ch c 4 bit u tin l c ngha. Cc bit cn li bng 0.
Thanh ghi nm (YEAR): nm a ch 0x06h. Thanh ghi YEAR mang gi
tr t 0 n 99. Chip DS1307 ch dng cho 100 nm, nn gi tr nm ch c 2 ch
s, phn u ca nm do ngi dng t thm vo.
Thanh ghi iu khin (CONTROL REGISTER): c a ch l 0x07h, thanh
ghi CONTROL REGISTER c dng iu khin tn s xung vung ng ra
SQW/OUT. Gi tr cc bt trong thanh ghi CONTROL REGISTER c biu din
nh sau:
Bit 7_Output Control (OUT): dng kim sot mc logic ti SQW/OUT.

Bit 4_Square-Wave Enable (SQWE): bit ny c set ln bng 1 to dao
ng u ra.
Bits 1 and 0_ Rate Select (RS[1:0]): 2 bit ny dng iu khin tn s dao
ng ng ra SQW/OUT, vi 4 tn s c chn nh sau:
Gio vin hng dn:

XL
Sinh vin thc hin:

Nguyn Vn Bnh
2. Khi qut giao din I2C

I2C l vit tc ca t Inter - Integrated Circuit l mt chun truyn thng
ni tip ng b do hng in t Philips Semiconductor sng lp v xy dng
thnh chun nm 1990.
Cc khi nim c bn trong giao din I2C:
Master (chip ch): l chip khi ng qu trnh truyn nhn, pht i a ch
ca thit b cn giao tip v to xung gi nhp trn ng SCL.
Slave (chip t): l chip c mt a ch c nh, c gi bi Master v phc
v yu cu t Master.
SDA (Serial Data): l ng d liu ni tip, tt c cc thng tin v a ch
hay d liu u c truyn trn ng ny theo th t tng bit mt. Ch
l trong chun I2C, bit c trng s ln nht (MSB) c truyn i trc nht.
SCL (Serial Clock): l ng xung gi nhp ni tip. I2C l chun truyn
thng ni tip ng b, cn c 1 ng to xung gi nhp cho qu trnh
truyn/nhn, c mi xung trn ng gi nhp SCL, mt bit d liu trn
ng SDA s c ly mu (sample). D liu ni tip trn ng SDA
c ly mu khi ng SCL mc cao trong mt chu k gi nhp, v th
ng SDA khng c i trng thi khi SCL mc cao (tr iu kin
START v STOP). Chn SDA c th c i trng thi khi SCL mc
thp.
Mt giao tip I2C gm c 2 dy: Serial Data (SDA) v Serial Clock
(SCL). SDA l ng truyn d liu theo 2 hng (t master n slave v
ngc li), cn SCL l ng truyn xung ng h ch truyn theo mt hng
(t master n slave).
Gio vin hng dn:

XLI
Sinh vin thc hin:

Nguyn Vn Bnh

Trong mt giao din I2C th c mt thit b l ch (master) v mt thit b
l t (slave). Ti sao li c s phn bit ny? l v trn mt giao din I2C th
quyn iu khin thuc v thit b ch. Thit b ch nm vai tr to xung ng b
cho ton h thng, khi gia 2 thit b ch/t giao tip th thit b ch c nhim v
to ra xung ng b v qun l n thit b t trong sut qu trnh giao tip. Thit
b ch gi vai tr ch ng, cn thit b t gi vai tr b ng trong qu trnh giao
tip.
Mt giao din I2C c th hot ng nhiu ch khc nhau:
- Mt ch mt t (one master one slave)
- Mt ch nhiu t (one master multi slave)
- Nhiu ch nhiu t (Multi master multi slave)
Vi iu kin cn bit khi thit lp mt giao tip I2C:
- iu kin START (gi tt l S): iu kin START c thit lp khi c
mt s chuyn i trng thi t cao xung thp ti SDA, khi SCL ang mc
cao (mc cao l 1, mc thp l 0).
- iu kin STOP (gi tt l P): iu kin STOP c thit lp khi c mt
s chuyn i trng thi t thp ln cao ti SDA, khi SCL ang mc cao.
- iu kin REPEAT START (bt u lp li): khong gia iu kin
START v STOP l khong bn ca ng truyn, cc master khc khng tc
ng c vo ng truyn trong khong ny. Trng hp sau khi kt thc
qu trnh truyn/nhn m master khng gi iu kin STOP li gi thm 1 iu
kin START gi l REPEAT START. Kh nng ny thng c dng khi
master mun ly d liu lin tip t cc Slaves.
M t iu kin START, STOP v REPEAT

Gio vin hng dn:
START
XLII
Sinh vin thc hin:

Nguyn Vn Bnh

- Bit ACK: dng bo hiu d liu c nhn, bit ACK c
to ra ti thi im xung clock th 9 bng cch ko chn SDA xung mc
thp.
- Bit NACK: dng bo hiu d liu b li hoc byte truyn cui
cng, bit NACK cng c to ra ti thi im xung clock th 9 bng cch ko
chn SDA ln mc cao.
Bit ACK/NACK trong giao din I2C

nh dng d liu truyn:
D liu c truyn trn bus I2C theo tng bit, bit d liu c truyn
i ti mi sn ln ca xung ng h trn ng dy SCL, qu trnh thay i bit d
liu xy ra khi SCL ang mc thp.
Qu trnh truyn nhn 1 bit d liu

Mi byte d liu c truyn c di l 8 bit. S byte c th truyn trong
mt ln l khng hn ch. Mi byte c truyn i theo sau l mt bit ACK, bit c
trong s ln nht (MSB) s c truyn i u tin, cc bit k tip s c truyn i
ln lt. Sau 8 xung clock th d liu c truyn i, xung clock th 9 th bit
Gio vin hng dn:

XLIII
Sinh vin thc hin:

Nguyn Vn Bnh

ACK c truyn i bo hiu nhn 8 bits. Thit b truyn sau khi nhn c
bit ACK s tip tc thc hin qu trnh truyn hoc kt thc.
D liu c truyn trn giao din I2C

Mt byte truyn i c km theo bit ACK l iu kin bt buc, nhm m
bo cho qu trnh truyn nhn c chnh xc. Khi khng nhn c ng a ch
hay mun kt thc qu trnh giao tip, thit b nhn s gi mt xung Not_ACK
(NACK) bo cho thit b ch bit. Thit b ch s to ra xung STOP kt thc
hay lp li mt xung START bt u qu trnh mi.
3. Mode (ch ) truyn d liu gia DS1307 v AT89S52

Trong giao tip I2C gia DS1307 v 89S52 th chip 89S52 ng vai tr l
mt master v DS1307 ng vai tr l mt slave. Do ch c mt master v mt chip
giao tip vi nhau nn ch c 2 mode (ch ) hot ng giao tip gia 2 chip ny.
Hai mode l: Data Write (t AT89S52 n DS14307) v Data Read (t DS1307
vo AT89S52).
3.1. Mode Data Write (ch ghi d liu)

Mode Data Write (ch truyn d liu t master n slave) c dng khi
xc lp gi tr ban u cho cc thanh ghi thi gian hoc dng canh chnh thi
Gio vin hng dn:
XLIV
Sinh vin thc hin:

Nguyn Vn Bnh

gian cho chip DS1307. Cu trc truyn d liu trong mode Data Write c m t
nh hnh sau:
Ch data write
Trc ht hy ni v a ch SLA (Slave Address) ca chip DS1307
trong mng I2C, trn mng I2C mi thit b s c mt a ch ring gi l SLA.

SLA c tnh theo l thuyt chun I2C s c gi tr ti a l 128 (do c 128 thit b
trong 1 mng I2C). Chip DS1307 l mt Slave nn cng c mt a ch SLA, gi tr
ny c set c nh l 1101000b (68h). Do SLA ca DS1307 c nh nn trong 1
mng I2C s khng th tn ti cng lc 2 chip ny.
Quan st hnh trn ta thy, u tin master (AT89S52) s gi iu kin
START n Slave (DS1307), tip theo sau master s l 7 bit a ch SLA ca slave
(c nh l: 1101000b). Do ch ny l Data Write nn bit W = 0 v s c gi
km sau SLA. Bit ACK (A) c slave tr v cho master sau mi qu trnh giao
tip.
Tip theo sau a ch SLA s l 1 byte cha a ch ca thanh ghi cn
truy cp (Word Address). Cn phn bit a ch ca thanh ghi cn truy cp v a
ch SLA. Nh cp trn, a ch ca thanh ghi cn truy cp s c lu trong
thanh ghi a ch (hay con tr a ch), v vy byte d liu u tin s c cha
trong thanh ghi a ch ca DS1307.
Sau byte a ch thanh ghi l mt dy cc byte d liu c ghi vo b
nh ca DS1307. Byte d liu u tin s c ghi vo thanh ghi c a ch c
ch nh bi Word Address, sau khi ghi xong 1 byte th Word Address t ng tng
nn cc byte tip theo s c ghi lin tip vo DS1307 cc thanh ghi k sau. S
Gio vin hng dn:
XLV
Sinh vin thc hin:

Nguyn Vn Bnh

lng bytes d liu cn ghi do master quyt nh v khng c vt qu dung
lng b nh ca DS1307. Qu trnh ghi kt thc khi master pht ra iu kin
STOP.
Ch : Sau khi ghi thnh cng 1 byte th DS1307 s tr li li bng mt bit
ACK. Nu nh byte c ghi vo l byte cui cng th DS1307 s tr li li bng 1
bit Not_ACK (NACK).
Nu sau khi gi byte Word Address, master khng gi cc byte d liu m
gi lin iu kin STOP th khng c thanh ghi no c ghi. Trng hp ny c
dng set a ch Word Address phc v cho qu trnh c.
3.2. Mode Data Read (ch dc d liu)

Mode Data Read (ch truyn d liu t salve v master) c s dng khi
c thi gian thc t DS1307 v AT89S52. Cu trc truyn d liu trong mode
Data Write c m t nh hnh sau:
Ch Data Read
Nguyn tt truyn trong ch Data Read c bn cng ging nh trong
truyn ch Data Write. Trong ch Data Read bit R = 1 s c gi km sau 7
bit SLA. Sau lin tip cc byte d liu c truyn t DS1307 n AT89S52.
im khc bit trong cch b tr d liu ca ch ny so vi ch Data Write l
khng c byte a ch thanh ghi d liu no c gi n. Tt c cc byte theo sau
SLA+R u l d liu c t b nh ca DS1307.
Gio vin hng dn:

XLVI
Sinh vin thc hin:

Nguyn Vn Bnh

Lu : d liu c c ti thanh ghi c ch nh bi con tr a ch, v
vy mun c chnh xc d liu t mt a ch no , chng ta cn thc hin qu
trnh ghi gi tr cho con tr nh a ch trc khi thc hin qu trnh c. ghi
gi tr vo con tr nh a ch chng ta s gi chng trnh Data Write vi ch 1
byte c ghi sau SLA+W nh phn ch trn.
Gio vin hng dn:

XLVII
Sinh vin thc hin:

Nguyn Vn Bnh
CHNG III: THIT K PHN CNG

A. O NHIT
I. S V CHC NNG TNG KHI
1. S khi
Hin th th 1
(LED 7 on)
Bin i ADC v
Cm bin nhit
khi x ltrung tm
v khuch i
(CPU_1)
Hiu ng dng
LED n
2. Chc nng ca tng khi

2.1. Cm bin nhit v khuch i
Trong phn o nhit th y l khi to ra s thay i in th t 0V n
1.97V tng ng vi s thay i nhit bn ngoi t 00C n 1000C.
2.2. Bin i ADC v khi x l trung tm (CPU_1)

y l khi quang trng dng iu khin mi hot ng ca mch. Khi
ny thc hin qu trnh bin tn hiu tng t sang tn hiu s thng qua b bin i
ADC, sau xut d liu ny ra khi hin th th nht. Cc qu trnh ny c iu
Gio vin hng dn:

XLVIII
Sinh vin thc hin:

Nguyn Vn Bnh

khin bi vi x l AT89S52.
2.3. Khi hin th th 1 s dng LED 7 on

y l khi giao din vi ngi s dng, dng cht li d liu cho ngi
dng quan st.
2.4. Hiu ng dng LED n

y cng l khi giao din vi ngi dng, khi ny gp phn lm cho sn
phm c thit k thm p hn.
II. S CHI TIT V NGUYN TT HOT NG

1. S chi tit
1.1. Cm bin nhit v b khuch i
V
/ T O
V
U
2 A
3
2
Vout1
R F 2
1 . 5 K
I 1
L M
3 5 8
1 K
5
6
C
U
2 B
L M
Vout2
I N
3 5 8
G N D
Vin
3 5 D
L M
V S +
R F 1
4 7 0
V
1 . 5 K
4 7 0
R I 2
1 K
Thit lp thng s:
Do cm bin nhit LM35D c phn gii l 10mV/10C m phn gii
ca ADC0804 c chn l 19.53mV/10C. V vy phi thit k mt b khuch i
vi h s khuch i (K) l 1.953 (chn K = 1.97), cch chn h s K c tnh nh
sau:
+ Xt ti 2 im A v B:
Gio vin hng dn:

XLIX
Sinh vin thc hin:

Nguyn Vn Bnh

in th ti 2 im A v B c tnh nh sau:
VA = VB = Vout1.
RF 3 + RF 4
RF 1 + RF 2
= Vout1.
( R F 3 + RF 4 ) + R I
( RF 1 + RF 2 ) + RI 1
(1)
2
+ Quan st s mch ta thy:

Dng in i vo t Vout1 qua RI1 s i qua RF1, RF2 nn:
V A V A Vout 2
=
RI 1 R F 1 + R F 2
(2)
Thay gi tr ca VA vo biu thc 2 ta tm c:

Vout2 =
RF 1 + RF 2
.Vout1
RI 1
(3)
+ Vi cch tnh tng t nh vy ta c:

Vin = Vout1
(4)
T (3) v (4) ta c:
Vout2 =
RF 1 + RF 2
.Vin
RI 1
(5)
Thay cc gi tr in tr vo (5) ta c:
Vout2 =
1.5 + 0.47
.Vin
1
Vout2 =1.97.Vin
1.2. Bin i ADC v khi x l trung tm (CPU_1)
Gio vin hng dn:

Sinh vin thc hin:

Nguyn Vn Bnh
+ I N
- I N
C
1
2
5
R 1
1 0 K
p
R
f
W
1
D
9 C
C
L
L
R
W
C
2
3
1
R
C
C
1
3
4
0
U
L
L
L
L
L
D
D
D
D
D
R
R
R
R
R
R
R
R
5
6
7
8
9
13
23
33
43
53
63
73
83
1 8
D B 10 7
D B 11 6
D B 12 5
E F D/ 2 B 1 3 4
D B 14 3
K I N D B 15 2
K R D B 16 1
D B 7
I N
C
/ V
T
R
1
2
3
4
5
6
7
8
I N
R
E
F
V
4
R
2
9
8
7
6
5
4
3
2
T X RT
X T
V
S
1
1
1
2
C
T
P
P
P
P
P
P
P
P
0
0
0
0
0
0
0
0
.
.
.
.
.
.
.
.
0
1
2
3
4
5
6
7
/ PA
/ PA
/P A
/P A
/P A
/P A
/P A
/P A
P
P
P
P
P
P
P
P
1
1
1
1
1
1
1
1
.
.
.
.
.
.
.
.
1 0
0 P/ T 3 2 . 0 / 1 R 1 X D R
W
1 /P T 3 2 . - 1 E /1 XT 2 X D
2 P 3 . 2 / 1 I N3 T 0 L
3 P 3 . 3 / 1 I N4 T 1 I
L
4
P 3 . 4 1 / 5T 0
L
5
P 3 . 5 1 / 6T 1
D
6 P 3 . 6 /1 W 7
R
D
7 P 3 . 7 / R D
9
8 X
X
1
T
T
E
R
2D
2D
2D
2D
2D
2D
2D
2D
.
.
.
.
.
.
2 1
. 00 2 / A2
. 11 2 / A3
2 2 /2 A 4
3 3 /2 A 5
4 4 /2 A 6
5 5 /2 A 7
6 6 /2 A 8
77 / A
1
1
1
1
1
1
3 0
LA 1 L E / P 2 R 9
L 2 P S E N
A
A
A / V
S T
8
9
A
B
C
D
E
F
G
L D
0
1
2
3
4
5
1 1
X 1
3 Y 3 1p
C 1 52
VREF/2 h).
Chn in tr R1 v t C2 cho b dao ng ca ADC0804:
Ta c tn s dao ng c xc nh bng cng thc:
1
1.1RC
Ta chn R1 = 10k v C2 = 150pf.

Vy tn s dao ng ca ADC0904 l: f = 606khz
256
.Vin
5
Gio vin hng dn:

LI
X 2
3
Chn phn gii cho ADC0804 l 19.53mV (tng ng vi chn
S mc u ra l: N =
D
D
Thit lp thng s:
f =
f
R
Sinh vin thc hin:

Nguyn Vn Bnh
1
D
C
A
5
2
VCC
1
2
3
4
5
6
7
8
40
6
7
GND
AGND
R
R
R
R
R
R
R
R
20
GND
I N
K
9
8
7
6
5
4
3
2
10
1 13 0
R
T
I S
I S
2
3
4
R
1
2

Vin .100
vi K = 1.97 l h s ca b khuch i dng IC LM358.
K
T0 cn o =
1.3. Khi hin th th 1 s dng LED 7 on
L E
O E
4
3
2
1
0
7
6
4
2
1
9
A
B
C
D
E
1 0 F
5 G
D
10
l Pe
I S
1
1
1
1
2
3
4
7
8
3
4
7
8
1
20
D
D
D
D
D
D
D
D
0
1
2
3
4
5
6
7
Q
Q
Q
Q
Q
Q
Q
Q
2
05
16
29
31
41
51
61
7
1
2
3
4
25
56
67
9
1
1
1
1
1
9
8
2
L E
O E
4
3
2
1
0
7
6
4
2
1
9
A
B
C
D
E
1 0 F
5 G
D
Vcc
Vcc
1
1
1
1
1
9
8
Thit lp thng s:
Led 7 on c cu to gm 8 led n, thp sng 1 led 7 on th phi c
dng in chy qua mi led n ny, dng in ny phi c ln t 10mA15mA
led sng va v khng b t. Vy dng in qua led c tnh nh sau:
IL =
Vcc V L
RL
RL =
Vcc V L
IL
5V 2V
= 10mA
= 300
Chn RL = 220 IL = 13.6mA
Gio vin hng dn:

LII
l Pe
8
3
1
2
3
4
2 5
5 6
6 7
9
VCC
VCC
2
05
16
29
31
41
51
61
7
GND
Q
Q
Q
Q
Q
Q
Q
Q
10
0
1
2
3
4
5
6
7
8
3
I S
D
D
D
D
D
D
D
D
GND
3
4
7
8
74H C 374
1
1
1
1
3
4
7
8
74H C 374
A
B
C
D
E
F
G
20
Vcc
Vcc
Sinh vin thc hin:

Nguyn Vn Bnh
1.4. Hiu ng dng LED n

V
R
1
R
L D
Q 1
2 S C
L D 2
8 1 5
Q 2
2 S C
2 0
L D
Q 4
2 S C
L D 5
8 1 5
Q 7
2 S C
2 0
1 8
L D 6
1 5
Q 6
2 S C
2 2 0
V
L D 8
8 1 5
R
Q 8
2 S C
2 0
1 8
L D 9
1 5
Q 9
2 S C
2 2 0
Dng in thp sng 1 led l t 10mA 15mA, thp sng 12 led mc

song song th phi cn dng in t 120mA 180mA.
Chn dng in qua 12 led l 180mA Ic = 180mA
LIII
1 5
Thit lp thng s:
Gio vin hng dn:

1 8
1 0
1 5
1 0
R
1 8
1 5
1 0
Q 5
2 S C
2 0
1 8
L D
2 2 0
V
0
V
Q 3
2 S C
1 0
R
2 0
L D 3
1 5
1 8
1 0
R
0
V
1 0
R
2 0
Sinh vin thc hin:

Nguyn Vn Bnh

Vcc V L
Rc
M IC =
RC =
Vcc V L
5V 2.4V
= 180mA = 14.4
Ic
Chn Rc = 10
Mt khc ta c:
IB =
VB 0.7V
RB
RB =
VB 0.7V
RB
BJT hot ng trong vng bo ho th:

Ic
IB
RB
180 mA
100
1.8mA
VB 0.7V
5V 0.7V
2.39 K
RB
1.8mA
Chn RB = 2.2 K
2. Nguyn tt hot ng
Khi h thng c cp ngun (Vcc = 5V) tt c cc linh kin trong mch
bt u hot ng. u tin chip AT89S52 (CPU_1) kch hot b bin i
ADC0804, khi b bin i ny thc hin xong qu trnh bin i, CPU_1 s c
d liu t b bin i ADC0804 v hin th kt qu ra led 7 on (s dng k thut
cht). Sau CPU_1 chy chng trnh to hiu ng bn ngoi s dng led n,
khi kt thc chng trnh ny CPU_1 quay li thc hin qu trnh nh ban u.
Gio vin hng dn:

LIV
Sinh vin thc hin:

Nguyn Vn Bnh

REMOTE HNG NGOI
I. S V CHC NNG TNG KHI
1. S khi
Thi gian thc
m thanh
(DS1307)
Pht tn hiu
hng ngoi
Khi x l trung
tm (CPU_2)
Thu tn hiu
Hin th th 2
hng ngoi
2. Chc nng ca tng khi

2.1. Khi thi gian thc
Trong h thng ng h thi gian thc, khi ny gi mt vai tr rt quang
trng, khi ny quyt nh n chnh xc ca sn phm. V y l khi to thi
gian thc cho h thng.
2.2. Khi pht hng ngoi

Thit b pht s dng Remote SONY, khi n mt phm trn remote th
Remote ny s pht i mt chui d liu hng ngoi tng ng vi mi phm n.
Gio vin hng dn:

LV
Sinh vin thc hin:

Nguyn Vn Bnh
2.3. Khi thu hng ngoi.

Thit b thu hng ngoi c s dng l mt mt thu hng ngoi 3 chn c
bn sn trn th trng (TSOP1738). Mt thu hng ngoi c s dng thu li
chui d liu m remote pht ra.
2.4. Khi x l trung tm (CPU_2)

y c xem l khi quang trong nht. Chc nng l c/ghi d liu vo
chip thi gian thc (DS1307), gii m tn hiu hng ngoi c pht ra t remote
SONY. Cui cng l xut tt c cc d liu c x l ra bn ngoi thng qua
khi hin th th 2 v khi m thanh.
2.5. Khi m thanh v hin th th 2

y l 2 khi giao din cho ngi dng, dng xut d liu ra bn ngoi.
II.S CHI TIT V NGUYN TT HOT NG

1. S chi tit
1.1. Khi thi gian thc (DS1307)
3 2 . 7 6 8 K
YZ
1
2
X 1
X 2 D
S C
1 3 0S 7 D
T 1
V
V
B
C
1 0 4
/ O
C
D
L
A
T
R 9
1 0 0
A T
C
4
3
8
S
S
G N D
6
L 5
A
3 V
Thit lp thng s:
Dng in chy qua 4 led l:
I=
Vcc VL
5V 2V
=
= 30mA
100
R9
Gio vin hng dn:

LVI
Sinh vin thc hin:

Nguyn Vn Bnh

Do 4 led c mc song song vi nhau nn dng in chy qua mi led l
nh nhau:
I1 = I2 = I3 = I4 = I/4 = 30mA/4 = 7.5mA
Ch : do ng ra SCL v SDA c cu to dng cc thu h (ging nh
port_0 ca vi iu khin) nn cn phi c in tr ko ln (chn R = 10 K ).
1.2. Khi thu hng ngoi

S kt ni mt thu hng ngoi TSOP1738 nh sau:
V C
V C
1 9
R
2 0
2 2 0
C
1 5
1 0 K
V s
1 0 u f
1
V O
S I G
A L
D
T S O
P 1 7 3 8
1.3. Khi x l trung tm (CPU_2)

C CC 1 1
A
B
C
D
E
F
G
1
2
3
4
5
6
7
8
1
2
3
4
5
6
1 2
R N 41 1
1 0
1 0 K 9
8
7
8
9
1
1
1
1
1
7
56
5
2 2 0 4
3
2
1
R
0
1
2
3
4
4
A
1 0 1 5
R
1 9
1 8
8 V
V C
T 2
9
8
7
6
5
4
3
2
1
2
3
4
5
6
7
8
X L 1
X L 2
R
3
3
3
3
3
3
3
3
3 1
9
A
A
A
A
A
A
A
A
DP
DP
PD
PD
PD
PD
PD
PD
02
12
22
23
24
25
26
27
.
.
2
3
4
5
6
7
1
82
93
0
0
0
0
0
0
0
0
.
.
.
.
.
.
.
.
0
1
2
3
4
5
6
7
P
P
P
P
P
P
P
P
1
1
1
1
1
1
1
1
.
.
.
.
.
.
.
.
1 0
0 / T P2 3 . 0 / R 1X 1D
1 / T P2 - 3 E . 1X / T 1X 2D
2
P 3 . 2 / I N 1 T3 0
3
P 3 . 3 / I N 1 T4 1
4
P 3 . 4 / T1 05
5
P 3 . 5 / T1 16
6
P 3 . 6 / W 1 R7
7
P 3 . 7 / R D
X T A
X T A
E
R
/
/
/
/
/
/
/
/
2
0 / A2
1 / A2
/ A 21
/ A 21
/ A 21
/ A 21
/ A 21
/ A 1
P
P
P
P
P
P
P
P
V C C
A
B
C
D
E
F
G
V
V
V
V
V
V
V
V
L
A
3
4
5
6
7
8
.
.
.
.
.
.
40
51
62
73
84
5
A T 89S 52
C
D
is
is
is
is
is
is
1 0 4
L 1A
L 2
A / V
S T
G N D
S
S
d
d
d
d
d
d
40
L E
P
1
2
3
4
5
6
7
8
1
2
3
4
5
1
1
R N 31
1
1 0 K 1
1
1
9
6
5
4
3
2
1
0
1 0
69
8
1 0 K 7
6
R
1 3
L E
L E
R 1 0
2 2 0
1 7
1 22 2 0
1 0 u f
R
6
Q
C
E A K E
L L
N A L
9
1 8
1 9
2 0
2 1
1 3
3 3 p
1 4
1 0 K
6
1 8 1 5
1 0 K
Gio vin hng dn:

LVII
1 8
1 0 K
0
1
2
3
4
5
6
7
1 2
3 3 p
1
2
3
4
5
6
7
8
L L
1
1
1
1
1
1
1
1
1 4
V
V
V
V
V
V
V
V
s
s
s
s
s
s
s
s
X L 2
9
8
7
6
5
4
3
2
P
E
I G
is
is
is
is
is
Y 3
1 2 M
2 2 0
D
S
B
S
d
d
d
d
d
X L 1
20
i
i
i
i
i
i
i
i
3 0
/ P R 2O 9 G
S E N
1 0 K
C
d
d
d
d
d
d
d
d
Sinh vin thc hin:

Nguyn Vn Bnh
T 2
1.4. Khi m thanh
C
L
R
1
1
2
R 1 4
0 1 5
4 1A 0
K
V
GND
. 7
T
K
IC UM66 l IC nhc c s dng rt nhiu, bi v UM66 d s dng, r

tin v ting nhc pht ra cng kh hay. UM66 thng c s dng trong cc ng
h bo thc hay l cc thit b chi in t. S khi ca UM66 c m t
nh hnh sau:
1.5. Khi hin th th 2
Gio vin hng dn:

LVIII
S P E A K E
Q 4
2 S C 1 8 1 5
Sinh vin thc hin:

Nguyn Vn Bnh
0 C
1
E
1
02
13
24
35
46
57
6
7
1
1
1
1
1
9
8
2
5
6
9
7
6
4
2
1
9
4
3
3A
4
2B
7
C1
8
D0
1
E
1
1 F0
1
G
5
1
D l e P d
d i s
2 0
1
1
V
L
O
3
4
7
8
1
VCC
VV cc cc
10
Gio vin hng dn:

1
D
D
D
D3
D4
D7
D8
D7
L
O
1
E
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
E
1
02
13
24
35
46
57
6
7
N
1
1
1
1
1
9
8
2
5
6
9
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
4
3
3A
4
B2
7
C1
8
D0
1
E
1
1 F0
1
G
5
1
D l e P d
d i s
2 0
1
1
2
5
6
9
1
1
1
1
6
1
02
13
24
35
46
57
6
7
1
1
1
1
1
9
8
2
5
6
9
2
7
6
4
2
1
9
4
3
3A
4
2B
7
C1
8
D0
1
E
1
1 F0
1
G
5
1
D l e P d
d i s
2 0
1
1
L
O
0 C
3
4
7
8
1
0 C
L
O
3
4
7
8
1
2
E
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1
02
13
24
35
46
57
6
7
N
1
1
1
1
1
9
8
2
5
6
9
2
5
6
9
1
1
1
1
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
7
C
3 R
2
5
6
9
1
1
1
1
VCC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1 3
1
L E
O
E
1
20
31
42
53
64
75
6
7
N
1
1
1
1
1
9
8
2
5
6
9
2
1
02
13
24
35
46
57
6
7
1
1
1
1
1
9
8
4
3
3A
4
B2
7
C1
8
D0
1
E
1
1 F0
1
G
5
1
D l e P d
d i s
2 0
1
1
2
5
6
9
2
4
3A
2B
1C
0D
E
1 F0
5 G
D l e P d
2 0
0 C
D
D
D
D
D
D
D
D7
L
O
3
4
7
8
1
2
E
VV cc cc
83
DE
1 R
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1
E
2
5
6
9
1
1
1
1
1
20
31
42
53
64
75
6
7
N
1
1
1
1
1
9
8
2
5
6
9
2
4
3A
2B
1C
0D
E
1 F0
5 G
D l e P d
2 0
7
6
4
2
1
9
1
7
6
4
2
1
9
7
6
4
2
1
9
20
7 R
0 R
2
5
6
9
1
1
1
1
4
3A
2B
1C
0D
E
1 F0
5 G
D l e P d
7
IS P I S 7 T O
GND
C
1
7
6
4
2
1
9
4
3A
2B
1C
0D
E
1 F0
5 G
D l e P d
2 0
7
6
4
2
1
9
1
D
D
D
D
D
D
D
D7
1
1
1
1
1
9
8
10
D
D
D
D3
D4
D7
D8
D7
0 C
2
D
D
D
D
D
D
D
D7
VCC
VV cc cc
83
0 C
0
C
LIX
7
6
4
2
1
9
4
3
3A
4
2B
7
1C
8
D0
1
E
1
1 F0
1
G
5
1
D l e P d
d i s
2 0
1
1
V
1
20
31
42
53 2
64 5
75 6
69
7
VV cc cc
2
5
6
9
1
1
1
1
38
7
6
4
2
1
9
6 R
9 R
2
5
6
9
1
1
1
1
VV cc cc
GND
1
1
1
1
1
9
8
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
8
O1 R
L E
O
E
10
L
O
1
20
31
42
53 2
64 5
75 6
69
7
20
20
VCC
GND
10
38
1
D
D
D
D
D
D
D
D7
0 C
VV cc cc
4
3
3A
4
B2
7
C1
8
D0
1
E
1
1 F0
1
G
5
1
D l e P d
d i s
2 0
1
1
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
1
1
1
1
74H C 374
7
6
4
2
1
9
2 R
0
C
D
D
D
D3
D4
D7
D8
D7
VV cc cc
20
D
D
D
D3
D4
D7
D8
D7
0 C
74H C 374
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1
1
1
1
1
9
8
VV cc cc
VCC
VV cc cc
4
3
3A
4
B2
7
1C
8
0D
1
E
1
1 F0
1
G
5
1
D l e P d
d i s
S I S T1
1
83
GND
1
20
31
42
53 2
64 5
75 6
69
7
83
VCC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
1
1
1
1
74H C 374
GND
5 R
8 R
2
5
6
9
1
1
1
1
7
6
4
2
1
9
10
74H C 374
7
6
4
2
1
9
VV cc cc
L
O
20
4
3
3A
4
2B
7
1C
8
D0
1
E
1
1 F0
1
G
5
1
D l e P d
d i s
2 0
1
1
0
C
38
D
D
D
D3
D4
D7
D8
D7
83
10
VCC
3
4 D
7 D
8 D
1 D3
1 D4
1 D7
1 D8
D
i s 1
1 1
1 L
O
2
5
6
9
83
1
1
1
1
1
9
8
VV cc cc
GND
4
3
3A
4
2B
7
C1
8
D0
1
E
1
1 F0
1
G
5
1
D l e P d
d i s
2 0
1
1
VV cc cc
7
6
4
2
1
9
10
20
1
20
31
42
53
64
75
6
7
2
5
6
9
74H C 374
1
1
1
1
1
9
8
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
1
1
1
1
74H C 374
1
20
31
42
53 2
64 5
75 6
69
7
74H C 374
74H C 374
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
1
1
1
1
38
83
1
1
1
1
1
9
8
83
20
4 R
1
20
31
42
53
64
75
6
7
20
L
O
0 C
VCC
20
GND
0 C
VCC
D
D
D
D3
D4
D7
D8
D7
0
V
2
5
6
9
1
1
1
1
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
GND
4
3
3A
4
2B
7
1C
8
D0
1
E
1
1 F0
1
G
5
1
D l e P d
d i s
2 0
1
1
V
1 R
20
L
O
3
4
7
8
VCC
VV cc cc
3
4 D
7 D
8 D
1 D3
1 D4
1 D7
1 D8
D
i s 1
1 1
1 L
O
GND
VV cc cc
83
7
6
4
2
1
9
VV cc cc
D
D
D
D
D
D
D
D7
20
VCC
0 C
2
5
6
9
10
VV cc cc
N
1
1
1
1
1
9
8
GND
1
20
31
42
53
64
75
6
7
4
3
3A
4
B2
7
1C
8
0D
1
E
1
1 F0
1
G
5
1
D l e P d
d i s
2 0
1
1
10
L
O
3
4
7
8
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
1
1
1
1
7
6
4
2
1
9
20
0 R
38
D
D
D
D
D
D
D
D7
VV cc cc
1
20
4
3
3A
4
2B
7
1C
8
D0
1
E
1
1 F0
1
G
5
1
D l e P d
d i s
2 0
1
1
83
VCC
GND
7
6
4
2
1
9
10
2
5
6
9
2
5
6
9
74H C 374
1
1
1
1
1
9
8
1
1
1
1
1
9
8
74H C 374
1
02
13
24
35
46
57
6
7
74H C 374
74H C 374
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
1
1
1
1
VCC
GND
74H C 374
3
4 D
7 D
8 D
1 D3
1 D4
1 D7
1 D8
D
i s 9
1 1
1 L
O
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1
02
13
24
35
46
57
6
7
10
20
3
4
7
8
2
5
6
9
1
1
1
1
83
3
4 D
7 D
8 D
1 D
1 D
1 D
1 D
D7
i s
1
1 L
O
GND
4
3A
2B
1C
0D
E
1 F0
5 G
D l e P d
d
10
7
6
4
2
1
9
20
VCC
0 C
GND
10
2
5
6
9
10
20
VCC
L
O
1
1
1
1
1
9
8
VCC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1
02
13
24
35
46
57
6
7
GND
D
D
D
D3
D4
D7
D8
D7
2
5
6
9
1
1
1
1
10
4
3
3A
4
B2
7
1C
8
0D
1
E
1
1 F0
1
G
5
1
D l e P d
d i s
2 0
1
1
20
0 C
7
6
4
2
1
9
VCC
GND
10
L
O
1
1
1
1
1
9
8
83
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1
20
31
42
53 2
64 5
75 6
69
7
GND
VV cc cc
2
5
6
9
1
1
1
1
10
D
D
D
D3
D4
D7
D8
D7
38
VCC
4
3
3A
4
B2
7
1C
8
0D
1
E
1
1 F0
1
G
5
1
D l e P d
d i s
2 0
1
1
10
GND
7
6
4
2
1
9
74H C 374
2
5
6
9
74H C 374
1
1
1
1
1
9
8
74H C 374
1
20
31
42
53
64
75
6
7
74H C 374
3
4
7
8
2
5
6
9
1
1
1
1
74H C 374
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
74H C 374
A
B
C
D
E
F
G
3
A
4 D
B
7 D
C
8 D
D
1 D
E
1 D
F
1 D
G
1 D
D
d i s
1
1 L
O
VV cc cc
83
20
VCC
20
GND
10
Sinh vin thc hin:

Nguyn Vn Bnh
2. Nguyn tt hot ng
Khi h thng c cp ngun chip AT89S52 (CPU_2) bt u c thi gian
thc RTC. Khi thi gian c c, CPU_2 tin hnh x l (kim tra xem thi
gian va c c trng vi thi gian bo thc hay khng? Nu trng th CPU_2 kch
hot h thng m thanh v ngc lai). Khi thc hin xong qu trnh x l kt qu,
CPU_2 xut d liu ra led 7 on. Sau CPU_2 quay v thc hin qu trnh nh
ban u. Trong trng hp CPU_2 nhn c tn hiu truyn v t mt thu hng
ngoi, CPU_2 tm ngng hot ng tt c cc chng trnh phc v chng
trnh ngt, CPU_2 bt u gii m tn hiu hng ngoi c pht ra t remote
SONY. Khi gii m xong CPU_2 gi chng trnh to hiu ng khi iu chnh,
cui cng d liu c CPU_2 ghi vo RTC v thot khi chng trnh ngt.
Gio vin hng dn:

LX
Sinh vin thc hin:

Nguyn Vn Bnh
CHNG III: THIT K PHN MM

vit mt chong trnh c nhiu cch v d nh vit mt mch t trn
xung di theo phng php ny CPU s c tng t theo cc ch th trong
chng trnh t i ch thp n a ch cao v thc hin chng cho n a ch cui
cng. Trong trng hp ny ngi c rt d theo di chng trnh v nm c
ca ngi vit, tuy nhin n c nhc im l kch thc chng trnh ln. Gii
hn cu phng php lp trnh tun t lm pht sinh mt phng php lp trnh
khc l lp trnh cu trc. Trong chng trnh ny vi nhng on thng xuyn lp
li trong chng trnh ngi ta em chng ra khi chng trnh chnh (gi l
chng trnh con) chng c th c t u hoc cui chng trnh chnh (tu
theo phn mm). Ti mt a ch xc nh ni chng ta em i c thay bng lnh
LCALL xxxx. Trong xxxx l i ch chng ta t chng trnh con. Khi gp ch
th ny CPU s nhy n ch th c t sau ch th LCALL v thi hnh on
chng trnh . qu trnh lm vic khng b gin on cui on chng
trnh ta t ch th RET (Return). Khi gp ch th ny CPU s quay v chng trnh
chnh v tip tc cng vic b b d. Phng php ny kh hiu qu trong vic gim
kch thc chng trnh. Tuy nhin n lm cho ngi s dng kh theo di chng
trnh do mt tnh lin tc. khc phc nhc im ny ngi ta t cho mi on
chng trnh nh th mt ci tn hay nhn (label). Tn t phi gip ngi c hnh
dung c chc nng ca chng trnh con, nh rng on chng trnh con c tc
dng dng chng trnh chnh trong mt khong thi gian t no . Chng ta cng
qui nh on chng trnh con l ni chng trnh chnh t d liu x l cng
nh ni chng trnh chnh s ly kt qu v bng cch ny ngi c ch cn nh
chng trnh c gi s lm cng vic g v ni t (lu) d liu c lin quan.
Phn mm phc v cho h thng ca ti cng c thit k da trn
quan im ny. vit chng trnh iu khin h thng c th dng mt trong cc
ngn ng nh Assembler, passcal, C. y ti vit chng trnh bng ngn ng
assembler (ASM) ca h thng 8 bit dng chip AT89S52.
Gio vin hng dn:

LXI
Sinh vin thc hin:

Nguyn Vn Bnh
A. O NHIT
I. LU V GII THUT CHNG TRNH
1. Gii thut
1.1. Gii thut chng trnh chnh
Bc 1:Truy xut d liu t b bin i ADC
Bc 2: Hin th kt qu
Bc 3: To hiu ng cho led n, sau quay li bc 1
1.2. Gii thut chng trnh con TRUY_CAP_ADC

To mt xung t thp ln cao p n chn WR ADC0804 bt u qu
trnh chuyn i.
Ch cho qu trnh bin i c thc hin xong (chn INTR xung mc
thp).
To mt xung t cao xung thp p n chn RD c d liu ra t
chip ADC0804.
a liu vo thanh ghi R0 v thot khi chng trnh.
2. Lu
2.1. Lu chng trnh chnh
Gio vin hng dn:

LXII
Sinh vin thc hin:

Nguyn Vn Bnh

BEGIN
Khi to gi tr
ban u
Truy cp vo chip
ADC0804
Hin th nhit ra
led 7 on
Hiu ng th 1
(dng led n)
Hiu ng th 2
(dng led n)
END
2.2. Lu chng trnh con

2.2.1. Lu chng trnh con TRUY_CAP_ADC
Gio vin hng dn:

LXIII
Sinh vin thc hin:

Nguyn Vn Bnh

START
Kch hot b bin i

ADC0804
Ch qu trnh bin i
hon thnh
INTR = = 0?
Y
c d liu t chip
ADC0804
Da d liu
vo thanh ghi R0
RET
2.2.2. Lu chng trnh con HIENTHI_1
STAR
TT
Thit lp gi tr
A = R0, B = 10
P_D
Ly A chia B
P_Nguyn
Xut ra led th 2
Xut ra led th 1
RET
Gio vin hng dn:
LXIV
Sinh vin thc hin:

Nguyn Vn Bnh
II. PHN MM DO NHIT (CODE_1)

Phn mm o nhit (Code_1) c lp trnh bng ngn ng Assembler
(ASM), son tho v bin dch bng chng trnh Keil Version. Ni dung Code_1
nm th mc ph lc trang 76.
Gio vin hng dn:

LXV
Sinh vin thc hin:

Nguyn Vn Bnh
B. NG H THI GIAN THC V B IU KHIN T

XA DNG REMOTE HNG NGOI.
I. LU V GII THUT CHNG TRNH
1. Gii thut
1.1. Gii thut chng trnh chnh
Bc 1: c thi gian thc t RTC (chip DS1307)
Bc 2: Hin th thi gian va c ra led 7 on
Bc 3: Kim tra thi gian bo thc
Bc 4: Kim tra ch chung bo theo tng gi
Bc 5: To hiu ng chnh khi ci t gi, sau quay li bc 1.
1.2. Gii thut chng trnh ngt GIAI_MA_REMOTE_SONY

Bc 1: Thit lp gi tr thanh ghi A = 01000000B (40h)
Bc 2: Ch cho tn hiu ln
(y l bit m lnh u tin)
Bc 3: Ch tn hiu i xung
Bc 4: Ch khong 900 s
Bc 5: o mc tn hiu
Bc 6: Nu mc tn hiu l mc cao th bit nhn c l bit 0
- Thit lp bit nh C = 0 (bit m lnh thu c)
- Quay phi c nh A, nh vy C s c gi vo MSB ca A, LSB ca A
gi vo C.
- Ban u, A = 01000000B th sau khi quay ta c C = 0 v MSB ca A l
bit u tin ca m lnh.
- Nh vy sau 7 ln quay th C = 1 v 7 bit bn tri ca A s cha m lnh
- Kim tra bit nh C, nu C = 1 nhy ti bc 8, nu C = 0 quay li bc 3
Bc 7: Nu mc tn hiu l mc thp th bit nhn c l bit 1
Gio vin hng dn:

LXVI
Sinh vin thc hin:

Nguyn Vn Bnh

- Thit lp Bit nh C = 1 (bit m lnh thu c)
- Quay phi c nh A
- Kim tra bit nh C, nu C = 1 nhy ti bc 8, nu C = 0 quay li bc 2
Bc 8: Lc ny 7 bit m lnh cha trong 7 bit bn tri ca thanh ghi A :
A = D6D5D4D3D2D1D00
Quay phi thanh ghi A thu c 7 bit m lnh nm bn phi thanh ghi A
A = 0D6D5D4D3D2D1D0
To tr di chng nhiu (chn 0.1s)
Bc 9: Nhn dng cc phm c n:
- Nu phm c n l KEY_ON_OFF th m ch iu chnh ngc li
th nhy n bc 10.
- Nu phm c n l KEY_NEXT hoc KEY_BACK th tng hoc gim
thanh ghi R0 mt n v cho mi ln n. K tip gi chng trnh to ra
hiu ng iu chnh tng ng, sau nhy n bc 10.
- Nu phm c n l cc s th chng trnh x l s c gi
chuyn cc s c n vo bin c la chn trn, ghi gi tr ny vo
RTC. Sau c v hin th cc gi tr ra ngoi, cui cng nhy n bc
10.
- Nu phm c n l KEY_ON_BELL / KEY_OFF_BELL th tng ng
vi vic m/tt chung theo tng gi, sau nhy n bc 10.
Bc 10: To tr 0.1s v thot khi ngt
1.3. Gii thut chng trnh con WRITE_CLOCK

Gi iu kin START n RTC
Gi tip a ch Slave + W (0D0h)
Gi a ch thanh ghi u tin c chn ghi (00h: a ch thanh ghi
SECOND)
Ghi tt c cc byte d liu vo RTC nh: giy, pht, gi, th, ngy, thng,
nm, gi tr thanh ghi control v cui cng l thi gian bo thc
Gio vin hng dn:
LXVII
Sinh vin thc hin:

Nguyn Vn Bnh

Gi iu kin STOP v thot.
Ch : Nu khng phi l ln ghi/c cui cng th ko bin LAST
xung mc thp gi bit ACK, ngc li a bin LAST ln cao gi bit
Not_ACK (NACK).
1.4. Gii thut chng trnh con READ_CLOCK

Gi iu kin START n RTC
Gi tip a ch Slave + W (0D0h).
Gi a ch thanh ghi u tin c chn ghi (00h: a ch thanh ghi
SECOND).
Gi iu kin STOP.
Gi li iu kin START.
Gi a ch Slave + R (0D1h).
Bt u c ln lt tng byte d liu t RTC. u tin l giy, pht, gi,
th, ngy, thng, nm, gi tr thanh ghi control v cui cng l thi gian bo
thc
Gi iu kin STOP v thot.
2. Lu
2.1. Lu chng trnh chnh
Gio vin hng dn:

LXVIII
Sinh vin thc hin:

Nguyn Vn Bnh

BEGIN
Khi to gi tr
ban u
c thi gian
thc t RTC
Hin th thi gian

ra led 7 on
Thi gian bo
thc
M/tt chung
theo tng gi
To hiu ng khi
iu chnh
END
2.2. Lu chng trnh ngt GIAI_MA_REMOTE_SONY
Gio vin hng dn:

LXIX
Sinh vin thc hin:

Nguyn Vn Bnh

START
Gn gi tr
A = 01000000h
Ch tn hiu ln
mc cao
Ch tn hiu xung
mc thp
To tr 900 s
o mc tn hiu
Tn hiu
mc thp
t c nh C=1
t c nh C=0
Quay phi c nh A
Quay phi c nh A
N
C=1
C=1
Y
Quay phi A
TIEP
Gio vin hng dn:
LXX
Sinh vin thc hin:

Nguyn Vn Bnh

TIEP
Y
A = = KEY_ON_OFFF
N
A = = KEY_NEXT
Y
hoc
A = = KEY_BACK
N
Hiu ng
iu chnh
N
A = = KEY_1,
KEY_2..
X l s
N
Write
clock
Read
A = = KEY_0N_BELL
hoc KEY_OFF_BELL
clock
Hin
th_2
Tt/m
chung
To tr 0.1s
RETI
Gio vin hng dn:
LXXI
Sinh vin thc hin:

Nguyn Vn Bnh
2.3. Lu chng trnh con

2.3.1. Lu chng trnh con WRITE_CLOCK
BEGIN
Gi iu kin
START
Gi a ch
Slave+W (0D0h)
Gi 1 byte a ch
con tr (00h)
Ghi tt c byte d liu

nh: giy, pht,....,thi
gian bo thc vo RTC
Gi iu kin
STOP
RET
Gio vin hng dn:

LXXII
Sinh vin thc hin:

Nguyn Vn Bnh
2.3.2. Lu chng trnh con READ_CLOCK

BEGIN
Gi iu kin
START
Gi a ch
Slave+W (0D0h)
Gi 1 byte a ch
con tr (00h)
Gi iu kin
STOP
Gi iu kin
START
Gi a ch
Slave+R (0D1h)
c tt c byte d liu
nh: giy, pht,....,thi
gian bo thc t RTC
Gi iu kin
STOP
RET
Gio vin hng dn:
LXXIII
Sinh vin thc hin:

Nguyn Vn Bnh
2.3.3. Lu chng trnh con ghi 1 byte vo DS1307SEND_BYTE

BEGIN
Gn gi tr
BITCOUNT = 08
ACC.7 = = 0
Y
SDA = 0
SDA = 1
To mt xung nhip
ti chn SCL
Quay tri thanh ghi

A
BITCOUNT = =
0
Y
N
LAST = = 0
Y
Gi bit ACK
Gi bit NACK
RET
Gio vin hng dn:
LXXIV
Sinh vin thc hin:

Nguyn Vn Bnh
2.3.4. Lu chng trnh con c 1 byte t DS1307READ_BYTE

BEGIN
Gn gi tr: A = 00
BITCOUNT = 08
To mt xung nhip
ti chn SCL
a d liu t SDA
vo c C
Quay tri thanh ghi A

c c nh C
BITCOUNT = = 0
Y
N
LAST = = 0
Gi bit ACK
Gi bit NACK
RET
Gio vin hng dn:
LXXV
Sinh vin thc hin:

Nguyn Vn Bnh
2.3.5. Lu chng trnh con ALARM_CLOCK_TEST

BEGIN
HOUR = = ALK_HOUR
Y
N
MINUTE = =
ALK_MINUTE
Y
Kch hot h thng
m thanh
MINUTE = =
ALK_MINUTE
N
c thi gian thc
t RTC
Hin th
ra led 7 on
Dng kch hot

h thng m thanh
RET
Gio vin hng dn:
LXXVI
Sinh vin thc hin:

Nguyn Vn Bnh
2.3.6. Lu chng trnh con TAT_MO_CHUONG

BEGIN
R3 = = 0FFH
Y
N
MINUTE = = 0
Y
SECOND = = 0
Y
Kch hot h thng
m thanh
Y
To tr
khong 0.5s
Dng kch hot

h thng m thanh
RET
Gio vin hng dn:
LXXVII
Sinh vin thc hin:

Nguyn Vn Bnh
2.3.7. Lu chng trnh con HIEU_UNG_CHINH

BEGIN
R0 = = 20H
Y
To hiu ng chnh gi
R0 = = 21H
Y
To hiu ng chnh pht
R0 = = 22H
Y
To hiu ng chnh giy
R0 = = 27H
Y
To hiu ng chnh gi bo thc
R0 = = 28H
Y
To hiu ng iu pht bo thc
RET
Gio vin hng dn:

LXXVIII
Sinh vin thc hin:

Nguyn Vn Bnh
2.3.8. Lu chng trnh con HIENTHI_2

BEGIN
a ni dung bin HOUR vo

thanh ghi A
Tch s BCD
Xut ra led 7 on
a ni dung bin MINUTE vo
thanh ghi A
Tch s BCD
Xut ra led 7 on
a ni dung bin
ALK_MINUTE vo thanh ghi A
Tch s BCD
Xut ra led 7 on
RET
Gio vin hng dn:
LXXIX
Sinh vin thc hin:

Nguyn Vn Bnh
II. PHN MM NG H THI GIAN THC V B IU KHIN

T XA DNG REMOTE HNG NGOI (CODE_2)
Phn mm ng h thi gian thc v b iu khin t xa dng remote hng
ngoi (Code_2) cng c lp trnh bng ngn ng Assembler (ASM), son tho v
bin dch bng chng trnh Keil Version. Ni dung Code_2 nm th mc ph
lc trang 80.
Gio vin hng dn:

LXXX
Sinh vin thc hin:

Nguyn Vn Bnh
CHNG IV: KT LUN V NGH

I. KT LUN
Sau mt thi gian nghin cu v tm hiu v ti ny. Cng vi s ch dn
tn tnh ca cc Thy Lng Vinh Quc Danh. n nay em thit k thnh cng
Lch Vn Nin in T , mch hot ng rt n nh v p ng c yu cu
ca ti t ra. Do thi gian v nng lc gii hn nn sn phm c thit k
khng th trnh khi mt s khuyt im: sn phm hi th, khng c p
knh mong qu thy c v cc bn thng cm.
Sau y l mt s hnh nh ca Lch Vn Nin in T:
Modul hin th
Gio vin hng dn:

LXXXI
Sinh vin thc hin:

Nguyn Vn Bnh
Modul hiu ng dng led n
Modul x l trung tm
Gio vin hng dn:

LXXXII
Sinh vin thc hin:

Nguyn Vn Bnh
Lch Vn Nin in T
Gio vin hng dn:
LXXXIII
Sinh vin thc hin:

Nguyn Vn Bnh
II. NGH
Sau khi thit k thnh cng ti ny, em c mt s ngh khc phc
nhng khuyt im m em mc phi.
Thay i IC cht 74HC374 bng IC ghi dch v cht 74LS595. Bng cch
ny s l gim bt qu trnh phc tp khi thit k phn cng, gp phn lm cho sn
phm gn nh hn.
Thit k thm b chuyn i t ngy dng lch sang ngy m lch.
Thay i ting chung bo thc bng mt bi nhc m bn yu thch.
Gio vin hng dn:

LXXXIV
Sinh vin thc hin:

Nguyn Vn Bnh
TI LIU THAM KHO

[1] Gio trnh Vi iu Khin _ Tc gi Th.Phm Hng Kim Khnh
[2] Ti liu hng dn Thc Tp Vi iu Khin _ Bin son Th.Trn Nht Khi
Hon, KS.Trn Hu Danh.
[3] Gio trnh MCH XUNG _ Bin son Th.Lng Vn Sn, KS.Nguyn
Khc Nguyn.
[4] Gio trnh MCH S _ Tc gi Th.Nguyn Trung Lp.
[5] Gio trnh MCH TNG T _ Tc gi KS. Trng Vn Tm
[6] http://alldatasheet.com/
[7] http://www.dientuvienthong.net/diendan/index.php
[8] http://www.dientuvietnam.net/forums/
Gio vin hng dn:

LXXXV
Sinh vin thc hin:

Nguyn Vn Bnh
PH LC
1. Phn mm o nhit (CODE_1)
RDL
WRL
INT
LED1
LED2
LED3
LED4
BIT P3.0
BIT P3.1
BIT P3.3
BIT P2.7
BIT P3.2
BIT P3.4
BIT P3.5
ORG
LJMP
0000H
MAIN
MAIN:
MOV P0,#00H
MOV
P2,#00H
CLR
LED1
CLR
LED2
CLR
LED3
CLR
LED4
MOV
DPTR,#LED7S
MOV
R0,#00H
MOV
R7,#05
SETB
RDL
SETB
WRL
HERE:
CALL
TRUY_CAP_ADC
CALL
HIENTHI
CALL
HIEU_UNG_1
CALL
TRUY_CAP_ADC
CALL
HIENTHI
CALL
HIEU_UNG_2
JMP
HERE
;------------------------------------------------------------------------------------;--------Truy nhap vao chip ADC0804-------TRUY_CAP_ADC:
CLR
WRL
SETB
WRL
;Tao xung canh len tai chan WR
;de bat dau qua trinh bien doi
JB
INT,$
;Cho qua trinh bien doi hoan thanh
Gio vin hng dn:
LXXXVI
Sinh vin thc hin:

Nguyn Vn Bnh

SETB
CLR
RDL
RDL
CALL
MOV
SETB
RET
DELAY
R0,P1
RDL
;Tao xung canh xuong tai chan

;RD de doc du lieu
;Dua du lieu vao thanh ghi R0
;------Hien thi nhiet do ra led 7 doan-----HIENTHI:

MOV
A,R0
MOV
B,#10
DIVAB
;Chia Gia tri thanh ghi A cho 10,
;phan nguyen luu trong A, du luu trong B
CALL
READ
CLR
P3.7
SETB
P3.7
;Tao xung canh len de xuat du lieu
CALL
DELAY_6us
MOV
CALL
CLR
SETB
CALL
RET
A,B
READ
P3.6
P3.6
DELAY_6us
;------Hieu ung thu 1 cho led doan-----HIEU_UNG_1:

LOOP1:
SETB
LED1
CLR
LED2
CLR
LED3
SETB
LED4
MOV
P0,#04H
CALL
DELAY
CALL
DELAY
CLR
LED1
SETB
LED2
CLR
LED3
CLR
LED4
MOV
P0,#09H
CALL
DELAY
CALL
DELAY
Gio vin hng dn:

LXXXVII
Sinh vin thc hin:

Nguyn Vn Bnh

CLR
LED1
CLR
SETB
CLR
MOV
CALL
CALL
DJNZ
MOV
MOV
CLR
RET
LED2
LED3
LED4
P0,#12H
DELAY
DELAY
R7,LOOP1
R7,#10
P0,#00H
LED3
;------Hieu ung thu 2 cho led doan-----HIEU_UNG_2:

LOOP2:
SETB
LED1
CALL
DELAY
CLR
LED1
SETB
LED2
CALL
DELAY
CLR
LED2
SETB
LED3
CALL
DELAY
CLR
LED3
SETB
LED4
CALL
DELAY
CLR
LED4
MOV
P0,#01H
CALL
DELAY
MOV
P0,#02H
CALL
DELAY
MOV
P0,#04H
CALL
DELAY
MOV
P0,#08H
CALL
DELAY
MOV
P0,#10H
CALL
DELAY
MOV
P0,#00H
CALL
DELAY
DJNZ
R7,LOOP2
MOV
R7,#05
Gio vin hng dn:

LXXXVIII
Sinh vin thc hin:

Nguyn Vn Bnh

RET
;------Doc noi dung o nho DPTR----READ:
MOVC
MOV
A,@A+DPTR
P2,A
RET
;------Tao tre 6us-----DELAY_6us:
NOP
NOP
NOP
NOP
NOP
NOP
RET
;------Tao tre (250*200*2)/10^6 = 0.1s-----DELAY:
MOV
R1,#250
L1:
MOV
R2,#200
DJNZ
R2,$
DJNZ
R1,L1
RET
LED7S: DB 40H,79H,24H,30H,19H,12H,02H,78H,00H,10H
END
Gio vin hng dn:

LXXXIX
Sinh vin thc hin:

Nguyn Vn Bnh
2. Phn mm ng h thi gian thc v b iu khin t xa dng

remote hng ngoi (CODE_2)
SCL
SDA
SPEAKER
BELL
SIGNAL
DIS3
DIS4
DIS5
DIS6
DIS8
DIS7
DIS9
DIS15
DIS13
DIS12
DIS14
DIS10
DIS11
DIS16
DIS17
DIS18
DIS19
DIS21
DIS20
CO
LAST
HOUR
MINUTE
SECOND
DAY
DATE
MONTH
YEAR
ALK_HOUR
ALK_MINUTE
SQW_OUT
BYTECOUNT
BITCOUNT
TAM
BIT P0.0
BIT P0.1
BIT P3.0
BIT P3.1
BIT P3.2
BIT P0.2
BIT P0.3
BIT P0.4
BIT P0.5
BIT P0.6
BIT P0.7
BIT P3.3
BIT P2.0
BIT P2.1
BIT P2.2
BIT P2.3
BIT P2.4
BIT P2.5
BIT P2.6
BIT P2.7
BIT P3.4
BIT P3.5
BIT P3.6
BIT P3.7
DATA
BIT
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
Gio vin hng dn:

2DH
CO.7
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
XC
Sinh vin thc hin:

Nguyn Vn Bnh
ORG
LJMP
ORG
LJMP
0000H
MAIN
0003H
GIAI_MA_ROMOTE_SONY
MAIN:
MOV
R0,#1FH
MOV
R1,#00H
MOV
R2,#0FFH
MOV
R3,#00H
MOV
DPTR,#LED7S
MOV
P0,#0FFH
MOV
P1,#0FFH
MOV
P2,#0FFH
MOV
P3,#0FFH
CLR
LAST
CLR
SPEAKER
CLR
BELL
MOV
SECOND,#50H
MOV
MINUTE,#59H
MOV
HOUR,#00H
MOV
DAY,#02H
MOV
DATE,#01H
MOV
MONTH,#01H
MOV
YEAR,#10H
MOV
ALK_MINUTE,#30H
MOV
ALK_HOUR,#22H
MOV
SQW_OUT,#90H
MOV
TAM,#00H
MOV
IE,#00H
MOV
TMOD,#10H
SETB EA
SETB EX0
SETB IT0
MOV
SP,#256-32
HERE:
CALL
READ_CLOCK
CALL
HIENTHI_2
CALL
ALARM_TEST
CALL
TAT_MO_CHUONG
CALL
HIEU_UNG_CHINH
JMP
HERE
Gio vin hng dn:

XCI
Sinh vin thc hin:

Nguyn Vn Bnh

;-----------------------------------------------------------------------------;----Chuong trinh ngat de giai ma tin hieu hong ngoai---GIAI_MA_ROMOTE_SONY:
MOV
R1,A
CALL
DELAY_900us
MOV
A,#40H
JB
SIGNAL,EXIT_GIAIMA
RP1:
JNB
SIGNAL,RP1
;Cho tin hieu len muc cao
RP2:
JB
SIGNAL,RP2
;Cho tin hieu xuong muc thap
CALL
DELAY_900us
;Tao tre 900us
MOV
C,SIGNAL
;Dua de lieu vao C
JC BIT0
; Neu C=1 du lieu la bit 0
;neu C=0 du lieu la bit 1
BIT1:
SETB
C
;Dat C bang 1
RRC
A
;Ghi vao A
JC
END_SIGNAL
JMP
RP1
BIT0:
CLR
RRC
JC
JMP
END_SIGNAL:
CALL
RR
JMP
C
A
END_SIGNAL
RP2
;Dat C bang 0
;Ghi vao A
LONG_DELAY
A
KEY_ON_OFF
;Tao tre de chong nhieu

; Quay phai A
;----Phim cho phep mo/tat che do dieu chinh---KEY_ON_OFF:

CJNE
A,#15H,SOSANH
MOV
A,R2
CPLA
MOV
R2,A
MOV
R0,#20H
CJNE
R2,#0FFH,EXIT_KEY_ON_OFF
MOV
R0,#01FH
EXIT_KEY_ON_OFF:
JMPEXIT_GIAIMA
Gio vin hng dn:

XCII
Sinh vin thc hin:

Nguyn Vn Bnh
SOSANH:
CJNE
R2,#0FFH,KEY_NEXT
JMP
EXIT_GIAIMA
;----Phim lua chon vi tri dieu chinh---KEY_NEXT:

CJNE
A,#18H,KEY_BACK
INC R0
CJNE
R0,#29H,EXIT_KEY_NEXT
MOV
R0,#20H
EXIT_KEY_NEXT:
CALL
HIEU_UNG_CHINH
JMP
EXIT_GIAIMA
KEY_BACK:
CJNE
A,#19H,KEY_01
DEC
R0
CJNE
R0,#1FH,EXIT_KEY_NEXT
MOV
R0,#28H
EXIT_KEY_BACK:
CALL
HIEU_UNG_CHINH
EXIT_GIAIMA:
CALL
LONG_DELAY
JNB
SIGNAL,EXIT_GIAIMA
MOV
A,R1
CLR
IE0
RETI
;-----Cac phim du lieu cai dat-----KEY_01:
CJNE
A,#00H,KEY_02
MOV
TAM,#01H
CALL
XULY
JMP
EXIT_GIAIMA
KEY_02:
CJNE
MOV
CALL
JMP
A,#01H,KEY_03
TAM,#02H
XULY
EXIT_GIAIMA
Gio vin hng dn:

XCIII
Sinh vin thc hin:

Nguyn Vn Bnh

KEY_03:
CJNE
MOV
CALL
JMP
A,#02H,KEY_04
TAM,#03H
XULY
EXIT_GIAIMA
CJNE
MOV
CALL
JMP
A,#03H,KEY_05
TAM,#04H
XULY
EXIT_GIAIMA
CJNE
MOV
CALL
JMP
A,#04H,KEY_06
TAM,#05H
XULY
EXIT_GIAIMA
CJNE
MOV
CALL
JMP
A,#05H,KEY_07
TAM,#06H
XULY
EXIT_GIAIMA
CJNE
MOV
CALL
JMP
A,#06H,KEY_08
TAM,#07H
XULY
EXIT_GIAIMA
CJNE
MOV
CALL
JMP
A,#07H,KEY_09
TAM,#08H
XULY
EXIT_GIAIMA
CJNE
MOV
CALL
JMP
A,#08H,KEY_10
TAM,#09H
XULY
EXIT_GIAIMA
KEY_04:
KEY_05:
KEY_06:
KEY_07:
KEY_08:
KEY_09:
KEY_10:
Gio vin hng dn:

XCIV
Sinh vin thc hin:

Nguyn Vn Bnh

CJNE
MOV
CALL
JMP
A,#09H,KEY_MO_CHUONG
TAM,#00H
XULY
EXIT_GIAIMA
KEY_MO_CHUONG:
CJNE
A,#12H,KEY_TAT_CHUONG
MOV
R3,#0FFH
SETB
BELL
JMP
EXIT_GIAIMA
KEY_TAT_CHUONG:
CJNE
A,#13H,EXIT_GIAIMA
MOV
R3,#00H
CLR
BELL
JMP
EXIT_GIAIMA
;----Dua gia tri duoc dieu chinh vao cac o nho du lieu---XULY:
MOV
A,@R0
SWAP
A
ANL
A,#0F0H
ORL
A,TAM
MOV
@R0,A
CALL
WRITE_CLOCK
CALL
READ_CLOCK
CALL
HIENTHI_2
RET
;----Tao ra hieu ung khi dieu chinh---HIEU_UNG_CHINH:
CJNE
R0,#20H,TT1
MOV
P1,#0FFH
CLR
DIS3
SETB
DIS3
CLR
DIS4
SETB
DIS4
CALL
LONG_DELAY
CALL
LONG_DELAY
CALL
HIENTHI_2
CALL
LONG_DELAY
CALL
LONG_DELAY
JMP
EXIT_HUC
Gio vin hng dn:

XCV
Sinh vin thc hin:

Nguyn Vn Bnh

TT1:
CJNE
MOV
CLR
SETB
CLR
SETB
CALL
CALL
R0,#21H,TT2
P1,#0FFH
DIS5
DIS5
DIS6
DIS6
LONG_DELAY
LONG_DELAY
CALL
CALL
CALL
JMP
HIENTHI_2
LONG_DELAY
LONG_DELAY
EXIT_HUC
CJNE
MOV
CLR
SETB
CLR
SETB
CALL
CALL
CALL
CALL
CALL
JMP
R0,#22H,TT3
P1,#0FFH
DIS7
DIS7
DIS8
DIS8
LONG_DELAY
LONG_DELAY
HIENTHI_2
LONG_DELAY
LONG_DELAY
EXIT_HUC
CJNE
MOV
CLR
SETB
CALL
CALL
CALL
CALL
CALL
JMP
R0,#23H,TT4
P1,#0FFH
DIS9
DIS9
LONG_DELAY
LONG_DELAY
HIENTHI_2
LONG_DELAY
LONG_DELAY
EXIT_HUC
CJNE
MOV
CLR
SETB
R0,#24H,TT5
P1,#0FFH
DIS10
DIS10
TT2:
TT3:
TT4:
Gio vin hng dn:

XCVI
Sinh vin thc hin:

Nguyn Vn Bnh

CLR
SETB
CALL
CALL
CALL
CALL
CALL
JMP
DIS11
DIS11
LONG_DELAY
LONG_DELAY
HIENTHI_2
LONG_DELAY
LONG_DELAY
EXIT_HUC
CJNE
MOV
R0,#25H,TT6
P1,#0FFH
CLR
SETB
CLR
SETB
CALL
CALL
CALL
CALL
CALL
JMP
DIS12
DIS12
DIS13
DIS13
LONG_DELAY
LONG_DELAY
HIENTHI_2
LONG_DELAY
LONG_DELAY
EXIT_HUC
CJNE
MOV
CLR
SETB
CLR
SETB
CLR
SETB
CLR
SETB
CALL
CALL
CALL
CALL
CALL
JMP
R0,#26H,TT7
P1,#0FFH
DIS14
DIS14
DIS15
DIS15
DIS16
DIS16
DIS17
DIS17
LONG_DELAY
LONG_DELAY
HIENTHI_2
LONG_DELAY
LONG_DELAY
EXIT_HUC
CJNE
MOV
CLR
R0,#27H,TT8
P1,#0FFH
DIS18
TT5:
TT6:
TT7:
Gio vin hng dn:

XCVII
Sinh vin thc hin:

Nguyn Vn Bnh

SETB
CLR
SETB
CALL
CALL
CALL
CALL
CALL
JMP
DIS18
DIS19
DIS19
LONG_DELAY
LONG_DELAY
HIENTHI_2
LONG_DELAY
LONG_DELAY
EXIT_HUC
CJNE
MOV
CLR
R0,#28H,EXIT_HUC
P1,#0FFH
DIS20
TT8:
SETB
CLR
SETB
CALL
CALL
CALL
CALL
CALL
EXIT_HUC:
RET
DIS20
DIS21
DIS21
LONG_DELAY
LONG_DELAY
HIENTHI_2
LONG_DELAY
LONG_DELAY
;----Chon che do tat/mo chuong theo tung gio---TAT_MO_CHUONG:

CJNE
R3,#0FFH,TT10
MOV
A,MINUTE
CJNE
A,#00H,TT10
MOV
A,SECOND
CJNE
A,#00H,TT10
CLR
SPEAKER
;Mo am thanh bao thuc
CALL
LONG_DELAY
CALL
LONG_DELAY
CALL
LONG_DELAY
CALL
LONG_DELAY
TT10:
SETB
SPEAKER
;Tat am thanh bao thuc
RET
;----Gui dieu kien STARRT den DS1307----SEND_START:
Gio vin hng dn:

XCVIII
Sinh vin thc hin:

Nguyn Vn Bnh

SETB
SETB
CALL
CLR
CALL
CLR
CALL
RET
SDA
SCL
DELAY6US
SDA
DELAY6US
SCL
DELAY6US
;-----Gui dieu kien STOP den DS1307---SEND_STOP:

CLR
SDA
SETB
SCL
CALL
DELAY6US
SETB
SDA
CALL
CLR
CALL
RET
DELAY6US
SCL
DELAY6US
;----Ghi 8 bit du lieu vao DS1307--SEND_BYTE:

MOV BITCOUNT,#08H
SEND_BYTE_LOOP:
JNB ACC.7,LEVEL_LOW
SETB SDA
JMP SEND_BITS
LEVEL_LOW:
CLR SDA
SEND_BITS:
SETB
SCL
CALL
DELAY6US
CLR
SCL
;Ket thuc 1 xung nhip
RL
A
DJNZ
BITCOUNT,SEND_BYTE_LOOP
JB
LAST,NOT_ACK1 ;Neu lan doc cuoi cung thi
;khong gui bit ACK
ACK1:
;Gui bit ACK
CLR
SDA
SETB
SCL
CALL
DELAY6US
CLR
SCL
Gio vin hng dn:

XCIX
Sinh vin thc hin:

Nguyn Vn Bnh

CALL
RET
NOT_ACK1:
SETB
SETB
CALL
CLR
CALL
RET
DELAY6US
;Gui bit Not_ACK (NACK)
SDA
SCL
DELAY6US
SCL
DELAY6US
;----Doc 8 bit du lieu tu DS1307---READ_BYTE:

MOV
BITCOUNT,#08H
MOV
A,#00H
SETB
SDA
READ_BITS:
SETB
MOV
CALL
RLC
CLR
CALL
DJNZ
JB
SCL
C,SDA
DELAY6US
A
;Dua SDA vao thanh ghi A
SCL
DELAY6US
BITCOUNT,READ_BITS
LAST,NOT_ACK2 ;Neu lan doc cuoi cung thi
;khong gui bit ACK
ACK2:
;Gui bit ACK
CLR
SDA
SETB
SCL
CALL
DELAY6US
CLR
SCL
CALL
DELAY6US
RET
NOT_ACK2:
SETB SDA
SETB SCL
CALL
DELAY6US
CLR SCL
CALL
DELAY6US
RET
Gio vin hng dn:

;Gui bit NACK
Sinh vin thc hin:

Nguyn Vn Bnh

;----Doc thoi gian thuc tu DS1307---READ_CLOCK:
CALL
SEND_START
CLR
LAST
MOV
A,#0D0H
CALL
SEND_BYTE
SETB
LAST
MOV
A,#00H
CALL
SEND_BYTE
CALL
SEND_STOP
CALL
CLR
MOV
CALL
CALL
MOV
CALL
MOV
SEND_START
LAST
A,#0D1H
SEND_BYTE
READ_BYTE
SECOND,A
READ_BYTE
MINUTE,A
CALL
MOV
CALL
MOV
CALL
MOV
CALL
MOV
CALL
MOV
CALL
MOV
CALL
MOV
SETB
CALL
MOV
CALL
RET
READ_BYTE
HOUR,A
READ_BYTE
DAY,A
READ_BYTE
DATE,A
READ_BYTE
MONTH,A
READ_BYTE
YEAR,A
READ_BYTE
SQW_OUT,A
READ_BYTE
ALK_HOUR,A
LAST
READ_BYTE
ALK_MINUTE,A
SEND_STOP
;----Cai dat thoi gian cho DS1307---WRITE_CLOCK:
Gio vin hng dn:

CI
Sinh vin thc hin:

Nguyn Vn Bnh

CALL
CLR
MOV
CALL
MOV
CALL
MOV
CALL
MOV
CALL
MOV
CALL
MOV
CJNE
MOV
SEND_START
LAST
A,#0D0H
SEND_BYTE
A,#00H
SEND_BYTE
A,SECOND
SEND_BYTE
A,MINUTE
SEND_BYTE
A,HOUR
SEND_BYTE
A,DAY
A,#08H,TTD
A,#01H
CALL
MOV
CALL
MOV
CALL
SEND_BYTE
A,DATE
SEND_BYTE
A,MONTH
SEND_BYTE
MOV
CALL
MOV
CALL
MOV
CALL
SETB
MOV
CALL
CALL
RET
A,YEAR
SEND_BYTE
A,#90H
SEND_BYTE
A,ALK_HOUR
SEND_BYTE
LAST
A,ALK_MINUTE
SEND_BYTE
SEND_STOP
TTD:
;----Thoi gian bao thuc---ALARM_TEST:

MOV
A,MINUTE
CJNE
A,ALK_MINUTE,EXIT_ALARM_TEST
MOV
A,HOUR
CJNE
A,ALK_HOUR,EXIT_ALARM_TEST
CLR
SPEAKER
LOOP_ALK_TEST:
MOV
A,MINUTE
Gio vin hng dn:

CII
Sinh vin thc hin:

Nguyn Vn Bnh

CJNE
A,ALK_MINUTE,EXIT_ALARM_TEST
CALL
HIENTHI_2
CALL
READ_CLOCK
JMP
LOOP_ALK_TEST
EXIT_ALARM_TEST:
SETB
SPEAKER
RET
;----Xuat ket qua ra led 7 doan---HIENTHI_2:
MOV
A,HOUR
ANL
A,#0F0H
SWAP
A
CALL
READ
CLR
DIS3
SETB
DIS3
CALL
DELAY6US
MOV
A,HOUR
ANL
A,#0FH
CALL
READ
CLR
DIS4
SETB
DIS4
CALL
DELAY6US
MOV
ANL
SWAP
CALL
CLR
SETB
CALL
MOV
ANL
CALL
CLR
SETB
CALL
A,MINUTE
A,#0F0H
A
READ
DIS5
DIS5
DELAY6US
A,MINUTE
A,#0FH
READ
DIS6
DIS6
DELAY6US
MOV
ANL
SWAP
CALL
CLR
A,SECOND
A,#0F0H
A
READ
DIS7
Gio vin hng dn:

CIII
Sinh vin thc hin:

Nguyn Vn Bnh

SETB
CALL
MOV
ANL
CALL
CLR
SETB
CALL
DIS7
DELAY6US
A,SECOND
A,#0FH
READ
DIS8
DIS8
DELAY6US
MOV
CJNE
MOV
A,DAY
A,#01H,TTDD
A,#08H
CALL
CLR
SETB
CALL
READ
DIS9
DIS9
DELAY6US
MOV
ANL
SWAP
CALL
CLR
SETB
CALL
A,DATE
A,#0F0H
A
READ
DIS10
DIS10
DELAY6US
MOV
ANL
CALL
CLR
SETB
CALL
A,DATE
A,#0FH
READ
DIS11
DIS11
DELAY6US
MOV
ANL
SWAP
CALL
CLR
SETB
CALL
MOV
ANL
CALL
A,MONTH
A,#0F0H
A
READ
DIS12
DIS12
DELAY6US
A,MONTH
A,#0FH
READ
TTDD:
Gio vin hng dn:

CIV
Sinh vin thc hin:

Nguyn Vn Bnh

CLR
SETB
CALL
DIS13
DIS13
DELAY6US
MOV
MOV
DIVAB
CALL
CLR
SETB
CALL
MOV
CALL
CLR
SETB
CALL
A,#20
B,#10
MOV
ANL
SWAP
CALL
CLR
SETB
CALL
MOV
ANL
CALL
A,YEAR
A,#0F0H
A
READ
DIS16
DIS16
DELAY6US
A,YEAR
A,#0FH
READ
CLR
SETB
CALL
DIS17
DIS17
DELAY6US
MOV
ANL
SWAP
CALL
CLR
SETB
CALL
MOV
ANL
CALL
CLR
A,ALK_HOUR
A,#0F0H
A
READ
DIS18
DIS18
DELAY6US
A,ALK_HOUR
A,#0FH
READ
DIS19
READ
DIS14
DIS14
DELAY6US
A,B
READ
DIS15
DIS15
DELAY6US
Gio vin hng dn:

CV
Sinh vin thc hin:

Nguyn Vn Bnh
SETB
CALL
DIS19
DELAY6US
MOV
ANL
SWAP
CALL
CLR
SETB
CALL
MOV
ANL
CALL
CLR
SETB
CALL
RET
A,ALK_MINUTE
A,#0F0H
A
READ
DIS20
DIS20
DELAY6US
A,ALK_MINUTE
A,#0FH
READ
DIS21
DIS21
DELAY6US
;----Doc noi dung o nho DPTR---READ:

MOVC
A,@A+DPTR
MOV
P1,A
RET
;----Tao tre 900us---DELAY_900us:
MOV
MOV
SETB
JNB
CLR
CLR
RET
TH1,#HIGH(-900)
TL1,#LOW(-900)
TR1
TF1,$
TF1
TR1
;----Tao tre 6us---DELAY6US:

NOP
NOP
NOP
NOP
NOP
NOP
Gio vin hng dn:
CVI
Sinh vin thc hin:

Nguyn Vn Bnh

RET
;----Tao tre (250*200*2)/10^6 = 0.1s---LONG_DELAY:
MOV
R7,#250
L2:
MOV
R6,#200
DJNZ
R6,$
DJNZ
R7,L2
RET
LED7S: DB 40H,79H,24H,30H,19H,12H,02H,78H,00H,10H
END
Gio vin hng dn:

CVII
Sinh vin thc hin:

Nguyn Vn Bnh
3. Hng dn s dng b iu khin dng Remote SONY

Cc bc thc hin ci t
thi gian cho Lch Vn Nin in
T
Bc 1: n phm POWER
ln th nht m ch ci t.
Lu nu nh ch ci t
khng c m th tt c cc phm
cn li u b v hiu ho.
Bc 2: Sau khi ch ci
t c m, s dng phm
CONT hoc CONT chn v
tr ci t. Phm CONT next
(chuyn) n v tr k tip, phm
CONT back (tr v) v tr pha
sau.
S dng 2 phm VOL hoc
VOL chn ch bo chung
theo tng gi (6h,7h,8h..), phm VOL dng m v VOL dng tt ch
ny.
Bc 3: Nhp vo cc gi tr cn ci t bng cc s trn remote t 1 n
10 (do remote khng c s 0 nn s 10 lc ny c xem l s 0), vy gi tr c
nhp gii hn t 0 n 9. Nguyn tt nhp s ci t tng t nh nguyn tt nhp
s trong my tnh b ti.
Bc 4: n phm POWER ln th hai tt ch ci t.
Gio vin hng dn:

CVIII
Sinh vin thc hin:

Nguyn Vn Bnh
4. Code word ca remote SONY

c c cc code word remote SONY ti s dng cc led n (mt port 0)
ch th cho mi ln n phm. Sau y l mt vi code word m ti gii m:
Tn hiu hin th
Port 0
00000000B
00000001B
00000010B
00000011B
00000100B
00000101B
00000110B
00000111B
00001000B
00001001B
00010101B
00011000B
00011001B
00010010B
00010011B
00100101B
01111000B
00001011B
01110110B
01110111B
01101100B
01111100B
01100101B
01100110B
00010000B
00010001B
Gio vin hng dn:

Phm n remote
1
2
3
4
5
6
7
8
9
10
POWER
CONT
COUNT
VOL
VOL
TV/VIDEO
MEMD
TUNE2
FINE
FINE
TUNE1
SELECT
ENTER
MENU
PROGR
PROGR
CIX
M lnh khi n phm

(hex)
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
15H
18H
19H
12H
13H
25H
78H
0BH
76H
77H
6CH
7CH
65H
66H
10H
11H
Sinh vin thc hin:

Nguyn Vn Bnh

Dien Tu 6937

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Dien Tu 6937

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TRNG I HC CN TH

KHOA CNG NGH

Sinh vin thc hin:

TS.LNG VINH QUC DANH

THIT K LCH VN NIN IN T

NHN XT CA GIO VIN HNG DN

Gio vin hng dn:

Sinh vin thc hin:

THIT K LCH VN NIN IN T

Gio vin hng dn:

Sinh vin thc hin:

THIT K LCH VN NIN IN T

Sinh vin thc hin

Gio vin hng dn:

Sinh vin thc hin:

THIT K LCH VN NIN IN T

Gio vin hng dn:

Sinh vin thc hin:

THIT K LCH VN NIN IN T

Sinh vin thc hin:

THIT K LCH VN NIN IN T

Gio vin hng dn:

Sinh vin thc hin:

THIT K LCH VN NIN IN T

Gio vin hng dn:

Sinh vin thc hin:

THIT K LCH VN NIN IN T

Gio vin hng dn:

Sinh vin thc hin:

THIT K LCH VN NIN IN T

II. LCH S GII QUYT VN

Gio vin hng dn:

Sinh vin thc hin:

THIT K LCH VN NIN IN T

Gio vin hng dn:

Sinh vin thc hin:

THIT K LCH VN NIN IN T

CHNG II: C S L THUYT

Gio vin hng dn:

Sinh vin thc hin:

THIT K LCH VN NIN IN T

Gio vin hng dn:

Sinh vin thc hin:

THIT K LCH VN NIN IN T

khc nhau, chng hn nh hai hng

ngt. Cn phi lu mt s hng

2.2. Chc nng ca cc chn 89S52

Gio vin hng dn:

Sinh vin thc hin:

THIT K LCH VN NIN IN T

Chc nng chuyn i

Ng xut d liu ni tip.

Tn hiu ghi d liu ln b nh ngoi.

Tn hiu c b nh d liu ngoi.

PSEN (Program store enable):

Sinh vin thc hin:

THIT K LCH VN NIN IN T

3. T chc b nh bn trong 89S52

Gio vin hng dn:

Sinh vin thc hin:

THIT K LCH VN NIN IN T

Gio vin hng dn:

Sinh vin thc hin: