N-CHANNEL 24V - 0.

011 - 38A DPAK/IPAK STripFET III POWER MOSFET

TYPE STD38NH02L
s s s s s s s

STD38NH02L

VDSS 24 V

RDS(on) < 0.0135

ID 38 A

TYPICAL RDS(on) = 0.011 @ 10 V TYPICAL RDS(on) = 0.015 @ 5 V RDS(ON) * Qg INDUSTRYs BENCHMARK CONDUCTION LOSSES REDUCED SWITCHING LOSSES REDUCED LOW THRESHOLD DEVICE THROUGH-HOLE IPAK (TO-251) POWER PACKAGE IN TUBE (SUFFIX -1") SURFACE-MOUNTING DPAK (TO-252) POWER PACKAGE IN TAPE & REEL (SUFFIX T4")

3 2 1
IPAK TO-251 (Suffix -1) DPAK TO-252 (Suffix T4)

3 1

DESCRIPTION
The STD38NH02L utilizes the latest advanced design rules of STs proprietary STripFET technology. This is suitable fot the most demanding DC-DC converter application where high efficiency is to be achieved.

INTERNAL SCHEMATIC DIAGRAM

APPLICATIONS s SPECIFICALLY DESIGNED AND OPTIMISED FOR HIGH EFFICIENCY DC/DC CONVERTES

ABSOLUTE MAXIMUM RATINGS

Symbol Vspike(1) VDS VDGR VGS ID ID IDM(2) Ptot EAS (3) Tstg Tj Parameter Drain-source Voltage Rating Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuous) at TC = 25C Drain Current (continuous) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Derating Factor Single Pulse Avalanche Energy Storage Temperature Max. Operating Junction Temperature Value 30 24 24 20 38 27 152 40 0.27 250 -55 to 175 Unit V V V V A A A W W/C mJ C

September 2003

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STD38NH02L
THERMAL DATA
Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Thermal Resistance Junction-ambient Maximum Lead Temperature For Soldering Purpose Max Max 3.75 100 275 C/W C/W C

ELECTRICAL CHARACTERISTICS (TCASE = 25 C UNLESS OTHERWISE SPECIFIED) OFF

Symbol V(BR)DSS IDSS IGSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 25 mA, VGS = 0 VDS = 20 V VDS = 20 V VGS = 20V Min. 24 1 10 100 Typ. Max. Unit V A A nA

TC = 125C

ON (4)
Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS VGS = 10 V VGS = 5 V ID = 250 A ID = 19 A ID = 9.5 A Min. 1 Typ. 1.8 0.011 0.015 Max. 2.5 0.0135 0.025 Unit V

DYNAMIC
Symbol gfs (4) Ciss Coss Crss RG Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Input Resistance Test Conditions VDS = 10 V ID = 19 A Min. Typ. 19 1070 305 45 Max. Unit S pF pF pF

VDS = 15V f = 1 MHz VGS = 0

f = 1 MHz Gate DC Bias = 0 Test Signal Level = 20 mV Open Drain

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STD38NH02L
ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON
Symbol td(on) tr Qg Qgs Qgd Qoss (5) Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Output Charge Test Conditions ID = 19 A VDD = 10 V RG = 4.7 VGS = 10 V (Resistive Load, Figure 3) 0.44V VDD 10V, VGS= 10 V VDS= 16 V Min. Typ. 7 62 18 4 2.5 6.5 24 Max. Unit ns ns nC nC nC nC

ID= 38 A

VGS= 0 V

SWITCHING OFF
Symbol td(off) tf Parameter Turn-off Delay Time Fall Time Test Conditions ID = 19 A VDD = 10 V RG = 4.7, VGS = 10 V (Resistive Load, Figure 3) Min. Typ. 25 12 Max. 16 Unit ns ns

SOURCE DRAIN DIODE

Symbol ISD ISDM VSD (4) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 19 A VGS = 0 27 22 1.6 Test Conditions Min. Typ. Max. 38 152 1.3 36 29 Unit A A V ns nC A

di/dt = 100A/s ISD = 38 A VDD = 18 V Tj = 150C (see test circuit, Figure 5)

(1) Garanted when external Rg=4.7 and tf < tfmax. (2) Pulse width limited by safe operating area (3) Starting Tj = 25 oC, ID = 19A, VDD = 18V .

(4) Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. (5) Qoss = Coss* Vin , Coss = Cgd + Cds . See Appendix A

Safe Operating Area

Thermal Impedance

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STD38NH02L
Output Characteristics Transfer Characteristics

Transconductance

Static Drain-source On Resistance

Gate Charge vs Gate-source Voltage

Capacitance Variations

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Normalized Gate Threshold Voltage vs Temperature Normalized on Resistance vs Temperature

Source-drain Diode Forward Characteristics

Normalized Breakdown Voltage vs Temperature

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STD38NH02L
Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform

Fig. 3: Switching Times Test Circuits For Resistive Load

Fig. 4: Gate Charge test Circuit

Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times

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STD38NH02L

TO-251 (IPAK) MECHANICAL DATA

DIM. MIN. A A1 A3 B B2 B3 B5 B6 C C2 D E G H L L1 L2 0.45 0.48 6 6.4 4.4 15.9 9 0.8 0.8 0.3 0.95 0.6 0.6 6.2 6.6 4.6 16.3 9.4 1.2 1 0.017 0.019 0.236 0.252 0.173 0.626 0.354 0.031 0.031 2.2 0.9 0.7 0.64 5.2 mm TYP. MAX. 2.4 1.1 1.3 0.9 5.4 0.85 0.012 0.037 0.023 0.023 0.244 0.260 0.181 0.641 0.370 0.047 0.039 MIN. 0.086 0.035 0.027 0.025 0.204 inch TYP. MAX. 0.094 0.043 0.051 0.031 0.212 0.033

H
C A C2

L2

D
B3 B6

A1

B5

A3
=

B2

G
=

L1

0068771-E

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TO-252 (DPAK) MECHANICAL DATA

mm MIN. A A1 A2 B B2 C C2 D E G H L2 L4 0.6 2.2 0.9 0.03 0.64 5.2 0.45 0.48 6 6.4 4.4 9.35 0.8 1 0.023 TYP. MAX. 2.4 1.1 0.23 0.9 5.4 0.6 0.6 6.2 6.6 4.6 10.1 MIN. 0.086 0.035 0.001 0.025 0.204 0.017 0.019 0.236 0.252 0.173 0.368 0.031 0.039 inch TYP. MAX. 0.094 0.043 0.009 0.035 0.212 0.023 0.023 0.244 0.260 0.181 0.397

DIM.

C2

DETAIL "A"

A1

L2

D DETAIL "A"
B

B2

L4

A2

0068772-B

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APPENDIX A Buck Converter: Power Losses Estimation

SW1

SW2

The power losses associated with the FETs in a Synchronous Buck converter can be estimated using the equations shown in the table below. The formulas give a good approximation, for the sake of performan comparison, of how different pairs of devices ce affect the converter efficiency. However a very important parameter, the working temperature, is not considered. The real device behavior is really dependent on how the heat generated inside the devices is emoved to allow for a safer working junction r temperature. The low side (SW2) device requires: Very low RDS(on) to reduce conduction losses Small Qgls to reduce the gate charge losses Small Coss to reduce losses due to output capacitance Small Qrr to reduce losses on SW1 during its turn-on The Cgd/Cgs ratio lower than Vth/Vgg ratio especially with low drain to source voltage to avoid the cross conduction phenomenon;

The high side (SW1) device requires: Small Rg and Ls to allow higher gate current peak an to limit the voltage d feedback on the gate Small Qg to have a faster commutation and to reduce gate charge losses Low RDS(on) to reduce the conduction losses.

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High Side Switch (SW1)

Low Side Switch (SW2)

Pconduction

R DS(on)SW1 * I 2 * d L

R DS(on)SW2 * I 2 * (1 d ) L

Pswitching

Vin * (Q gsth(SW1) + Q gd(SW1) ) * f *

IL Ig

Zero Voltage Switching

Pdiode

Recovery

Not Applicable

Vin * Q rr(SW2) * f

Conduction

Not Applicable

Vf(SW2) * I L * t deadtime * f Q gls(SW2) * Vgg * f

Pgate(Q G )

Q g(SW1) * Vgg * f

PQoss

Vin * Q oss(SW1) * f 2

Vin * Q oss(SW2) * f 2

Parameter d Qgsth Qgls Pconduction Pswitching Pdiode Pgate PQoss

Meaning Duty-cycle Post threshold gate charge Third quadrant gate charge On state losses On-off transition losses Conduction and reverse recovery diode losses Gate drive losses Output capacitance losses

Dissipated by SW1 during turn-on

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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics 2002 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com

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