Ordering number : EN4797A

CMOS LSI

LC72322
Single-Chip Microcontroller with PLL and LCD Driver

Overview
The LC72322 is a single-chip microcontroller for use in electronic tuning applications. It includes on chip both LCD drivers and a PLL circuit that can operate at up to 150 MHz. It features a large-capacity ROM, a highly efficient instruction set, and powerful hardware.

Functions
Stack: Eight levels Fast programmable divider General-purpose counters: HCTR for frequency measurement and LCTR for frequency or period measurement LCD driver for displays with up to 56 segments (1/2 duty, 1/2 bias) Program memory (ROM): 4 k words by 16 bits Data memory (RAM): 256 4-bit digits All instructions are single-word instructions Cycle time: 2.67 s, 13.33 s, or 40.00 s (option) Unlock FF: 0.55 s detection, 1.1 s detection Timer FF: 1 ms, 5ms, 25ms, 125ms Input ports*: One dedicated key input port and one high-breakdown voltage port Output ports*: Two dedicated key output ports, one high-breakdown voltage open-drain port Two CMOS output ports (of which one can be switched to be used as LCD driver outputs) Seven CMOS output ports (mask option switchable to use as LCD ports) I/O ports*: One switchable between input and output in four-bit units and one switchable between input and output in one-bit units Note: * Each port consists of four bits.
This LSI can easily use CCB that is SANYOs original bus format.

Program runaway can be detected and a special address set (Programmable watchdog timer). Voltage detection type reset circuit One 6-bit A/D converter Two 8-bit D/A converters (PWM) One external interrupt Hold mode for RAM backup Sense FF for hot/cold startup determination PLL: 4.5 to 5.5 V CPU: 3.5 to 5.5 V RAM: 1.3 to 5.5 V

Package Dimensions
unit: mm 3174-QFP80E
[LC72322]

SANYO: QFP80E

CCB is a trademark of SANYO ELECTRIC CO., LTD. CCB is SANYOs original bus format and all the bus addresses are controlled by SANYO.

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
32896HA (OT)/83194TH (OT) No. 4797-1/13

LC72322 Pin Assignment

No. 4797-2/13

LC72322 Block Diagram

No. 4797-3/13

LC72322

Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Input voltage Symbol VDD max VIN1 VIN2 VOUT1 VOUT2 IOUT1 Output current IOUT2 IOUT3 IOUT4 Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg HOLD, INT, RES, ADI, SNS, and the G port Inputs other than VIN1 H port Outputs other than VOUT1 All D and H port pins All E and F port pins All B and C port pins S1 to S28 and all I port pins Ta = 40 to +85C Conditions Ratings 0.3 to +6.5 0.3 to +13 0.3 to VDD + 0.3 0.3 to +15 0.3 to VDD + 0.3 0 to 5 0 to 3 0 to 1 0 to 1 300 40 to +85 45 to +125 Unit V V V V V mA mA mA mA mW C C

Output voltage

Allowable Operating Ranges at Ta = 40 to +85C, VDD = 3.5 to 5.5 V

Parameter Symbol VDD1 Supply voltage VDD2 VDD3 VIH1 VIH2 VIH3 Input high level voltage VIH4 VIH5 VIH6 VIL1 VIL2 VIL3 Input low level voltage VIL4 VIL5 VIL6 VIL7 fIN1 fIN2 fIN3 Input frequency fIN4 fIN5 fIN6 fIN7 fIN8 VIN1 VIN2 Input amplitude VIN3 VIN4, 5 VIN6, 7 Input voltage range VIN8 Conditions CPU and PLL operating CPU operating Memory retention voltage G port RES, INT, HOLD SNS A port E, F port LCTR (period measurement), VDD1, PE1, PE3 G port RES, INT, PE1, PE3 SNS A port PE0, PE2, F port LCTR (period measurement), VDD1 HOLD XIN FMIN, VIN2, VDD1 FMIN, VIN3, VDD1 AMIN (L), VIN4, VDD1 AMIN (H), VIN5, VDD1 HCTR, VIN6, VDD1 LCTR (frequency), VIN7, VDD1 LCTR (frequency), VIH6, VIL6, VDD1 XIN FMIN FMIN AMIN LCTR, HCTR ADI Ratings min 4.5 3.5 1.3 0.7 VDD 0.8 VDD 2.5 0.6 VDD 0.7 VDD 0.8 VDD 0 0 0 0 0 0 0 4.0 10 10 0.5 2.0 0.4 100 1 0.50 0.10 0.15 0.10 0.10 0 4.5 typ max 5.5 5.5 5.5 8.0 8.0 8.0 VDD VDD VDD 0.3 VDD 0.2 VDD 1.3 0.2 VDD 0.3 VDD 0.2 VDD 0.4 VDD 5.0 130 150 10 40 12 500 20 103 1.5 1.5 1.5 1.5 1.5 VDD Unit V V V V V V V V V V V V V V V V MHz MHz MHz MHz MHz MHz kHz Hz Vrms Vrms Vrms Vrms Vrms V

No. 4797-4/13

LC72322 Electrical Characteristics for the Allowable Operating Ranges

Parameter Hysteresis Rejected pulse width Power-down detection voltage Symbol VH PREJ VDET IIH1 IIH2 Input high level current IIH3 IIH4 IIH5 IIL1 Input low level current IIL2 IIL3 IIL4 Input floating voltage Pull-down resistance VIF RPD IOFFH1 Output high level off leakage current IOFFH2 IOFFH3 Output low level off leakage current IOFFL1 IOFFL2 VOH1 VOH2 VOH3 Output high level voltage VOH4 VOH5 VOH6 VOH7 VOL1 VOL2 VOL3 Output low level voltage VOL4 VOL5 VOL6 VOL7 VOL8 Output middle level voltage A/D conversion error IDD1 IDD2 IDD3 Current drain IDD4 VM1 INT, HOLD, RES, ADI, SNS, and the G port: VI = 5.5 V A, E, and F ports: E and F ports with outputs off, A port with no RPD, VI = VDD XIN: VI = VDD = 5.0 V FMIN, AMIN, HCTR, LCTR: VI = VDD = 5.0 V A port: With an RPD, VI = VDD = 5.0 V INT, HOLD, RES, ADI, SNS, and the G port: VI = VSS A, E, and F ports: E and F ports with outputs off, A port with no RPD, VI = VSS XIN: VIN = VSS FMIN, AMIN, HCTR, LCTR: VI = VSS A port: With an RPD A port: With an RPD, VDD = 5.0 V EO1, EO2: VO = VDD B, C, D, E, F, and I ports: VO = VDD H port: VO = 13 V EO1, EO2: VO = VSS B, C, D, E, F, and I ports: VO = VSS B and C ports: IO = 1 mA E and F ports: IO = 1 mA EO1, EO2: IO = 500 A XOUT: IO = 200 A S1 to S28 and the I port: IO = 0.1 mA D port: IO = 5 mA COM1, COM2: IO = 25 A B and C ports: IO = 50 A E and F ports: IO = 1 mA EO1, EO2: IO = 500 A XOUT: IO = 200 A S1 to S28 and the I port: IO = 0.1 mA D port: IO = 5 mA COM1, COM2: IO = 25 A H port: IO = 5 mA, VDD1 COM1, COM2: VDD = 5.0 V, IO = 25 A ADI: VDD1 VDD1, fIN2 = 130 MHz VDD1, PLL stopped, CT = 2.67 s (HOLD mode, Figure 1) VDD1, PLL stopped, CT = 13.33 s (HOLD mode, Figure 1) VDD1, PLL stopped, CT = 40.00 s (HOLD mode, Figure 1) VDD = 5.5 V, oscillator stopped, Ta = 25C (BACK UP mode, Figure 2) VDD = 2.5 V, oscillator stopped, Ta = 25C (BACK UP mode, Figure 2) 0.3 (150 ) 0.75 2.0 1/2 15 1.5 1.0 0.7 5 1 2.5 0.5 VDD 2.0 VDD 1.0 VDD 1.0 VDD 1.0 VDD 1.0 VDD 1.0 VDD 0.75 0.5 VDD 0.5 1.0 VDD 0.3 2.0 1.0 1.0 1.0 1.0 1.0 0.75 (400 ) 2.0 3.0 1/2 20 VDD 1.0 0.01 75 100 0.01 2.0 4.0 5.0 10 2.0 4.0 5.0 10 50 3.0 3.0 15 30 0.05 VDD 200 10 3.0 5.0 10 3.0 VDD 0.5 Conditions LCTR (period), RES, INT, PE1, PE3 SNS 2.7 3.0 Ratings min 0.1 VDD 50 3.3 3.0 3.0 15 30 typ max Unit V s V A A A A A A A A A V k nA A A nA A V V V V V V V V V V V V V V V V LSB mA mA mA mA A A

IDD5

No. 4797-5/13

LC72322 Test Circuits

Note: PB to PF, PH, and PI are all open. However, PE and PF are output selected.

Figure 1 IDD2 to IDD4 in HOLD Mode

Note: PA to PI, S1 to S4, COM1, and COM2 are all open.

Figure 2 IDD5 in BACK UP Mode

No. 4797-6/13

LC72322 Pin Functions

Pin Pin No. Functions I/O I/O circuit type

Low-threshold type dedicated input port PA0 PA1 PA2 PA3 35 34 33 32 These pins can be used, for example, for key data acquisition. Built-in pull-down resistors can be specified as an option. This option is in 4-pin units, and cannot be specified for individual pins. Input through these pins is disabled in BACK UP mode. Input

PB0 PB1 PB2 PB3 PC0 PC1 PC2 PC3

30 29 28 27 26 25 24 23 Dedicated output ports Since the output transistor impedances are unbalanced CMOS, these pins can be effectively used for functions such as key scan timing. These pins go to the output highimpedance state in BACK UP mode. These pins go to the low level during a reset, i.e., when the RES pin is low. Output

PD0 PD1 PD2 PD3

22 21 20 19

Dedicated output ports These are normal CMOS outputs. These pins go to the output high-impedance state in BACK UP mode. These pins go to the low level during a reset, i.e., when the RES pin is low.

I/O port PE0 PE1 PE2 PE3 18 17 16 15 These pins are switched between input and output as follows: Once an input instruction (IN, TPT, or TPF) is executed, these pins latch in the input mode. Once an output instruction (OUT, SPB, or RPB) is executed, they latch in the output mode. These pins go to the input mode during a reset, i.e., when the RES pin is low. In BACK UP mode these pins go to the input mode with input disabled.

I/O

I/O port PF0 PF1 PF2 PF3 14 13 12 11 These pins are switched between input and output by the FPC instruction. The I/O states of this port can be specified for individual pins. These pins go to the input mode during a reset, i.e., when the RES pin is low. In BACK UP mode these pins go to the input mode with input disabled.

PG0 PG1 PG2 PG3

6 5 4 3 Dedicated input port Input through these pins is disabled in BACK UP mode. Input

Continued on next page.

No. 4797-7/13

LC72322
Continued from preceding page.
Pin Pin No. Dedicated output port PH0 PH1 PH2/DAC1 PH3/DAC2 10 9 8 7 Since these pins are high-breakdown voltage n-channel transistor open-drain outputs, they can be effectively used for functions such as band power supply switching. Note that PH2 and PH3 also function as the DAC1 and DAC2 outputs. These ports go to the high impedance state during a reset, i.e., when the RES pin is low, and in BACK UP mode. Functions I/O I/O circuit type

Output

Dedicated output port While these pins have a CMOS output circuit structure, they can be switched to function as LCD drivers. Their function is switched by the SS and RS instructions. These pins cannot be switched individually. The LCD driver function is selected and a segment-off signal is output when power is first applied or when RES is low. These pins are held at the low level in BACK UP mode. Note that when the general-purpose port use option is specified, these pins output the contents of IPORT when LPC is 1, and the contents of the general-purpose output port LATCH when LPC is 0. Output

PI0/S25 PI1/S26 PI2/S27 PI3/S28

39 38 37 36

LCD driver segment outputs A frame frequency of 100 Hz and a 1/2 duty, 1/2 bias drive type are used. S1 to S24 63 to 40 A segment-off signal is output when power is first applied or when RES is low. These pins are held at the low level in BACK UP mode. The use of these pins as general-purpose output ports can be specified as an option. Output

LCD driver common outputs COM1 COM2 65 64 A 1/2 duty, 1/2 bias drive type is used. The output when power is first applied or when RES is low is identical to the normal operating mode output. These pins are held at the low level in BACK UP mode. Output

FM VCO (local oscillator) input FMIN 74 The input must be capacitor coupled. The input frequency range is from 10 to 130 MHz.

AM VCO (local oscillator) input AMIN 75 The band supported by this pin can be selected using the PLL instruction. High (2 to 40 MHz) SW Low (0.5 to 10 MHz) LW and MW

Input

Continued on next page.

No. 4797-8/13

LC72322
Continued from preceding page.
Pin Pin No. Universal counter input HCTR 70 The input should be capacitor coupled. The input frequency range is from 0.4 to 12 MHz. This input can be effectively used for FM IF or AM IF counting. Universal counter input The input should be capacitor coupled for input frequencies in the range 100 to 150 kHz. LCTR 71 Capacitor coupling is not required for input frequencies from 1 to 20 Hz. This input can be effectively used for AM IF counting. This pin can also be used as a normal input port. Input Functions I/O I/O circuit type

A/D converter input ADI 69 A 1.28 ms period is required for a 6-bit sequential comparison conversion. The full scale input is ((63/96) VDD) for a data value of 3FH. Input

External interrupt request input INT 66 An interrupt is generated when the INTEN flag is set (by an SS instruction) and a falling edge is input. This pin can also be used as a normal input port. Input

EO1 EO2

77 78

Reference frequency and programmable divider phase comparison error outputs Charge pump circuits are built in. EO1 and EO2 are the same. Output

SNS

72

Input pin used to determine if a power outage has occurred in BACK UP mode This pin can also be used as a normal input port.

Input

Input pin used to force the LC72322 to HOLD mode HOLD 67 The LC72322 goes to HOLD mode when the HOLDEN flag is set (by an SS instruction) and the HOLD input goes low. A high-breakdown voltage circuit is used so that this input can be used in conjunction with the normal power switch. System reset input RES 68 This signal should be held low for 75 ms after power is first applied to effect a power-up reset. The reset starts when a low level has been input for at least six reference clock cycles. Input Input

XIN XOUT

1 80

Crystal oscillator connections (4.5 MHz) A feedback resistor is built in.

Input Output

TEST1 TEST2 VDD VSS

2 79 31, 73 76

LSI test pins. These pins must be connected to VSS.

Power supply

Continued on next page. No. 4797-9/13

LC72322 Mask Options

No. 1 Description WDT (watchdog timer) inclusion selection Selections WDT included No WDT Pull-down resistors included No pull-down resistors 2.67 s 3 Cycle time selection 13.33 s 40.00 s 4 LCD port/general-purpose port selection LCD ports General-purpose output ports

Port A pull-down resistor inclusion selection

Development Environment The LC72P321 is used for OTP. The LC72EV321 is used as the evaluation chip. A total debugging system is available in which the TB-72EV32 evaluation chip board and the RE32 multi-function emulator are controlled by a personal computer.

No. 4797-10/13

LC72322 LC72321 Instruction Table Abbreviations: ADDR: Program memory address [12 bits] b: Borrow B: Bank number [2 bits] C: Carry DH: Data memory address high (row address) [2 bits] DL: Data memory address low (column address) [4 bits] I: Immediate data [4 bits] M: Data memory address N: Bit position [4 bits] Pn: Port number [4 bits] r: General register (one of the locations 00 to 0FH in bank 0) ( ): Contents of register or memory ( )N: Contents of bit N of register or memory
Instruction Group Operand Mnemonic 1st AD ADS Addition instructions AC ACS AI AIS AIC AICS SU SUS SB r r r r M M M M r r r 2nd M M M M I I I I M M M Add M to r Add M to r, then skip if carry Add M to r with carry Add M to r with carry, then skip if carry Add I to M Add I to M, then skip if carry Add I to M with carry Add I to M with carry, then skip if carry Subtract M from r Subtract M from r, then skip if borrow Subtract M from r with borrow Subtract M from r with borrow, then skip if borrow Subtract I from M Subtract I from M, then skip if borrow Subtract I from M with borrow Subtract I from M with borrow, then skip if borrow Skip if r equals M Skip if r is greater than or equal to M Skip if M equal to I Skip if M is greater than or equal to I r (r) + (M) r (r) + (M) skip if carry r (r) + (M) + C r (r) + (M) + C skip if carry M (M) + I M (M) + I skip if carry M (M) + I + C M (M) + I + C skip if carry r (r) (M) r (r) (M) skip if borrow r (r) (M) b r (r) (M) b skip if borrow M (M) I M (M) I skip if borrow M (M) I b M (M) I b skip if borrow rM skip if zero rM skip if not borrow (r) (M) MI skip if zero MI skip if not borrow (M) I Function Operation D15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 1 1 1 1 0 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 0 1 0 1 0 1 0 DH DH DH DH DH DH DH DH DH DH DH 7 6 5 4 DL DL DL DL DL DL DL DL DL DL DL 3 2 1 D0 Rn Rn Rn Rn I I I I Rn Rn Rn Machine code

Subtraction instructions

SBS SI SIS SIB

r M M M

M I I I

0 0 0 0

1 1 1 1

1 1 1 1

0 1 1 1

0 0 0 1

0 0 1 0

DH DH DH DH

DL DL DL DL

Rn I I I

SIBS

DH

DL

Comparison instructions

SEQ

DH

DL

Rn

SGE

DH

DL

Rn

SEQI

DH

DL

SGEI

DH

DL

Continued on next page.

No. 4797-11/13

LC72322
Continued from preceding page.
Instruction Group Operand Mnemonic 1st AND OR EXL LD ST Transfer instructions MVRD M M r r M r 2nd I I M M r M AND I with M OR I with M Exclusive OR M with r Load M to r Store r to M Move M to destination M referring to r in the same row Move source M referring to r to M in the same row Move M to M in the same row Move I to M Load M to PLL registers Test M bits, then skip if all bits specified are true Test M bits, then skip if all bits specified are false Jump to the address Call subroutine Return from subroutine Return from interrupt Test timer F/F then skip if it has not been set Test unlock F/F then skip if it has not been set Set status register Reset status register Test status register true Test status register false M (M) M (M) r (r) r (M) M (r) [DH, Rn] (M) I I (M) Function Operation D15 14 13 12 11 10 9 8 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 DH DH DH DH DH DH 7 6 5 4 DL DL DL DL DL DL 3 2 1 D0 I I Rn Rn Rn Rn Machine code

Logical operation instructions

MVRS

M [DH, Rn] [DH, DL1] [DH, DL2] MI PLL r PLL DATA if M (N) = all 1, then skip if M (N) = all 0, then skip PC ADDR Stack (PC) + 1 PC Stack PC Stack if timer F/F = 0, then skip if UL F/F = 0, then skip (Status register 1) N1 (Status register 1) N0 if (Status register 2) N = all 1, then skip if (Status register 2) N = all 0, then skip

DH

DL

Rn

MVSR MVI PLL

M1 M M

M2 I r

1 1 1

0 0 0

0 0 0

1 1 1

0 0 1

0 1 0

DH DH DH

DL1 DL DL

DL2 I Rn

Bit test instructions

TMT

DH

DL

TMF

DH

DL

Jump and subroutine call instructions

JMP CAL RT RTI

ADDR ADDR

1 1 1 1

0 1 1 1

1 0 0 0

1 0 1 1 0 0 1 1 0 0 0 1

ADDR (12 bits) ADDR (12 bits) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

F/F test instructions

TTM

1 0

0 0 0 0

TUL

1 1

0 0 0 0

Bank switching Status register instructions instructions

SS RS TST TSF

N N N N

1 1 1 1

1 1 1 1

0 0 0 0

1 1 1 1

1 1 1 1

1 1 1 1

0 0 0 1 1 0 1 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

N N N N

BANK

Select bank

BANK B

0 0 0 0

0 0 0

Continued on next page.

No. 4797-12/13

LC72322
Continued from preceding page.
Instruction Group Operand Mnemonic 1st LCD LCP I/O instructions IN OUT SPB RPB TPT M M M M P P P 2nd I I P P N N N Output segment pattern to LCD digit direct Output segment pattern to LCD digit through PLA Input port data to M Output contents of M to port Set port bits Reset port bits Test port bits, then skip if all bits specified are true Test port bits, then skip if all bits specified are false Set I to UCCW1 LCD (DIGIT) M LCD (DIGIT) PLA M M (Port (P)) (Port (P)) M (Port (P)) N 1 (Port (P)) N 0 if (Port (P)) N = all 1, then skip if (Port (P)) N = all 0, then skip Function Operation D15 14 13 12 11 10 9 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 DH DH DH DH 0 0 0 1 1 0 7 6 5 4 DL DL DL DL P P P 3 2 1 D0 DIGIT DIGIT P P N N N Machine code

TPF Universal counter instructions

1 1

UCS

UCCW1 I

0 1

0 0 0 0

UCC FPC CKSTP DAC NOP

I N

Set I to UCCW2 F port I/O control Clock stop

UCCW2 I FPC latch N Stop clock if HOLD = 0 DAreg DAC DATA

0 0 0 0 0

0 0 0 0 0

0 0 0 0 0

0 1 1 0 0

0 0 0 0 0

0 0 0 0 0

1 1 0 0 0 1 1 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

I N 0 0 0 I 0 0 0 0 0

Other instructions

Load M to D/A registers No operation

s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 1997. Specifications and information herein are subject to change without notice. No. 4797-13/13