Prime University

2A/1, Darus Salam Road, Mirpur-1, Dhaka-1216, Bangladesh

Faculty of Engineering Department of Electrical and Electronic Engineering

Course Conducted by: Shuvodip Das

Course Title: Digital Electronics Course Code: EEE 357 Sequential System
Sequential System:
In digital circuit theory, sequential logic is a type of logic circuit whose output depends not only on the present input but also on the history of the input. This is in contrast to combinational logic, whose output is a function of, and only of, the present input. In other words, sequential logic has state (memory) while combinational logic does not. Difference between Combinational and Sequential Logic Circuit? Sequential Logic can be divided as a) Synchronous Sequential Logic and b) Asynchronous Sequential Logic.

Synchronous sequential logic Nearly all sequential logic today is 'clocked' or 'synchronous' logic: there is a 'clock' signal, and all internal memory (the 'internal state') changes only on a clock edge. The basic storage element in sequential logic is the flip-flop. The main advantage of synchronous logic is its simplicity. Every operation in the circuit must be completed inside a fixed interval of time between two clock pulses, called a 'clock cycle'. Asynchronous sequential logic Asynchronous sequential logic expresses memorizing effect by fixing moments of time, when digital device changes its state. These moments are represented not in explicit form, but taking into account principle before/after in temporal relations of logical values. For asynchronous logic it is sufficient to determine a sequence of switchings irrespective of any connections of the corresponding moments with real or virtual time. Example of Sequential Logic Circuit: Flip-Flop, Counter, Register etc.

Flip-Flop:
In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state information. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems.
1

Fli l l t t t l while clocked devices are descri ed as flip-fl p .

Si le S_R (set-reset) l t es:

l t h i mai l used for storage elements,

SR NOR latch

When using static gates as building blocks, the most fundamental latch is the simpleSR l t h, where S and R stand for t and t. It can be constructed from a pair of cross-coupled OR logic gates. The stored bit is present on the output marked Q.
SR NAND latch

An SR latch, constructed from a pair of cross-coupled

A D gates

This is an alternate model of the simple SR latch built with A D logic gates. Set and eset now become active low signals, denoted S and R respectivel . Otherwise, operation is identical to that of the SR latch.
SS

l t R 0 1 0 1

oper tion Action Restricted combination Q=1 Q=0 o Change

0 0 1 1

Symbol of S - R Latch



R 0 1 0 1 An R latch, constructed from OR gates

S 0 0 1 1

 

Q Qb o Change o Change 0 1 1 0 Invalid Invalid a pair of cross-coupled

Level Triggered R-S Flip-Flop/ Clocked R-S Flip-Flop:

The clocked RS NAND latch is shown below. The clocked RS latch circuit is very similar in operation to the basic. The S and R inputs are normally at logic 0, and must be changed to logic 1 to change the state of the latch. However, with the third input, a new factor has been added. This input is typically designated C or CLK, because it is typically controlled by a clock circuit of some sort, which is used to synchronize several of these latch circuits with each other. The output can only change state while the CLK input is a logic 1. When CLK is a logic 0, the S and R inputs will have no effect.

Clock Signal:
In electronics and especially synchronous digital circuits, a clock signal is a particular type of signal that oscillates between a high and a low state and is utilized like a metronome to coordinate actions of circuits. Circuits using the clock signal for synchronization may become active at either the rising edge, falling edge. In digital circuit, clock pulse can be expressed as CLK, CK or CP. Clock is of two types. a) Level Triggered Clock Pulse and b) Edge Triggered Clock Pulse. a) Level Triggered Clock Pulse: In level triggered clock pulse, for bit 1 and 0 the output of the device changes . If the output changes due to bit 1 then its called positive triggering or positive clocking. If output changes due to 0 then its called negative triggering.

b) Edge Triggering Clock Pulse:

Positive Edge Triggering:

This type of triggering is used for flip flops that are to respond during the LOW to HIGH transition state of a clock pulse. It is mainly identified from the clock input lead along with a triangle.

Positive Edge Triggering

4. Negative Edge Triggering

Negative Edge Triggering

This type of triggering is used for flip flops that are to respond during the HIGH to LOW transition state of a clock pulse. It is mainly identified from the clock input lead along with a low-state indicator and a triangle.

D flip-flop

The D ip-op is the most common flip-flop in use today. It is better known as data or delay flip-flop (as its output Q looks like a delay of input D). The Q output takes on the state of the D input at the moment of a positive edge at the clock pin (or negative edge if the clock input is active low). It is called the D flip-flop for this reason, since the output takes the value of the D input or data input, and delays it by one clock cycle. Truth table:
Clock
Rising edge Rising edge Non-Rising

D
0 1 X

Q
0 1 Qprev

Qprev
X X

JK Flip-Flop: A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate state of the SR type is defined in the JK type. Inputs J and K behave like inputs S and R to set and clear the flip-flop (note that in a JK flipflop, the letter J is for set and the letter K is for clear). When logic 1 inputs are applied to both J and K simultaneously, the flip-flop switches to its complement state, ie., if Q=1, it switches to Q=0 and vice versa. Output Q is ANDed with K and CP inputs so that the flip-flop is cleared during a clock pulse only if Q was previously 1. Similarly, ouput Q' is ANDed with J and CP inputs so that the flip-flop is set with a clock pulse only if Q' was previously 1.

(a) Logic diagram

(b) Graphical symbol Figure. Clocked JK flip-flop

(c) Transition table

T Flip-Flop
The T flip-flop is a single input version of the JK flip-flop. As shown in Figure, the T flip-flop is obtained from the JK type if both inputs are tied together. The output of the T flip-flop "toggles" with each clock pulse.

(a) Logic diagram Figure . Clocked T flip-flop

(b) Graphical symbol

(c) Transition table

The Master-Slave JK Flip-flop

The Master-Slave Flip-Flop is basically two gated SR flip-flops connected together in a series configuration with the slave having an inverted clock pulse. The outputs from Q and Q from the "Slave" flip-flop are fed back to the inputs of the "Master" with the outputs of the "Master" flip-flop being connected to the two inputs of the "Slave" flip-flop. This feedback configuration from the slave's output to the master's input gives the characteristic toggle of the JK flip-flop as shown below.
The Master-Slave JK Flip-Flop

The input signals J and K are connected to the gated "master" SR flip-flop which "locks" the input condition while the clock (Clk) input is "HIGH" at logic level "1". As the clock input of the "slave" flip-flop is the inverse (complement) of the "master" clock input, the "slave" SR flip-flop does not toggle. The outputs from the "master" flip-flop are only "seen" by the gated "slave" flip-flop when the clock input goes "LOW" to logic level "0". When the clock is "LOW", the outputs from the "master" flip-flop are latched and any additional changes to its inputs are ignored. The gated "slave" flip-flop now responds to the state of its inputs passed over by the "master" section. Then on the "Low-to-High" transition of the clock pulse the inputs of the "master" flip-flop are fed through to the gated inputs of the "slave" flip-flop and on the "Highto-Low" transition the same inputs are reflected on the output of the "slave" making this type of flip-flop edge or pulse-triggered.

Then, the circuit accepts input data when the clock signal is "HIGH", and passes the data to the output on the falling-edge of the clock signal. In other words, the Master-Slave JK Flip-flop is a "Synchronous" device as it only passes data with the timing of the clock signal.