AV8 Service Manual Issue2 Complete

Service Manual AV8
Issue 2.0
FMJ AV8
Preamp Processor
ARCAM
Contents List
Section Issue
Manual Updates
! Service Manual changes issue 1.0 to 2.0 -
Technical specifications
! Front & rear view diagram -
! Dimension diagram -
! Specification -
Service guide
! Engineering Mode -
! AV8 Programmer software -
! AV8 Loader software -
Build Sequence
! How to assemble the AV8 -
Phono board L870

! Circuit description -
! Component overlay 2
! Parts list 2.0
! Circuit diagrams 2.0
Digital board L896

! Parts list 1.6
PSU board L897

! Parts list 4.1
Display board L898

! Parts list 1.2
! Circuit diagrams 1.2 (N.B. circuit diagram marked as 1.1 not 1.2)
Audio board L921

! Parts list 1.2
Video board L922

Circuit description -
Component overlay 3
Parts list 3.2
Circuit diagrams 3.2
Phase Locked Loop board L948

Circuit description -
Component overlay 1
Parts list 1.0
Circuit diagrams 1.0
Mechanical
Mechanical parts list -
Phono card upgrade parts list -
Manual Updates
Service Manual changes issue 1.0 to 2.0
L896 Digital Board
02_E101 IC906 EEPROM changed from 5G24LC08 to 5G24LC16

Parts list updated to issue 1.3
02_E127 R803 removed from parts list
02_E160 R921 changed from 10K 0805 1% (1M310 ) to 33K 0805 1% (1M333)
02_E161 IC907 changed from 74HC14 (5K7414) to 74LVC14 (5KLVC14)
IC803 changed from CS8415A-CZ (5A8415) to CS8415A-CR (5A8415R)
R820 changed from 5K1 (1M251) to 1K2 (1M212)
C820 changed from 82N (2J382) to 100N (2J410)
C821 changed from 2N2 (2J222) to 4N7 (2JA247)
Circuit plus parts list updated to issue1.6
L897 Power Supply Board
02_E090 Vias added to connect chassis planes between top and bottom layers
Plating removed from holes of PSU heat sink HS3
On mechanical parts list for E918RS 1xHA3V06A removed and 1xHA3V10B added
02_E094 1xHA3V06A deleted
1xHA3V10A added for MOSFET clip
1x F224 removed
02_E142 R1 removed
Opto added HCNW137
Circuit plus parts list updated to issue 4.0
PCB changed to allow wider opto to be fitted
L898 Display Board
02_E081 R128 changed from 22K (1M322) to 33K (1M333)

arts list updated to issue1.2
L922 Video Board
02_E103 Change of PCB routing

02_E112 R431 and R430 changed from 4K7 (1M247) to 470R (1M147)
L948 Phase Locked Loop Board
02_E100 Circuit plus parts list updated to issue 1.0 for production release
Summary Issue 1.0 to 2.0

Update New section added
Technical Specification Specification included
Service Guide Engineering mode updated
AV8 programmer software added
AV8 Loader software added
Build Sequence Layout changes to manual
Figure 3 changed (F224 blanking plug removed)
Figure 8 changed (E042AY replaced with E876MC)
Figure 12 changed (note for blanking plug removed)
Digital Board L896 Updated circuit diagrams and parts list issue 1.2 to 1.6
Power Supply L897 Updated circuit diagrams to issue 4.0 and parts list issue to 4.1
Display Board L898 Updated parts list issue 1.1 to 1.2
Audio Board L921 Circuit plus parts list updated from 1.1 to 1.2
Video Board L922 Updated circuit diagrams and parts list issue 2.0 to 3.2
Phase Looked Loop L948 Updated circuit diagrams and parts list issue B to 1.0
Technical
Specifications
Contents
! Front & rear view

diagram
! Dimensions diagram
! Specifications
THX SURROUND EX
AV8 PREAMP PROCESSOR
THX EFFECT MODE
DISPLAY MENU OK DVD SAT AV VCR PHONO/AUX CD TUNER TAPE DVD-A DIRECT MUTE POWER
DESIGNED & MADE REMOTE DIGITAL INPUTS HIGH QUALITY VIDEO

IN THE UK BY:-
A & R CAMBRIDGE,
IN 1 2 VIDEO
WATERBEACH, CB5 9PB. DVD AV TAPE Y/G U/B V/R Y/G U/B V/R
OUT LOCAL
ZONE 2 1 2
VCR VCR
MONITOR OUT TAPE AV SAT DVD
RS232 OUT IN
CONTROL VIDEO
TRIGGERS MM
12V IN
50/60Hz OUT TUNER CD VCR SAT Y/G U/B V/R Y/G U/B V/R
TRIGGER ZONE 2 1/RGB 2/S-VIDEO PROG
100-240VAC~ OUT 3 MC
MAX 40VA
TAPE VCR
LEFT CENTRE SUB 2 L SURR LS BACK LEFT CENTRE L SURR LS BACK TUNER CD OUT IN OUT IN AV SAT DVD AUDIO
L L L
GROUND
LIFT (IN)
N1501
R R R
RIGHT SUB 1 SUB 3 R SURR RS BACK RIGHT SUB R SURR RS BACK ZONE 2 OUT AUX/
OUTPUTS DVD-A/SACD IN PHONO
SERIAL No. LABEL CAUTION – SHOCK HAZARD, DO NOT OPEN.
WARNING: THIS APPLIANCE MUST BE EARTHED ACHTUNG – VOR OEFFNEN DES GERAETES NETZSTECKER ZIEHEN. ATTENTION – RISQUE DE CHOC, NE PAS ENLEVER. PRECAUCION – PELIGRO DESCARGA, NO ABRIR.
Technical Specifications
Audio
Line input sensitivity (set to Reference) 2V rms
Input impedance 10k ohm
Preamp output level (nominal) 2V rms
Output impedance 25 ohm
Signal/noise ratio (unwtd 20Hz –20kHz)– analogue >100dB
Signal/noise ratio (unwtd 20Hz –20kHz)– digital (24-bit) >98dB
THD+N – analogue 0.0012%
THD+N – digital (24-bit) 0.0015%
Headphone maximum output level into 600 ohm 5V p-p
Output impedance 5 ohm
Video inputs and outputs

Input and output impedance 75 ohm
Composite video level 1V
HF response to (–3dB) 12MHz
S-video level (Y/C) 1V/0.28V
HQ (component) video
level (Y/Cr/Cb) 1V/0.5V/0.5V
level (R/G/B) 1V/1V/1V
Digital inputs
Coaxial connection (level/impedance) 0.5V/75 ohm
Acceptable sampling frequencies, all inputs 44.1kHz, 48kHz,
(96kHz stereo only)
Digital output
Output level/impedance 0.5V/75 ohm
Sampling frequency in ADC output mode 44.1kHz
Trigger outputs
Output D.C. voltage (excl. RGB status) 12V ±1V
Allowable load 30mA max (min 400 ohm)
Remote inputs and output
Signal modulated 36kHz carrier
Coding Philips RC-5
General
Mains voltage range 85V to 265V
Power consumption 35VA
Power consumption (standby) 32VA
Dimensions Width x Depth x Height (including feet) 433mm x 360mm x 130mm
Weight (net) 9kg
Weight (packed) 14kg
Supplied accessories Mains lead
CR80 remote control
2 x AAA batteries
Service Guide
Contents
! Engineering mode
! AV8 Programmer
software
! AV8 Loader software

AV8 Engineering Mode Restore Defaults
This allows you to reset the AV8 to the factory default
settings.
To access the software versions simultaneously press OK,
Diagnostics (For factory diagnostics only)
DVD & CD on the front panel.
This switches on RS232 messaging to allow remote
analysis (hyperterminal at 38400 baud, 8 data bits, no
The software versions will be displayed on the OSD.
parity, 1 stop bit and no flow control).
Please note that this will disable the RS232 interface for
AV8 Version: 2.0 user control via crestron or similar controllers.
THX Ul2: 13.0 DTS –ES: 15.0 Front Panel IR Rx

This allows you to disable the front panel IR receiver and
Dolby D: 16.0 DTSNeo6: 18.0 prevent the AV8 from responding to these signals.
Plogic 2 : 4.0 Cos Eff : 15.0
With the Engineering Menu title bar highlighted use the
volume control to select the second engineering page.
Exit this menu Engineering Menu 2
PLL Module
Select EXIT and OK to leave the menu. DVD : AUTO (or OFF)
SAT : AUTO (or OFF)
If no buttons have been pressed for 30 seconds the AV8
will automatically exit the menu. AV : AUTO (or OFF)
VCR : AUTO (or OFF)
Press THX, this takes you to the engineering menu first AUX : AUTO (or OFF)
page. CD : AUTO (or OFF)
Use the up/down buttons on the front panel to select the TUNER :AUTO (or OFF)
option followed by the volume control to adjust the TAPE : AUTO (or OFF)
setting.
EXIT
Engineering Menu
RC5 Code Zone 1 : 16* (or 19) If the source equipment clock rates are operating outside
the specification of the AV8 phase locked loop circuit you
RC5 Code Zone 2 : 16* (or 19) may experience “a hissing noise” from the audio outputs.
Scrolling Message: Off (or On) In this situation it is advisable to switch the phase locked
Restore Defaults: No (or Yes) loop circuit off of the input giving the problem. Using the
Diagnostics : Off (or On) second page of the engineering menu select the input and
turn the PLL (phase locked loop) from AUTO to Off.
Front Panel IR Rx : On (or Off) This can happen with Broadcast signals particularly from
satellite, cable or terrestrial digital TV.
EXIT
RC5 Code Zone 1

This allows you to select which RC5 system code zone 1
responds to (16 or 19). If set to code 19 the AV8 will not
respond to the CR80 remote control.
RC5 Code Zone 2

This allows you to select which RC5 system code zone 2
responds to (16 or 19).
Scrolling Message
This allows you to turn the display scrolling message
on/off. When the messages are turned on you can select
the displayed message by pressing the corresponding input
button.
Button Message
DVD Arcam AV8 FMJ Home Theatre
SAT AV8 Multichannel Processor
AV arcam sideways
VCR Arcam AV8 Sound and Vision
AUX AV8 Designed in Cambridge UK
CD Arcam AV8 Preamp Processor
TUNER AV8 THX ULTRA 2, DTS ES, DOLBY PL2
AV8 Programmer AV8 Loader (Preset Backup)
Future software upgrades can be installed via the RS232 The AV8 Loader utility allows the unit settings to be either
port on the back of the AV8. The following equipment will downloaded from or uploaded to the AV8. The following
be required: equipment will be required:
! IBM PC compatible computer running Windows 98 ! IBM PC compatible computer running Windows 98
or later or later
! Software – ARCAM AV8 Programmer utility ! Software – ARCAM AV8 Loader utility (included
(included on the AV8 CD-ROM) on the AV8 CD-ROM)
! Lead – RS232 9-way female D type to 9-way female ! Lead – RS232 9-way female D type to 9-way female
D type (null modem) D type (null modem)
Installation procedure
Installation procedure
The AV8 Programmer utility needs to be installed on your
PC before you can use it: The AV8 Loader utility can be run directly from the CD-
ROM, or you can copy the entire ‘Preset Backup Utility’
! Close down any programs which are running, then folder to your hard drive (e.g. C:\ Program Files \ Arcam \
insert the CD-ROM into the CD drive Preset Backup Utility).
! The setup program normally starts up automatically
when the disc is inserted. If this does not happen,
you can instruct the PC to install the program as Operation procedure
follows:
o Click on ‘Start’ and select ‘Run…’ from the To run the AV8 Loader program:
pop-up menu
o In the box, type ‘D:\setup.exe’, where ‘D’ is ! Connect the RS232 lead from the PC to the RS232
your CD-ROM drive control connector on the AV8
o Click ‘OK’ ! Switch off all the power amps connected to the AV8
! Run the AV8 Loader program:
The install process will then begin. You will be prompted o Click on ‘Start’ and select ‘Run…’ from the
for your Name, Organization and Destination Folder for pop-up menu
the installation (default is C:\Program Files\Arcam\AV8 o In the box, type ‘D:\ Preset Backup Utility \
Programmer\). Follow the instructions on-screen. AV8Loader_GUI.exe’ or the location of the file
on the hard drive if not using the CD-ROM
Operation procedure o Click ‘OK’
! Select the Com port you are using:
! Open the AV8 Programmer utility by double clicking o Select ‘File -> Settings…’
the desktop icon, or from the Programs list within the o Select the Com port you are using from the
Start menu drop down menu
! Switch off all the power amps connected to the AV8 o Close the window
! Switch off the AV8
! Connect the RS232 lead from the PC to the RS232 To download the settings from the AV8 to the PC:
control port on the AV8
! From within the AV8 Programmer software: ! Create a new backup file:
o Select the new software file to be uploaded o Select ‘File -> New…’
using the ‘Open file’ button o Locate a suitable place to save the backup file
o Select the Com port you are using (e.g. C:\ Program Files \ Arcam \)
! Put the AV8 into program mode: o Enter a name for the file in the ‘File name’ box
o Press and hold the program button on the back (e.g. AV8.epr). Note the ‘.epr’ name extension
of the AV8 (located with the video output o Click ‘Save’
connections) ! Download the AV8 settings:
o Turn the AV8 on with the program button still o Select ‘Transfer -> Download From AV8…’
pressed
o Wait 5 seconds and then release the program The AV8 Loader utility will then download the
button. The display will remain completely configuration from the AV8 and save it using the filename
blank and no LEDs will light. you gave. Once the setup is read from the AV8 it is
! From within the AV8 Programmer software: automatically stored as a “working file”.
o Click ‘Program’
To upload a configuration to the AV8 from the PC:
The PC will now upload the software and display the
following information: ! Locate the backup file you wish to upload:
Connecting: 0 to 100% o Select ‘File -> Open…’
Programming: 0 to 100% o Locate the folder where the backup file is saved
Verifying: 0 to 100% o Select the name of the ‘.epr’ file you wish to
upload
This process will take up to four minutes. When the o Click ‘Open’
software has been uploaded the message ‘Status: ! Upload the AV8 settings:
SUCCESS’ will be displayed. o Select ‘Transfer -> Upload To AV8…’
! Turn the AV8 off and unplug the RS232 lead The AV8 automatically resets after the configuration has
! Wait 10 seconds before turning the AV8 back on been uploaded.
If, after programming the AV8 the unit displays

“Populating EEPROM” when first turned on, it will be
necessary to reset the user configurations within the unit.
This is dependent on the degree of the software changes
and will not always be necessary.
Build
Sequence
Contents
! How to assemble the

AV8
1. Assemble the damping plate to chassis floor. Screw 6. Assemble 5x H038 to audio board, L921AY, using 5x
through from underneath the chassis and thoroughly degrease the HA3V06A in the holes running along the EMC can, only then fit
chassis floor before assembling the damping plate. See FIG1. the board into the chassis with the other 5x H039 pillars (do not fit
rear panel). Loosely screw all the pillars through the pcb into the
Part No. Description Qty chassis, once these pillars are in place tighten them all.
E816CH Chassis 1 See FIG5.
E873MC Damping Plate 1
HE6V06B Self-tapping No6x6mm Pan Torx-Slot 4
Part No. Description Qty
Steel Zinc-Plate Black
HF4V09B Screw Self-Tapping-SEMS No4x9mm 3
Pan Torx-Slot Steel Zinc-Plate Black
(into EMC shield)
2. Assemble the feet to the chassis. Screw through the
chassis floor into the foot. Stick the bumpon foot onto the base of H038 38 ff pillars 5
turned foot. See FIG2. H039 38 mf pillars 5
HA3V06A Screw Machine M3x6mm Pan Torx 5
Part No. Description Qty Steel Zinc-Plate Clear (from
E935MC Turned Foot 4 underneath)
Steel Zinc-Plate Clear
(into sockets)
F225 Black ‘Bumpon’ Foot 4
NB. Screws in italics are to be used when rear panel is fitted in
step 18.
3. Assemble the power socket to rear panel before

assembling the rear panel to the chassis. See FIG3. 7. Once the audio board is in place, fit the following
cables to the audio board. Ensure the cables, especially the flex
Part No. Description Qty foil, are the correct way round.
E040AY Rear Panel Assembly 1
8A016 8A016 IEC Inlet with EMI Filter 1 Part No. Description Reference Qty
YB10T1 L925CA 8-way AMP CT from SK901 1
HA3V10B Screw Machine M3x10mm Pan Torx- 2 audio to snap-off 280mm
Slot Steel Zinc-Plate Black L927CA 6-way AMP CT from SK801 1
HJ3A00F Nut Nyloc M3 Steel Zinc-Plate Clear 2 audio to horiz power
HL3IB Washer Internal Shakeproof M3 Steel 2 100mm
Zinc-Plate Black L930CA 5-way AMP CT from SK917 1
headphone to audio
250mm
4. Assemble power loom to IEC power inlet before L922CA 22-way foil cable from SK916 1
assembling the rear panel to the chassis. The live connection is digital to audio 100mm
the right hand spade as viewed from behind (spade terminals) L933CA 5-way AMP CT from SK915 1
with the earth spade at the top. digital to audio 100mm
L923CA 8-way AMP CT from SK913 1
Part No. Description Qty digital to audio 120mm
L939CA AV8 power loom 1 L923CA 8-way AMP CT from SK914 1
digital to audio 120mm
5. N.B. If a phono card is to be fitted then you do not fit

the “Aux” snap-off board at this stage, move to step 6. See step
23 for fitting the Phono upgrade kit.
Fit the “Aux” input snap-off board (snap-off from Audio board,
L921AY) to the rear panel before assembling the rear panel to the
chassis. See FIG4.

FIG1
FIG2
FIG3
FIG4
FIG5
8. Fit the video board (L922AY – main board) to the 11. Fit the horizontal power PCB (L897AY – snap-off
chassis (do not fit rear panel yet). Ensure the board is pushed to part 2) using 6x HA3V06A screws into standoffs. Refer to FIG8.
the back of the chassis before tightening down the board. Use Once the pcb is in place, fit the cables below.
the H041 pillars in the two holes closest to the S-video
connectors (right hand side nearest the EMC screen as viewed
from the connector side). See FIG6. Part No. Description Reference Qty
HA3V06A Screw Machine 6
Part No. Description Qty M3x6mm Pan Torx
HF4V09B Screw Self-Tapping-SEMS No4x9mm 2 Steel Zinc-Plate Clear
Pan Torx-Slot Steel Zinc-Plate Black into standoffs
(into EMC shield) L925CA 8-way AMP CT from SK5 1
H041 22 mf pillars 2 horiz power to digital
HA3V06A Screw Machine M3x6mm Pan Torx 9 280mm
Steel Zinc-Plate Clear thro’ video PCB L926CA 7-way AMP CT from SK7 1
into standoffs horiz power to digital
HF4V09B Screw Self-Tapping-SEMS No4x9mm 9 350mm
Pan Torx-Slot Steel Zinc-Plate Black L928CA 6-way AMP CT from SK2 1
(thro’ RP into sockets) horiz power to digital
540mm
Once the video board is in place, fit the following horiz power to phase
cables to the video board: lock loop 280mm
Part No. Description Reference Qty

L922CA 22-way foil cable from SK700 1 Connect the following cables using the reference table below:
top video to video
100mm Part No. From To
L925CA 8-way AMP CT from SK1000 1 L927CA Audio / SK801 Horizontal power /
video to horiz power SK3
280mm L925CA Video / SK1000 Horizontal power /
L931CA 30-way foil cable from SK702 1 SK5
digital to video 190mm N.B. The Video cable L925CA has an excess of length so that the
video board may be removed but still remain connected when the
unit is serviced. A cable tie should be used to hold this excess
9. Fit the top video board (L922AY – sub board) to when the board is installed.
chassis (do not fit rear panel). See FIG7.
12. Fit the mains power button to the power switch, with
Part No. Description Qty the button to the top. Refer to FIG8.
Pan Torx-Slot Steel Zinc-Plate Black Part No. Description Qty
(into EMC shield) E887PM DiVA power button adapter 1
HA3V06A Screw Machine M3x6mm Pan Torx 2 E850PM FMJ mains button (silver) 1
Steel Zinc-Plate Clear through top E850PMB FMJ mains button (black)
video PCB into standoffs
Pan Torx-Slot Steel Zinc-Plate Black 13. Fit the vertical power PCB. Once the pcb is in place,
(thro’ RP into sockets) fit the cable specified below.
Connect L922CA from the video board (SK700) to the top-video Part No. Description Reference Qty
board (SK209) HA3V06A Screw Machine 2
M3x6mm Pan Torx
10. Fit the power can using 2x HA3V06A into standoffs. Steel Zinc-Plate Clear
See FIG8. into standoffs
Part No. Description Qty digital to vertical
E876MC Power Can 1 power 220mm
Steel Zinc-Plate Clear into standoffs
14. Fit the headphone PCB (snap-off from video board).
Fit with socket facing to the front. Refer to FIG8.

Steel Zinc-Plate Clear into standoffs
Connect L930CA from audio board (SK917) to the headphone

board (SKP1).
FIG6
FIG7
FIG8
Connect the cable assemblies listed below.
15. Fit the digital PCB (L896AY) such that the notch in
the board is by the headphone board. Once the pcb is in place, fit Part No. From To
the cables below. See FIG9. L939CA IEC Inlet Horizontal Power /
SK1
Part No. Description Reference Qty L925CA Audio / SK901 Aux snap-off / SK927
H039 M3x38mm mf pillars 7
into standoffs
H030 M3x18mm mf pillars 4 19. Assemble the phono can assembly to the chassis (3
into standoffs screws) and the rear panel (1 screw) making sure the cable loom
L931CA 30-way foil cable from SK901 1 fits into notch in top of the phono can. See FIG11.
digital to display 190mm
L923CA 8-way AMP CT from SK903 1 Part No. Description Qty
digital to phase lock loop E041AY Phono Can Assembly 1
120mm HF4V09B Screw Self-Tapping-SEMS 4
L933CA 5-way AMP CT from SK801 1 No4x9mm Pan Torx-Slot Steel
digital to phase lock loop Zinc-Plate Black
100mm
Connect the cable assemblies listed below. 20. Assemble the display PCB to the fascia assembly
Part No. From To Part No. Description Qty

L923CA Audio / SK914 Digital / SK102 E919AY Fascia Assembly (silver) 1
L923CA Audio / SK913 Digital / SK103 E919AYB Fascia Assembly (black)
L933CA Audio / SK915 Digital / SK100 HA3V06A Screw Machine M3x6mm Pan Torx 14
L922CA Audio / SK916 Digital / SK902 Steel Zinc-Plate Clear into standoffs
L931CA Video / SK702 Digital / SK900
L929CA Vertical Power / SK8 Digital / SK1002
21. Assemble the fascia assembly and the display PCB to
L925CA Horizontal Power / Digital / SK1001 the chassis. Check the operation of mains button at this stage.
SK6 Keep the foil bent upwards. Connect the flexfoil after the fascia
L926CA Horizontal Power / Digital / SK1003 assembly is fitted to the chassis.
SK7
L928CA Horizontal Power / Digital / SK1000 Part No. Description Qty
SK2 HE6V06B Self Tapping No6x6mm Pan Torx- 4
Slot Steel Zinc-Plate Black
16. Fit the phase lock loop PCB (L948AY). See FIG9.
Connect L931CA from the digital board (SK901) to the display
Part No. Description Qty board (SK100).
H030 M3x18mm mf pillars into standoffs 4
Connect the cable assemblies listed below. 22. Assemble the cover plate to the chassis
Part No. From To Part No. Description Qty

L923CA Digital / SK903 Phase lock loop / SK1 E826CP Cover Plate (Silver) 1
L933CA Digital / SK801 Phase lock loop / SK3 E826CPB Cover Plate (black)
L925CA Horizontal Power / Phase lock loop / SK2 HA4V06S Screw Machine M4x6mm Pan Torx 4
SK4 St Steel Nickel
HA4V06B Screw Machine M4x6mm Pan Torx
17. Clip 2 F219 cable clips into top of EMC shield. Then St Steel Black
using the cable clips as handles fit EMC digital PCB shield. HF4V09B Screw Self-Tapping-SEMS 4
Refer to FIG9. No4x9mm Pan Torx-Slot Steel
Zinc-Plate Black
E919MC Digital EMC Shield 1
HA3V06A Screw Machine M3x6mm Pan Torx 11 23. Fit the Phono Board Upgrade Kit, using L870AY
Steel Zinc-Plate Clear into standoffs board and the following parts. See FIG12 for assembly
thro’ EMC shield into pillars instructions.
F219 Twist Lock cable clip 2
18. Assemble the rear panel to the chassis using all the H031 20 ff pillars 3
screws in italics on previous pages. Fit the power can lid over HF4V09B Screw Self-Tapping-SEMS 1
the chassis and the vertical can wall with vents directly above the No4x9mm Pan Torx-Slot Steel Zinc-
EMC can on the power board. See FIG10. Plate Black into rear panel
Part No. Description Qty Steel Zinc-Plate Clear into pillars
HF4V09B Screw Self-Tapping-SEMS No4x9mm 6 L925CA 8-way AMP CT from phono (SK2) to 1
Pan Torx-Slot Steel Zinc-Plate Black audio (SK901) 280mm
(rear chassis return) 8-way connector 2
E877MC Power Can Lid 1
(2 into power can wall and 2 into
chassis wall)
FIG9
FIG10
FIG11
FIG12
Phono
Board
L870
Contents
! Circuit description
! Component overlay
! Parts list
! Circuit diagrams
AV8 Phono Board
Circuit Description
Refer to circuit diagram L870 sheet 1
The phono board is a simple single stage RIAA amplifier
and consists of two channels of high gain amplification,
and the ability to switch between moving magnet (MM)
and moving coil (MC) settings.
PSU
The unit derives its + 15V regulated rails from the unit it is
fitted into with only local decoupling capacitors on board.
Interface
The unit connects to the host unit via a 8 way connector.
Amplification
The left channel has designators beginning with 100, and
the right with 200. For the purposes of this description the
left channel will be described, as the right channel is the
same in all respects.
The amplifier is a small signal class A voltage feedback

amplifier with switch able gain. The input consists of an
actively loaded differential pair of very low noise PNP
transistors (TR106, TR107). These transistors are very
specific and should only be replaced with identical parts
with the E grade high gain. TR100 and TR101 form a
current source for the pair, which sets the quiescent current
for the entire amplifier. The active load consists of TR110
and TR111, which forms part of the differential current
mirror with TR112, TR113 & TR114. This differential
stage also has an active load (TR102 & TR103) to keep
gain to a maximum.
Both of these differential stages are designed to have as

much gain as possible to enable the single stage design.
The RIAA response is achieved in the feedback network:
C101, C110, C111, C112, C119, C120 and R115, R112.
C115 is used to correct between MM and MC gains as the
amplifier is non-inverting.
SW100 switches between MM and MC. Two poles of the

switch change between the different loading required for
each type of the cartridge: R108 & C109 for MM and
added in parallel for MC R104 & C108. The other two
poles change the feedback resister value to alter the gain:
R105 for MM and added in parallel for MC R123.
The DC offset is controlled by a non-inverting servo built

around IC100. The amount of servo current is different for
each gain setting via R111 (MM) and R124 (MC) so that
the low frequency high pass point remains the same for
both settings. However the high pass point for the circuit
is set by C113. This gives a warp filter, stops DC start-up
thumps from upsetting DC coupled circuitry and an
approximation of the RIAA/IEC curve (-2dB @ 20Hz)
The output is class A buffered by a dual mirror follower

(TR104, TR105, TR108, TR109). The quiescent current is
set by D100 and R118 and R119.
Closed loop stability is achieved with C16, C117, giving

symmetrical slewing capability.
L870 Phono Board Parts List Issue 2.0
Designator Part Description

C1 2A410 CERD 100N 63V -20% +80% RA
C100 2N622 ELST 22U 63V
C101 2D210 PPRO 1N0 5% 63V RA
C102 2P710AS ELEC 100U 25V SILMIC
C104 2K410 PEST 100N 63V 10%
C105 2K410 PEST 100N 63V 10%
C106 2K410 PEST 100N 63V 10%
C107 2K410 PEST 100N 63V 10%
C108 2D147W PPRO W 470P 63V 5% RA
C109 2D110W PPRO W 100P 63V 5% RA
C110 2D247N PPRO 4N7 63V 5% RA
C111 2D310 PPRO 10N 63V 1% AXIAL
C113 2K510 CAP MKS2 1U0 16V 10%
C115 2D213N PPRO 1N3 63V 5% RA
C116 2D147W PPRO W 470P 63V 5% RA
C117 2D147W PPRO W 470P 63V 5% RA
C118 2U610 ELST NON POLAR 10UF 35V
C119 2D110N PPRO 100P 63V 5% RA
C120 2D210 PPRO 1N0 5% 63V RA
C200 2N622 ELST 22U 63V
C201 2D210 PPRO 1N0 5% 63V RA
C204 2K410 PEST 100N 63V 10%
C205 2K410 PEST 100N 63V 10%
C206 2K410 PEST 100N 63V 10%
C207 2K410 PEST 100N 63V 10%
C208 2D147W PPRO W 470P 63V 5% RA
C209 2D110W PPRO W 100P 63V 5% RA
C210 2D247N PPRO 4N7 63V 5% RA
C213 2K510 CAP MKS2 1U0 16V 10%
C215 2D213N PPRO 1N3 63V 5% RA
C216 2D147W PPRO W 470P 63V 5% RA
C217 2D147W PPRO W 470P 63V 5% RA
C218 2U610 ELST NON POLAR 10UF 35V
C219 2D110N PPRO 100P 63V 5% RA
C220 2D210 PPRO 1N0 5% 63V RA
D100 3A4148 SSDIODE 1N4148 75V
D101 3A4148 SSDIODE 1N4148 75V
D102 3A4148 SSDIODE 1N4148 75V
D200 3A4148 SSDIODE 1N4148 75V
D201 3A4148 SSDIODE 1N4148 75V
D202 3A4148 SSDIODE 1N4148 75V
IC100 5B071 IC FET OPAMP TL071
IC200 5B071 IC FET OPAMP TL071
PCB1 L870PB_2 PRINTED CIRCUIT BOARD
R100 1H133 RES MF W4 1% 330R
R101 1H110 RES MF W4 1% 100R
R102 1H110 RES MF W4 1% 100R
R104 1H110 RES MF W4 1% 100R
R105 1H110 RES MF W4 1% 100R
R106 1H110 RES MF W4 1% 100R
R108 1H347 RES MF W4 1% 47K
R109 1H312 RES MF W4 1% 12K
R110 1H312 RES MF W4 1% 12K
R111 1H356 RES MF W4 1% 56K
R112 1H410 RES MF W4 1% 100K
R113 1H410 RES MF W4 1% 100K
R114 1H410 RES MF W4 1% 100K
R115 1H315 RES MF W4 1% 15K
R116 1H522 RES MF W4 1% 2M2
L870 Phono Board Parts List Issue 2.0

R117 1H522 RES MF W4 1% 2M2
R118 1H022 RES MF W4 1% 22R
R119 1H022 RES MF W4 1% 22R
R120 1H022 RES MF W4 1% 22R
R121 1H022 RES MF W4 1% 22R
R122 1H339 RES MF W4 1% 39K
R123 1H010 RES MF W4 1% 10R
R124 1H256 RES MF W4 1% 5K6
R200 1H133 RES MF W4 1% 330R
R201 1H110 RES MF W4 1% 100R
R202 1H110 RES MF W4 1% 100R
R204 1H110 RES MF W4 1% 100R
R205 1H110 RES MF W4 1% 100R
R206 1H110 RES MF W4 1% 100R
R208 1H347 RES MF W4 1% 47K
R209 1H312 RES MF W4 1% 12K
R210 1H312 RES MF W4 1% 12K
R211 1H356 RES MF W4 1% 56K
R212 1H410 RES MF W4 1% 100K
R213 1H410 RES MF W4 1% 100K
R214 1H410 RES MF W4 1% 100K
R215 1H315 RES MF W4 1% 15K
R216 1H522 RES MF W4 1% 2M2
R217 1H522 RES MF W4 1% 2M2
R218 1H022 RES MF W4 1% 22R
R219 1H022 RES MF W4 1% 22R
R220 1H022 RES MF W4 1% 22R
R221 1H022 RES MF W4 1% 22R
R222 1H339 RES MF W4 1% 39K
R223 1H010 RES MF W4 1% 10R
R224 1H256 RES MF W4 1% 5K6
SK1 8D230 PHONO SKT 2-WAY HOR EMC GOLD
SK2 8K2408 8-WAY AMP CT CONN
SW100 A1013 SW PUSH 4PCO
TR100 4A556 TRANS LF SS P BC556B
TR106 4A1085 TRANS LF SS P 2SA1085
TR108 4A546 TRANS LF SS N BC546B
1 2 3 4 5 6 7 8
D D
C C
LEFT CHANNEL
Q_1 L870C2_2.0.SCH +15V
SK1 Q_3
LEFT IN LEFT OUT
PHONO2HG SK2
1 Q_5 1
2
3
4
EMC 0V_SIG 5
C1 Q_2 RIGHT CHANNEL 6
100N CD L870C3_2.0.SCH 7
Q_4 Q_6 8
RIGHT IN RIGHT OUT
0V_SIG AMPCT8
Q_7 -15V Q_8
0V_SIG 0V_HF
B B
PCB1 DRAWING TITLE

A EL1 A
PCB
A85 PHONO STAGE - TOP LEVEL
Update Box
Circuit Diagram
23425
UPDATE_BOX
L870PB_2
Notes:
01_1070 JAG 17/4/01 updated pcb and scm 2
A & R Cambridge Ltd.
Pembroke Avenue 00_1051 JAG 22/3/01 PRODUCTION ISSUE 1
Denny Industrial Centre ECO No. INITIALS DATE DESCRIPTION OF CHANGE ISSUE
Waterbeach Drawn by:
Cambridge CB5 9PB Filename Date Printed
Sheet 1 of 3
G:\DATA\ECO\ECO AGENDA\01_1070 l870 A85 PHONO ISSUE2\L870_2.0.ddb - L870c1_2.0.PRJ 23-Apr-2001 JBR DRAWING NO. L870C1
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
+15V
Q_102
+
C102 C104
100U SILMIC
100N PE
C119
D 0V_HF 0V_SIG D
R100 R101 R102
330R MF 100R MF 100R MF
100P PP
C101
TR100
BC556B TR102
1N0 PP TR103
BC556B BC556B
C110
TR101
BC556B
+ C100 4N7 PP
22U EL C120
R109 1N0 PP
12K MF C112
TR108 TR109
10N PP AX BC546B BC546B
C111
R115
R110
12K MF 15K MF
10N PP AX
R118
LEFT IN R112 22R MF
100K MF D100
SW100B 1N4148 C106
C 4PCO 100N PE C113 C
C105
C115 100N PE R116 LEFT OUT
1N3 PP
1U0 PE
6
2M2 MF
R119
TR106 TR107
7
IC100 22R MF R122
2SA1085 2SA1085 R117
3 C118 39K MF
R111 Q_101 6 2M2 MF
56K MF 2
TL071CD 10U NP
R124
4
SW100D 5K6 MF R113 0V_SIG
R108 4PCO 100K MF TR104 TR105
47K MF BC556B BC556B
R104 C109
10
11
100R MF C108 100P PPW 12

470P PPW R105 R123 R114
100R MF 10R MF 100K MF
C117
C116
0V_SIG 0V_SIG 470P PPW
470P PPW
TR112 TR113
BC546B BC546B
B B
TR110
BC546B TR111
BC546B
TR114
BC546B
D101 D102
1N4148 1N4148
R106
100R MF
R120 R121 + C107

22R MF 22R MF 0V_HF C103 0V_SIG 100N PE
100U SILMIC
Q_103 -15V
DRAWING TITLE
A A
A85 PHONO STAGE - LEFT CHANNEL
Circuit Diagram
23425 Notes:
Sheet 2 of 3
1 2 3 4 5
G:\DATA\ECO\ECO AGENDA\01_1070 l870 A85 PHONO ISSUE2\L870_2.0.ddb 6
- L870C2_2.0.SCH 23-Apr-2001 JBR 7 DRAWING NO. 8L870C2
1 2 3 4 5 6 7 8
+15V
Q_202
+
C202 C204
100U SILMIC
100N PE
C219
D 0V_HF 0V_SIG D
R200 R201 R202
330R MF 100P PP 100R MF 100R MF
C201
TR200
BC556B TR202
TR203
1N0 PP BC556B BC556B
C210
TR201
BC556B
+ C200 4N7 PP
22U EL C220
R209 1N0 PP
12K MF C212
TR208 TR209
10N PP AX BC546B BC546B
C211
R215
R210
12K MF 15K MF
10N PP AX
R218
RIGHT IN R212 22R MF
100K MF D200
SW100A 1N4148 C206
C 4PCO 100N PE C213 C
C205
C215 100N PE R216 RIGHT OUT
1N3 PP 1U0 PE
3
2M2 MF
R219
TR206 TR207
7
IC200 22R MF R222
2SA1085 2SA1085 R217
3 39K MF
R211 Q_201 6 2M2 MF
56K MF 2
TL071CD C218
SW100CR224 10U NP
4
4PCO 5K6 MF R213 0V_SIG
R208 100K MF TR204 TR205
47K MF BC556B BC556B
C208 C209
R204
7
100R MF 100P PPW 9

R205 R223 R214
470P PPW 100R MF 10R MF 100K MF
C217
0V_SIG 0V_SIG C216 470P PPW
470P PPW
TR212 TR213
BC546B BC546B
B B
TR210
BC546B TR211
BC546B
TR214
BC546B
D201 D202
1N4148 1N4148
R206
100R MF
R220 R221 + C207

22R MF 22R MF 0V_HF C203 0V_SIG 100N PE
100U SILMIC
Q_203 -15V
DRAWING TITLE
A A
A85 PHONO STAGE - RIGHT CHANNEL
Circuit Diagram
23425 Notes:
Sheet 3 of 3
1 2 3 4 5
G:\DATA\ECO\ECO AGENDA\01_1070 l870 A85 PHONO ISSUE2\L870_2.0.ddb 6
- L870C3_2.0.SCH 23-Apr-2001 JBR 7 DRAWING NO. 8L870C3
Digital
Board
L896
Contents
! Component overlay
! Parts list
! Circuit diagrams
Pin22 SIGGND - signal ground
AV8 Digital Board Pin23 TXDATA - txdata
Pin24 DGND - digital ground via 22R
Pin25 DEM1 - demod1
Introduction Pin27 DEM2 - demod2
Refer to circuit diagram L896 sheet 1 Pin28 DGND - digital ground via 22R
Pin29 SPDIFATX - spdif adc tx
The AV8 digital board is the heart of the AV8 surround sound Pin30 DGND - digital ground via 22R
decoder. It includes the H8S system control micro, the RS232
interface chip, the two Crystal DSPS one used for the surround
sound decoding the other for THX post processing, a SPDIF SK901 connections to display board
receiver, four DACS, the bass redirection multiplexers and one Pin1 0VF2GND
ADC along with the associated support circuits and Power Pin2 P5VF2
supply.
Pin3 P36VF1
Pin4 0VF1GND
Connections Pin5 DISPBLK
Pin6 DGND
SK100 ADC input Pin7 DISPLAT
Pin1 AGND Pin8 DGND
Pin2 Analogue right input Pin9 DISPCLK
Pin3 AGND Pin10 DGND
Pin4 Analogue left input Pin11 DISPDAT
Pin5 AGND Pin12 P3V3D
Pin13 FCK2 - fclock2
Pin14 FCK1 - fclock1
SK102 DAC output for left, right, centre and sub
Pin15 DGND
Pin1 DACL
Pin16 IRFP - irfp in
Pin2 DACGL
Pin17 LEDEN - led enable
Pin3 DACR
Pin18 PHB - phase B
Pin4 DACGR
Pin19 PHA - phase A
Pin5 DACC
Pin20 KEYB2 - keyB2
Pin6 DACGC
Pin21 KEYB1 - keyB1
Pin7 DACS
Pin22 KEYB0 - keyB0
Pin8 DACGS
Pin23 P5VD
Pin24 KEYBL - keyboard latch
Pin25 DGND
SK103 DAC output for left / right surround and left / right
surround back Pin26 LEDL - led latch
Pin1 DACLS Pin27 DGND
Pin2 DACGLS Pin28 KEYBCK - keyboard clock
Pin3 DACRS Pin29 DGND
Pin4 DACGRS Pin30 KEYBD - keyboard data
Pin5 DACLSB
Pin6 DACGLSB
SK902 connections to audio board
Pin7 DACRSB
Pin1 PHINS - phones inserted 3V3
Pin8 DACGRSB
Pin3 AUDSD - aud sdata
SK900 connections to video board Pin4 DGND - digital ground via 22R
Pin1 VIDSD - video serial data Pin5 AUDSCK - aud sclock
Pin2 DGND - digital ground via 22R Pin6 DGND - digital ground via 22R
Pin3 VIDSCLK - video serial clk Pin7 AUDSEL0 - aud sel 0
Pin5 VIDCL - video comp latch Pin9 AUDSEL1 - aud sel 1
Pin6 VIDSL - video svid latch Pin10 DGND - digital ground via 22R
Pin7 SPDIFL - spdif latch Pin11 AUDSEL2 - aud sel 2
Pin8 VIDZCS - video zone2 cs Pin12 DGND - digital ground via 22R
Pin9 VIDOC - video osd cs Pin13 AUDCTRL - aud control enable
Pin10 Z2 VID - zone2 video in present Pin14 DGND - digital ground via 22R
Pin11 OSDVID - osd video in present Pin15 DGND - digital ground via 22R
Pin12 PROG - Program Pin16 DGND - digital ground via 22R
Pin13 VSYNC - vsync Pin17 DGND - digital ground via 22R
Pin15 VSYNCZ2 - vsync zone2 Pin19 DGND - digital ground via 22R
Pin17 CSYNC - comp sync Pin21 DGND - digital ground via 22R
Pin19 SPDIFRX - spdif rxn
Pin21 RX DATA - rxdata
and stereo DAC. The DAC is in hardware configuration mode
SK1000 (the control of emphasis and serial interface mode is set by
Pin1 P18V pulling pins high and low on the DAC). The serial interface is
Pin2 AGND set to I2S. The pins DM0 and DM1 control the de-emphasis
Pin3 N18V filters and are controlled via a serial to parallel latch (IC905)
Pin4 P21V connected to the micro.
Pin5 AGN
DAC reset is used to initialise the part and is under the control
Pin6 N21V
of the microprocessor via a latch (IC905), it is an active low
signal. DAC MUTE on the same latch is an active low signal
and forces a soft mute of the output of the DAC.
SK1001
Pin1 P12V The serial audio data interface consists of the DAC I2S LRCLK,
Pin2 DGND DAC I2S BCLK and DAC I2S DATA.
Pin3 N12V DAC I2S LRCLK is the left right clock for the audio frames it
Pin4 DGND should be a square wave at the sampling frequency. The signal
Pin5 P5V is low during the left frame and high during the right frame.
Pin6 DGND DAC I2S BCLK is the bit clock for the data and data is clocked
Pin7 P3V3 into the DAC on the rising edge of this clock. The bit clock
Pin8 DGND operates at 64 times the left right clock.
DAC I2S DATA is the actual audio data it is should be
presented in I2S format that is one bit offset MSB first data of
SK1002 up to 24bits. Each data frame consists of 32bits one offset bit 24
Pin1 PSU SYNC data bits and 7 empty zero bits. (If the actual data is less than 24
bits (i.e. from CD) the unused bits may also be empty zero.)
Pin2 PSU GOOD
Pin3 PSU KILL
The output of the DAC is differential on the pins 16,17 for left
Pin4 DGND and 12,13 for right. This signal passes into a second order
multiple feedback type balanced to single ended filter. The filter
is a second order Bessel function with a three dB point of
SK1003 approximately 75KHz. This filter has been reworked on the
Pin1 P36VF1 Bass output to have a three dB point of approximately 300Hz to
Pin2 0VF1 reduce the HF noise introduced by the bass management section.
Pin3 P36VSET The filter is unity gain however the balanced to single ended
Pin4 P5VF2 conversion introduces a gain of two. The output of the balanced
Pin5 OVF2 to single ended converter should be 2Vrms for a full scale input.
Pin6 P5VF2SET Following the filter is a buffer stage. The buffer stage performs
Pin7 N/C two functions, it is a virtual earth mixer used to mix bass
information into the other channels when a sub woofer is not
present. Switching the CMOS switch 74HCT4053 controls the
mix. The control of the CMOS switch is under microprocessor
ADC control via a latch (IC904). The second function of the buffer is
Refer to circuit diagram L896 Sheet 2 to provide a ground sense to the Audio board. This allows the
two boards to be loosely connected via a high impedance
The signals to the ADC are converted to balanced by the three without introducing hum. The difference between the grounds
opamps that also correct the level to the input of the ADC so on the two PCBS is sensed by the positive input of the opamp
that 2VRMS on the input of the first opamp provides a full-scale and added into the signal, this effectively removes any ground
input to the ADC. 2.45V p-p (Note: not RMS) variation between the two PCBS. The full-scale output of the
A bias is added to the incoming signal so that it can be input to DAC should produce 2v RMS at the output of the buffer stage.
the ADC analogue section which operates on a single 5V rail.
The bias is generated by the potential divider R216 and R217 DAC performance specification
this is 1.75V it is amplified by 1.43 by the opamp to give
approximately 2.5V at the output of the opamps IC202 and THD better than -95dB (0.0018%)
IC203. Noise level at output of buffer better than -100dB ref 2VRMS or
94dBV
The diodes D200, D201, D202, D203 prevent over voltage Frequency response +/- 0.4dB 10Hz to 20KHz
signals from being presented to the input of the ADC, they do
not protect the ADC if one of the opamp fails, as the diode will The other components on the circuit are decoupling for the
blow as well. The ADC itself is set to operate as a master for the DAC, OPAMP and CMOS multiplexer. VMIDR and VMIDL
I2S interface and to have its internal high pass filter enabled. are the output bias chains and should be at approximately half
the Analogue Voltage rail (2.5V). AVDDL and AVDDR are the
Data is output from the ADC on pin 15, it also generates a bit logic supply rails for the digital filter and the switched capacitor
clock at 64xFS on pin 14 and a word clock at Fs on pin 13. The filter.
master clock on pin 17 is an input and should be at 256xFs.
DSP
DAC Refer to circuit diagram L896 Sheet 7
Refer to circuit diagram L896 Sheets 3,4,5,6
This is the Digital signal Processor sheet. IC701 is the main
The DAC sheets are all essentially the same and so are only DSP it decodes the in coming data stream to provide the 5
described once below. The Sub DAC output has some minor channels of discrete audio from Dolby Digital, DTS or MPEG
differences that are described in the text. encoded material or a matrix decode of stereo information to 4
or five channel. The decoded data is passed to the second DSP
The DAC is a 24bit 192KHz part it consists of a serial interface IC702 that performs post processing on the signal, performing
port, digital interpolation filter, multi bit sigma delta modulator the THX equalisation Tone controls and Bass management.
The signal arrives at the first DSP either on the SPDIF I2S SPDIF RST This is the reset signal, at power up it is held low to
DATA line from the digital inputs or on ADC DATA 3.3V for keep the device in reset until the power is stable.
analogue inputs. The SPDIF chip generates the clocks for its
interfaces, and the master clocks as it is the system master. The IC802 is the master clock buffer and fans out the master clock to
ADC generates its own bit clock and word clock from the the other chips inside the product. Each line is series terminated
master clock it receives from the ADC. When the ADC is in use to reduce reflections on the line.
the master clock is generated by an 11.2896MHz crystal
attached to the SPDIF receiver (IC803).
Microprocessor
The audio data is passed between the two DSPS in a time
domain multiplexed form on the DSP_AUD0 line. The clocks
Refer to circuit diagram L896 Sheet 9
for this line are on DSP1_SCLK and DSP1_LRCLK. As six
This sheet contains the circuits for the H8S micro-controller.
channels are passed between the two DSPS the interfaces works
The micro-controller has control of all the system functions via
at 3x the normal I2S speed. (3x stereo channels equal to six
its I/O ports.
channels).
UARTS
Audio data passes out of the second DSP IC IC702 to the four
DAC’s via the serial terminators on pins 41 40 39 and 3. At this
The RS232 port is connected to one (TXD1 RXD1) of the three
point the audio data is in I2S format. The DSP generates clocks
UART interfaces the other two are used for the serial VFD
for this audio data on pins 43 and 42 these are re-clocked and
display updates (TXD0, SCK0) and the control of the DSP chips
buffered by IC1102 and IC1100.
(TXD2, RXD2, SCLK2).
A system clock is passed to the DSP via pin30. This clock is
RS232 input is buffered via IC902, which generates and
multiplied inside the DSP chip using a phase locked loop. The
receives the levels required for RS232 communication (+/- 12V)
phase locked loop filter (PLL) is made up of the components on
pins 33 and 32. A smoothed supply is provided for the PLL via
INTERUPTS
the ferrites L701 and L700.
Pins 33,34,37,38 are used as interrupts to the micro-controller.
Control of the DSPs from the micro-controller is via an SPI
Pin 33 is the SPDIF interrupt, Pins 34 and 37 are the interrupts
(serial peripheral interface) and uses pins 6,7,18,19,20. SPI is a
from the two DSP chips and 38 is the power fail interrupt.
Serial interface with clock (pin 7) and chip select (pin 18) in this
implementation the read (pin 6) and write (pin19) lines are
RESET
independent and pin 20 is the interrupt line.
The chip reset is formed using the Schmitt trigger inverters in
Chips IC704 to IC708 are the SRAM and SRAM interface.
IC907 and the RC delay formed of C936 and R921. This is used
IC704 is a level shifter from the 2.5V out of the DSP’s to the
to latch the information on the program button through the d-
3.3V of the SRAM The components IC705 IC706 IC707 are
type flip-flop IC908A. The reset is further delayed by the RC
the address latch. The address from the 8bit port on the DSP is
C903 R916 then used to release the reset on the Micro-
latched through these three chips to form a 19 bit address for the
controller. This is so that the micro-controller mode (Program or
SRAM chip. IC708 is the SRAM chip. The SRAM interface is
normal run) is set up before the reset is released on the micro.
used to provide the lip-sync function within the DSP.
DSP Clock
The clock for the DSP is generated from the Micro-controller

SPDIF clock and is output on PF7/0.
Refer to circuit diagram L896 Sheet 8 This output is at 24.576MHz. The 24.567MHz clock is divided
by two by the D type Flip Flop IC908B. A 74LV74 is required
The SPDIF receiver decodes the in coming SPDIF data into an to provide sufficient speed to generate a 12.288MHz signal to
I2S stream and extracts the clocks from the signal. the DSPs. This output is under micro-controller control and is
shut off when the DSPs are not being used. (I.e. stereo bypass
The SPDIF signal arrives at the input through the coupling cap mode and standby).
C824. The SPDIF signal is BIPHASE decoded to extract the
data and a PLL is synchronised to the left right preamble to Static Port expanders
generate the system clocks. In the absence of an input signal the
chip switches over to the crystal oscillator on pin 21 this IC904 and 905 provide static control lines for the noise sensitive
assumes that the input is now coming from the ADC. In this parts of the circuit, the DACs and ADC. They are serial
situation the only clock generated is the master clock, which is programmed via a bit bashed SPI type interface. Q900 generates
used by the ADC to generate the clocks for its I2S interface and a output enable low signal from the reset signal.
by the DSPs to generate clocks at their outputs. If the system is
in Stereo bypass mode (i.e. pure stereo operation) OMCLK Buffers
STOP is used to shut down the crystal oscillator to reduce noise
in the box. IC900 is a level shifting buffer between 5V signals and the 3.3V
tolerant inputs on the micro.
The phase locked loop filter is made up of C820, C821 and
R820. The supply for the PLL comes from P5VD via the local EEPROM
inductor to give a local smooth supply.
A 8k EEPROM is used to store the configuration information
The SPDIF chip is controlled via an SPI interface on pins this is IC906 it is addressed using a bit bashed I2C interface.
1,28,27,2,19. Data is received on pin 27 CDIN, transmitted on
pin 1 CDOUT, the clock is on pin 28 CCLK, Chip select is on Connectors
Pin 2 and the interrupt line is on pin 19.
The three main control connectors are also on this sheet and
SPDIS EMPH indicates weather the incoming signal has connect to the video SK900 audio SK902 and front panel SK
emphasis or not. (Low = emphasis) 901 PCBs.
Power Supply
The power supply sheet contains the connectors from the power
supply.
SK1003 display supply.
SK1000 Analogue supply.
SK1001 Digital Supplies.
SK1002 Power supply control.
Each of the supplies that is used passes through a LC filter to

reduce any noise in both directions i.e. noise coming in from the
switched mode supply or noise getting out from the noise on the
digital board.
PSU Sync signal
The sync signal is derived from the I2S bit clock (64xFS) signal,
which is divided down by IC1001 and the appropriate output to
sent ( either 96KHz or 88.1 KHz ) to the PSU by the multiplexer
IC1002.
Voltage set and VFD HT shut down
Two resistors set the voltage the Switch mode supply generates
for the display R1008 sets the HT voltage to 36V and R1007 set
the Heater voltage to 5V.
To prevent anode stripping when the heater is switched off the

VFD display has a HT shut down this is performed by Q1000
which shorts the voltage set resistor R1008 to ground.
Regulators
Three regulators are used to provide secondary regulation for

the +/- 15V signal (it is already regulated to +/- 18V on the PSU
PCB) and the 5V analogue supply that is derived from the 18V
regulated supply.
The 2.5V supply for the DSP chips is derived from the 3.3V
supply by using the forward voltage drop of a diode. And a
negative 5V rail is generated using a zenner to provide the bias
voltage for the CMOS switches used in the bass management.
Re-clocking
The re-clocking of all of the I2S signals to the DACs is
performed by IC1102 which clocks them all through the d-type
flip flops synchronous to the master clock on pin 9. The Data
signals then go straight to the DACs via series termination
resistors. The Bit clock and word clocks are buffered by IC1100
to provide fan out to the four DACs each with their own series
terminator to reduce reflections.
L896 Digital Board Parts List Issue 1.6

C1 2J210 Capacitor SM 0805 X7R Ceramic 10% 50V 1N
C101 2L110 Capacitor SM 0805 NPO Ceramic 5% 100V 100P
C103 2W110X4 Capacitor Network SM 0612 NP0 100P X 4 50V
C200 2V710 Capacitor Non-Polar Radial Electrolytic 100UF 16V
C206 2K322 Capacitor Boxed Polyester 5mm Pitch 5% 63V 22N
C221 2P610 Capacitor Radial Electrolytic ELNA ROD 10UF 35V

C340 2D222 Capacitor Boxed Polyprop 5mm Pitch 63V 5% 2N2
C342 2D168 Capacitor Boxed Polyprop 5mm Pitch 63V 5% 680P

C702 2N522 Capacitor Radial Electrolytic Dia 5mm Pitch 5mm 2U2 50V
C709 2N510 Capacitor Radial Electrolytic Dia 5mm Pitch 5mm 1UF 50V

C821 2JA247 Capacitor SM 0805 X7R Ceramic 10% 100V 4N7

C1000 2W210X4 Capacitor Network SM 0612 NP0 Ceramic 1000P X 4 50V
C1012 2N810A Capacitor Radial Electrolytic Dia 10mm Pitch 5mm 1000UF 10V

CP700 2W110X4 Capacitor Network SM 0612 NP0 100P X 4 50V
D200 3AV99W Diode Dual Surface Mount Small Signal BAV99 SOT-23 Package
D900 3AS16W Diode Surface Mount Small Signal BAS16W SOT-23 Package
D1000 3B4003 Diode 1N4003 DO-41 Package
D1002 3B5403 Diode 1N5403 DO-201AD Package
D1003 3C05104 Zener Diode 0.5W BZX79C5V1 DO-35 Package
HS1 F004 HEATSINK BLACK TO220 23.7 degC/W
IC200 5A5383 IC DUAL 24BIT ADC 96KHZ SM
IC201 5B2134 Opamp OPA2134UA SO-8 Package
IC302 5A8740 IC AUDIO DAC XWM8740EDS SSOP-28 PACKAGE
IC303 5K4053HCT IC Triple 2 Channel Analogue Mux 74HCT4053 SO-16
IC701 5H49326 IC AUDIO DSP CS49326 PLCC-44 PACKAGE
IC702 5H49330 IC AUDIO DSP CS49330 PLCC-44 PACKAGE
IC704 5KLVC245 IC OCTAL 3 STATE TRANSCIEVER 5V TOL 74LVC245AD SMT
IC705 5KLVC574 IC OCTAL D TYPE 5V TOL74LVC574AD SMT
IC708 5H1049 IC Static RAM 512Kx8 15ns CY7C1049BV33 SOJ-36 Package
IC801 5K7404LVCU IC HEX INVERTER UNBUFFERED 5V TOL 74LVCU04D SMT
IC802 5KLVC244 IC OCTAL 3 STATE BUFFER 5V TOL 74LVC244AD SMT
IC803 5A8415R IC DIGITAL AUDIO RECEIVER CS8415A-CR TSSOP-28 PACKAGE

IC902 5N202E IC RS232 Charge Pump Driver MAX202ECSE Static protected
IC903 5H64F2329 IC Microprocessor H8 HD64F2329VF25 QFP-128 Package
IC904 5K595 IC 8 BIT SERIAL TO PARALLEL LATCH 74HCT595D SMT
IC906 5G24LC16 IC SERIAL EEPROM 24LC16BT/SN 8K SO-8 PACKAGE
IC907 5KLVC14 IC HEX INVERTING SCHMITT TRIGGER WITH 5V TOLERANT INPUT
IC908 5K74LV74 LOW VOLTAGE HCMOS 74LV74D DUAL FF SM
IC1000 5D317T IC VOLTAGE REGULATOR ADJ LM317T TO-220 PACKAGE
IC1001 5K4040 IC 12-STAGE BINARY RIPPLE COUNTER74HCT4040D SMT
IC1002 5K4051 IC 8 CHANNEL ANALOG MUX 74HC4051D SMT
IC1004 5D337 IC VOLTAGE REGULATOR NEG ADJ LM337T TO-220 PACKAGE
IC1102 5KLV174 5KLV174 74LV174 D SM HEX DTYPE FF
L304 7F004 Ferrite Bead SM1206 70R@100MHz
L801 7B033 Inductor Surface Mount 33U
L1000 7D968A Inductor 6U8
PB L896PB BLANK PCB AV8 DIGITAL PCB
Q801 4D10KN Digital Transistor MMUN2211LT1 SOT23 Package, 2x 10k resistors
R200 1M247 Resistor 0805 Surface Mount 0.125W 1% 4K7
R212 1M047 Resistor 0805 Surface Mount 0.125W 1% 47R
R216 1M310 Resistor 0805 Surface Mount 0.125W 1% 10K


R803 1M000 Resistor 0805 Surface Mount 0.125W 1% 0R0

R837 1M547 Resistor 0805 Surface Mount 0.125W 1% 4M7
R1004 1D110 Resistor Carbon Film 0W5 5% 100R
R1005 1H233 Resistor Metal Film 0.25W 1% 3K3
RP200 1V110B Resistor Pack Surface Mount 4 Isolated Resistors 100R
RP700 1V310B Resistor Pack Surface Mount 4 Isolated Resistors 10K
SK100 8K2005 CON CT SERIES VERTICAL 5WAY

SK900 8K8330 CON 1.00MM VERTICAL SM FFC 30WAY
X2 7X036 Crystal 24.576MHz HC49
X800 7X011 Crystal 11.2896MHz
AV8 DIGITAL BOARD
DD DSP
AVD DD DSP.sch
AVD RECLOCKING
ADC
DSP 1 & 2 AVD RECLOCKING.SCH
AVD ADC.SCH
TO ANALOGUE BOARD
SK100
1 AUDIO_GROUND
ADC_AR
2
3 ADC I2S LRCLK ADC I2S LRCLK
4 ADC_AINR ADC I2S SCLK ADC I2S SCLK
DAC LR
5 ADC DATA ADC DATA
ADC AVD DAC LR.Sch
ADC_AL
AMPCT5 ADC_AINL ADC HS DAC I2S MCLK LR
ADCGND ADC PDN RST SCDOUT DAC I2S BCLK LR DAC I2S BCLK LR
ADC I2S MCLK SCDIN DAC I2S LRCLK LR DAC I2S LRCLK LR
SCCLK DAC I2S DATA LR DAC I2S DATA LR
C101 C102 DSP1 CS DAC L
AGND
100PX4 SM
100PX4 SM
100PX4 SM
100PX4 SM
DSP2 CS DAC GND L
DACL
CHASSIS 4
100P NPO 0805 RAMENABLE DAC MUTE DAC R
DACGL
DSP1_INTREQ DM0 DAC GND R
DACR
100P NPO 0805 DSP2_INTREQ DSP2 BCLK DSP2 BCLK DM1
CHASSIS 2
DACGR
DSP2 LRCLK DSP2 LRCLK
C109C
C109D
C109A
C109B
TO ANALOGUE BOARD
FIX3 DATA LR DATA LR DAC RESET
SK102
FIXING HOLE 4.1 DATA CS DATA CS REDIRECT BASS
1
DATA LSRS DATA LSRS BASS L
DAC LR 2
DATA LSBRSB DATA LSBRSB BASS R
C111 3
RCLK MCLK
1N 0805 DAC CS 4
AVD DAC CS.Sch 5
AGND 6
DACC
DAC I2S MCLK CS
7
DACGC
DAC I2S BCLK CS DAC I2S BCLK CS
8
DACS
DSP_RESET1 DAC I2S LRCLK CS DAC I2S LRCLK CS
DACGS
DSP_RESET2 DAC I2S DATA CS DAC I2S DATA CS DAC C
100PX4 SM
100PX4 SM
100PX4 SM
100PX4 SM
AMPCT8
SPDIF I2S LRCLK DAC GND C
SPDIF I2S BCLK DAC S
SPDIF I2S DATA DAC I2S BCLK LSRS DAC MUTE DAC GND S
DSP1_MCLK DAC I2S LRCLK LSRS DM0
DSP2_MCLK DAC I2S DATA LSRS DM1
C103C
C103D
C103A
C103B
FIX4
FIXING HOLE 4.1
DAC I2S BCLK LSBRSB DAC RESET
DAC I2S LRCLK LSBRSB REDIRECT BASS
DAC I2S DATA LSBRSB BASS C
CHASSIS 4
SUB OFF DAC CS
SPDIF ADC TX
DAC LSRS C112
AVD DAC LSRS.Sch 1N 0805
CPU24.576MHz PSU SYNC BCLK
DAC I2S MCLK LSRS
AGND
DAC I2S BCLK LSRS
DAC I2S LRCLK LSRS
DAC I2S DATA LSRS
100PX4 SM
100PX4 SM
100PX4 SM
100PX4 SM
DAC LS
DAC GND LS
DACLS
CHASSIS 5
DAC MUTE DAC RS
DACGLS
DM0 DAC GND RS
DACRS
DM1
C110C
C110D
C110A
C110B
SPDIF_RCV
DACGRS
AVD SPDIF_RCV.sch TO ANALOGUE BOARD
DAC RESET
SK103
ADC I2S MCLK REDIRECT BASS
1
BASS LS
DAC LSRS 2
SPDIF I2S LRCLK BASS RS
MICRO 3
SPDIF I2S BCLK
AVD MICRO.sch DAC LSBRSB 4
SPDIF I2S DATA
AVD DAC LSBRSB.Sch 5
DSP1_MCLK CPU24.576MHz
6
DSP2 MCLK SPDIF ADC TX DAC I2S MCLK LSBRSB
DACLSB
7
ADC PDN RST DAC I2S BCLK LSBRSB
8
DACGLSB
ADC HS DAC I2S LRCLK LSBRSB
DACRSB
DAC I2S DATA LSBRSB
100PX4 SM
100PX4 SM
100PX4 SM
100PX4 SM
AMPCT8
DACGRSB
BASS L DAC LSB
DAC I2S MCLK LR SCDOUT BASS R DAC GND LSB
DAC I2S MCLK CS SCDIN DAC MUTE DAC RSB
DAC I2S MCLK LSRS SCCLK BASS C DM0 DAC GND RSB
DAC I2S MCLK LSBRSB DSP1 CS SUB OFF DM1
RCLK MCLK DSP2 CS BASS LS
C104C
C104D
C104A
C104B
FIX5
RAMENABLE BASS RS DAC RESET
FIXING HOLE 4.1
DSP1_INTREQ BASS LSB REDIRECT BASS
DSP2_INTREQ BASS RSB BASS LSB
DSP_RESET2 BASS RSB DAC LSBRSB
CHASSIS 5
DSP_RESET1
DAC RESET
SPDIF RCV MICRO C113
DAC MUTE 1N 0805
DM0
DM1
AGND
FIX6 FIX7
FIXING HOLE 4.1 FIXING HOLE 4.1
SPDIF RXN SPDIF RXN

PSUCHSS
SPDIF CS SPDIF CS C105 C106
SPDIF RST SPDIF RST 1N 0805 1N 0805
SPDIF EMPH SPDIF EMPH

DGND DGND
OMCLK STOP OMCLK STOP
SPDIF RCVERR SPDIF RCVERR
AVD PSU
SPDIF INT SPDIF INT
AVD PSU.Sch
FIX8 FIX9
SPDIF CDOUT SPDIF CDOUT PSU SYNC BCLK
FIXING HOLE 4.1 FIXING HOLE 4.1
SPDIF CCLK SPDIF CCLK PSU GOOD PSU GOOD
SPDIF CDIN SPDIF CDIN PSU SYNC B PSU SYNC B
PSU SYNC A PSU SYNC A
SPEED DETECT SPEED DETECT
APSUCHSS
VFD EHT VFD EHT C107 C108
1N 0805 1N 0805
DGND DGND
PSU
FIX1 FIX10
FIXING HOLE 4.1 FIXING HOLE 4.1 DRAWING TITLE 02_E161 WAF 1/8/02 CHANGES TO SOME PHASE LOCKED LOOP COMPS AND IC907 1.6.0
P3V3D P3V3D P3V3D P3V3D

AV8 DIGITAL BOARD TOP LEVEL 02_E160 WAF 27/06/02 R921 FROM 10K TO 33K 1.5.0
PB
PSUCHSS Filename: L896CT_1.6.0.sch 02_E127 AD 27/06/02 Remove R803 for PLL board upgrade 1.4.0
23425
PCB
C1 C2 C3 C4 C5 C6
1N 0805 1N 0805 1N 0805 1N 0805 1N 0805 1N 0805 Notes: 02_101 WF/AD 16/5/02 IC906 FROM 5G24LC08 TO 5G24LC16 TO GIVE MORE SPACE 1.3.0
L896PB
C200, C201 & C228 changed from 10U 35V to 100U 16V R911 TO 10K
DGND DGND DGND DGND DGND DGND A & R Cambridge Ltd. 02_E044 WAF 12/02/02 1.2
R701 TO R704 & R708 TO R711 CHANGED TO 3K3 IC104 UPDATED
Pembroke Avenue ECO No. INITIALS DATE DESCRIPTION OF CHANGE ISSUE
Waterbeach
Cambridge CB5 9PB Contact Engineer: EngName A Dutton Contact Tel: (01223) 203200 Printed: 1-Aug-2002 Sheet 1 of 11 DRAWING NO. L896CT
P5VA
D200
BAV99W DUAL SM
C228
P5VA
AUDIO_GROUND
100U NP D201
BAV99W DUAL SM
R218 R208
R201 5K1 0805 1% 2K2 0805 1% AGND

C202
4K7 0805 R219
5K1 0805 1%
47P NPO 0805
C200 IC201A AGND

1 2 R200 2 IC202B
ADC_AINL R204
4K7 0805 1 6
100U NP 3 7 R212
5K1 0805 1%
5 47R 0805
OPA2134PA SM
P3V3A
BIAS
BIAS OPA2134PA SM
R209 AGND
11
12
20
2K2 0805 1% IC200
C206 + C221
SMODE1
SMODE2
TEST
C203 C210 10U EL SG C212
22N PE C208
100N 0805 100N 0805 1
100N 0805 VREFL
2 15 8RP200 1
47P NPO 0805 GNDL DSATA ADC DATA
3 7 2
VCOML
AGND 14 6 3
SCLK ADC I2S SCLK
4 13 5 4
IC202A AINL+ LRCLK ADC I2S LRCLK
R205 5 16 100R X 4 ISO
2 AINL- FSYNC
R213 17
5K1 0805 1% 1 P3V3A MCLK ADC I2S MCLK
3 47R 0805 6 18 ADC HS
ZCAL DFS ADC HS
19
BIAS OPA2134PA SM HPFE
25 P3V3A
AINR+
24
AINR-
26
VCOMR
C211 28
C209 VREFR
DGND
AGND
BGND
100N 0805 27
100N 0805 + C222 GNDR
RST
CAL
VD
VA
10U EL SG C213
100N 0805
AK5383
23
22
21
9
10
8
AGND
AGND AGND AGND
P3V3A
+ C223
C214 10U EL SG
100N 0805
AGND
R220 R210
R203 5K1 0805 1% 2K2 0805 1%

C204
4K7 0805 R221
5K1 0805 1% ADC PDN RST

47P NPO 0805
C201 IC201B
R202 P5VA
6 IC203B
ADC_AINR R206
4K7 0805 7 6
100U NP 5 7 R214
5K1 0805 1% + C224
5 47R 0805 C215
OPA2134PA SM 10U EL SG
100N 0805
BIAS BIAS OPA2134PA SM
R211 AGND
2K2 0805 1% C207
C205 22N PE
47P NPO 0805
IC203A
R207 2
1 R215
5K1 0805 1%
3 47R 0805
BIAS OPA2134PA SM P5VA
D202 P5VA
BAV99W DUAL SM
AGND D203
BAV99W DUAL SM
AGND
P5VA
P15VA
R216
10K 0805 1%
C216 C218 C226
100N 0805 100N 0805 100N 0805
8
IC201C IC202C IC203C BIAS
R217 DRAWING TITLE 02_E161 WAF 1/8/02 CHANGES TO SOME PHASE LOCKED LOOP COMPS AND IC907 1.6.0
AGND AGND AGND
10K 0805 1% + C225
AV8 Analogue to Digital Converter
4
OPA2134PA SM OPA2134PA SM OPA2134PA SM

C220 02_E160 WAF 27/06/02 R921 FROM 10K TO 33K 1.5.0
10U EL SG
100N 0805
C217 C219 C227 Filename: AVD ADC.SCH 02_E127 AD 27/06/02 Remove R803 for PLL board upgrade 1.4.0
23425
100N 0805 100N 0805 100N 0805
Notes: 02_101 WF/AD 16/5/02 IC906 FROM 5G24LC08 TO 5G24LC16 TO GIVE MORE SPACE 1.3.0
N15VA
AGND C200, C201 & C228 changed from 10U 35V to 100U 16V R911 TO 10K
A & R Cambridge Ltd. 02_E044 WAF 12/02/02 1.2
Waterbeach
10U EL SG
C305
+
AGND
C333
100N 0805
R314
P5VA 4K7 0805
C336
C323
100N 0805 R300 R308 33P NPO 0805
3K3 0805 1% 680R 0805 1%
AGND IC304B
DAC RESET C340 R304 C342 IC301B 5
DAC RESET 3K3 0805 1% OPA2134PA SM R316
C300 2N2 PP 680P PP 5 7 DAC C
R325 DAC C
330P NPO 0805 7 6 47R 0805
6 4K7 0805
OPA2134PA SM
DAC MUTE AGND
DAC MUTE
C343
R301 R309 DAC GND C
DM0
DM0
3K3 0805 1% 680R 0805 1%
DM1 680P PP
DM1 C341
2N2 PP R305
P3V3D_CS R318 DAC GND C
3K3 0805 1%
1K0 0805
IC303A
IC302 P5VA 12
R312 1Y0
WM8740 REDIRECT BASS 14 R326
REDIRECT BASS 1Z
AGND 4K7 0805 1% 13 1K0 0805
1Y1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
2
2Y0
AGND 15
AVDDL
MUTE
VOUTLN
ML/IIS
MODE
CS/IWO
RST
Vcc
ZERO
AGND2L
VOUTLP
VMIDL
MC/DM1
MD/DM0 2Z
1
2Y1
5
R315 3Y0
+ C306 4 AGND
C337 3Z
10U EL SG 4K7 0805 1% 3
100N 0805 3Y1
VOUTRN
MODE8X
VOUTRP
AGND2R
WM8740 DIFFHW
AVDDR
AGND1
VMIDR
BCKIN
LRCIN
DGND
DVDD
11
SCLK
1S
DIN
6 10
INH 2S
9
3S
1
10
11
12
13
14
DAC I2S LRCLK CS SUB OFF AGND 74HCT4053D SM
DAC I2S LRCLK CS SUB OFF R327
BASS C
BASS C
DAC I2S DATA CS 4K7 0805
DAC I2S DATA CS
AGND C345
DAC I2S BCLK CS
DAC I2S BCLK CS
AGND
DAC I2S MCLK CS R302 R306 33P NPO 0805
DAC I2S MCLK CS
2K2 0805 1% 820R 0805 1%
IC301A IC304A
OPA2134PA SM
C314 R311 C316 3
470N PE 6K8 0805 1% 47N PE 3 1 R317 DAC S
DAC S
C301 1 2 47R 0805
AGND 330P NPO 0805 2
REDIRECT BASS
OPA2134PA SM
AGND
C317
R303 R313 DAC GND S
2K2 0805 1% 820R 0805 1%
47N PE
C315
470N PE R307
C351 R319 DAC GND S
6K8 0805 1%
100N 0805 1K0 0805
C308
+
R336
10U EL SG AGND 1K0 0805
AGND3A
P3V3A AGND
L304
70R@100MHz P3V3D_CS P5VA AGND
7F004 + C307
NF C346 C348
100N 0805 10U EL SG 100N 0805 + C309
C354 10U EL SG
100N 0805
AGND3B
AGND
DGND
P5VA P15VA P15VA
+ C318
C360 C364 C370
100N 0805 IC304C 100N 0805 10U EL SG IC301C 100N 0805
16
OPA2134PA SM OPA2134PA SM
8
IC303B
AGND3C AGND3D
VDD
74HCT4053D SM 7
VEE
GND
AGND AGND AGND

4
C361 + C319
8
100N 0805 C365 C371

100N 0805 10U EL SG 100N 0805 DRAWING TITLE 02_E161 WAF 1/8/02 CHANGES TO SOME PHASE LOCKED LOOP COMPS AND IC907 1.6.0
AV8 DAC Centre and Sub 02_E160 WAF 27/06/02 R921 FROM 10K TO 33K 1.5.0
AGND N5VA N15VA N15VA
Filename: AVD DAC CS.Sch 02_E127 AD 27/06/02 Remove R803 for PLL board upgrade 1.4.0
23425 Notes: 02_101 WF/AD 16/5/02 IC906 FROM 5G24LC08 TO 5G24LC16 TO GIVE MORE SPACE 1.3.0
Waterbeach
10U EL SG
C409
+
AGND
C433
100N 0805
R414
4K7 0805
C436
R412 R404 33P NPO 0805
3K3 0805 1% 680R 0805 1%

IC404B
DAC RESET P5VA C440 R400 C442 IC403B 5
DAC RESET 3K3 0805 1% R411
2N2 PP 680P PP 5 7 DAC L
R425 DAC L
C400 7 6 47R 0805
C419 330P NPO 0805 6 4K7 0805
OPA2134PA SM
DAC MUTE AGND OPA2134PA SM
DAC MUTE
100N 0805 C443
DM0 R413 R405
DM0 DAC GND L
3K3 0805 1% 680R 0805 1%
DM1 680P PP
DM1 C441
P3V3D_LR 2N2 PP R401
R418 DAC GND L
3K3 0805 1%
1K0 0805
AGND IC401A
IC402 P5VA 12
R408 1Y0
WM8740 14 R426
1Z
AGND 4K7 0805 1% 13 1K0 0805
1Y1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
2
2Y0
AGND 15
AVDDL
MUTE
VOUTLN
ML/IIS
MODE
CS/IWO
RST
Vcc
ZERO
AGND2L
VOUTLP
VMIDL
MC/DM1
MD/DM0 2Z
1
100N 0805
2Y1
5
R409 3Y0
+ C410 REDIRECT BASS 4 AGND
REDIRECT BASS 3Z
C438 10U EL SG 4K7 0805 1% 3
3Y1
VOUTRN
MODE8X
VOUTRP
AGND2R
WM8740 DIFFHW
AVDDR
AGND1
VMIDR
BCKIN
LRCIN
DGND
DVDD
11
SCLK
1S
DIN
6 10
INH 2S
9
3S
1
10
11
12
13
14
DAC I2S LRCLK LR 74HCT4053D SM
DAC I2S LRCLK LR R427
AGND AGND
DAC I2S DATA LR BASS R 4K7 0805
DAC I2S DATA LR BASS R
AGND BASS L C445
BASS L
DAC I2S BCLK LR
DAC I2S BCLK LR
R415 R406 33P NPO 0805
3K3 0805 1% 680R 0805 1%

DAC I2S MCLK LR IC404A
DAC I2S MCLK LR R402
C455 C457 IC403A 3
3K3 0805 1% R417
2N2 PP 680P PP 3 1 DAC R
C401 R436 DAC R
1 2 47R 0805
330P NPO 0805 2 4K7 0805
OPA2134PA SM
AGND AGND OPA2134PA SM
C458
R416 R407
DAC GND R
3K3 0805 1% 680R 0805 1%
680P PP
C456
C451 2N2 PP R403
R419 DAC GND R
3K3 0805 1%
1K0 0805
100N 0805
C412
R437
AGND 1K0 0805
+
10U EL SG
AGND4A
P3V3A
AGND
L404
70R@100MHz P3V3D_LR P5VA AGND
7F004 + C411
NF C446 C448 + C413
100N 0805 10U EL SG 100N 0805 10U EL SG
C454
100N 0805
AGND4B
AGND
DGND
P5VA P15VA P15VA
+ C414
C460 C464 C470
10U EL SG
100N 0805 100N 0805 100N 0805
16
IC401B IC403C IC404C

AGND4C AGND4D
VDD
74HCT4053D SM 7
VEE
GND
DRAWING TITLE 02_E161 WAF 1/8/02 CHANGES TO SOME PHASE LOCKED LOOP COMPS AND IC907 1.6.0
AGND AGND AGND
AV8 DAC Left and Right
4
C461 + C415
8
100N 0805 C465 C471 02_E160 WAF 27/06/02 R921 FROM 10K TO 33K 1.5.0
10U EL SG
100N 0805 100N 0805
Filename: AVD DAC LR.Sch 02_E127 AD 27/06/02 Remove R803 for PLL board upgrade 1.4.0
AGND N5VA N15VA N15VA 23425 Notes: 02_101 WF/AD 16/5/02 IC906 FROM 5G24LC08 TO 5G24LC16 TO GIVE MORE SPACE 1.3.0
Waterbeach
10U EL SG
C509
+
AGND
C533
100N 0805
R514
4K7 0805
C536
R512 R504 33P NPO 0805
3K3 0805 1% 680R 0805 1%

IC505B
DAC RESET C540 R500 C542 IC502B 5
DAC RESET 3K3 0805 1% R511
P5VA 2N2 PP 680P PP 5 7 DAC LSB
R525 DAC LSB
C500
7 6 47R 0805
C520
330P NPO 0805
6 4K7 0805
OPA2134PA SM
DAC MUTE 100N 0805
C543
R513 R505 DAC GND LSB
DM0
DM0
3K3 0805 1% 680R 0805 1%
DM1 680P PP
DM1 C541
2N2 PP R501
P3V3D_LSBRSB R518 DAC GND LSB
3K3 0805 1%
1K0 0805
AGND IC503A
IC501 P5VA 12
R508 1Y0
WM8740 14 R526
1Z
AGND 4K7 0805 1% 13 1K0 0805
1Y1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
2
2Y0
AGND 15
AVDDL
MUTE
VOUTLN
ML/IIS
MODE
CS/IWO
RST
Vcc
ZERO
AGND2L
VOUTLP
VMIDL
MC/DM1
MD/DM0 2Z
1
100N 0805
2Y1
5
R510 3Y0
+ C510 REDIRECT BASS 4 AGND
REDIRECT BASS 3Z
C538 10U EL SG 4K7 0805 1% 3
3Y1
VOUTRN
MODE8X
VOUTRP
AGND2R
WM8740 DIFFHW
AVDDR
AGND1
VMIDR
BCKIN
LRCIN
DGND
DVDD
11
SCLK
1S
DIN
6 10
INH 2S
9
3S
1
10
11
12
13
14
DAC I2S LRCLK LSBRSB BASS RSB 74HCT4053D SM
DAC I2S LRCLK LSBRSB BASS RSB R527
BASS LSB
BASS LSB
DAC I2S DATA LSBRSB 4K7 0805
DAC I2S DATA LSBRSB
AGND C545
DAC I2S BCLK LSBRSB AGND AGND
DAC I2S BCLK LSBRSB
DAC I2S MCLK LSBRSB R515 R506 33P NPO 0805
DAC I2S MCLK LSBRSB
3K3 0805 680R 0805 1%
IC505A
C555 R502 C557 IC502A 3
3K3 0805 R517
2N2 PP 680P PP 3 1 DAC RSB
R536 DAC RSB
1 2 47R 0805
C501 2 4K7 0805
AGND 330P NPO 0805 OPA2134PA SM
AGND OPA2134PA SM
C558
R516 R507
DAC GND RSB
3K3 0805 680R 0805 1%
680P PP
C556
C516 2N2 PP R503
R519 DAC GND RSB
3K3 0805
100N 0805 1K0 0805
C512
R537
AGND
+
1K0 0805
10U EL SG
AGND5A
P3V3A AGND
L504 7F004
70R@100MHz10U EL SG P3V3D_LSBRSB P5VA AGND
+ C511
NF C546 C548 + C513
100N 0805 100N 0805 10U EL SG
C554
100N 0805
AGND5B
AGND
DGND
P5VA P15VA P15VA
+ C514
C560 C564 C570
10U EL SG
100N 0805 100N 0805 100N 0805
16
IC503B IC502C AGND5C AGND5D

IC505C
VDD
OPA2134PA SM
74HCT4053D SM OPA2134PA SM
7
VEE
GND
AGND AGND AGND
AV8 DAC Left and Right Surround Back
4
C561 + C515
8
100N 0805 C565 C571 02_E160 WAF 27/06/02 R921 FROM 10K TO 33K 1.5.0
10U EL SG
100N 0805 100N 0805
Filename: AVD DAC LSBRSB.Sch 02_E127 AD 27/06/02 Remove R803 for PLL board upgrade 1.4.0
AGND N5VA N15VA N15VA 23425 Notes: 02_101 WF/AD 16/5/02 IC906 FROM 5G24LC08 TO 5G24LC16 TO GIVE MORE SPACE 1.3.0
Waterbeach
C609
+
AGND 10U EL SG
C633
100N 0805
R616
4K7 0805
C636
R612 R604 33P NPO 0805
3K3 0805 1% 680R 0805 1%

IC605B
DAC RESET P5VA C640 R600 C642 IC604B 5
DAC RESET 3K3 0805 1% R617
2N2 PP 680P PP 5 7 DAC LS
R625 DAC LS
C600 7 6 47R 0805
C619 330P NPO 0805 6 4K7 0805
OPA2134PA SM
DAC MUTE
100N 0805 C643
DM0 R613 R605
DM0 DAC GND LS
3K3 0805 1% 680R 0805 1%
DM1 680P PP
DM1 C641
P3V3D_LSRS 2N2 PP R601
R619 DAC GND LS
3K3 0805 1%
1K0 0805
AGND
IC602 P5VA IC601A
WM8740 12 R626
R608 1Y0
AGND 14 1K0 0805
1Z
13
28
27
26
25
24
23
22
21
20
19
18
17
16
15
4K7 0805 1% 1Y1
AGND 2
AVDDL
MUTE
VOUTLN
ML/IIS
CS/IWO
RST
Vcc
ZERO
AGND2L
MODE
VOUTLP
VMIDL
MC/DM1
MD/DM0
2Y0
15
100N 0805
2Z
1
2Y1
+ C610 5 AGND
R610 3Y0
C638 10U EL SG REDIRECT BASS 4
REDIRECT BASS 3Z
VOUTRN
MODE8X
VOUTRP
AGND2R
WM8740 3
DIFFHW
AVDDR
AGND1
4K7 0805 1% 3Y1
VMIDR
BCKIN
LRCIN
DGND
DVDD
SCLK
DIN
11
1S
6 10
INH 2S
9
1
10
11
12
13
14
3S R627
DAC I2S LRCLK LSRS
DAC I2S LRCLK LSRS 74HCT4053D SM
4K7 0805
DAC I2S DATA LSRS AGND AGND
DAC I2S DATA LSRS
AGND BASS RS C645
BASS RS
DAC I2S BCLK LSRS BASS LS
DAC I2S BCLK LSRS BASS LS
DAC I2S MCLK LSRS R614 R606 33P NPO 0805
DAC I2S MCLK LSRS
3K3 0805 1% 680R 0805 1%
IC605A
C655 R602 C657 IC604A 3
3K3 0805 1% R618
2N2 PP 680P PP 3 1 DAC RS
R636 DAC RS
1 2 47R 0805
AGND C601 2 4K7 0805
330P NPO 0805
OPA2134PA SM
AGND OPA2134PA SM
C658
R615 R607 DAC GND RS
3K3 0805 1% 680R 0805 1%
680P PP
C656
C651 2N2 PP R603
R620 DAC GND RS
3K3 0805 1%
1K0 0805
100N 0805
C612 R637
AGND 1K0 0805
+
10U EL SG
AGND6A
P3V3A AGND
L604
70R@100MHz P3V3D_LSRS P5VA AGND
7F004 + C611
NF C646 C648
100N 0805 10U EL SG 100N 0805
+ C613
C654
100N 0805 10U EL SG
AGND6B
DGND
AGND
P5VA P15VA P15VA
+ C614
C660 C664 C670
10U EL SG
100N 0805 100N 0805 100N 0805
16
IC604C AGND6C AGND6D

IC605C
VDD
IC601B OPA2134PA SM
7 OPA2134PA SM
74HCT4053D SM
VEE
GND
AGND AGND AGND

4
C661 + C615
8
100N 0805 C665 C671 DRAWING TITLE 02_E161 WAF 1/8/02 CHANGES TO SOME PHASE LOCKED LOOP COMPS AND IC907 1.6.0
100N 0805
10U EL SG
100N 0805 AV8 DAC Left and Right Surround 02_E160 WAF 27/06/02 R921 FROM 10K TO 33K 1.5.0
AGND N5VA N15VA N15VA
Filename: AVD DAC LSRS.Sch 02_E127 AD 27/06/02 Remove R803 for PLL board upgrade 1.4.0
Waterbeach
R715
DSP2 BCLK
100R 0805
R712
RP701 DSP2 LRCLK
P2V5D 100R 0805
10K X 4 ISO P2V5D
8
7
6
5
DGND CP700
DGND
100P X 4 ISO
8
7
6
5
8
7
6
5
R704
R707 R711
1
2
3
4
RP700 R700 R701 R702 R702 3K3 0805 1%
10K X 4 ISO 10K 0805 3K3 0805 1%
R708 R709 R710
10K 0805 1% 3K3 0805 1% 3K3 0805 1% 3K3 0805 1% IC701
1
2
3
4
1
2
3
4
3K3 0805 1% 3K3 0805 1% 3K3 0805 1% IC702 DGND

CS49326
CS49330
CS49326 44 R736 DSP1_MCLK

MCLK 100R 0805 DSP1_MCLK CS49330 44 DSP2_MCLK
4 43 DSP1_SCLK MCLK DSP2_MCLK
WR,DS,EMWR,GPIO10 SCLK R738 WR 4 43
5 42 DSP1_LRCLK WR,DS,EMWR,GPIO10 SCLK
RD,R/W,EMOE,GPIO11 LRCLK EMOE 5 42
100R 0805 RD,R/W,EMOE,GPIO11 LRCLK
SCDIN 6 41 R737 DSP1_AUD0
A1,SCDIN AUDATA0 SCDIN 6 41 1RP702 8
SCCLK 7 40 100R 0805 A1,SCDIN AUDATA0 DATA LR
A0,SCCLK AUDATA1 SCCLK 7 40 2 7
DSP1 CS 18 39 A0,SCCLK AUDATA1 DATA CS
CS AUDATA2 DSP2 CS 18 39 3 6
SCDOUT 19 3 SPDIF ADC TX CS AUDATA2 DATA LSRS
SCDIO,SCDOUT,PSEL,GPIO9 AUDDATA3/XMT958 SPDIF ADC TX SCDOUT 19 3 4 5
SCDIO,SCDOUT,PSEL,GPIO9 AUDDATA3/XMT958 DATA LSBRSB
DSP1_INTREQ 20 27 SPDIF I2S DATA 100R X 4 ISO
8
7
6
5
BOOT,INTREQ CPMDAT,SDATAN2,RCV958 SPDIF I2S DATA DSP2_INTREQ 20 27 DSP1_AUD0
21 28 SPDIF I2S BCLK BOOT,INTREQ CPMDAT,SDATAN2,RCV958
EXTMEM,GPIO8 CMPCLK,SCLKN2 SPDIF I2S BCLK EXTMEM 21 28 DSP1_SCLK
29 SPDIF I2S LRCLK EXTMEM,GPIO8 CMPCLK,SCLKN2
CMPREQ,LRCLKN2 SPDIF I2S LRCLK 29 DSP1_LRCLK
8 CMPREQ,LRCLKN2
DATA7,EMAD7,GPIO7 DSP_D7 8
9 DATA7,EMAD7,GPIO7 CP703
DATA6,EMAD6,GPIO6 DSP_D6 9
1
2
3
4
10 22 DATA6,EMAD6,GPIO6
DATA5,EMAD5,GPIO5 SDATAN1 ADC DATA DSP_D5 10 22 SPDIF ADC TX
11 25 DATA5,EMAD5,GPIO5 SDATAN1
DATA4,EMAD4,GPIO4 SCLKN1,STCCLK2 ADC I2S SCLK DSP_D4 11 25
14 26 DATA4,EMAD4,GPIO4 SCLKN1,STCCLK2
DATA3,EMAD3,GPIO3 LRCLKN1 ADC I2S LRCLK DSP_D3 14 26 DGND
15 DATA3,EMAD3,GPIO3 LRCLKN1
DATA2,EMAD2,GPIO2 DSP_D2 15 100P X 4 ISO
16 30 CPU24.576MHz DATA2,EMAD2,GPIO2
DATA1,EMAD1,GPIO1 CLKIN CPU24.576MHz DSP_D1 16 30 CPU24.576MHz
17 31 DATA1,EMAD1,GPIO1 CLKIN
DATA0,EMAD0,GPIO0 CLKSEL DSP_D0 17 31
C702 P2V5A1 DATA0,EMAD0,GPIO0 CLKSEL C705 P2V5A2
DSP_RESET1 36 32
RESET FILT2 DSP_RESET2 36 32
P2V5D RESET FILT2
+
P2V5D
+
R717 37 2U2 EL R724
DD (RESERVED) 37 2U2 EL
4K7 0805 38 33 DD (RESERVED)
DC (RESERVED) FILT1 4K7 0805 38 33
P2V5D DC (RESERVED) FILT1
R718 R720
R725 R727
DGND1
DGND2
DGND3
DGND1
DGND2
DGND3
AGND
AGND
4K7 0805 180K 0805 RP705
VD1
VD2
VD3
5 4 DSP_D7 4K7 0805 180K 0805
VD1
VD2
VD3
VA
VA
6 3 DSP_D6
7 2 DSP_D5
1
12
13
23
24
34
35
12
13
23
24
34
35
8 1 DSP_D4
C706 C707
10K X 4 ISO 220P NPO 0805 10N 0805
C703 C704
RP706
P2V5D P2V5A1 220P NPO 0805 10N 0805 5 4 DSP_D3
SCDOUT P2V5D P2V5A2
SCDOUT 6 3 DSP_D2
SCDIN
SCDIN 7 2 DSP_D1
SCCLK
SCCLK 8 1 DSP_D0
DSP1 CS
DSP1 CS 10K X 4 ISO
DSP2 CS
DSP2 CS R719
RAMENABLE
RAMENABLE DGND DGND 10K 0805 1%
DSP1_INTREQ DGND DGND R726
DSP1_INTREQ
DSP2_INTREQ 10K 0805 1%
DSP2_INTREQ
DSP_RESET1
DSP_RESET1 DGND
DSP_RESET2
DSP_RESET2
DGND
L708
P3V3D P3V3D P3V3D P3V3D 70R@100MHz
7F004 IC708
+ C729 CY7C1049BV33-15
C734 C738 C740 C742 C743 C744 27 512K x 8 6 RAMENABLE
100N 0805 100N 0805 100N 0805 100N 0805 47U EL 35V 100N 0805 100N 0805 VCC CE
9 STATIC RAM 13 WR
VCC WE
P3V3D 31 EXTMEM
OE
DGND DGND DGND DGND DGND DGND DGND A0 1
A0
A1 2
A1
+ C718 DGND A2 3
C728 A2
47U EL 35V DGND DGND DGND A3 4 30 D7
100N 0805 A3 I/O 7
A4 5 29 D6
A4 I/O 6
IC704 IC705 IC706 IC707 A5 14 26 D5
A5 I/O 5
DGND DGND 20 10 10 20 10 20 10 20 A6 15 25 D4
VCC GND GND VCC GND VCC GND VCC A6 I/O 4
1 WR 1 1 1 A7 16 12 D3
DIR OE OE OE A7 I/O 3
19 EXTMEM EMOE 11 EMOE 11 EMOE 11 A8 17 11 D2
OE CP CP CP A8 I/O 2
A9 18 8 D1
A9 I/O 1
A10 20 7 D0
A10 I/O 0
DSP_D0 18 2 D0 DSP_D0 2 19 A0 A0 2 19 A8 A8 2 19 A16 A11 21
B0 A0 D0 Q0 D0 Q0 D0 Q0 A11
B1 A1 D1 Q1 D1 Q1 D1 Q1 A12
B2 A2 D2 Q2 D2 Q2 D2 Q2 A13
DSP_D3 15 5 D3 DSP_D3 5 16 A3 A3 5 16 A11 5 16 A14 24 19
B3 A3 D3 Q3 D3 Q3 D3 Q3 A14 NC
DSP_D4 14 6 D4 DSP_D4 6 15 A4 A4 6 15 A12 6 15 A15 32 36
B4 A4 D4 Q4 D4 Q4 D4 Q4 A15 NC
DSP_D5 13 7 D5 DSP_D5 7 14 A5 A5 7 14 A13 7 14 A16 33
B5 A5 D5 Q5 D5 Q5 D5 Q5 A16
DSP_D6 12 8 D6 DSP_D6 8 13 A6 A6 8 13 A14 8 13 A17 34 28
B6 A6 D6 Q6 D6 Q6 D6 Q6 A17 GND
DSP_D7 11 9 D7 DSP_D7 9 12 A7 A7 9 12 A15 9 12 A18 35 10
B7 A7 D7 Q7 D7 Q7 D7 Q7 A18 GND
74LVC245A D 74LVC574A D 74LVC574A D 74LVC574A D
CY7C1049BV33-15
DGND
DGND
L701
L700 P2V5D P2V5A1
P2V5D P2V5A2 70R@100MHz
70R@100MHz
7F004
7F004
+ C724 + C725 + C735 + C727 + C736

+ C709 + C711 + C717 + C714
C708 C710 C712 C716
C719
1U0 EL
C720
1U0 EL
C721
1U0 EL
C726
1U0 EL 47U EL 35V DRAWING TITLE 02_E161 WAF 1/8/02 CHANGES TO SOME PHASE LOCKED LOOP COMPS AND IC907 1.6.0
100N 0805
1U0 EL
100N 0805
1U0 EL
100N 0805 100N 0805
1U0 EL 47U EL 35V 100N 0805 100N 0805 100N 0805 100N 0805
AV8 Dolby Digital and THX DSP 02_E160 WAF 27/06/02 R921 FROM 10K TO 33K 1.5.0
Filename: AVD DD DSP.sch 02_E127 AD 27/06/02 Remove R803 for PLL board upgrade 1.4.0
DGND
DGND 23425 Notes: 02_101 WF/AD 16/5/02 IC906 FROM 5G24LC08 TO 5G24LC16 TO GIVE MORE SPACE 1.3.0
Waterbeach
SPDIF RCVERR
SK801
1
2
3
4
5
AMPCT5
DGND
P5VD L801
33UH SM
C802
DGND
+
10U EL R820
1K2 0805 1% C821
4N7 0805 100V
C818
100N 0805
C820
C819
100N 0805 L802 DSP1_MCLK
1N 0805 DSP1_MCLK
DGND8D 70R@100MHz P3V3D
R821 IC802
DGND 10K 0805 10 20 DSP2 MCLK
GND VCC 7F004 DSP2 MCLK
1
SPDIF RCVERR 1OE
19 C822 C823
R822 2OE 100N 0805 100N 0805
10K 0805 DAC I2S MCLK LSRS
DAC I2S MCLK LSRS
DGND
2 18 R823 DGND DGND
1A0 1Y0
11
4 16 33R 0805 R825 DAC I2S MCLK LSBRSB
8
IC803 1A1 1Y1 R824 33R 0805 DAC I2S MCLK LSBRSB
6 14
1A2 1Y2
VA+
FILT
AGND
RERR
8 12 33R 0805 R826
R828 1A3 1Y3
17 3 R832 33R 0805 DAC I2S MCLK LR
33R 0805 2A0 2Y0 33R 0805 R834 DAC I2S MCLK LR
R803 15 5
2A1 2Y1 R833 33R 0805 33R 0805
13 7
C824 5 NF 2A2 2Y2 R802
R808 RXN0 0R0 0805 11 9 DAC I2S MCLK CS
SPDIF RXN 4 10 2A3 2Y3 DAC I2S MCLK CS
SPDIF RXN RXP0 RMCLK C810
33R 0805
1K0 0805 17
OLRCK 22P NPO 0805 74LVC244AD
10N 0805 16
OSCLK ADC I2S MCLK
SPDIF Reciever 18 DGND ADC I2S MCLK
SDOUT
12
RXP1
13
C804 RXP2 R800 RCLK MCLK
14 SPDIF I2S LRCLK
RXP3 SPDIF I2S LRCLK
15
SDA/CDOUT
10N 0805 33R 0805
RXP4 R801
25 SPDIF I2S BCLK
SCL/CCLK
AD1/CDIN
RXP5 SPDIF I2S BCLK
22P NPO 0805
22P NPO 0805
22P NPO 0805
22P NPO 0805

26
AD0/CS
RXP6 33R 0805
OMCK
DGND
EMPH
C811 C813 C815 C817
RST
VD+
R831
H/S
INT
SPDIF I2S DATA
SPDIF I2S DATA
U
33R 0805
22P NPO 0805
22P NPO 0805
22P NPO 0805
22P NPO 0805

DGND DGND
2
20
21
24
22
23
28
27
19
CS8415A-CR
C803 C812 C814 C816
IC801A IC801B
R836 1 2 3 4 R838
C826
1K0 0805 1% 33R 0805
74LVCU04 SM 74LVCU04 SM DGND8E
1N 0805
DGND
C827
R827
R837 47K 0805
100N 0805
4M7 0805
X800
DGND C809
Q801 P3V3D
DTRANN SM
OMCLK STOP 11.2896MHZ NO GROMMET
+
OMCLK STOP 10U EL L804
C805 C806 70R@100MHz
47P NPO 0805
47P NPO 0805
7F004
DGND
DGND DGND DGND
SPDIF RST
SPDIF RST
SPDIF EMPH
SPDIF EMPH
SPDIF CDOUT
SPDIF CDOUT
SPDIF CCLK
SPDIF CCLK
SPDIF CDIN
SPDIF CDIN
SPDIF CS
SPDIF CS
SPDIF INT
SPDIF INT
IC801D
9 8
74LVCU04 SM
IC801C
5 6 P3V3D
L800
74LVCU04 SM 70R@100MHz
IC801F
14
7F004
13 12 C800 C801
100N 0805 100N 0805 IC801G
74LVCU04 SM
IC801E
74LVCU04 SM
AV8 SPDIF Receiver 02_E160 WAF 27/06/02 R921 FROM 10K TO 33K 1.5.0
7
11 10
Filename: AVD SPDIF_RCV.sch 02_E127 AD 27/06/02 Remove R803 for PLL board upgrade 1.4.0
23425
DGND DGND
74LVCU04 SM Notes: 02_101 WF/AD 16/5/02 IC906 FROM 5G24LC08 TO 5G24LC16 TO GIVE MORE SPACE 1.3.0
DGND C200, C201 & C228 changed from 10U 35V to 100U 16V R911 TO 10K
Waterbeach
P3V3D
P3V3D
4
IC908A
PROGRAM 2 5 FWE = 0 (NORMAL) = 1 (BOOT PROGRAM) FWE
SD
D Q
P3V3D
+ C936
R900 uRESET 3
10
CLK 100U EL
10K 0805 IC908B IC907A IC907B IC907C
DGND
6 MD2 = 1 (NORMAL) = 0 (BOOT PROGRAM) MD2 9 12
SD
CD
Q Q D 22P NPO 0805 C901 C902 22P NPO 0805 2 1 R916 4 3 6 5 R918
R901 R912
74LV74 SM 11 MCLK 10K 0805 10K 0805
1
CPU24.576MHz CLK 74LVC14 74LVC14 74LVC14
DGND D900
P3V3D 100R 0805 100R 0805 X2 R921
8 C903 BAS16W SM
CD
Q 1N 0805
33K 0805
P3V3D 74LV74 SM
13
P3V3D
24.576MHZ DGND uRESET
IC900
10 20
GND VCC C900 DGND
1
1OE 100N 0805
19
2OE
PSU SYNC B
PSU SYNC B P5VD
DGND
DGND C904 IC902
ZONE2 VIDEO IN PRESENT 2 18 FCLOCK2 PSU SYNC A
1A0 1Y0 PSU SYNC A 1 C908
OSD VIDEO IN PRESENT 4 16 FCLOCK1 C1+
1A1 1Y1 2
VSYNC 6 14 V+
1A2 1Y2 100N 0805 3
VSYNC ZONE2 8 12 C1- 100N 0805
1A3 1Y3 C905
COMP SYNC 17 3 LED LATCH
2A0 2Y0 4 6 C906
DEMOD1 15 5 DEMOD1 3V3 C2+ V-
2A1 2Y1
DEMOD2 13 7 DEMOD2 3V3
2A2 2Y2 100N 0805 5
11 9 AUD SDATA C2- 100N 0805
2A3 2Y3
AUD SCLK
STATIC PROTECTED DGND
74LVC244AD AUD SEL 2
RS232 TX 11 14 TXDATA
T1IN T1OUT
SCDIN AUD SEL 1
DGND SCDIN 10 7 P5VD
IC907E IC907F T2IN T2OUT
SCDOUT SPEED DETECT
TO VIDEO BOARD SCDOUT
10 1112 13 12 13 RXDATA
SK900 SCCLK AUD SEL 0 R1OUT R1IN
SCCLK
C913A VIDSD 1 VIDEO SERIAL DATA AUD CTRL EN P3V3D
100PX4 SM 74LVC14 74LVC14 9 8
C909A 100PX4 SM 2 R2OUT R2IN
C913B VIDSCLK 3 VIDEO SERIAL CLK
100PX4 SM 15 16
C909B 100PX4 SM 4 GND VCC
C913C VIDCL 5 VIDEO COMP LATCH R919
SIGGND MAX202ECSE
C909C 100PX4 SM 100PX4 SM VIDSL 6 VIDEO SVID LATCH C907
C913D SPDIFL 7 SPDIF LATCH 0R0 0805 100N 0805
102
101
100
C909D 100PX4 SM 100PX4 SM VIDZCS 8 VIDEO ZONE2 CS
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
C914A VIDOC 9 VIDEO OSD CS IC903 DGND
100PX4 SM DGND DGND
10
P22/PO2/TIOCC3/TMRI0
P23/PO3/TIOCD3/TMCI0
XTAL
PF4/HWR
P24/PO4/TIOCA4/TMRI1
P25/PO5/TIOCB4/TMCI1
P61/TEND0/CS5
VSS
VSS
VCC
VSS
VCC
VSS
VSS
VSS
P51/RXD2/IRQ5
P50/TXD2/IRQ4
PF5/RD
PF6/AS
PF7/o
P63/TEND1
C910A 100PX4 SM ZONE2 VIDEO IN PRESENT
P53/ADTRG/IRQ7/WAIT/BREQ0
WDTOVF(FWE,EMLE)
P26/PO6/TIOCA5/TMO0
P27/PO7/TIOCB5/TMO1
PF1/BACK
PF2/LCAS/WAIT/BERQ0
P20/PO0/TIOCA3
P21/PO1/TIOCB3
P60/DREQ0/CS4
EXTAL
RES
PF3/LWR
P52/SCK2/IRQ6
PF0/BREQ
P62/DREQ1
STBY
NMI
Z2 VID
C914B OSDVID 11 OSD VIDEO IN PRESENT
C910B 100PX4 SM 100PX4 SM PROG 12 PROGRAM
C914C VSYNC 13 VSYNC
C910C 100PX4 SM 100PX4 SM 14 P3V3D
C914D VSYNCZ2 15 VSYNC ZONE2 P3V3D
C910D 100PX4 SM 100PX4 SM 16
C915A CSYNC 17 COMP SYNC R902 R903
C911A 100PX4 SM 100PX4 SM 18 10K 0805 10K 0805
C915B SPDIFRX 19
100PX4 SM SPDIF RXN
C911B 100PX4 SM 20 103 64 R904
AVCC P35/SCK1 100R 0805
C915C RXDATA 21 RXDATA 104 63 DISPCLK
100PX4 SM VREF P34/SCK0
C911C 100PX4 SM SIGGND 22 SIGGND PHONES INSERTED 3V3 105 62 RS232 RX
P40/AN0 P33/RXD1
C915D TXDATA 23 TXDATA 106 61
100PX4 SM P41/AN1 P32/RXD0 100R 0805
C911D 100PX4 SM 24 107 60 R906
P42/AN2 P31/TXD1
C916A DEM1 25 DEMOD1 KEYB0 108 59 DISPDAT
100PX4 SM P43/AN3 P30/TXD0 R905
FIX902 C916B 26 KEYB1 109 58 100R 0805
100PX4 SM P44/AN4 VCC
FIXING HOLE 4.1 C916C DEM2 27 DEMOD2 KEYB2 110 57 DSP_RESET2
100PX4 SM P45/AN5 PD7/D15 DSP_RESET2
28 PHASE A 111 56 DSP_RESET1
P46/AN6/DA0 PD6/D14 DSP_RESET1
C916D SPDIFATX 29 PHASE B 112 55 DSP1 CS
100PX4 SM SPDIF ADC TX P47/AN7/DA1 PD5/D13 DSP1 CS
30 113 54 DSP2 CS
AVSS PD4/D12 DSP2 CS
114 53
CHASSIS 2 VSS VSS
C938 FFC30V SM KEYB LATCH 115 52 RAMENABLE
Q_900 P17/PO15/TIOCB2/TCLKD PD3/D11 RAMENABLE
100N 0805 DEMOD1 3V3 116 51
P16/PO14/TIOCA2 PD2/D10
R917 C935 KEYB DATA 117 50 1RP900 8 100R X 4 ISO
22R 0805 P15/PO13/TIOCB1/TCLKC PD1/D9 SPDIF CDIN
DGND 100N 0805 DEMOD2 3V3 118 49 2 7
P14/PO12/TIOCA1 PD0/D8 SPDIF CDOUT Expansion Connector.
KEYB CLK 119 48 3 6 P3V3D
P5VD P36VF1 P13/PO11/TIOCD0/TCLKB PE7/D7 SPDIF CCLK
120 47 4 5 SK903
DGND9A P12/PO10/TIOCC0/TCLKA PE6/D6 SPDIF CS
TO DISPLAY BOARD DISPLAT 121 46 1
P11/PO9/TIOCB0/DACK1 PE5/D5
SK901 DGND IRFP IN 122 45 2
P10/PO8/TIOCA0/DACK0 PE4/D4
C912D 100PX4 SM KEYBD 30 KEYB DATA 123 44 3
MD0 VSS
29 124 43 4
MD1 PE3/D3
C912C 100PX4 SM KEYBCK 28 KEYB CLK 125 42 5
MD2 PE2/D2
27 DISPBLK 126 41 6
PG0/CAS PE1/D1
C912B 100PX4 SM LEDL 26 LED LATCH I2C SDA 100R 0805 127 40 7
PG1/CS3 PE0/D0
25 I2C SCL R908 128 39 8
PG2/CS2 VCC
C912A 100PX4 SM KEYBL 24 KEYB LATCH 100R 0805 R907
C917A 100PX4 SM 23 C926 C929 C937 C939 C941 C942 AMPCT8
DGND9E
100P NPO 0805 100P NPO 0805 100P NPO 0805 100P NPO 0805 100P NPO 0805 100P NPO 0805 C925
C921D KEYB0 22 KEYB0 C924
100N 0805
C917B 100PX4 SM 100PX4 SM KEYB1 21 KEYB1 DGND DGND DGND 100N 0805
C921C KEYB2 20 KEYB2
C917C 100PX4 SM 100PX4 SM PHA 19 PHASE A uRESET
C921B PHB 18 PHASE B P3V3D DGND9G IC904 P3V3D PSUCHSS
C917D 100PX4 SM 100PX4 SM LEDEN 17 LED ENABLE 8 16
GND VCC
P67/CS7/IRQ3
P66/CS6/IRQ2
PA4/A20/IRQ4
PA5/A21/IRQ5
PA6/A22/IRQ6
PA7/A23/IRQ7
C921A IRFP 16 IRFP IN
C918A 100PX4 SM 100PX4 SM 15 P3V3D DGND 13
OE
P65/IRQ1
P64/IRQ0
PG3/CS1
PG4/CS0
PB2/A10
PB3/A11
PB4/A12
PB5/A13
PB6/A14
PB7/A15
PA0/A16
PA1/A17
PA2/A18
PA3/A19
C922D FCK1 14 FCLOCK1 14 C931
PC0/A0
PC1/A1
PC2/A2
PC3/A3
PC4/A4
PC5/A5
PC6/A6
PC7/A7
PB0/A8
PB1/A9
100PX4 SM DS
C918B 100PX4 SM FCK2 13 FCLOCK2 11 100N 0805
SHcp(DATA)
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C922C 12 P3V3D 10
100PX4 SM MR
C918C 100PX4 SM DISPDAT 11 DISPDAT 12
STcp(LATCH)
C922B 10 HD64F2329VF25 R920 DGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
C918D 100PX4 SM 100PX4 SM DISPCK 9 DISPCLK P3V3D 10K 0805 15
Q0 BASS L
C922A 8 1
100PX4 SM Q1 BASS R
C919A 100PX4 SM DISPLAT 7 DISPLAT 2
Q2 BASS C
C923D 6 3
100PX4 SM Q3 BASS LS
C919B 100PX4 SM DISPBLK 5 DISPBLK 0VF1GND P5VF2 0VF2GND R911 4
Q900 Q4 BASS RS
C923C 4 10K 0805 1% 5
100PX4 SM IC907D DTRANN SM Q5 BASS LSB
C919C 100PX4 SM 3 VIDEO SVID LATCH DGND 6
Q6 BASS RSB
C923B 2 VIDEO SERIAL CLK 8 9 7
100PX4 SM 100PX4 SM PSU GOOD Q7 SUB OFF
C919D 1 VIDEO SERIAL DATA
VIDEO ZONE2 CS 74LVC14 9
DGND9B Q7OUT
FFC30V SM VIDEO OSD CS DSP1_INTREQ
DSP1_INTREQ
SPDIF LATCH DSP2_INTREQ DGND 74HCT595D
DGND DSP2_INTREQ
FIX901 C923A VIDEO COMP LATCH SPDIF INT
100PX4 SM SPDIF INT
FIXING HOLE 3.5
DAC DATA
DAC CLK
TO AUDIO BOARD BASS LATCH
CHASSIS 1 VFD EHT
LED ENABLE
SK902
SPDIF RST IC905 P3V3D
C927A PHINS 1 PHONES INSERTED 3V3 SPDIF RST
100PX4 SM 8 16
2 GND VCC
SPDIF EMPH
C927B AUDSD 3 AUD SDATA SPDIF EMPH
100PX4 SM OMCLK STOP 13
4 OMCLK STOP OE
SPDIF RCVERR 14 C934
C927C AUDSCK 5 AUD SCLK SPDIF RCVERR DS
100PX4 SM P3V3D P3V3D 11 100N 0805
6 SHcp(DATA)
10
C927D AUDSEL0 7 AUD SEL 0 MR
100PX4 SM 12
8 STcp(LATCH)
DGND
C928A AUDSEL1 9 AUD SEL 1
100PX4 SM 15 DAC RESET
10 Q0 DAC RESET
1 DAC MUTE
C928B AUDSEL2 11 AUD SEL 2 Q1 DAC MUTE
100PX4 SM R910 2 DM0
12 Q2 DM0
10K 0805 3 DM1
C928C AUDCTRL 13 AUD CTRL EN DGND9F Q3 DM1
100PX4 SM 4 ADC PDN RST
14 Q4 ADC PDN RST
5 ADC HS
C928D 15 Q5 ADC HS
100PX4 SM 6
16 Q6
DGND 7
17 Q7
18
9
19 I2CSDA I2CSCL Q7OUT
20
P3V3D 74HCT595D
21
P3V3D
22
5
6
C920 IC906
FFC22V SM
C930
WP
SDA
SCL
Q_901
100N 0805 C940
14
14
1N 0805 4 8 100N 0805

VSS VDD IC907G DRAWING TITLE 02_E161 WAF 1/8/02 CHANGES TO SOME PHASE LOCKED LOOP COMPS AND IC907 1.6.0
VCC
R909
AV8 Micro Controller
GND
C932 74LVC14 IC908C

22R 0805 DGND
A2
A1
A0
100N 0805 74LV74 SM 02_E160 WAF 27/06/02 R921 FROM 10K TO 33K 1.5.0
24LC16 SM C933 DGND
3
2
1
Filename: AVD MICRO.sch 02_E127 AD 27/06/02 Remove R803 for PLL board upgrade 1.4.0
23425
CHASSIS 2 DGND9C 100N 0805
DGND Notes: 02_101 WF/AD 16/5/02 IC906 FROM 5G24LC08 TO 5G24LC16 TO GIVE MORE SPACE 1.3.0
DGND9D DGND8
DGND DGND DGND R701 TO R704 & R708 TO R711 CHANGED TO 3K3 IC104 UPDATED
Waterbeach
SK1003 P36VF1 P5VD
1 P36VF1
P36VF1 SPEED SELECT FOR PSU SYNC
2 0VF1GND
0VF1
3 P36VSET
P36VSET A B Sample Rate PSU SYNC
4 P5VF2 R1010
P5VF2
5 0VF2GND R1008 Q1000 10K 0805
OVF2 0 0 = 32KHz + 24KHz no sync sent
6 P5VF2S 33K 0805
P5VF2SET 1 0 = 44.1KHz +48KHz 88.1KHz 96KHz
7 P5VF2
VFD EHT 0 1 = 96KHz + 88.2KHz 96KHz 88.1KHz
1 1 = 192KHz + 176.4KHz 96KHz 88.2KHz
100K 0805
AMPCT7
R1007
DTRANN SM
0VF2GND
R1002
L1006
0R0 0805 70R@100MHz P5VD
0VF1GND DGND
C1000B C1000A C1005A C1005B C1005C C1005D
C1000C C1000D 1000PX4 SM 1000PX4 SM 1000PX4 SM 1000PX4 SM 1000PX4 SM 1000PX4 SM 7F004
P18V P5VD
1000PX4 SM 1000PX4 SM
L1000 C1015 C1020
IC1001 100N 0805 100N 0805
PSUCHSS P18V C1016
PSUCHSS PSUCHSS 6U8H RADIAL 8 16
GND VCC 100N 0805
PSUCHSS DGND DGND
+ C1006 DGND 9
Q0
P21V 100U EL C1047 7 DGND
Q1
SK1000 100N 0805 6 IC1002
Q2
1 Q_1000A PSU SYNC BCLK 10 5 13 16
P18V PSU SYNC BCLK CP Q3 X0 VDD
2 Q_1000B 2 14
AGND AGND1A Q5 X1 R1009
3 Q_1000C 3 15 3 PSU SYNC
N18V Q4 X2 X
4 11 4 12 100R 0805
P21V R1006 MR Q6 X3
5 C1007 + 13 1
AGND Q7 X4
6 100U EL 0R0 0805 12 5
N21V Q8 X5
AGND C1042 AGND 14 2
Q9 X6
N21V L1001 100N 0805 DGND 15 4
AMPCT6 Q10 X7
C1035 1
C1001A C1001B C1001C C1001D N18V Q11
6U8H RADIAL 6
1000PX4 SM 1000PX4 SM 1000PX4 SM 1000PX4 SM INH
74HCT4040 SM PSU SYNC A 11
PSU SYNC A A
N18V 100N 0805 PSU SYNC B 10
PSU SYNC B B
C1037 9
C
8
GND
APSUCHSS 100N 0805 7
VEE
C1038
74HC4051 SM
100N 0805
C1039 DGND
100N 0805
C1040
SPEED DETECT
100N 0805
AGND DGND
SK1001 P12V
1 P12V
P12V
2
DGND
3 N12V
N12V
4 DGND
DGND
5 P5V L1003 P5VD N12V
P5V
6 DGND
DGND P5VD
7 P3V3 6U8H RADIAL
P3V3
8 DGND1A C1017 + C1012
DGND
100N 0805 1M0 10V
DGND1B
AMPCT8
C1002A C1002B C1002C C1002D C1003A C1003B C1003C C1003D DGND
1000PX4 SM 1000PX4 SM 1000PX4 SM 1000PX4 SM 1000PX4 SM 1000PX4 SM 1000PX4 SM 1000PX4 SM L1004 P3V3D L1002 P3V3A
P3V3D
6U8H RADIAL 6U8H RADIAL
+ C1013
C1018
100N 0805 1M0 10V
PSUCHSS DGND1C
DGND
SK1002
1 PSUSYNC PSU SYNC
PSU SYNC
2 PSUGOOD
PSU GOOD PSU GOOD
3
PSU KILL
4 DGND1E
DGND
AMPCT4 DGND
MICRO CONTROLLER DECOUPLING
C1004A C1004B C1004C C1004D
1000PX4 SM 1000PX4 SM 1000PX4 SM 1000PX4 SM P3V3D
D1004 + C1028 + C1033

PSUCHSS
P18V C1021 C1022 C1023
47U EL 35V 47U EL 35V
100N 0805 100N 0805 100N 0805
1N4003 P15VA
IC1003
+ C1046
LM317T
R1012
AGND
I O 100U EL
Vin Vout P15VA 2K4 0805 1%
DGND
ADJ
MICRO CONTROLLER DECOUPLING

D1005 R1013 + C1043
1N4003 220R 0805 470U EL 25V
A
100N 0805 P3V3D

C1027
P3V3D D1002 P2V5D C1036 D1006 R1014 + C1044
A
100N 0805 1N4003 220R 0805 470U EL 25V
ADJ
+ C1034
1N5403 C1024 C1025 C1026
+ C1019 R1011 47U EL 35V
R1003 2K4 0805 1% I O 100N 0805 100N 0805 100N 0805
1M0 10V + C1045 Vin Vout N15VA
390R 0805 1% 100U EL
AGND1G IC1004
LM337T
D1007
DGND N15VA DGND
AGND
N18V
1N4003
D1000
P18V
1N4003 P5VA
IC1000 HS1
LM317T
R1004 I O
Vin Vout P5VA
100R W2 CF
ADJ
D1001 R1001 + C1009

1N4003 390R 0805 470U EL 25V
A
100N 0805 TO220HS23REG

+ C1011 C1008
470U EL 25V
AGND
+ C1010
D1003
R1000 10U EL ZENER 5V1 400MW
1K2 0805 1% + C1014
100U EL
AGND1B
R1005
3K3 MF
AV8 Digital Board Power Supply 02_E160 WAF 27/06/02 R921 FROM 10K TO 33K 1.5.0
AGND N5VA
Filename: AVD PSU.Sch 02_E127 AD 27/06/02 Remove R803 for PLL board upgrade 1.4.0
N18V 23425 Notes: 02_101 WF/AD 16/5/02 IC906 FROM 5G24LC08 TO 5G24LC16 TO GIVE MORE SPACE 1.3.0
Waterbeach
R1100 PSU SYNC BCLK
PSU SYNC BCLK
100R 0805
L1101
70R@100MHz P3V3D
L1100 IC1100 7F004
70R@100MHz P3V3D 10 20
GND VCC
1 C1100 C1103
7F004 1OE
19 100N 0805 100N 0805
2OE
C1101 C1104
RP1101 DGND DGND
100N 0805 100N 0805 100R X 4 ISO
2 18 1 8
1A0 1Y0 DAC I2S BCLK LR
4 16 2 7
DGND DGND 1A1 1Y1 DAC I2S BCLK CS
16
DGND 6 14 3 6
IC1102 1A2 1Y2 DAC I2S BCLK LSRS
R1101 8 12 4 5
1A3 1Y3 DAC I2S BCLK LSBRSB
VCC
17 3 8 1
1 100R 0805 1% 2A0 2Y0 DAC I2S LRCLK LR
MR 15 5 7 2
2A1 2Y1 DAC I2S LRCLK CS
13 7 6 3
9 R1102 2A2 2Y2 DAC I2S LRCLK LSRS
RCLK MCLK CP 11 9 5 4
2A3 2Y3 DAC I2S LRCLK LSBRSB
100R 0805 1% 100R X 4 ISO
3 2
8
7
6
5
8
7
6
5
DSP2 BCLK D0 Q0 74LVC244AD RP1100
4 5 CP1100 CP1101
DSP2 LRCLK D1 Q1 100P X 4 ISO 100P X 4 ISO
6 7
DATA LR D2 Q2
11 10
DATA CS D3 Q3
13 12
DATA LSRS D4 Q4
1
2
3
4
1
2
3
4
14 15
DATA LSBRSB D5 Q5
DGND
GND 74LV174 D SM
8
DGND
RP1102
8 1
DAC I2S DATA LR
7 2
DAC I2S DATA CS
6 3
DAC I2S DATA LSRS
5 4
DAC I2S DATA LSBRSB
100R X 4 ISO
5
6
7
8
CP1102
100P X 4 ISO
4
3
2
1
SK1100
DGND 1
2
3
4
5
6
7
8
AMPCT8
DGND
SK1101
1
DSP2 BCLK
2
3
DSP2 LRCLK
4
5
DATA LR
6
DATA CS
7
DATA LSRS
8
DATA LSBRSB
AMPCT8
DGND
AV8 Reclocking 02_E160 WAF 27/06/02 R921 FROM 10K TO 33K 1.5.0
Filename: AVD RECLOCKING.SCH 02_E127 AD 27/06/02 Remove R803 for PLL board upgrade 1.4.0
Waterbeach
Power Supply
Board
L897
Contents
! Component overlay
! Parts list
! Circuit diagrams
These supplies are floating to allow them to be configured
AV8 Power Supply Board as positive or negative supplies to suit the particular
display used.
The outputs are semi-regulated by a zener/emitter follower
circuit. The Output voltages my be trimmed by addition of
The 40W Resonant supply is designed to produce resistors between the lines +40V_SET and +5V_SET.
extremely low levels of conducted and radiated noise. The
supply is based around a discontinuous inductor current Note. The +40V rail was originally to be set to +36V as
single ended flyback topology with active clamp. The marked on the drawings but it was found that the display
active clamp eliminates the power losses normally was to bright and subsequently has been adjusted to +21V.
associated with RCD type clamps and also eliminates the
high voltage ringing waveform normally present on the
primary inductance. In addition current is transferred to the
output capacitors as a half wave sinusoid rather than a
External Synchronisation Input
triangle wave which would normally be expected from a
The free running frequency of the PSU is around 75KHz.
flyback supply. The sinusoidal current waveform into the
For applications which require synchronisation to a system
output capacitors results in reduced output noise with
clock, the PSU may be entrained to an applied Sync signal.
attenuated high frequency response.
The Sync signal should be between 85KHz and 100KHz.
The Sync signal is applied via line SYNC (SK8-1) and
The PSU provides the following functionality
should be a TTL level 50%duty cycle square wave.
! Universal input voltage range 85V ac rms to
265V ac rms.
! Eight regulated supply rails.
External PSU Kill Signal
The output voltages are provided as 3 groups of supplies. For applications which require a means of shutting down
the PSU (e.g. in the event of a detected fault scenario) then
! Digital supplies PSU latched shutdown may be initiated by pulling and
The digital supplies are for use on non audio circuits e.g holding line PSUKILL* to DGND. The PSU will enter a
microprocessor and similar circuitry, they are referenced to latched shutdown state after around 1second. The Latched
DGND. shutdown forces all output supplies to 0V and can be
defeated only by removing the mains input to the PSU for
>15seconds.
Digital supply Voltage tolerance Max current
rails
+3V3 3% 1.5A
+5V 3% 1A Under-voltage lockout
+12V 12.9V 5% 500mA
The PSU is protected against the input voltage being too
-12V 12.9V 5% 500mA
low (which would otherwise cause the input current to be
excessive for a given output power). In the event of the
input voltage being <75V ac rms then the PSU control IC
will disable gate drive signals and the PSU output voltages
! Analogue supplies
will fall to zero.
The analogue supplies are for use on audio circuitry, they
are referenced to AGND.
Output Over-voltage Protection
Analogue supply Voltage tolerance Max current
rails The output voltages are monitored and in the event of the
+20.8V 5% 300mA output voltages rising approx 15% above specified limits
-20.8V 5% 300mA for >0.5 seconds then a latched shutdown event will be
+18V 2% 300mA triggered. This mechanism is not intended to protect
-18V 2% 300mA sensitive components from damaging transients but is
intended to protect the PSU and its load in the event of the
feedback signal failure.
Note. The rated supply currents for the analogue supplies
are 300mA per rail. The +18V and –18V supplies are In this design both the 3V3 and +5V are sensed. In the
provided by 3 terminal regulators which derive their event of a failure in e.g. the 5V rail then the feedback loop
current from the +21V and –21V rails. The current ratings will try to make the other rail voltage high enough to
can thus be written. supply all of the feedback current which the other, now
broken, supply was formerly contributing toward. This
Sum of output current from +21V and +18V = 0.3A max would normally force the 3V3 supply to more than twice
Sum of output current from -21V and -18V = 0.3A max its expected value (and all of the other supplies would be
multiplied by the same factor). The provided mechanism
prevents this eventuality.
AGND and DGND are joined together at 1 place on the
PSU (LK1)
Feedback loop failure protection
! Adjustable supplies In the event of the feedback loop failing (eg. due to a
o +40V (adjustable) broken feedback component) then the supply will enter
o +7V5 (adjustable)) latched shutdown after around 1 second.
Adjustable supply Max current

rails
+21V 30mA
5V 150mA
Overcurrent Protection Figure 2
A number of mechanisms protect the PSU in the event of a These waveforms are for a non resonant ordinary
short circuit or very high load being placed on one of the discontinuous flyback supply to illustrate the operation of
outputs. the circuit. The drain waveform starts at the voltage on the
input capacitor C35 and falls to near zero when the mosfet
The PSU has a power limit of around 45W. If an attempt is is switched on. When the mosfet is switched off the drain
made to draw more power than this then the PSU will voltage flies above the input voltage and produces the
power limit. This will show up as a reduction in the output ringing waveform as shown. The current then ramps down
voltages. This will in turn force the feedback loop to into Cout. When the current has fallen to zero there is
attempt to demand more power throughput to correct the again some ringing. The frequency of the ringing is
low output voltages. The feedback signal will then trigger dependent on circuit parasitics.
the feedback loop failure mechanism which will then force
the PSU into latched shutdown if this persists for more The primary current can be viewed by looking at the
than around 1second. voltage across R30. The output diode current can be
measured by using a current probe around Dout or inferred
by looking at the voltage waveform across Cout. The
Mains Present Signal falling ramp should produce a small voltage ramp across
the ESR of Cout.
The PSU provides a signal MAINSOK* (active low when
mains supply is OK). This signal is provided as an open By considering the simplified circuit it can be seen that all
collector signal from SK8-2. The signal will go high (via a of the output rails are developed in the same way. The
pull-up resistor external to the PSU) when the mains output diodes provide current to the large reservoir
supply is removed and will then provide > around 20mS capacitors on each rail.
warning of the imminent collapse of the output rails.
The actual time between the rising edge of MAINSOK*

and the output voltage rails falling out of spec is dependent
on mains input voltage and output load current. The output
voltages will hold up longer when the load current is low
and the mains input is high. The 20mS hold up spec is
based on low mains voltage and full load.
Inrush current protection

The PSU has an NTC in series with the input reservoir
capacitor. When the supply is first powered up the NTC is
cold and exhibits a resistance of around 25Ohms which
limits the current into the capacitor and prevents damage to
the capacitor, fuses and mains switch. After several
seconds the NTC temperature rises to around 90C and the
resistance falls to a low value allowing normal operation.
PSU Over-temperature Protection

The PSU transformer is fitted with a one shot thermal fuse.
This opens at 120C and removes the supply to the primary
side controller. The thermal trip is taped to the outside of
the transformer so that it could in principal be changed.
The materials from which the transformer is constructed
are rated for operation at 130C and in normal operation the
TX surface temperature is < 90C.
Figure 1
This diagram shows a very simplified PSU block diagram.
Only one output is shown and the active clamp is omitted.
The basis operation is as follows.
At the beginning of the switching cycle the gate drive

signal to M2 goes high. M2 is turned ON and the voltage
across C35 is applied across the primary of L1. During this
stage the voltage on the anode of Dout is negative the
diode is reverse biased and no current flows in the
secondary winding. The voltage applied across the primary
causes the current in L1 primary to ramp up from zero.
When the control circuit turns off M2 by taking gate drive
low then the bottom of the inductor flies back above the
input voltage . This flyback action causes the output diode
Dout to conduct and current is transferred to the output
capacitor Cout.
Figure 1
LIVE
Input Filter and Rectifier C35 L1 31DQ10 Cout
NEUTRAL 250U DO-201AD
100UF 2200UF
EARTH 400V 16V
YXF
DGND
M2
GDRV MTP6N60E
TO-220
PRIMARY CONTROLLER Isns
R30
0R22
0W25
MF
DC FEEDBACK
DGND
SYNC PULSE
SHUTDOWN
PRIMARY SIDE FEEDBACK BLOCK SECONDARY SIDE CONTROLLER
1
IC2
Figure 2
M2 Drain
Gate Drive
Primay Current
Dout Current
L897 Power Supply Parts List Issue 4.1

BR1 3BGBU4K Diode Bridge Rectifier GBU4K Plastic Package 4A 800V
C1 2K233 Capacitor X1 Y2 RATED Ceramic 7.5mm Pitch 3N3 250V
C2 2D422 Capacitor X2 Boxed Polypropylene 22.5mm Pitch 275V 220NF
C3 2D422 Capacitor X2 Boxed Polypropylene 22.5mm Pitch 275V 220NF
C32 2Y410 Capacitor Radial Boxed PE Pitch 15mm 100NF 400V
C35 2N710F Capacitor Radial Electrolytic Claw Mount 100UF 400V
C37 2ZL810C Capacitor Ultra Low Impedance Radial Electrolytic Dia 12.5mm Pitch 5mm 1000UF 35V
C40 2ZL847 Capacitor Ultra Low Impedance Radial Electrolytic Dia 12.5mm Pitch 5mm 4700UF 10V
C42 2ZL847 Capacitor Ultra Low Impedance Radial Electrolytic Dia 12.5mm Pitch 5mm 4700UF 10V
C53 2E147 Capacitor High Voltage Ceramic 470PF 1KV
C54 2A122 Capacitor Ceramic 5mm Pitch 50V 10% 220pF
C58 2Z710E Capacitor Low Impedance Radial Electrolytic Dia 10mm Pitch 5mm 100UF 63V
C59 2Z710E Capacitor Low Impedance Radial Electrolytic Dia 10mm Pitch 5mm 100UF 63V

C64 2K210 Capacitor Boxed Polyester 5mm Pitch 5% 100V 1NF
C65 2K210 Capacitor Boxed Polyester 5mm Pitch 5% 100V 1NF
C82 2K247A Capacitor Boxed Polyester 5mm Pitch 5% 100V 4N7
D1 3C11504 Zener Diode 0.5W BZX79C15V DO-35 Package
D3 3B5403F DIODE ULTRAFAST UF5403 DO-201AD Package
D6 3F5822 DIODE SCHOTTKY 1N5822 DO-201AD Package
D7 3F5822 DIODE SCHOTTKY 1N5822 DO-201AD Package
D9 3B4004F Diode Fast Recovery UF4004 DO-41 Package
D11 3A4148 Diode Small Signal 1N4148 DO-35 Package
D22 3F5711 DIODE SCHOTTKY 1N5711 DO-35 Package
F1 C12166 C12166 FUSE 20MM 1A6 T S5021.6A SPRING REDUNDANT
F1-1 8S004 FUSEHOLDER 20MM PCB
F1-2 F022 FUSEHOLDER COVER TO SUIT 8S004
HS1 F007 HEATSINK TO-220 23 degC/W CLIP ON
HS3 E918MC SHIELD EMC 40W RES PSU
HS3-1 HA3V06A M SCREW TORX P/H M3x6MM ST ZP
HS3-2 HA3V10A M SCREW TORX M3x10MM ST ZP
HS3-3 F216 HEATSINK CLIP DOUBLE TO-220 WARTH TSC607-ZP
HS3-4 E941MC INSULATOR FOR 40W RES PSU 30MM X 40MM KOOL PAD
IC1 5D35804 IC Power Supply Controller UCC3580-4N DIP-16 Package
IC2 5THCNW137 Opto Isolator HCNW137
IC3 5D3843 IC Pulse Width Modulator UC3843AN DIP-8 Package
IC4 5T6283 OPTO ISOLATOR SFH628-A3
L1 L910TX FLYBACK TRANSFORMER FOR 40W PSU
L2 7C033 Inductor 33UH 10%

L9 7E031 CHOKE MAINS COMMON MODE 7.7MH
M1 4K6N60E Transistor Mosfet MTP6N60E TO-220 Package
M2 4K6N60E Transistor Mosfet MTP6N60E TO-220 Package
M3 4K120 Transistor Mosfet ZVNL120A Eline Package
PB1 L897PB BLANK PCB 40W RESONANT PSU PCB
PK1 E66901 MAINS SWITCH SPACER GASKET M01/0387
PL10 8K2904 CON VERT HEADER 4WAY
R1 1K515 Resistor Metal Glazed 0.25W 5% 1M5
R2 1C422 Resistor Carbon Film 2W 5% 220K
R3 1H847 Resistor Metal Film 0.25W 1% 4R7
R5 1H422 Resistor Metal Film 0.25W 1% 220K
R17 1H022 Resistor Metal Film 0.25W 1% 22R
R30 1R922 Resistor Metal Film 0.25W 5% 0R22

R53 1H847 Resistor Metal Film 0.25W 1% 4R7
REG1 5D7818 IC VOLTAGE REGULATOR +18V L7818CV TO-220 PACKAGE
REG2 5D7918 IC VOLTAGE REGULATOR -18V L7918CV TO-220 PACKAGE
SK1 8K2306 CON MINIFIT HCS 6WAY
SK10 8K2804 CON HORIZ PCB SKT 4WAY
SW1 A1007 SW PUSH MAINS
TH1 1T005 INRUSH CURRENT LIMITER 25R 3A NTC
TR1 4A546 Transistor BC546B TO92 Package
TR7 4B677 Transistor Darlington BD677 TO-126 Package
TR8 4B677 Transistor Darlington BD677 TO-126 Package
TX1 L909TX GATE DRIVE TRANSFORMER FOR 40W PSU
P21 P25 SK2
SCOPE POINT L5
D5 SCOPE POINT 1
+18VA
13B 2
+12VD
3
UF5403 33UH 2A RA -18VA
L1 DGND 4
C75 + C37 + C45 C7 +21VA
F1 L TX ETD34 250UH 21PIN 7T 5
L8 C CER 220PF 1KV 100N PE
SW1A 1000U 35V LOW Z 100U EL 6
-21VA
2
BR1
LK6
SK1 BRGBU4K 12A AMPCT6
2
33UH 2A RA DGND AGND
4 1 L9 MAINS_SW P35 LK1
PCB NET LINK
~
4 3 AS1A6 VDC325VP SCOPE POINT DGNDN DGND 10MM LINK
+ C41 + C50 C14
5 2 R1 C2 C3 R57 P28
100N PE
1M5 VR25 220N X2 CLASS 220N X2 CLASS 4 1 7T 100R MF 1000U 35V LOW Z 100U EL SCOPE POINT SK3
1
- + L7
6 3 NF D8 1
+18VA
1 2 TH1 12B 2
-12VD AGND
MOLEXPWR6 THERMISTOR 25R 3A 3
~
+ C35 UF5403 33UH 2A RA -18VA
CM_CHOKE 1.5MH SW1B 4
C32 +21VA
3
100U/400V EL 5
C PE 100NF 400V +21VA
P18 SCOPE POINT 6
D3 L2 -21VA
MAINS_SW
LK2
4 14B I O AMPCT6
Vin Vout +18VA AGND
C80 C81
GND
PCB NET LINK 33UH 2A RA
3N3 MAINS 3N3 MAINS TX1 P29 SCOPE POINT
PGND2 UF5403 + C38 + C43 + C48
TX 1:1 GATE DRV M1 24T 11T C74 SK4
C5 P20 C9
MOSFET MTP6N60E C CER 470PF 1KV 1000U 35V LOW Z 22U EL 100U EL 1
G
SCOPE POINT 100N PE +12VD
M1G 3 1 3 REG1 HS1 2
LK7
14A 7818 TO220HS30REG 3
AGND -12VD
20T 20T 2 REG2 HS2 4
PGND1 100N PE D1 + C39 PCB NET LINK
4 2 R4 7918 TO220HS30REG 5
C1 +5VD
G
PGND1 1K0 MF 15V 400MW P2 R58 1000U 35V LOW Z AGND + C44 + C49 6
3N3 MAINS AGNDN C10
SCOPE POINT 24T 11T 100R MF P19 SCOPE POINT 22U EL 100U EL 7
GND
D4 L3 100N PE +3V3D
8
PD1 PGND2 1 13A I O
Vin Vout -18VA
MTG PAD 3.5MM TOP AMPCT8
33UH 2A RA DGND
P30 SCOPE POINT
D18 UF5403
R53 C53 -21VA AGND +21VA
-21VA
C CER 470PF 1KV R61 SK5
1
+12VD
R10 R5 R7 4R7 MF P26 2
1N4148
220K MF 220K MF 220K MF 10R MF +5VNFB SCOPE POINT C29 C26 C24 3
L6 -12VD
M2G 100N PE 100N PE 100N PE 4
11B 5
+5VD +5VD
R17 M2 6
+ C40 33UH 2A RA + C46
PD2 22R MF R20 MOSFET MTP6N60E P27 7
D6 1N5822 +3V3D
MTG PAD 3.5MM TOP R28 R2 R6 R8 10K MF 3T 4700U 10V LOW Z +3V3NFB 100U EL C8 SCOPE POINT 8
D7 1N5822 L4
220K MF 220K CF 2W 220K MF 220K MF 100N PE
11A -12VD DGND +3V3D +5VD +12VD AMPCT8
+3V3D DGND
33UH 2A RA
10B
PGND2
MAINS
R62 10R MF + C42 + C47 SK6

RAMP
C55 P24
LINE
4700U 10V LOW Z 100U EL C15 C30 C27 C23 C21 C20 1
SCOPE POINT +12VD
HT
ISNS 2T 100N PE 100N PE 100N PE 100N PE 100N PE 100N PE 2

C CER 470PF 1KV
3
-12VD
10A 4
DGND
R30 5
DGNDN DGND +5VD
PD3 0R22 MF 6
MTG PAD 3.5MM TOP 7
+3V3D
TR7 0VF2 +7VF2 0VF1 +46VF1 8
D9 UF4004
+46VF1 TRANS MP NPN DARL BD677
AMPCT8
+40VF1 DGND
PGND1 P32 SCOPE POINT C31 C28 C25 C22
C76
R33 100N PE 100N PE 100N PE 100N PE SK7
D14 1K0 MF 1
+40VF1
AUX 5 9B 2
0VF1
R59 R43 3
UF4004 C CER 220PF 1KV +40V_VSET +40V_VSET
PD4 100R MF 4
+ C59 +5VF2
MTG PAD 3.5MM TOP 120C 23T 5
0VF2
NC 100U 63V YXF LOW Z 22K MF 6
+ C61 + C13 + C68 +5V_VSET
9A 7
100U EL 6 D13 22U EL 22U EL
ZENER 500MW 43V P31 SCOPE POINT AMPCT7
0VF1
7T
7 TR8 P34 SCOPE POINT

D10 UF4004
+7VF2 TRANS MP NPN DARL BD677
FIX1 FIX3
FIXING HOLE FIXING HOLE +5VF2
PGND3
C77
HS3 R34
PSU HEATSINK R60 1K0 MF
FIX2 FIX4
8B 100R MF
FIXING HOLE FIXING HOLE +5V_VSET
R44
C CER 220PF 1KV
5T + C58
1
2
3
4
5
6
100U 63V YXF LOW Z 1K0 MF + C69
8A + C18 22U EL
PB1 D12 22U EL
PCB C71 5V6 400MW P33 SCOPE POINT
3N3 MAINS +3V3NFB +5VNFB +12VD
MAINS
LK3
RAMP
0VF2
ISNS
LINE
M1G
M2G
AUX
L897PB DGND
HT
PCB NET LINK

PGND2 PGND2 PGND3 PGND2
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
PL10 PL11 PL12
MAIN PCB PL13
CON 4W 0.1 HDR CON 4W 0.1 HDR CON 4W 0.1 HDR CON 4W 0.1 HDR
SK10 SK11 SK12 SK13

CON 4W MOL4455C CON 4W MOL4455C CON 4W MOL4455C CON 4W MOL4455C
CONTROL PCB
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
IC4
OPTO AC SFH628-A3 +5VNFB' +3V3NFB' +12VD'
M1G'
M2G'
MAINS'
RAMP'
LINE'
VREF5V
HT'
ISNS'
AUX'
PGND2' PGND2' D11

R36
AUX'
DGND'
P10
47R MF
1N4148 SCOPE POINT
R63 PGND4'
VREF5VP 4K7 MF
TR1
ISNS'
M1G'
M2G'
P1 SCOPE POINT BC546B

R35 TR12
BC546B
+5VP
D19 D2 47K MF
+ C57 15V 400MW C4 C78 D21 P11 18V 400MW R69
C12 100U EL 100N PE 100N PE 1N4148 SCOPE POINT C33 47K MF
100N PE NF NF 100N PE +3V3NFB' +5VNFB'
NF
P23 P22
3
PGND2' PGND2' PGND2' R3 R31 D20 + C34 DGND' DGND' DGND' SCOPE POINT SCOPE POINT
4R7 MF 470R MF 5V6 400MW 22U EL
VDD
R11
NFB 13 R51 R52
E/A IN
R18 R19 10K MF 16K MF
100K MF 6 10R MF 10R MF
OUT2
+12VD'
R16 220K MF PGND4' PGND4'
R12 12 P7 SCOPE POINT +5VP
E/A OUT
RAMP'
LINE'
220K MF VREF5V
P3 SCOPE POINT R32 TR6 TR9
4 470R BC556B BC556B
C54 220P CD OUT1
2 NF R39
LINE
P8 SCOPE POINT C16 1K0 MF C17 IC3
P4 SCOPE POINT 100N PE 100N PE IC PWM UC3843
7
P5 SCOPE POINT TR3
LK4
9 5 M3 2
VCC
RAMP PGND BC546B VFB
ZVNL120 R48 PGND4'
PCB NET LINK DGND'
14 NF C82 4N7 PE BA 2500
VREF5VP VREF PGND2' IC2
15 PGND4' 470R MF 8 P12
SS VDD
16 7 2 SCOPE POINT
SHTDWN P9 EN D15
1 6 R24 C66
DELAY
11 SCOPE POINT 3 6 1
GND
OSC1 OUT COMP

10 7 5 +12VD'
R14 47K MF OSC2 CLK C65 GND
LK5 10K MF 47N PE
1N PE 1N4148
PCB NET LINK HCNW137 OPTO R66
8
R15
IC1 D22 15K MF
IC PWM UCC3580-4 1N5711 R68 C79
33K MF P6
C51 R9 C52 C6 C11 R13 10K R22 C72
+
100N PE 33K MF 680P PP 100N PE 100N PE 100K MF C56 SCOPE POINT NF C60 10K MF 3 8 VREF5V 100N PE
PGND4' ISEN VREF
NF 220P PP 220P CD
C83 R64
33P CD 470R MF R50 1U0 EL R25 DGND'
P13 6K8 MF 15K MF
P14
SCOPE POINT
PGND3' SCOPE POINT
GND
4 TR11
RT/CT
R21 R23 TR5 BC546B
10K MF 100K MF BC546B
5
R54 C70 C19
R37 C73 P17 22K MF 3N3 PP 100N PE P36
+ C36 SCOPE POINT SCOPE POINT SK8
C62 D17 C63
100U EL
1K0 MF TR2 100N PE TR13 SYNC 1
C64
R40 TR10 BC546B BC546B MAINSOK* 2
PGND3' PGND4' 1N PE
BC556B PSUKILL* 3
100P CD 1N4148 100P CD
R29 R55 R67 R46 R56 4
1K0 MF 10K MF 22R MF 15K MF 1K0 MF 10K MF
TR4 R47 R38
BC546B R26 470R MF 1K0 MF R65 R27 R49 AMPCT4
10K MF 470R MF 10K MF 2K2 MF
DGND'
DGND'
PGND4'
P15 P16
SCOPE POINT SCOPE POINT
D16
R42
1K0 MF
1N4148
R41 R45
C67
1K0 MF 1K0 MF
100N PE
DRAWING TITLE 02_E142 KAL 15/07/02 R1 SET TO NF IC2 CHANGED TO HCNW137 4.0
40W Universal Power Supply 02_E094 WAF 25/04/02 SCREW ON MOSFET LONGER 3.1
PGND4'
Filename: L897CT_4.0.sch
23425
02_E090 WAF 16/04/02 PCB ONLY UPDATED FOR CHASSIS PLANES 3.0
Notes: 02_E051 KAL 18/02/02 ADDED R69 TO MAINS OK CCT C33 CHANGED TO NF 2.0
A & R Cambridge Ltd. WAF 13/11/01 1.0

Waterbeach
Cambridge CB5 9PB Contact Engineer: Kevin Lamb Contact Tel: (01223) 203252 Printed: 23-Jul-2002 Sheet 1 of 1 DRAWING NO. L897CT
Display
Board
L898
Contents
! Component overlay
! Parts list
! Circuit diagrams
AV8 Display Board
Introduction
The AV8 display board contains the front panel graphical
VFD display module, buttons, LEDs, remote IR receiver
and encoder.
The graphical VFD display receives data directly from the

micro on the digital board (via SK100).
Power Supply
The supply rails are supplied to the Display PCB Via
SK100 from the digital board.
Please note that the supply rail marked P36VF1 has been
reset to a voltage of +21volts, this is because the display
was found to be to bright when supplied with +36volts.
LEDs
These are driven using two 74HCT595 (IC101 and IC102)
output latches controlled via SK100 by the micro on the
digital board.
! LED 100 is a bi-colour LED and is used for
standby.
! LED 101 to LED 110 are function and source
indicators.
Remote receiver
The remote receiver (RX101) output is buffered via a
74HC14D (IC104) this is then connected to the digital
board via SK100 pin15.
Volume/encoder
The encoder (SW124) output A and B is buffered via a
74HC14D (IC104) as PHASE A and PHASE B to the
digital board via SK100 pins 12,13.
Keyboard
The keyboard is polled using a 74HCT595 (IC100), this is
controlled by the micro on the digital board which scans
the keyboard output.
Scanning sequence:
! The outputs of IC100 Q0 to Q7 are set low in
sequence
! The keyboard lines KB0, KB1 and KB2 are
read
When a key is pressed it will result in a low on KB0, KB1

or KB2.
The micro knows which output has been polled low
(IC100 Q0 to Q7) and which line is low KB0, KB1 or KB2
and therefore the intersecting point will represent the key
which has been pressed e.g. Q2 is polled low and KB1 is
read as low means that the “CD” button has been pressed.
L898 Display Board Parts List Issue 1.2

C115 2M610 Capacitor Surface Mount Electrolytic Dia 5mm 10UF 50V
DC100 E916PM DISPLAY CRADLE B1013 (ITRON MN12818A)
DC101 E916PM DISPLAY CRADLE B1013 (ITRON MN12818A)
DISP100 B1013 DISPLAY GRAPHICS 128X18
IC104 5K7414 IC HEX INVERTING SCHMITT TRIGGER 74HC14 SMT
IC105 5M8532 Opamp AD8532AR SM
LED100 3D006 LED 3mm Red/Green Tri-colour L-93WEGW
LED101 3D001 LED 5mm Green SLR-56MGT32
PB L898PB BLANK PCB AV8 DISPLAY PCB
Q100 4A847 Transistor BC847B SOT23 Package
L898 Display Board Parts List Issue 1.2

Q101 4A847 Transistor BC847B SOT23 Package
RX101 B2107 IR RECEIVER MODULE KODENSHI PIC-26043TM2
SK100 8K8430 CON 1.00MM HORIZ SM FFC 30WAY
SP1 E822AP PAD ADHESIVE SPACING - DIVA REMOTE SENSOR
SP3 F195 F195 SPACER 3.2MM OD5MM ID3MM
SW100 A1505 SWITCH TACT SM
SW124 A1211 ROT ENCODER VERT ALPS
1 2 3 4 5 6 7 8
SP3
LED
SPACER P5VD
P3V3D
SPACER F195
THX MUTE EFFECT MODE OK MENU
SW100 SW101 SW104 SW106 SW108 SW110 R100 R101 R116 R117 R118 R119 R120 R121 R122 R123 R124 R125
14
P3V3D Q100 Q101
TACTSW SM TACTSW SM TACTSW SM TACTSW SM TACTSW SM TACTSW SM 220R 0805 220R 0805 220R 0805 220R 0805 220R 0805 220R 0805 220R 0805 220R 0805 220R 0805 220R 0805 220R 0805 220R 0805
+ C126 BC847B BC847B
R105
IC104G C114 100U EL SM
10K 0805 Q_101 Q_102 Q_103 Q_104 Q_105 Q_106 Q_107 Q_108 Q_109 Q_110
7
74HC14 100N 0805
R107 R108
KEYB0 DGND 10K 0805 10K 0805 LED111 LED112 LED101 LED102 LED103 LED104 LED105 LED106 LED107 LED108 LED109 LED110
MUTE DIRECT TONE PHONO/AUX CD TUNER TAPE/MON DVD SAT AV VCR DVD-A
D D
C100
330R 0805
330R 0805
330R 0805
100P NPO 0805 R113 R114 R115
DGND
P3V3D
PHONO/AUX CD TUNER TAPE/MON DIRECT IND12 IND11
SW103 SW105 SW107 SW109 SW102
TACTSW SM TACTSW SM TACTSW SM TACTSW SM TACTSW SM LED100
P3V3D
R106
G
10K 0805
DGNDA
DGND
KEYB1 LED RED/GRN 3MM
C101
100P NPO 0805 P5VD
DGND
R110
DVD SAT AV VCR DVD-A DISPLAY 10K 0805 P5VD
SW114 SW115 SW116 SW117 SW118 SW111
P3V3D TACTSW SM TACTSW SM TACTSW SM TACTSW SM TACTSW SM TACTSW SM IC101
8 16
GND VCC
LED ENABLE 13
R109 OE
KEYB DATA 14 C108
DS
10K 0805 KEYB CLK 11 100N 0805
SHcp(DATA)
10
MR
LED LATCH 12
STcp(LATCH) DGND
KEYB2
C 15 C
Q0
1
Q1
2
C102 Q2
3
100P NPO 0805 Q3
4 Q_100
Q4
5 Q_113
Q5
DGND 6 Q_114
Q6
7
Q7
P5VD
9
Q7OUT
P5VD 5VF2
74HCT595D Q_111
8
IC102
IC100
8 16 + C125
8 16 GND VCC
GND VCC IC105C 100U EL SM
13 AD8532 SM C113
13 OE C109 100N 0805
OE 14
4
KEYB DATA 14 C107 DS 100N 0805 R127 Q_112
DS 100N 0805 11
KEYB CLK 11 SHcp(DATA)
SHcp(DATA) 10 0R0 0805
10 MR
MR 12 DGND DGND 0VF2GND
KEYB LATCH 12 STcp(LATCH)
STcp(LATCH) RP100
DGND
100R X 4 ISO 15 Q_115
15 Q_123 8 1 Q0
Q0 1 Q_116
1 Q_124 7 2 Q1
Q1 2 Q_117
2 Q_125 6 3 Q2
Q2 3 Q_118
3 Q_126 5 4 Q3
Q3 4 Q_119
4 Q_127 8 1 Q4
Q4 5 Q_120
5 Q_128 7 2 Q5
Q5 6 Q_121
6 Q_129 6 3 Q6
Q6 7 Q_122
7 Q_130 5 4 Q7
Q7
RP101 9 SP1 SP2
DGNDD 9 Q7OUT
Q7OUT 100R X 4 ISO
DGNDB 74HCT595D IR RX IR RX
74HCT595D P5VD
SUPPORT PAD SUPPORT PAD
+ C124 DGND P36VF1
C111 P5VD
DGND 100U EL SM
100N 0805 P5VD IR RX SUPPORT PAD IR RX SUPPORT PAD
DISP100 F1 to F2 = 4Vac 150mA
B1013 VDD2 = 40Vdc 20mA To Digital Board IC104B IC104D
3
B DC100 DGND SK100 B
2 IR IN DISP R129 3 4 9 8 R130 IRFP IN
+5V
+5V
DISPLAY CRADLE Graphics Display C116A 100PX4 SM 1 KBDATA KEYB DATA O/P
E916PM C116B 100PX4 SM 2 O/P 10K 0805 100R 0805
C116C 100PX4 SM 3 KBCLK KEYB CLK C112 R128 74HC14 74HC14
DISPLAY CRADLE E916PM P36VF1 RX101
100N 0805
Case
Case
C116D 100PX4 SM 4
GND
GND
SBX1610-52/PIC-26043TM2 22K 0805
DC101 C117A 100PX4 SM 5 LED LATCH
SOUT
LEDL
VDD1
VDD2
VSS
VSS
100PX4 SM
CLK
BLK
LAT
DISPLAY CRADLE C117B 6

SIN
F1
F1
F1
F2
F2
F2
100PX4 SM
1
E916PM C117C 7 KBL KEYB LATCH
C117D 100PX4 SM 8
1
2
3
4
5
6
7
8
9
10
11
12
15
16
17
DISPLAY CRADLE E916PM 100PX4 SM DGNDC DGND

C121A 9 KB0 KEYB0
C121B 100PX4 SM 10 KB1 KEYB1
P5VD P36VF1 C121C 100PX4 SM 11 KB2 KEYB2 DGND
C121D 100PX4 SM 12 PHA PHASE A
+ C115 C118A 100PX4 SM 13 PHB PHASE B
C110 10U EL SM C118B 100PX4 SM 14 LEDEN LED ENABLE
100N 0805 C118C 100PX4 SM 15 IRFPIN IRFP IN
P3V3D
C118D 100PX4 SM 16
R126 P3V3D IC104C
DGND DGND DGND C122A 100PX4 SM 17 FCLK1 FCLOCK1
0R0 0805 74HC14
C122B 100PX4 SM 18 FCLK2 FCLOCK2 IC104A
DISPDAT C122C 100PX4 SM 19 R139 R131
R111 R112 1 2 5 6 PHASE A
DISPLAT C122D 100PX4 SM 20 DISPD DISPDAT
10K 0805 10K 0805 1K0 0805 1% 100R 0805
DISPBLK C119A 100PX4 SM 21
0VF1GND
DISPCLK C119B 100PX4 SM 22 DISPCLK DISPCLK 74HC14
SW124
C119C 100PX4 SM 23
ALPS_ENCODER
IC105A C119D 100PX4 SM 24 DISPL DISPLAT
1 IC104E
Q_132 Q_131 C123A 100PX4 SM 25 A
AD8532 SM 2 74HC14
P5VD C123B 100PX4 SM 26 DISPBLK DISPBLK B IC104F
0VF1GND 0VF2GND
3 C123C 100PX4 SM 27 R140 R132
R137 5VF2 13 12 11 10 PHASE B
1 C123D 100PX4 SM 28
FCLOCK1 R135 2 C120A 100PX4 SM 29 1K0 0805 1% 100R 0805
0R0 0805
R133 100R 0805 C120B 100PX4 SM 30 C103 74HC14 C105 C106
3
10K 0805 C 100P NPO 0805 100P NPO 0805 100P NPO 0805
FIX100
FIXING HOLE 4.1 FFC30H SM
5
DGND C104
5 0VF1GND 100P NPO 0805 DGNDE
R138 C120C
7 C127
FCLOCK2 R136 6 100PX4 SM
0R0 0805 C120D 1N 0805
100R 0805 100PX4 SM C137
R134 IC105B 1N 0805
A DGND A
10K 0805
AD8532 SM CHASSIS1
DGND
DGNDF FIX1 FIX5 FIX102 FIX104 FIX106 FIX108
FIXING HOLE 3.5 FIXING HOLE 3.5 FIXING HOLE 4.1 FIXING HOLE 4.1 FIXING HOLE 4.1 FIXING HOLE 3.5 DRAWING TITLE
DGND
FIX2 FIX3 FIX101
FIXING HOLE 3.5 FIXING HOLE 3.5 FIXING HOLE 4.1 FIX103 FIX105 FIX107 FIX109 AV8 DISPLAY AND KEYBOARD
FIXING HOLE 4.1 FIXING HOLE 4.1 FIXING HOLE 4.1 FIXING HOLE 3.5
23425
C129 C131
C1 1N 0805 1N 0805 C133 Circuit Diagram
1N 0805 1N 0805 PB A & R Cambridge Ltd. Notes:
C2 C3 C128 C135 Pembroke Avenue 02_E046 WAF 14/02/02 REMOTE SENSOR PADS ADDED 1.1
PCB
1N 0805 DGND 1N 0805 CHASSIS1 1N 0805 C130 C132 C134 1N 0805 C136 Denny Industrial Centre
1N 0805 1N 0805 1N 0805 1N 0805 Waterbeach 02_E030 A.D 24/1/02 PRODUCTION ISSUE 1.0
DGND
DGND DGND DGND DGND DGND DGND L898PB_1 Cambridge CB5 9PB ECO No. INITIALS DATE DESCRIPTION OF CHANGE ISSUE
DGND DGND DGND DGND Filename Date Printed Drawn by:
Sheet 1 of 1
J:\Change_Control\ECO_AGENDA\02_E046 AV8 disp pcb L898 add spacers\L898_1.1.ddb - Documents\L898CT_1.1.sch 14-Feb-2002 AD DRAWING NO. L898CT
1 2 3 4 5 6 7 8
Audio
Board
L921
Contents
! Component overlay
! Parts list
! Circuit diagrams
AV8 Audio Board
Introduction
This board forms part of the AV8 Preamp Processor, it performs analogue input selection and routing of analogue
signals to the various outputs. There are four sets of outputs; main, zone2 and two tape loops “Tape” and ”VCR”.
Main and zone2 outputs have volume controls (either of which can be the source for the on-board headphone
amplifier). A gain ranging stage in the middle of the audio path sets the headroom of the signal chain and also
provides a feed to the A-D converter on the digital board.
Control of the board is via the host micro-controller on the digital board.
BLOCK DIAGRAM
2 2
2 Tape out
2
2 Record loop buffers
2 2
2 2 VCR out
2 2
Stereo inputs
2
2
Input Mux
2 ZONE2
2 2 Volume Mute 2
2 2
2 Headphone amp
2 2
2 Headphone select
2
2 2 Headphone
2 2
To ADC Mute MAIN L/R
Gain range 2
2 2
Internal DAC L/R
2
External SACD input L/R Volume
Multichannel Mux
Internal DAC Surround 6
/Centre / Sub channel inputs 6 Surround/

6
6 Centre/
External SACD Surround Mute Sub outs
/Centre / Sub channel inputs Volume
n
Key: Signal bus where n is the number of audio channels
Input switching selects which of the three resistors are in circuit. It is
controlled by the micro via control line demultiplexer
Refer to circuit diagram L921 sheet 1 IC707. Several ranges, nominally +6dB, 0dB, -6dB and -
12dB can be generated depending on the state of the
The 24 off 74HCT4053 analogue multiplexers route the
‘GAIN RANGE’ lines A,B & C as shown below.
various analogue inputs to the four output mix buses:-
Gain Range +6dB 0dB -6dB -12dB
! VCR
! Tape A LOW HI HI HI
! Analogue B LOW LOW HI HI
! Zone2 C LOW LOW LOW HI
The main stereo inputs have 100pF NP0 capacitors to

ground to reduce any high frequency signals radiating IC301A output feeds into an inverting unity gain buffer
from the input cables which are connected to the unit. (IC301B) which is referenced to 0V_SIG. R315 links
This is an EMC preventative measure. 0V_SIG to the ADC circuits on the digital board via
connector SK915.
In addition to be able to select any particular input as the
source, the input impedance of each input connector was
required to remain constant regardless of whether it was External / internal multichannel & main
selected or not. Input selection is therefore performed stereo input multiplexer
using a method called “virtual earth mixing”. Each input
can be switched to one of the four stereo busses via an
input resistor, or switched to ground
This group of multiplexers selects the signals to be routed
to the output volume controls.
For simplicity consider only the main ANALOGUE L
The three signal sources are:-
MIX bus. Each input is fed onto the common bus via a
resistor and an electronic switch. The bus is the input to
! FROM MAIN GR(L/R)
an op-amp in an inverting configuration. The switch either
stereo from the gain ranger
allows the signal through to the op-amp, or shunts it to
! FROM INT MAIN(L/R)
ground. The inverting input of an inverting configured op-
multichannel from the digital-analogue
amp effectively behaves as a ground (hence “virtual
converters on the digital board
earth”), which is why the input impedance looks the same
! FROM EXT MAIN(L/R)
regardless of the state of the switch.
external analogue multichannel source
In theory all inputs can mix into the op-amp
These are selected by one of three control lines from the
simultaneously, but the control software only allows one
micro via control line demultiplexer IC707.
input switch to connect to the op-amp at a time. If
multiple inputs can be heard simultaneously then there
! ANALOGUE TO MAIN
may be a problem with the control logic (see L921 circuit
! INT DECODER
sheet 7), or the AUD SDATA line from the Digital board
! EXT DECODER
may be latched high.
The multiplexers (except for IC204) select the feed-
For the “ANALOGUE L MIX” and “ANALOGUE R
forward resistor in a unity gain inverting amplifier. Left
MIX” buses, the resistor is 15kΩ, for the other three buses,
and right sub-circuits are identical, therefore only left
the value is 100kΩ. The three 100kΩ in parallel with (IC201, IC203A) will be described.
15kΩ give a total input impedance of just over 10kΩ - the
minimum required for THX certification. These particular When ANALOGUE TO MAIN is high, the signal from the
values were chosen to maximise the noise performance of gain ranger is selected via R201. The feedback around op-
the main stereo ANALOGUE L/R MIX buses, bearing in amp IC203A is more complex than a standard inverting
mind that a larger value resistor has poorer noise configuration. Capacitor C203 removes any dc content to
performance. The 100kΩ resistors feed into the op-amps subsequent circuits. However, since capacitors have non-
of the less critical audio paths for ZONE2 and the record linear characteristics which are undesirable and adversely
loops VCR MIX and TAPE MIX. affect the sound, C203 is placed in the feedback path in
series with the feedback resistor R205 to compensate for
these errors. R204 is in parallel with C203 and R205 to
Input gain range provide a local dc feedback path. Without this the op-amp
Refer to circuit diagram L921 sheet 3 would be open-loop at dc and would therefore latch into
the power rail. C202 compensates for stray capacitance at
The gain ranger sets the headroom for the A-D converter the input of the op-amp and rolls off very high frequency
(on the digital board) and for the rest of the analogue gain to provide stability.
chain. The aim is to set the gain such that clip is not quite
reached with the input of the unit receiving a maximum It is normal to see a few volts of dc offset at the output pin
signal. Excessive headroom reduces signal-to-noise of the op-amp. This is because of the high dc gain of the
performance unnecessarily. Left and right channels are circuit (1M / 15k ≈ 67 or +36.5dB). This dc offset could
identical, therefore only the left channel will be described. be due to the input offset voltage of the op-amps
themselves (up to ±2mV for OPA2134, producing a dc
IC301A is the op-amp into which the input resistors feed offset at the output of 134mV) or because of a dc offset
(described in Input switching above). R302 in the fixed supplied by the signal source connected to the unit. In the
feedback path ensures the op-amp cannot go open loop, normal operating mode where the gain ranger is at unity,
causing it to latch into a power rail. C301 compensates for the absolute maximum permitted dc offset at the input to
small stray capacitances at the op-amp input, ensuring it the unit is approximately 150mV. This would produce a
does not oscillate. Switching in R303, R304, R305 or any dc offset at the output pin of the op-amp of about 10.2V.
combination in parallel with R302 sets the closed loop This would still leave sufficient headroom for a 2Vrms
gain with reference to the 15kΩ input resistor. IC302 audio signal on top of this offset.
The surround and sub channels (IC205/206/208/209) are The source for the headphone can be from the MAIN
very similar to the left channel described above except for output (IC502) or ZONE2 (IC505). Selection is by
the op-amp ground references being tied directly to 74HCT4053 multiplexers IC507 and IC508 under micro
0V_SIG. External multichannel inputs (FROM EXT control via control line demultiplexer IC708. IC509 is an
MAIN L, FROM EXT SURR L, etc) have 100pF NP0 LM4880 headphone driver IC which runs off the +5V
capacitors to ground as an EMC preventative measure. (analogue) rail. Its supply is drawn through a 2.2ohm
resistor to try to provide some crosstalk isolation to the
input multiplexers +5V power rail.
Volume control and headphones
Refer to circuit diagram L921 sheet 5,6
Zone2 and record loop outputs
Volume control is performed by a Burr-Brown PGA2310 Refer to circuit diagram L921 sheet 4
volume control chip. This chip is pin and software
compatible with the Crystal Semiconductor CS3310 The input switches on schematic page 1 mix onto a virtual
volume control chip. The only difference is that the earth bus (ZONE2, TAPE OUT or VCR OUT). The
internal op-amps run off ±15 volts rather than ±5 volts. associated op-amps are found here. Zone2 (IC401) has the
The gain is under micro control with steps of 0.5dB. All same type of dc blocking circuit as described before for
volume controls share data, clock and mute control lines sheet 2 of the schematics. Note however that the feed
but have individual chip select lines. The volume of each forward resistor is 100kΩ. To maintain unity gain, the
channel can be controlled individually. “Zero-crossing” feedback resistors R402 and R404 have been chosen such
detect is permanently enabled on each volume chip to give that their value in parallel with 1MΩ equates to 100kΩ.
click-free volume changes. If, however, clicking can be
heard when changing volume, especially at higher levels, TAPE and VCR record outputs (IC402 and IC403) have
it is likely that there is a dc offset into the volume control 100kΩ as the feedback resistor in series with a 47Ω output
chip. This points to an error in the previous stage which protection resistor. The outputs are capacitively coupled
should have removed all dc. The DCA XMUTE line is a without compensation with a weak 100kΩ pull-down to
power-on mute with a time constant set by R703 and C701 0V_SIG to prevent the outputs floating off.
(sheet7). The output op-amps (IC 502, 505 etc) are
configured to block dc and are inverting amplifiers to
restore the polarity of the signal as the volume control Control lines from the micro
chips are non-inverting.
Since all outputs are identical only the main left output
around IC502A will be described. IC501 is a self Control lines for individual switches etc are derived from
contained volume control with non-inverting op-amp. 16-bit words sent as serial data to three sets of serial to
C501 prevents oscillation of IC502A. C507 blocks dc to parallel latches (port expanders). In this way, many local
subsequent stages of the circuit but is in the feedback path. control lines can be provided whilst only using a few
This provides some compensation for capacitor non- micro I/O ports. The same data and clock lines also drive
linearities. R527 provides a local dc path to prevent the the PGA2310 volume control chip. IC702 decodes chip
op-amp latching into rail. R502 provides output selects for the volume control and latch devices. On
protection, limiting current in the event of the output being power up, the contents of the latches is cleared using a
shorted. R503 provides a weak 0V reference to prevent buffered R-C circuit (R703, C701, IC701E/F). This also
the output floating. IC503 is a DG413 analogue switch mutes the volume control chips. In practice however, this
which acts as a mute under micro control via latch clear and volume mute line is of limited use as the
demultiplexer IC708. The five DG413s play a vital role in +5V analogue supply collapses slowly. If the unit is
preventing thumps at turn on/off. switched off and back on within a period of 5 seconds,
C701 will not have discharged via D701 sufficiently for
At power on, the MAIN OUTS ENABLE and ZONE 2 the input of Schmitt trigger IC701E to interpret a LOW
OUTS ENABLE lines are forced low in hardware, pulling condition. The default power-on state for the volume
the output connectors to ground. The hardware control of control chips mute in any case.
these lines is determined by an RC time constant (see
‘control lines from micro’ below for details). This IC708 is a special case as it provides the control of the
allows sufficient time for the micro to boot up and take MAIN and ZONE 2 OUTS ENABLE. These must be low
control of these lines. at power up to prevent turn-on thumps, due to the
initialisation time period of the micro this must be done in
At power off, the micro detects power loss and forces the hardware. C710 and R729 generate a line that is HIGH at
outputs into the mute (grounded) state. This prevents any switch-on, which sets the output of the latch to tristate
pops. However, if the DG413s were run directly off the (high impedance). R535 and R536 pull these lines low so
+/- 15V rails, the outputs were found to drift to a dc level that the output mute ICs switch the outputs to ground,
that tripped power amplifiers into dc protect. This was due theoretically keeping the outputs silent during power-up.
to the way the power rails collapsed. (The -15V rail In practice a small tick may be heard because the logic
actually went slightly positive for a time causing the dc devices don’t begin to operate properly until they have a
output drift.) D506 and D507 isolate the output mutes few volts across them. C710 charges via R729 over a
from the main +/-15V supply. C543 keeps the supplies to period of approximately one second. The falling OE line
the output mutes up until long after the main +/-15V rails to IC708 enables the latch outputs, which have by now
have completely collapsed. R537 and R538 are actually been written to by the uC.
capacitors to decouple both local supplies to ground.
D503 protects the output stage by shunting over-voltage Power supply

spikes to the power rails. (It should be noted that the Refer to circuit diagram L921 sheet 8
diodes are not power devices, therefore they are likely to
fail if a high energy pulse is fired up the outputs of the
The board is powered from the +/-18V and +21V supplies
unit.) C502 shunts any high frequency signals at the
which are regulated using standard LM317T and
output to ground to help EMC.
LM337Ts. IC801 is a voltage regulator and is set for
+15V. IC802 gives -15V and its output is also used to
derive -5.1V using a Zener diode. IC803 gives a +5V
supply. R806 is used to reduce the voltage drop across
IC803 and therefore reduce heat dissipation in the part.
General Overlay / Interconnections

Switch SW901 allows a “ground lift” facility. 0V_SIG is
either isolated from the chassis or tied by R901 and C912
in parallel. Header SK917 connects to the headphone jack
board. R910 and R911 provide a switched 3.3V control
signal from a 5V supply back to the micro to indicate
when headphones are connected.
L921 Audio Board Parts List Issue 1.2


C412 2U610 Capacitor Non-Polar Radial Electrolytic 10UF 63V

C531 2N722 Capacitor Radial Electrolytic Dia 6.3mm Pitch 5mm 220UF 16V
C534 2N722 Capacitor Radial Electrolytic Dia 6.3mm Pitch 5mm 220UF 16V

C812 2Z810C Capacitor Low Impedance Radial Electrolytic Dia 12.5mm Pitch 5mm 1000UF 35V


IC402 5B072D Opamp TL072CD SO-8 Package
IC403 5B072D Opamp TL072CD SO-8 Package
IC501 5A2310 IC AUDIO DIGITAL STEREO VOLUME CTRL
IC503 5S413DY IC QUAD ANALOGUE SWITCH DG413DY SO-16 PACKAGE
IC509 5A4880 IC HeadPhone Amp Nat Semi LM4880M SO-8 Package
IC701 5J7414D DO NOT USE THIS PART! USE 5K7414
IC702 5K74138 IC 3 TO 8 LINE DECODER 74HC138D SMT
JP900 8K004 CON JUMPER SOCKET 0.1IN GOLD BLUE
JP901 8K004 CON JUMPER SOCKET 0.1IN GOLD BLUE
PCB1 L921PB BLANK PCB AV8 AUDIO BOARD
Q701 4A856B Transistor BC856B SOT23 Package



R516 1D847 Resistor Carbon Film 0W5 5% 4R7
R522 1D847 Resistor Carbon Film 0W5 5% 4R7
R537 2J410 Capacitor SM 0805 X7R Ceramic 10% 50V 100N
R538 2J410 Capacitor SM 0805 X7R Ceramic 10% 50V 100N

R806 1C122 Resistor Carbon Film 2W 5% 220R

SC1 E874MC SHIELD EMC AUDIO PCB FMJ AV8
SK902 8D226 Phono socket 2 way vertical gold
SK926 8D230 PHONO SKT 2-WAY HORIZ GOLD
SK928 8K2103 CON SINGLE ROW HDR 0.1IN VERTICAL 3WAY
SK929 8K2103 CON SINGLE ROW HDR 0.1IN VERTICAL 3WAY
SW901 A1008 SW PUSH 2PCO ALPS
1 2 3 4 5 6 7 8
SNAP OFF PCB

+15V
INPUT SWITCHING TAPE & VCR OUTPUTS
SK901
SK926 SK927
+15V1
PHONO2HG 1 1 TAPE L MIX TAPE OUT L
TO PHONO PCB
1 2 2 TAPE L MIX TAPE R MIX TAPE OUT R 1 SK918
Right channel AUXL1 (Page 4)
3 3 AUX L TAPE R MIX
4 4 (Page 1) VCR L MIX VCR OUT L TAPE OUT L F
5 5 VCR L MIX VCR R MIX VCR OUT R
AUXR1
EMC 6 6 AUX R VCR R MIX EMC
7 7 ZONE 2 MIX L ZONE 2 DCA IN L TAPE OUT R N TAPE OUT
8 8 ZONE 2 L MIX ZONE 2 MIX R ZONE 2 DCA IN R
-15V1
ZONE 2 R MIX CONTROL LOGIC
AMPCT8 PHONO2G
Left channel AMPCT8 L921C4_1.2_tape&vcr.sch
C929 AUX TO ZONE2 AUX TO ZONE 2 C913
-15V
1N 0805 0V_SIG DVD TO ZONE2 DVD TO ZONE 2 1N 0805
D SAT TO ZONE2 SAT TO ZONE 2 D
0V_SIGAU AV TO ZONE2 AV TO ZONE 2
(Page 7) 1 SK919
VCR TO ZONE2 VCR TO ZONE 2
DVD IN L TAPE TO ZONE2 TAPE TO ZONE 2 ZONE 2 & MAIN OUTPUTS VCR OUT L F
1 DVDINL
SK902 CD TO ZONE2 CD TO ZONE 2
TUNER TO ZONE2 TUNER TO ZONE 2 ZONE 2 DCA IN L EMC
VCR OUT
F
DVD IN INT MAIN TO ZONE 2 INT MAIN TO ZONE 2 ZONE 2 DCA IN R ZONE2 OUT L VCR OUT R N
EXT MAIN TO ZONE 2 EXT MAIN TO ZONE 2 ZONE2 OUT R
EMC
N
MAIN DCA IN L (Page 5)
DVD IN R AUX IN L AUX TO ANALOGUE AUX TO ANALOGUE MAIN DCA IN R PHONO2G
DVDINR
AUX IN R DVD TO ANALOGUE DVD TO ANALOGUE PHONES OUT L C914
SAT TO ANALOGUE SAT TO ANALOGUE ZONE 2 DCA /CS ZONE 2 DCA /CS PHONES OUT R 1N 0805
PHONO2G C901 DVD IN L AV TO ANALOGUE AV TO ANALOGUE DCA SDATA DCA SDATA
ZONE 2 TO PHONES
MAIN OUTS ENABLE

1N 0805 DVD IN R VCR TO ANALOGUE VCR TO ANALOGUE DCA SCLK DCA SCLK 1 SK920
MAIN TO PHONES
TAPE TO ANALOGUE TAPE TO ANALOGUE DCA XMUTE DCA XMUTE MAIN OUT L
1 SATINL
SK903 SAT IN L CD TO ANALOGUE CD TO ANALOGUE ZONE 2 OUTS ENABLE ZONE 2 OUTS ENABLE MAIN OUT R ZONE 2 OUT L F
SATINR
SAT IN L SAT IN R TUNER TO ANALOGUE TUNER TO ANALOGUE
F
SAT IN MAIN DCA /CS MAIN DCA /CS EMC ZONE 2 OUT
AVINL
AV IN L AUX TO VCR AUX TO VCR DCA SDATA ZONE 2 OUT R N
EMC AVINR
AV IN R DVD TO VCR DVD TO VCR DCA SCLK
N
SAT IN R SAT TO VCR SAT TO VCR DCA XMUTE
VCRINL
VCR IN L AV TO VCR AV TO VCR PHONO2G
VCRINR +5V
VCR IN R VCR TO VCR VCR TO VCR C915
PHONO2G C902 TAPE TO VCR TAPE TO VCR 1N 0805
TAPEINL
1N 0805 TAPE IN L CD TO VCR CD TO VCR L921C5_1.2_outs1.sch
TAPEINR
TAPE IN R TUNER TO VCR TUNER TO VCR MAIN TO PHONES
1 R910 0V_SIG
SK904 ZONE 2 TO PHONES
CDINL
AV IN L CD IN L AUX TO TAPE AUX TO TAPE 5K1 0805
F CDINR
AV IN CD IN R DVD TO TAPE DVD TO TAPE MAIN OUTS ENABLE
SAT TO TAPE SAT TO TAPE
TUNINL
EMC TUNER IN L AV TO TAPE AV TO TAPE SURROUND DCA /CS
N TUNINR
AV IN R TUNER IN R VCR TO TAPE VCR TO TAPE
SK917
TAPE TO TAPE TAPE TO TAPE C928D
EXTMINL 1
EXT MAIN IN L CD TO TAPE CD TO TAPE
PHONO2G EXTMINR 2 100PX4 SM C928C
C903 EXT MAIN IN R TUNER TO TAPE TUNER TO TAPE
PHONES INSERTED 3V3 3 C928B 100PX4 SM
1N 0805 SW901A CENTRE/SUB DCA /CS
2PCO 4 100PX4 SM C928A
1
INT MAIN IN L ANALOGUE L MIX GAIN RANGE A EL1

1 5 100PX4 SM
SK905 INT MAIN IN R ANALOGUE R MIX GAIN RANGE B
VCR IN L GAIN RANGE C Update Box
VCR IN F AMPCT5
C R911 CHS3 C
L921C1_1.2_ipmux.sch ANALOGUE TO MAIN EX DCA /CS 10K 0805 UPDATE_BOX
4
EMC
N
VCR IN R SW901B C912 INT DECODER
2PCO R901 100N 0805 EXT DECODER
PCB1
10K 0805
PHONO2G C904
L921PB bare audio
1N 0805
board 0V_SIG
0V_SIG
1
SK906 GND AT
CTRL EN
SPARE 1
SPARE 2
SPARE 3
SPARE 4
CTRL D0
CTRL D1
CTRL D2
TAPE IN L
SDATA
TAPE IN F L921PB
SCLK
5V PSU MAIN FRONT OUT L SK921
1
EMC
N
TAPE IN R F
L921C7_1.2_ctrlogic.sch EMC
PHONO2G C905 N
MAIN FRONT OUT R
1N 0805 Note: This connector MAIN FRONT OUT
1 reversed in relation to
SK907 SC1 PHONO2G
CD IN L E874MC
it's counterpart on the C916
F digital board
CD IN 1N 0805
EMC screen
EMC SURR OUT L
1
N CONTROL SK922
CD IN R
PHONO2G INPUTS F
10
1
2
3
4
5
6
7
8
9
INT DECODERS
C906 ( FROM DACS ) EMC SURROUND OUT
SK916
1N 0805 SK913 SURR OUT R N
22
DAC LS 1
1 21
SK908 2
20 AUD SDATA
TUNER IN L DAC RS 3 PHONO2G
TUNER IN F 19
4 Power Supply C917
MAIN ANALOG IP GAIN SET 18 AUD SCLK C900C
DAC LSB 5 1N 0805
EMC 17 100PX4 SM
6
N ANALOGUE L MIX GAIN RANGE A 16 AUD SEL 0 C900D
TUNER IN R DAC RSB 7
ANALOGUE R MIX GAIN RANGE B 15 100PX4 SM
A-D GROUND REF
8
GAIN RANGE C 14 AUD SEL 1 C921A CENTRE OUT SK923
1
PHONO2G 13 100PX4 SM (Page 8)
B R902 R904 AMPCT8 B
C907 FROM MAIN GR L 12 AUD SEL 2 C921B
0R0 0805 0R0 0805 F
1N 0805 FROM MAIN GR R 11 100PX4 SM
R905
(Page 3) 10 AUD CTRL EN C921C CENTRE
R903 0R0 0805 EMC
0V_SIG 9 100PX4 SM
0R0 0805 SUB OUT N & SUB OUT
8 AUD SPARE1 C921D
7 100PX4 SM
6 AUD SPARE2 C922A L921C8_1.2_psu.sch
EXT MAIN IN L PHONO2G
1 0V_SIG 5 100PX4 SM
SK909 C918
L921C3_1.2_gainrange.sch 4 AUD SPARE3 C922B
SK928 1N 0805
F 3 100PX4 SM
SK914 1
SK915 2 AUD SPARE4 C922C SK924
DAC L 1 2 JP900 1
EXT EMC 1 1 100PX4 SM
2 3JUMPER
N EXT MAIN IN R 2
MAIN IN DAC R 3 F
3 FFC22V SM C900A C900B SUB3 OUT
4 MOLEX3MV
4 100PX4 SM 100PX4 SM
DAC C 5 CHS1 SURROUND DCA /CS EMC SUB4 OUT
PHONO2G C908 5
6 DCA SDATA SK929 N
MAIN OUTS ENABLE

1N 0805 0V_SIG
DAC S 7 CHS1 CHS1 DCA SCLK 1
AMPCT5
8 DCA XMUTE 2 JP901
1 ANALOGUE
SK910 3 JUMPER PHONO2G
EXT R906 R908 AMPCT8 TO CENTRE/SUB DCA /CS C919
SURROUND F EXT SURR L
0R0 0805 0R0 0805 DCA SDATA MOLEX3MV 1N 0805
IN A-D CONVERTER DCA SCLK
EMC EX OUT L SK925
R907 R909 DCA XMUTE 0V_SIG 1
N EXT SURR R
0R0 0805 0R0 0805
EX DCA /CS F
EXT/ INT DECODER SELECT
DCA SDATA
PHONO2G C909
DCA SCLK EMC EX OUT
1N 0805 0V_SIG FROM MAIN GR L A-D GROUND REF
DCA XMUTE N
EXT FROM MAIN GR R EX OUT R
1 SURROUND OUT L
CENTRE SK911 ANALOGUE TO MAIN
SURR DCA IN L SURROUND OUT R
IN FROM INT MAIN L INT DECODER
F EXT CTR L SURR DCA IN R PHONO2G
FROM INT MAIN R EXT DECODER
CENTRE OUT C920
FROM INT SURR L
EMC CENTRE DCA IN SUB OUT 1N 0805
FROM INT SURR R
EXT N SUB DCA IN
EXT CTR R FROM INT CENTRE
SUB IN EX OUT L
FROM INT SUB MAIN DCA IN L
EX DCA IN L EX OUT R
FROM INT EX L MAIN DCA IN R
PHONO2G EX DCA IN R (Page 6)
C910 FROM INT EX R
1N 0805 SURR DCA IN L
A 0V_SIG A
FROM EXT MAIN L SURR DCA IN R
1 SURROUND,CENTRE,SUB,& EX OUTPUTS
SK912 FROM EXT MAIN R
L921C6_1.2_outs2.sch
EXT FROM EXT SURR L CENTRE DCA IN
F EXT EX IN L
EX IN FROM EXT SURR R SUB DCA IN
FROM EXT CENTRE DRAWING TITLE
EMC
N EXT EX IN R
FROM EXT SUB
FROM EXT EX L
EX DCA IN L
EX DCA IN R
L921CT - AV8 audio board interconnections
FROM EXT EX R
PHONO2G FIX900 FIX901 FIX902 FIX903 FIX904 (Page 2) 23425 Circuit Diagram
C911 FIXING HOLE 3.5 FIXING HOLE 3.5 FIXING HOLE 3.5 FIXING HOLE 3.5 FIXING HOLE 3.5 A & R Cambridge Ltd. Notes: 02_E143 WAF 16/7/02 2 JUMPER LINKS ADDED ACROS SK928 & SK929 1.2
1N 0805 C922D Pembroke Avenue
C926 L921C2_1.2_extintmux.sch 100PX4 SM Denny Industrial Centre
C923 C924 C925 CHS2 C927 Waterbeach 02_E028 MJT 29/01/02 Production release 1.1
0V_SIG CHS3 CHS4 CHS1 CHS5
100P NPO 0805 100P NPO 0805 100P NPO 0805 100P NPO 0805 100P NPO 0805 CHS1 Cambridge CB5 9PB ECO No. INITIALS DATE DESCRIPTION OF CHANGE ISSUE
Filename Date Printed Drawn by:
16-Jul-2002 AD/subcon Sheet 9 of 9 DRAWING NO. L921C9
0V_SIG 0V_SIG 0V_SIG 0V_SIG 0V_SIG J:\Change_Control\ECO_WIP\02_E143 L921 add 2 jumper links\L921_1.2.ddb - Documents\L921C9_1.2.PRJ
1 2 3 4 5 6 7 8
1 2 3 4
TP1 TP3
ANALOGUE L MIX ANALOGUE R MIX
IC301A IC303A
3 IC301B 3
D 1 1 IC303B D
2 5 2 5
C301 7 7
R306 +5V R313
+5V 6 C308 6
C312 33P NPO 0805
33P NPO 0805 4K7 0805 4K7 0805
R302 100N 0805 R309
C303
IC302B IC302A 30K 0805 IC304B 30K 0805 C310
74HCT4053 SM 74HCT4053 SM IC304A
12 33P NPO 0805
1Y0 R303 8
8 14 GND 12 33P NPO 0805
GND 1Z R307 16 1Y0 R310
16 13 VDD 14
VDD 1Y1 30K 0805 1Z
13
VEE
4K7 0805 1Y1 30K 0805 R314
VEE
2
2Y0 R304
15 2
2Z 2Y0 R311 4K7 0805
7
1 15
7
2Y1 15K 0805 AN-L 2Z

1 15K 0805
2Y1
5 R305
3Y0
4 5
3Z C313 100N 0805 3Y0 R312 AN-R
C 3 4 C
3Y1 4K3 0805 3Z
3
3Y1 4K3 0805
11
1S 0V_SIG -5V
-5V 10 6 11 MAINGRR
2S INH 0V_SIG 1S
0V_SIG 9 10 6
3S 2S INH
9
3S
74HCT4053 SM 0V_SIG
74HCT4053 SM
0V_SIG
FROM MAIN GR R
R315
0R0 0805
A-D GROUND REF
0V_SIG
MAINGRL
FROM MAIN GR L
+15V
B C314 C315 B
GAIN RANGE A IC303C
8
100N 0805 1N 0805
GAIN RANGE B
GAIN RANGE C
C317 OPA2134PA SM
4
C316
0V_SIG 100N 0805 1N 0805
+15V
-15V
C304 C305 IC301C DRAWING TITLE

8
100N 0805 1N 0805

L921CT - AV8 audio board gain range section
23425 Circuit Diagram

4
A C307 OPA2134PA SM A
C306 A & R Cambridge Ltd. Notes:
100N 0805 1N 0805 02_E143 WAF 16/7/02 2 JUMPER LINKS ADDED ACROS SK928 & SK929 1.2
0V_SIG Pembroke Avenue
Denny Industrial Centre
02_E028 MJT 29/01/02 Production release 1.1
Waterbeach
-15V Cambridge CB5 9PB ECO No. INITIALS DATE DESCRIPTION OF CHANGE ISSUE
J:\Change_Control\ECO_WIP\02_E143 L921 add 2 jumper links\L921_1.2.ddb - Documents\L921C3_1.2_gainrange.sch 16-Jul-2002 AD/SUBCON Sheet 3 of 9 DRAWING NO. L921C3
1 2 3 4
1 2 3 4
IC402A
R405 TAPEOUTL
IC401A 3 47R 0805 TAPE-L TAPE OUT L
OPA2134PA SM 1
C402
2
3 100U NP TAPE L MIX C411
1 33P NPO 0805 C412
Z2V-L
D 2 TL072 SM 10U NP D
R406
C401 R401
0V_SIG 1M 0805 100K 0805
33P NPO 0805
R402 5 IC402B R408 TAPE-R
Z2DCAINL 47R 0805 C413
ZONE 2 MIX L ZONE 2 DCA IN L 7 R407
110K 0805 6 100K 0805 100P NPO 0805
C403 C414
33P NPO 0805 C415
100P NPO 0805 TL072 SM 10U NP
IC401B R409 TAPEOUTR
OPA2134PA SM TAPE R MIX TAPE OUT R
C405
0V_SIG 100K 0805
5 100U NP TAPE OUTPUT
7
Z2V-R
6
C404 R403 C416 R410

0V_SIG 33P NPO 0805 1M 0805 100P NPO 0805 100K 0805
R404
C Z2DCAINR C
ZONE 2 MIX R ZONE 2 DCA IN R
110K 0805 0V_SIG
C406 IC403A R411
3
47R 0805 VCR-L
1
+15V
2
100P NPO 0805 VCR L MIX C421 VCROUTL
VCR OUT L
33P NPO 0805 C422
0V_SIG
TL072 SM 10U NP
+15V R412
C408 C407 100K 0805
1N 0805 100N 0805
8
IC401C IC403B R414

5 VCR-R
7 47R 0805 R413
C418 C417 6 100K 0805 C423
1N 0805 100N 0805 IC402C C424 100P NPO 0805
8
OPA2134PA SM C425
4
33P NPO 0805

C410 C409 TL072 SM 10U NP
R415 VCROUTR
100N 0805 1N 0805 VCR R MIX VCR OUT R
100K 0805
B 4
TL072 SM B
C419 C420 VCR OUTPUT
-15V 100N 0805 1N 0805
0V_SIG
C426 R416
100P NPO 0805 100K 0805
+15V
-15V
0V_SIG 0V_SIG
0V_SIG
C428 C427
1N 0805 100N 0805 IC403C
8
DRAWING TITLE
L921CT - AV8 audio board input matrix buffer amps
TL072 SM
4
A
C429 C430 23425 Circuit Diagram
A
100N 0805 1N 0805 A & R Cambridge Ltd. Notes:
02_E143 WAF 16/7/02 2 JUMPER LINKS ADDED ACROS SK928 & SK929 1.2
Pembroke Avenue
02_E028 MJT 29/01/02 Production release 1.1
Waterbeach
-15V Cambridge CB5 9PB ECO No. INITIALS DATE DESCRIPTION OF CHANGE ISSUE
0V_SIG Drawn by:
Filename Date Printed
Sheet 4 of 9
J:\Change_Control\ECO_WIP\02_E143 L921 add 2 jumper links\L921_1.2.ddb - Documents\L921C4_1.2_tape&vcr.sch 16-Jul-2002 AD/subcon DRAWING NO. L921C4
1 2 3 4
1 2 3 4 5 6 7 8
MAIN OUTS ENABLE

+15V
MAIN FRONT R535 +15V
+15V_MUTE_MAIN
10K 0805
+15V +5V C541
+5VS
100N 0805 D502
C511 C510 +5VS R526
0V_SIG BAV99W DUAL SM +15V
12
13
+ IC503 3K3 0805
C503 C504 DG413 1N 0805 100N 0805
V+
VL
8
D 10U EL 100N 0805 0V_SIG -15V D
R506 IC502C
OPA2134PA SM
IC501 10K 0805 2 3 MAINOUTR
12
MAIN OUT R
4
0V_SIG PGA2310UA 1 D501
D503 C512 C513 C538
4
5V1 400MW
VA+
VD+
15 14 BAV99W DUAL SM+15V
C501 R527
16 100N 0805 1N 0805
33P NPO 0805 1M 0805 100N 0805
R501 OUT MAIN L -15V
16 14 2 IC502A C507 7 6 MAINOUTL
MAIN DCA IN L VINL VOUTL R502 MAIN OUT L
10K 0805 1 8
3 47R 0805 -15V
OPA2134PA SM 0V_SIG
15 100U NP 10 11 0V_SIG
AGNDL
9
0V_SIG OUT MAIN R
GND
0V_SIG 10 R523 C509 +5V FOR OUTPUT
AGNDR
V-
R503 R505 100P NPO 0805
10K 0805
47K 0805 47K 0805 ENABLE ANALOGUE
4
9 11
MAIN DCA IN R VINR VOUTR SWITCHES ONLY
C508 R528
33P NPO 0805 1M 0805 C502
R524 100P NPO 0805
DGND
6 IC502B C520
MUTE
ZCEN
SCLK
SDO
7 R504
VA-
SDI
CS
10K 0805
5 47R 0805
OPA2134PA SM 100U NP +5V
1
8
2
6
3
5
13
0V_SIG -15V_MUTE_MAIN
0V_SIG IC507A
R511 12
C505 C506 1Y0
0V_SIG MAIN L 14 R525
10U EL
+ 1Z
100N 0805 13 2R2 0805
15K 0805 1Y1 HEADPHONES
-15V
2
R512 2Y0
0V_SIG +5V ZONE 2 L 15
2Z C531
1
15K 0805 2Y1 220U EL PHONES L
R516
+
+ C536 PHONOUTL
5 PHONES OUT L
3Y0 470U EL 25V
4 4R7 W2 CF
3Z R514
3 C537 IC509 R515
3Y1 C530 10K 0805 LM4880
8
100N 0805 47K 0805
C 11 33P NPO 0805 C
1S
6 10
INH 2S
9
DCA XMUTE 3S C529 2 1
74HCT4053 SM 1U0 EL
+
MAIN DCA /CS TO PHONES JACK
3
0V_SIG
7
DCA SCLK
IC508A 6
12
+
DCA SDATA R517 1Y0
MAIN R 14 C532
1Z R521
13 1U0 EL
15K 0805 1Y1 47K 0805
R513
5
R518 2 100K 0805 + R520
2Y0 PHONES R
ZONE 2 R 15 R519 C533 10K 0805 R522
2Z
+
C535 PHONOUTR
1 100K 0805 33P NPO 0805 PHONES OUT R
15K 0805 2Y1 10U EL
C534 4R7 W2 CF
5 220U EL
3Y0
4
3Z
3
3Y1
11 0V_SIG 100mW 20-30 ohms
1S
6 10
INH 2S
9 +15V
3S
74HCT4053 SM
D506
BAS16W SM
0V_SIG
R537 +15V_MUTE_MAIN
MAIN TO PHONES
ZONE 2 TO PHONES
ZONE 2 OUTS ENABLE 100N 0805
+ C543
R536 0V_SIG 10U EL 50V
10K 0805
ZONE 2 +15V_MUTE_MAIN R538
0V_SIG +5VS D507

+15V +5V C542 100N 0805 -15V_MUTE_MAIN
100N 0805 D504 BAS16W SM
12
13
IC506 BAV99W DUAL SM+15V
B B
DG413 0V_SIG
V+
VL
+
C516 C517
10U EL -15V
100N 0805 0V_SIG OUT Z2 L -15V
IC504 R532 2 3 Z2OUTL +5V
12
ZONE2 OUT L
4
PGA2310UA 10K 0805 1

0V_SIG C527 +5V
VA+
D505
VD+
C514 15 14 BAV99W DUAL SM+15V C515 100N 0805

33P NPO 0805 R529 16 100P NPO 0805
1M 0805 IC508B
R531 IC505A +15V IC507B
16 14 2 C539 7 6 -15V Z2OUTR 8
ZONE 2 DCA IN L VINL VOUTL R507 ZONE2 OUT R GND
10K 0805 1 8 8 16
GND VDD
3 47R 0805 16
VDD
VEE
15 OPA2134PA SM 100U NP 10 11
AGNDL
VEE
9
0V_SIG C524 C523 74HCT4053 SM
7
GND
0V_SIG 10 R533 OUT Z2 R C522 1N 0805 100N 0805 74HCT4053 SM
7
AGNDR
V-
100P NPO 0805 C528

10K 0805 R510 R508 IC505C
5
47K 0805 47K 0805 OPA2134PA SM

9 11 C521
ZONE 2 DCA IN R VINR VOUTR 0V_SIG
33P NPO 0805 R530 100N 0805
4
1M 0805
R534 6 C540 C526 C525 -5V
R509
DGND
7 1N 0805 100N 0805 0V_SIG -5V

MUTE
ZCEN
SCLK
10K 0805 IC505B

SDO
5
VA-
SDI
CS
47R 0805
100U NP
OPA2134PA SM
13
1
8
2
6
3
0V_SIG -15V
0V_SIG
-15V_MUTE_MAIN
C518 0V_SIG
+ C519 0V_SIG
10U EL 100N 0805 -15V
+5V
0V_SIG
A A
DCA XMUTE
DRAWING TITLE
ZONE 2 DCA /CS L921CT - AV8 audio Main, Zone 2 and Phones outputs
DCA SCLK
DCA SDATA A & R Cambridge Ltd. Notes: 02_E143 WAF 16/7/02 2 JUMPER LINKS ADDED ACROS SK928 & SK929 1.2
Pembroke Avenue
Denny Industrial Centre MJT 29/01/02 Production release 1.1
Waterbeach 02_E028
Cambridge CB5 9PB ECO No. INITIALS DATE DESCRIPTION OF CHANGE ISSUE
Text
Sheet 5 of 9
J:\Change_Control\ECO_WIP\02_E143 L921 add 2 jumper links\L921_1.2.ddb - Documents\L921C5_1.2_outs1.sch 16-Jul-2002 AD/subcon DRAWING NO. L921C5
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
MAIN OUTS ENABLE

+15V_MUTE_MAIN +15V_MUTE_MAIN
SURROUND +5VS CENTRE/SUB

+5VS
D +15V +5V C643 D601 +15V +5V C644 D602 D
12
13
12
13
100N 0805 IC603 BAV99W DUAL SM+15V 100N 0805 IC609 BAV99W DUAL SM+15V
DG413
V+
V+
VL
VL
DG413
+ +
C603 C604 -15V C629 C630 -15V
10U EL 100N 0805 0V_SIG OUT SUR L 2 3 SURROUTR 10U EL 100N 0805 0V_SIG OUT CTR 2 3 SUBOUT
R610 SURROUND OUT R R623 SUB OUT
IC601 1 IC607 1
12
12
4
4
PGA2310UA 10K 0805 PGA2310UA 10K 0805
0V_SIG 15 14 0V_SIG 15 14
VA+
VA+
VD+
VD+
C601 16 D600 C627 16 D603
33P NPO 0805 R616 BAV99W DUAL SM+15V 33P NPO 0805 R617 BAV99W DUAL SM+15V
1M 0805 7 6 1M 0805 7 6
16 14 R605 2 IC602A C607 8 16 14 R622 2 IC608A C633 8
SURR DCA IN L VINL VOUTL R601 CENTRE DCA IN VINL VOUTL R611
10K 0805 1 -15V 10K 0805 1 -15V
3 47R 0805 10 11 SURROUTL 3 47R 0805 10 11 CTROUT
OPA2134PA SM SURROUND OUT L CENTRE OUT
15 100U NP 9 15 OPA2134PA SM 100U NP 9
AGNDL AGNDL
GND
GND
0V_SIG 0V_SIG
V-
V-
0V_SIG 10 OUT SUR R 0V_SIG 10 OUT SUB
AGNDR R615 AGNDR R624 C635 C628
4
10K 0805 10K 0805 100P NPO 0805 100P NPO 0805
9 11 9 11
SURR DCA IN R VINR VOUTR C609 C602 SUB DCA IN VINR VOUTR
C608 C634 R614 R612
R618 100P NPO 0805 100P NPO 0805 R619 47K 0805
33P NPO 0805 33P NPO 0805
1M 0805 R604 R602 1M 0805
R625 R626
DGND
DGND
6 IC602B C620 6 IC608B C640
MUTE
MUTE
ZCEN
ZCEN
SCLK
SCLK
47K 0805
SDO
SDO
7 R603 7 R613
VA-
SDI
VA-
SDI
CS
CS
10K 0805 47K 0805 47K 0805 10K 0805
5 47R 0805 5 47R 0805 0V_SIG
OPA2134PA SM 100U NP 100U NP -15V_MUTE_MAIN
1
8
2
6
3
1
8
2
6
3
5
13
13
-15V_MUTE_MAIN OPA2134PA SM
0V_SIG 0V_SIG
0V_SIG
C605 C606 0V_SIG C631 C632 0V_SIG
+ +
10U EL 100N 0805 -15V 10U EL 100N 0805 -15V
+5V +5V
0V_SIG 0V_SIG
C C
DCA XMUTE
DCA XMUTE CENTRE/SUB DCA /CS
SURROUND DCA /CS DCA SCLK
DCA SCLK DCA SDATA
DCA SDATA
EX +15V_MUTE_MAIN
+5VS
+15V +5V C645
D605 +15V
100N 0805 +15V
12
13
IC606 BAV99W DUAL SM+15V +15V

V+
VL
+ DG413
C616 C617
10U EL 100N 0805 -15V
0V_SIG OUT EX L
IC604 R629 2 3 EXOUTR C611 C610
12
EX OUT R C624 C623

4
PGA2310UA 10K 0805 1 1N 0805 100N 0805 C637
8
1N 0805 100N 0805 C636
8
0V_SIG 1N 0805
VA+
VD+
8
IC602C 100N 0805
B C614 15 14 IC605C B
OPA2134PA SM IC608C
33P NPO 0805 R620 16 D604 OPA2134PA SM
OPA2134PA SM
1M 0805 BAV99W DUAL SM+15V
R627
4
16 14 2 IC605A C641 7 6
4
EX DCA IN L VINL VOUTL R606
4
10K 0805 1 8 C613 C612
C626 C625
3 47R 0805 -15V 1N 0805 100N 0805 C639 C638
1N 0805 100N 0805
15 OPA2134PA SM 100U NP 10 11 EXOUTL 1N 0805 100N 0805
AGNDL EX OUT L
9
0V_SIG
GND
0V_SIG 10 -15V
AGNDR 0V_SIG -15V
V-
OUT EX R 0V_SIG -15V

R630 0V_SIG
5
9 11 10K 0805
EX DCA IN R VINR VOUTR
C622 C615
C621 100P NPO 0805 100P NPO 0805
33P NPO 0805 R621 R609 R607
DGND
1M 0805
MUTE
ZCEN
SCLK
SDO
R628 6 IC605B C642

VA-
SDI
CS
R608 47K 0805 47K 0805

10K 0805 7
5 47R 0805
1
8
2
6
3
5
13
OPA2134PA SM 100U NP -15V_MUTE_MAIN
0V_SIG 0V_SIG
C618 C619 0V_SIG
+
10U EL 100N 0805 -15V
+5V
0V_SIG
DCA XMUTE
EX DCA /CS
DCA SCLK
A A
DCA SDATA
DRAWING TITLE
L921CT - AV8 audio Surround, Centre/Sub, & Ex outputs
A & R Cambridge Ltd. Notes: 02_E143 WAF 16/7/02 2 JUMPER LINKS ADDED ACROS SK928 & SK929 1.2
Pembroke Avenue
Denny Industrial Centre 02_E028 MJT 29/01/02 Production release 1.1
Waterbeach
J:\Change_Control\ECO_WIP\02_E143 L921 add 2 jumper links\L921_1.2.ddb - Documents\L921C6_1.2_outs2.sch 16-Jul-2002 AD/subcon Sheet 6 of 9 DRAWING NO. L921C6
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
D D
+5V
GAIN RANGE
+5V
+5V
INT/EXT
IP MUX IP MUX
Q701 Q702 Q703 MUTES
BC856B BC856B BC856B
R709 R711 R713 INT MAIN TO ZONE 2

CD TO TAPE IC705 CD TO ANALOGUE IC707
10K 0805 IC703 10K 0805
16
16
16
74HCT595D 10K 0805 74HCT595D 74HCT595D EXT MAIN TO ZONE 2
TAPE TO TAPE TAPE TO ANALOGUE
15 15 15
VCC
VCC
VCC
QA QA QA GAIN RANGE A
11 1 11 1 11 1
SCK QB VCR TO TAPE SCK QB VCR TO ANALOGUE SCK QB
14 2 14 2 14 2
SDI QC SDI QC SDI QC GAIN RANGE B
9 3 9 3 9 3
SDO QD AV TO TAPE SDO QD AV TO ANALOGUE SDO QD
4 4 4
QE QE QE GAIN RANGE C
10 5 10 5 10 5
SCLR QF SAT TO TAPE SCLR QF SAT TO ANALOGUE SCLR QF
6 6 6
QG QG QG INT DECODER
12 7 12 7 12 7
OPCK QH DVD TO TAPE OPCK QH DVD TO ANALOGUE OPCK QH
IC701A IC701B EXT DECODER
GND
GND
GND
13 13 13
R720 OE AUX TO TAPE OE AUX TO ANALOGUE OE
1 2 3 4
SDATA ANALOGUE TO MAIN
10K 0805
8
C703 TUNER TO TAPE C705 TUNER TO ANALOGUE C707
74HC14D 74HC14D 100N 0805 100N 0805 100N 0805
R701
100K 0805
0V_SIG
0V_SIG 0V_SIG
0V_SIG
IC701C IC701D
R721 5 6 9 8
SCLK
10K 0805 +5V
C +5V +5V C
74HC14D 74HC14D
R702
IC704 CD TO VCR CD TO ZONE 2 IC708 MAIN TO PHONES
100K 0805 IC706
16
16
16
74HCT595D 74HCT595D
74HCT595D
TAPE TO VCR TAPE TO ZONE 2 ZONE 2 TO PHONES
15 15 15
VCC
VCC
VCC
QA QA QA
11 1 11 1 11 1
SCK QB VCR TO VCR SCK QB VCR TO ZONE 2 SCK QB ZONE 2 OUTS ENABLE
0V_SIG 14 2 14 2 14 2
SDI QC SDI QC SDI QC
9 3 9 3 9 3
+5V SDO QD AV TO VCR SDO QD AV TO ZONE 2 SDO QD MAIN OUTS ENABLE
4 4 4
QE QE QE
10 5 10 5 10 5
SCLR QF SAT TO VCR SCLR QF SAT TO ZONE 2 SCLR QF CNCT5 CNCT1 SPARE 1
6 6 6
QG QG QG
12 7 12 7 12 7
OPCK QH DVD TO VCR OPCK QH DVD TO ZONE 2 OPCK QH CNCT6 CNCT2 SPARE 2
GND
GND
GND
D701 R710 13 R712 13 R714 13
R703 OE AUX TO VCR OE AUX TO ZONE 2 OE CNCT7 CNCT3 SPARE 3
BAS16W SM 4K7 0805 4K7 0805 4K7 0805
C702 1M 0805
14
8
TUNER TO VCR C706 TUNER TO ZONE 2 C708 CNCT8 CNCT4 SPARE 4
100N 0805 IC701G C704
IC701E IC701F 100N 0805 100N 0805
100N 0805
R704 11 1013 12 SPARE LOGIC
1K0 0805 CONNECTIONS
0V_SIG 0V_SIG 0V_SIG
7
74HC14D 74HC14D 74HC14D
C701 +5V
470N PE
+ C710
1U0 EL
+5V
R729 D702
0V_SIG 1M 0805
C709 BAS16W SM
100N 0805
R722 IC702
16
CTRL D0 74HC138D
0V_SIG
R723 10K 0805 1 15
VCC
CTRL D1 A Y0
2 14
R724 10K 0805 3
B Y1
13
CTRL D2 C Y2
B 12 B
R725 10K 0805 6
Y3
11
CTRL EN G1 Y4
10K 0805 4 10
G2A Y5
5 9
G2B Y6
GND
R707 7
R705 Y7
100K 0805
100K 0805
8
R708 R706
100K 0805 100K 0805
R715 R716 R717 R718 R719

MAIN DCA /CS ZONE 2 DCA /CS SURROUND DCA /CS CENTRE/SUB DCA /CS EX DCA /CS
R728100R 0805 100R 0805 100R 0805 100R 0805 100R 0805
0V_SIG DCA SDATA
100R 0805
R726
DCA SCLK
100R 0805
R727
DCA XMUTE
100R 0805
MAIN DCA ZONE 2 DCA SURROUND DCA CENTRE/SUB DCA EX DCA
A A
DRAWING TITLE
L921CT - AV8 audio board control logic circuit
Pembroke Avenue
Waterbeach 02_E028 MJT 29/01/02 Production release 1.1
J:\Change_Control\ECO_WIP\02_E143 L921 add 2 jumper links\L921_1.2.ddb - Documents\L921C7_1.2_ctrlogic.sch 16-Jul-2002 AD/subcon Sheet 7 of 9 DRAWING NO. L921C7
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
+5V
C208
100N 0805
+15V
8
GND
16
VDD
VEE
INT PROCESSOR ENABLE LINE
IC201B INT DECODER
74HCT4053 SM C205 C204
7
C209 1N 0805 100N 0805 +15V
8
D IC203C D
100N 0805
OPA2134PA SM
4
0V_SIG C221 C222
8
-5V C206 C207 IC207C
100N 0805 1N 0805
100N 0805 1N 0805
IC201A C224 OPA2134PA SM
4
C223
12 -15V 100N 0805 1N 0805 0V_SIG
R201 1Y0 0V_SIG
14
FROM MAIN GR L 1Z
13
15K 0805 1Y1
IC207B
2 OPA2134PA SM
R202 2Y0
15 IC207A -15V IC206A C220
FROM INT MAIN L 2Z IC203A
1 OPA2134PA SM 12 5 100U NP
15K 0805 2Y1 OPA2134PA SM IC205A C218 R217 1Y0
C203 14 7 SURVR
12 3 100U NP FROM INT SURR R 1Z SURV-R
5 3 100U NP R213 1Y0 13 6
R203 3Y0 14 1 SURVL 15K 0805 1Y1
4 1 MFVL FROM INT SURR L 1Z SURV-L
FROM EXT MAIN L 3Z MFV-L 13 2
3 0V_SIG 2 15K 0805 1Y1 2 C219 R219
15K 0805 3Y1 R225 2Y0
C217 R215 15 33P NPO 0805 1M 0805
C202 R204 2 FROM INT SUB 2Z
C201 11 R221 2Y0 1M 0805 1
1S 33P NPO 0805 1M 0805 15 33P NPO 0805 15K 0805 2Y1 R220
100P NPO 0805 6 10 0V_SIG FROM INT CENTRE 2Z
INH 2S 1 SURR DCA IN R
9 15K 0805 2Y1 R216 5
3S R205 R233 3Y0 15K 0805
SURR DCA IN L 4
MAIN DCA IN L 5 FROM INT EX R 3Z
0V_SIG 74HCT4053 SM R229 3Y0 15K 0805 3
15K 0805 4 15K 0805 3Y1
FROM INT EX L 3Z
3 0V_SIG
0V_SIG 15K 0805 3Y1 11
1S
6 10
11 INH 2S 0V_SIG
1S 9
6 10 3S SURROUND RIGHT
INH 2S
9
3S 74HCT4053 SM
SURROUND LEFT +5V
IC204A 74HCT4053 SM
12 C227
1Y0
14 +15V 100N 0805
1Z
13
1Y1 +5V
C 2 IC206B C
2Y0 C225
15 8
2Z 100N 0805 GND
1 16
2Y1 VDD
C240 C239 IC210C
8
IC205B
VEE
5 1N 0805 100N 0805
3Y0 74HCT4053 SM
4
3Z 8
3 GND 74HCT4053 SM
7
3Y1 16 C228
0V_SIG VDD
OPA2134PA SM
4
11
VEE
1S
6 10
INH 2S C242
9 C241 0V_SIG 100N 0805
3S
7
C226 100N 0805 1N 0805
74HCT4053 SM
0V_SIG
0V_SIG 0V_SIG -5V
100N 0805 -15V

IC210B
IC210A OPA2134PA SM C238
0V_SIG -5V OPA2134PA SM IC209A 5 100U NP
C236
R218 12 7 SUBV
3 100U NP 1Y0 SUBV
+5V 14 6
1 CTRV FROM EXT SURR R 1Z
CTRV 13
ANALOGUE TO MAIN C215 0V_SIG2 C230 15K 0805 1Y1 C237 R227
R223 100P NPO 0805 2 33P NPO 0805 1M 0805
100N 0805 C235 R226 2Y0
1M 0805 15 R228
33P NPO 0805 FROM EXT SUB 2Z
IC204B 1
C232 15K 0805 2Y1 SUB DCA IN
74HCT4053 SM R224
100P NPO 0805 15K 0805
8 5
GND R234 3Y0
16 15K 0805 4
VDD FROM EXT EX R 3Z
IC208A 3
15K 0805 3Y1
VEE
12 C234
R214 1Y0 100P NPO 0805
14 11
FROM EXT SURR L 1Z 1S
15K 0805 13 6 10 SUB
7
C216 C229 1Y1 INH 2S

9
100P NPO 0805 CENTRE 3S
2 CENTRE DCA IN
R222 2Y0 0V_SIG
15 74HCT4053 SM
FROM EXT CENTRE 2Z
100N 0805 15K 0805 1
C231 2Y1
100P NPO 0805 +15V
5
R230 3Y0 0V_SIG
0V_SIG -5V 4
B FROM EXT EX L 3Z B
15K 0805 30V_SIG
C233 3Y1
100P NPO 0805 +5V
11
1S
8
6 10 C247 C248 IC211C C253
INH 2S 1N 0805
9 100N 0805
IC202A 3S 100N 0805
12
R206 1Y0 74HCT4053 SM
14 0V_SIG
FROM MAIN GR R 1Z OPA2134PA SM IC209B
4
15K 0805 13
1Y1
+5V 8
C250 GND
2 C249 16
R207 2Y0 C251 0V_SIG VDD
15 100N 0805 1N 0805
FROM INT MAIN R 2Z
VEE
1 100N 0805
15K 0805 2Y1
5 IC208B 74HCT4053 SM IC211B
7
R208 3Y0 C254
4 74HCT4053 SM -15V
FROM EXT MAIN R 3Z IC211A OPA2134PA SM C246
3 0V_SIG IC203B 8
15K 0805 3Y1 GND OPA2134PA SM 5 100U NP
16 C244
OPA2134PA SM C212 VDD 7 EXVR
11 3 100U NP 100N 0805 EXV-R
1S 5 100U NP 6
VEE
6 10 1 EXVL
C210 INH 2S 7 MFVR EXV-L
9 MFV-R 0V_SIG
2 C245 R235
100P NPO 0805 3S 6
0V_SIG -5V 1M 0805
7
C252 C243 R231 33P NPO 0805

74HCT4053 SM C211 R209
33P NPO 0805 1M 0805 R236
33P NPO 0805 1M 0805
0V_SIG EX DCA IN R
R210 R232
100N 0805 EX DCA IN L 15K 0805
MAIN DCA IN R
15K 0805
15K 0805
0V_SIG -5V
+5V 0V_SIG
0V_SIG
C213 EX RIGHT
EX LEFT
100N 0805
EXT DECODER
IC202B
74HCT4053 SM
8
GND
16
VDD
A A
VEE
EXT PROCESSOR ENABLE LINE

7
C214
DRAWING TITLE
L921CT - AV8 audio volume controls source select
100N 0805
0V_SIG -5V A & R Cambridge Ltd. Notes: 02_E143 WAF 16/7/02 2 JUMPER LINKS ADDED ACROS SK928 & SK929 1.2
Pembroke Avenue
J:\Change_Control\ECO_WIP\02_E143 L921 add 2 jumper links\L921_1.2.ddb - Documents\L921C2_1.2_extintmux.sch 16-Jul-2002
Sheet 2 of 9 DRAWING NO. L921C2
1 2 3 4 5 6 7 8
1 2 3 4
+5V
+5V
+15V
D R806 D806 D
D801 R810
1N4003 1N4003 0R0 0805
C801A HS801 TO220HS30REG 220R 2W CF
IC803 LM317T
I O I O
Vin Vout +15V Vin Vout
1000PX4 SM
ADJ
ADJ
C801B D807
D802 1N4003
IC801 LM317T 1N4003
A
R801 C812 R807
1000PX4 SM
C805
C AL YXF 105C 35V 1000UF

100N 0805 220R 0805 390R 0805
CHS2
+ +
R802 C808 + +
R808 C815
2K4 0805 1% C807 0V_SIG C813 C814
100U EL 100N 0805 1K2 0805 100U EL 470U EL 25V
SK801 470U EL 25V
1 +18V
P18V AGND
2
AGND
3 -18V
C N18V C
4 +21V
P21V
5 R804
AGND
6 2K4 0805 1% + + + C811
N21V -21V C810 C809 D805 10U EL 0V_SIG
AMPCT6 100U EL 470U EL 25V 5V1 400MW
C806
R803
C801D 100N 0805
220R 0805
A
IC802 LM337T -5V

1000PX4 SM
ADJ
D804
C801C 1N4003 R805
I O
Vin Vout 3K3 0805
1000PX4 SM -5V
HS802 TO220HS30REG D803
1N4003
CHS2
B B
-15V
-15V
C802
1N 0805
DRAWING TITLE
CHS1
L921CT - AV8 audio board power supply regulators
A 23425 Circuit Diagram

A
A & R Cambridge Ltd. Notes:
02_E143 WAF 16/7/02 2 JUMPER LINKS ADDED ACROS SK928 & SK929 1.2
Pembroke Avenue
Denny Industrial Centre 02_E028 MJT 29/01/02 Production release 1.1
Waterbeach
J:\Change_Control\ECO_WIP\02_E143 L921 add 2 jumper links\L921_1.2.ddb - Documents\L921C8_1.2_psu.sch 16-Jul-2002 AD/subcon Sheet 8 of 9 DRAWING NO. L921C8
1 2 3 4
1 2 3 4 5 6 7 8
AUX DVD SAT AV VCR TAPE CD TUNER

VCRLMIX
VCR L MIX
VCRRMIX
IC101A IC104A IC107A IC110A IC113A IC116A IC119A IC122A VCR R MIX
R101 12 12 12 12 12 12 12 12
1Y0 R109 1Y0 R117 1Y0 R125 1Y0 R133 1Y0 R141 1Y0 R149 1Y0 R157 1Y0
14 14 14 14 14 14 14 14
1Z 1Z 1Z 1Z 1Z 1Z 1Z 1Z
100K 0805 13 100K 0805 13 100K 0805 13 100K 0805 13 100K 0805 13 100K 0805 13 100K 0805 13 100K 0805 13
D 1Y1 1Y1 1Y1 1Y1 1Y1 1Y1 1Y1 1Y1 D
2 2 2 2 2 2 2 2
R102 2Y0 R110 2Y0 R118 2Y0 R126 2Y0 R134 2Y0 R142 2Y0 R150 2Y0 R158 2Y0
15 15 15 15 15 15 15 15
2Z 2Z 2Z 2Z 2Z 2Z 2Z 2Z
1 1 1 1 1 1 1 1
100K 0805 2Y1 100K 0805 2Y1 100K 0805 2Y1 100K 0805 2Y1 100K 0805 2Y1 100K 0805 2Y1 100K 0805 2Y1 100K 0805 2Y1
5 5 5 5 5 5 5 5
4 4 4 4 4 4 4 4
3Z 3Z 3Z 3Z 3Z 3Z 3Z 3Z
3 3 3 3 3 3 3 3
11 11 11 11 11 11 11 11
1S 1S 1S 1S 1S 1S 1S 1S
6 10 6 10 6 10 6 10 6 10 6 10 6 10 6 10
INH 2S INH 2S INH 2S INH 2S INH 2S INH 2S INH 2S INH 2S
9 9 9 9 9 9 9 9
3S 3S 3S 3S 3S 3S 3S 3S
0V_SIG 74HCT4053 SM 0V_SIG 74HCT4053 SM 0V_SIG 74HCT4053 SM 0V_SIG 74HCT4053 SM 0V_SIG 74HCT4053 SM 0V_SIG 74HCT4053 SM 0V_SIG 74HCT4053 SM 0V_SIG 74HCT4053 SM
AUX TO VCR DVD TO VCR SAT TO VCR AV TO VCR VCR TO VCR TAPE TO VCR CD TO VCR TUNER TO VCR
AUX TO TAPE DVD TO TAPE SAT TO TAPE AV TO TAPE VCR TO TAPE TAPE TO TAPE CD TO TAPE TUNER TO TAPE
TAPELMIX
TAPE L MIX
TAPERMIX
IC102A IC105A IC108A IC111A IC114A IC117A IC120A IC123A TAPE R MIX
12 12 R120 12 R128 12 12 R144 12 12 12
R104 1Y0 R112 1Y0 1Y0 1Y0 R136 1Y0 1Y0 R152 1Y0 R160 1Y0
14 14 14 14 14 14 14 14
1Z 1Z 1Z 1Z 1Z 1Z 1Z 1Z
13 13 13 13 13 13 13 13
2 R113 2 2 2 2 2 2 2
R105 2Y0 2Y0 R121 2Y0 R129 2Y0 R137 2Y0 R145 2Y0 R153 2Y0 R161 2Y0
15 15 15 15 15 15 15 15
2Z 2Z 2Z 2Z 2Z 2Z 2Z 2Z
15K 0805 1 1 1 1 1 1 1 1
2Y1 15K 0805 2Y1 15K 0805 2Y1 15K 0805 2Y1 15K 0805 2Y1 15K 0805 2Y1 15K 0805 2Y1 15K 0805 2Y1
5 5 R122 5 5 5 5 5 5
R106 3Y0 R114 3Y0 3Y0 R130 3Y0 R138 3Y0 R146 3Y0 R154 3Y0 R162 3Y0
4 4 4 4 4 4 4 4
3Z 3Z 3Z 3Z 3Z 3Z 3Z 3Z
3 3 3 3 3 3 3 3
11 11 11 11 11 11 11 11
1S 1S 1S 1S 1S 1S 1S 1S
6 10 6 10 6 10 6 10 6 10 6 10 6 10 6 10
INH 2S INH 2S INH 2S INH 2S INH 2S INH 2S INH 2S INH 2S
9 9 9 9 9 9 9 9
3S 3S 3S 3S 3S 3S 3S 3S
C 74HCT4053 SM 74HCT4053 SM 74HCT4053 SM 74HCT4053 SM 74HCT4053 SM 74HCT4053 SM 74HCT4053 SM 74HCT4053 SM C
0V_SIG 0V_SIG 0V_SIG 0V_SIG 0V_SIG 0V_SIG 0V_SIG
0V_SIG
SAT TO ANALOGUE AV TO ANALOGUE VCR TO ANALOGUE TAPE TO ANALOGUE CD TO ANALOGUE TUNER TO ANALOGUE
AUX TO ANALOGUE DVD TO ANALOGUE
ANALLMIX
ANALOGUE L MIX
ANALRMIX
IC103A IC106A IC109A IC112A IC115A IC118A IC121A IC124A ANALOGUE R MIX
R107 12 R115 12 R123 12 R131 12 R139 12 R147 12 R155 12 R163 12

1Y0 1Y0 1Y0 1Y0 1Y0 1Y0 1Y0 1Y0
14 14 14 14 14 14 14 14
1Z 1Z 1Z 1Z 1Z 1Z 1Z 1Z
13 13 13 13 13 13 13 13
2 2 2 2 2 2 2 2
15 15 15 15 15 15 15 15
2Z 2Z 2Z 2Z 2Z 2Z 2Z 2Z
1 1 1 1 1 1 1 1
5 5 5 AVINR 5 VCRINR 5 5 CDINR 5 TUNINR 5
3Y0 3Y0 3Y0 3Y0 3Y0 3Y0 3Y0 3Y0
4 4 4 AVINL 4 VCRINL 4 4 CDINL 4 TUNINL 4
3Z 3Z 3Z 3Z 3Z 3Z 3Z 3Z
3 3 3 3 3 3 3 3
3Y1 3Y1 3Y1 3Y1 3Y1 3Y1 3Y1 3Y1
0V_SIG
AUX IN L DVD IN L SAT IN L AV IN L VCR IN L TAPE IN L CD IN L TUNER IN L
11 11 11 11 11 11 11 11
1S 1S 1S 1S 1S 1S 1S 1S
6 10 6 10 6 10 6 10 6 10 6 10 6 10 6 10
AUX IN R INH 2S DVD IN R INH 2S SAT IN R INH 2S AV IN R INH 2S VCR IN R INH 2S TAPE IN R INH 2S CD IN R INH 2S TUNER IN R INH 2S
9 9 9 9 9 9 9 9
100P NPO 0805
100P NPO 0805
100P NPO 0805
100P NPO 0805
100P NPO 0805
100P NPO 0805
100P NPO 0805
100P NPO 0805

3S 3S 3S 3S 3S 3S 3S 3S
74HCT4053 SM 74HCT4053 SM 74HCT4053 SM 74HCT4053 SM 74HCT4053 SM 74HCT4053 SM 74HCT4053 SM 74HCT4053 SM

C101 C102 C105 C106 C109 C110 C113 C114 C117 C118 C121 C122 C125 C126 C129 C130
AUX TO ZONE2 DVD TO ZONE2 SAT TO ZONE2 AV TO ZONE2 VCR TO ZONE2 TAPE TO ZONE2 CD TO ZONE2 TUNER TO ZONE2
100P NPO 0805 100P NPO 0805 100P NPO 0805 100P NPO 0805 100P NPO 0805 100P NPO 0805 100P NPO 0805 100P NPO 0805
0V_SIG 0V_SIG 0V_SIG 0V_SIG 0V_SIG 0V_SIG 0V_SIG 0V_SIG 0V_SIG 0V_SIG 0V_SIG 0V_SIG 0V_SIG 0V_SIG 0V_SIG 0V_SIG
Z2LMIX
ZONE 2 L MIX
Z2RMIX
R167
0V_SIG 0V_SIG 0V_SIG 0V_SIG R166 100K 0805
B R165 R168 ZONE 2 R MIX B
0V_SIG 0V_SIG
100K 0805 100K 0805 100K 0805
0V_SIG
INT MAIN IN L INT MAIN IN R INT MAIN TO ZONE 2 EXT MAIN IN L EXT MAIN IN R EXT MAIN TO ZONE 2
+5V +5V +5V +5V +5V +5V +5V +5V

16
16
16
16
16
16
16
16
IC101B IC104B IC107B IC110B IC113B IC116B IC119B IC122B
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
7 7 7 7 7 7 7 7
VEE VEE VEE VEE VEE VEE VEE VEE
GND
GND
GND
GND
GND
GND
GND
GND
-5V -5V -5V -5V -5V -5V -5V -5V
8
8
+5V +5V +5V +5V +5V +5V +5V +5V

16
16
16
16
16
16
16
16

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
7 7 7 7 7 7 7 7
GND
GND
GND
GND
GND
GND
GND
GND
-5V -5V -5V -5V -5V -5V -5V -5V

8
+5V +5V +5V +5V +5V +5V +5V +5V

C103 C107 C111 C115 C119 C123 C127 C131
16
16
16
16
16
16
16
16

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
7 7 7 7 7 7 7 7
GND
GND
GND
GND
GND
GND
GND
GND
A A
8

DRAWING TITLE
C104 C108 C112 C116 C120 C124 C128 C132
L921CT - AV8 Audio board input switching section
100N 0805 100N 0805 100N 0805 100N 0805 100N 0805 100N 0805 100N 0805 100N 0805
100N 0805 100N 0805 100N 0805 100N 0805 100N 0805 100N 0805 100N 0805 100N 0805
0V_SIG -5V 0V_SIG -5V 0V_SIG -5V 0V_SIG -5V 0V_SIG -5V 0V_SIG -5V 0V_SIG -5V 0V_SIG -5V 23425 Circuit Diagram
Pembroke Avenue
J:\Change_Control\ECO_WIP\02_E143 L921 add 2 jumper links\L921_1.2.ddb - Documents\L921C1_1.2_ipmux.sch 16-Jul-2002 AD/SUBCON Sheet 1 of 9 DRAWING NO. L921C1
1 2 3 4 5 6 7 8
Video
Board
L922
Contents
! Component overlay
! Parts list
! Circuit diagrams
will not work. This could happen if any of the output caps
AV8 Video Board are DC short.
The monitor 1 and 2 outputs and the Zone 2 output are fed
Introduction directly from the main PCB via SK209 to the 75R series
termination resistors, after the termination resistors are the
The L922 board is the video and I/O board for the AV8 mute transistors which pull to ground to shut down the
preamp processor. This board and its snap off contain the output. This only provides about 20dB of mute however
video multiplexing for composite, s-video and this is enough to shut down the sync so that a monitor will
component/RGB video switching as well as two On not recognise that a signal is present.
Screen display (OSD) chips, one for the main room and
one for Zone 2. The PCB also has the SPDIF digital input The multiplexers are controlled via the serial to parallel
multiplexing, RS232 connector, 12V triggers for zone 1 conversion latches IC204 and IC205. These are
and 2, RC5 input for zone 1 and 2, RC5 output and the programmed by a 16bit data word. The clock for the data
program button for reprogramming the micro controller is (Video Serial CLK A) and the DATA is (Video serial
flash memory. data A), once all sixteen bits have been clocked into the
latch the data is passed to the outputs by clocking the latch
The main video signal is not fed via OSD chip, instead the signal video comp latch.
OSD signal is generated synchronised to the incoming
Video and then cut into the video using a high speed
multiplexer. The only part of the display that comes from Screen Display
the OSD chip is the text and its background.
This technique avoids the whole picture going soft
This sheet contains; the on screen display chip for the
whenever text is displayed however it introduces
main zone 1, the input multiplexer for the onscreen display
significant extra complexity.
chip to select which type of video source to send to the
OSD, the clock oscillators for PAL and NTSC generation,
the clock multiplexer to select PAL or NTSC for each of
Video PCB Icons + Mechanical the zones, the RGB output buffers and sync on green
Refer to circuit diagram L922 sheet 1 insertion, a sync separator and mono-stable to generate a
black level clamp signal.
This sheet contains drawing symbols to enter items on the
run out BOM as well as the chassis fixing points and their IC301 selects the input signal from the composite, S video
associated EMC decoupling capacitors. or Y/G inputs, this signal is buffered by Q300 divided by
two by the two 75R resistors then AC coupled into the
input of the On Screen Display chip IC302. It is also
Video Board Top possible to route the output of the OSD chip itself via this
multiplexer to the input of the sync separator so that the
Refer to circuit diagram L922 sheet 2 black level clamp can still operate when the OSD chip is
generating RGB or YUV signals.
This sheet shows the interconnections between the
different sheets within the Schematic Hierarchy. It also
IC302 is the On Screen Display chip it generates the text
shows the snap off for the Headphone connector.
patterns which are multiplexed into the video using the fast
blanking signal. Fast blanking is asserted whenever there
is activity on the output of the OSD chip. The chip is
Video Board programmed via a serial bus made up of the lines Video
Refer to circuit diagram L922 sheet 3 serial data, Video serial clk and Video serial cs. The
Horizontal line lock is performed by a Phase Locked loop
This snap of PCB contains the composite video inputs the internal to the OSD chip the filter components for which
composite multiplexer and the composite outputs and their are R349, C349 and C350.
mute circuits. The video inputs are 75R terminated then LESCREEN input sets the screen intensity for the
AC coupled to the inputs of two RHOM BA7625 5 : 2 background and LECHAR sets the Screen intensity for the
multiplexers. These multiplexers have a gain of 2 (i.e. Characters. The potential dividers on the pins define the
6dB) expect to be AC coupled at the input and DC coupled voltages.
at the output, if the input is inadvertently DC coupled it
will shut down as the bias network will not operate. This The composite output of the OSD chip is sync tip clamped
could happen if any of the coupling caps are dc short at the by the circuit made up of Q302 Q304 and D300. This
input. circuit pulls the most negative part of the signal to a fixed
voltage, in this case approximately 0v.
IC 200 is the main signal path multiplexer. Output 1 from
the main multiplexer IC200 goes to the main PCB via the The sync tip clamp works in the following way. A fixed
buffer IC203 and SK209 to the OSD chip. IC 202 is the voltage of approximately 1.2v is generated by D300 and
VCR videotape loop it is buffered by IC203 then AC the 4K7 current limiting resistor R343, this holds the base
coupled and connected via a 75R series termination of Q304 at 1.2v which in turn holds the base of Q302 at
resistor to the RCA phono connector SK201. 0.6v. If the voltage on the collector of Q302 goes 0.6 v
below the voltage on the base (i.e. below 0v) the
IC201 is the Zone 2 multilexer output one from this is fed darlington pairQ302 and Q304 turns on and dumps charge
via the buffer IC203 and SK209 to the main PCB where it on the coupling capacitor C348 until the voltage is
goes to the Zone 2 OSD chip. increased to 0v. So the most negative part of the signal
always remains at 0v, the most negative part of a
The Buffer chip IC203 is a BA7623 video driver chip from composite video signal is the sync and hence this is pulled
RHOM, it expects to be DC coupled at the input and AC to 0v.
coupled at the output. If any DC current is drawn from the
output the chip will shut down as the output bias network This sync tip clamp circuit is used for all of the composite
signals so they are all clamped to the same level. This
means that when the output of the OSD is switched into In any other condition the colour is set to white because it
the output the DC level does not change avoiding any is a character i.e text is being displayed.
flickering or brightness changes. Zero volts is used when inserting characters as this
provides a colourless background. I.e. the characters are
The Y output is clamped to 0v at its sync tip by the white on a blue background.
transistor Q301. This is an active clamp that pulls the DC
level to 0v every time a sync pulse occurs. The clamp Q503, Q504 and Q505 are used to mute the RGB output of
signal is created from the composite sync stripped by the the unit when it is not in use and at power up.
OSD chip IC302 this is the shortened to a ~700nS pulse by
the mono stable IC308. The time of the pulse created by
IC308 is set by R310 and C304. The clamp signal is also SPDIF MUX and RXTX
used to clamp the incoming Y signal of both S video and
YUV signals. It is also used when the system is running in
RGB mode to clamp the RGB signals to black level.
The circuit on this sheet multiplexes the seven SPDIF
inputs to a single line that is buffered and passed to the
The RGB output is used when the system is operating in
digital pcb.
RGB mode and creates the colour information for the text
being inserted. The level is reduced from TTL levels to
The input signals are 75 R terminated then AC coupled
video levels by the potential dividers that feed into video
into the multiplexer. The multiplexer is made up of The
buffers made from the opamps IC300 and IC303. A sync
2:1 CMOS switches IC600 IC601 and IC602. The
signal can be added to the green output by activating the
multiplexer works in the same way as the audio
output of the AND gate IC502. This raises the DC level of
multiplexers. It switches the signal between the input to
the whole signal by 300mV then introduces 300mV syncs
the buffer circuit and a DC level at half the rail i.e. 2.5V.
to 0V.
Each multiplexer has a independent select line, only one
multiplexer should be selected at a time as the circuit will
The PAL and NTSC clocks are generated by the CMOS
mix the signal together if more than one is selected.
oscillators. The oscillator is made by applying feedback
around un-buffered 74HCU04 inverters. The oscillation is
After the input signal has been selected by the mux it is
then buffered and amplified by some of the extra gates left
buffered and amplified by IC603. Applying feedback
in the 74HCU04 pack. Both oscillators run at all times so
around a 74HCU04 biases it into the linear region. The
that the system can cope if Zone 1 is running NTSC and
three stages amplify the 0.5V P-P SPDIF signal up to a 5V
Zone 2 is running PAL. Which clock is used for the zone 1
logic level. Two outputs are buffered off of this logic
and zone 2 OSD chips is controlled by the Tri-state buffers
level, one to go to the digital board the other is used for the
in IC305, these form a low noise 2:1 mux for the clocks.
digital record loop.
The digital record output is driven by IC605 either the

RC5 I/O Triggers and RS232 buffered output of the input mux or the SPDIF output of
Refer to circuit diagram L922 sheet 5 the DSP (from the ADC input) can be selected. The signal
is select by the lines SPDIF LOOP and SPDIF ADC TX.
Sheet 5 has two RC5 demodulators made using IC400 and The 75R characteristic impedance is formed from the
IC401, one RC5 mixer and buffer, two 100mA current parallel combination of R613 100R, R626 680R and R627
limited trigger outputs, the RS232 output connector and 680R. The digital output is AC coupled.
the program button for reprogramming the Flash memory
in the micro controller. Control of all of the select lines for the Multiplexers and
Buffers is handled by IC604 and IC606. IC604 and IC606
are latched serial to parallel converters.
YUV/RGB Video Mux and OSD insert
SVIDEO and CVBS OSD insert
The circuit on this sheet multiplexes between the three Refer to circuit diagram L922 sheet 8
RGB/YUV inputs using the high speed multiplexers IC503
and IC505. Once the signal has been selected it is AC The circuits on this sheet switch the OSD generated test
coupled and DC restored using the active clamps into the incoming video. IC700 is the fast video switch that
Q511,Q500 and Q512. (operation of this clamp is inserts the text, it is controlled by the fast banking signal
described on sheet 4). The multiplexer following the DC directly out of the OSD chip. IC700 has a gain of 2 and
restore IC506 inserts text using the fast blanking signal can drive 75R loads.
from the OSD chip. IC506 has a gain of 2 and 75R output
capability to drive the output directly. The composite video signal is sync tip clamped at the
input to the switch by Q701 and Q705 this works in the
The type of signal that is inserted (RGB or YUV) is same way as the Sync tip clamp on sheet 4 that operates on
selected by the mux chip IC500A. The mux can select the the composite signal out of the OSD chip. These two sync
signals from the RGB buffers on Sheet 4 for RGB tip clamps ensure that the DC level is the same at the input
operation or the Y output of the OSD chip and DC levels to the switch so that the text is switched in at the correct
generated by the potential divider R519, R500 and DC level.
R520,R522. These DC levels generate a blue background
for the text when it is not being overlaid on the incoming The S-video Y input is actively clamped by the clamp
video. IC501 switches between the blue background levels signal as described on sheet 4. This ensures that the two S-
and zero volts the signal CHAR OUT is active when a video Y inputs, one from the input source and the other
character is present on the output and it is this that from OSD, are at the same DC level. Ensuring the DC
switches IC501. The OSD B and OSD G signals are In a levels are correct means the text can be inserted at the
logical AND with the Char Out signal to switch between correct level.
blue & white colour. When the circuit is set to blue output,
no green output & no char the colour is set to blue i.e it is
back ground.
The S-video C and OSD C signals do not need a DC clamp
as they will float to the same level due to the nature of the
signal.
S-Video Multiplexer
This contains the multiplexing for the S-Video signals. It
operates in the same way as the composite multiplexer
(Sheet 3 Video board) except two multiplexers are used for
each signal to carry the independent Luma and Chroma
signals.
IC800 and IC807 carry the main feed Luma and Chroma
respectively. IC801 and IC806 carry the VCR record loop
Chroma and Luma respectively. The Main feed is buffered
by IC803 it then goes to the OSD insert sheet, the VCR
output is buffered by IC802 and then output to the VCR
connector.
Control of the Multiplexer is via serial to parallel shift

registers IC804, IC805 and IC808 these also have the
control lines for the SCART control signals, sync on green
and the Mute signals.
Zone 2 OSD
This contains the OSD sync stripper and OSD insert
circuits for Zone 2. It works in a very similar way to the
circuits on sheets 4 and 8 combined together. As Zone 2
only operates in composite the circuit is without the extra
multiplexing for S-Video and Component signals.
The Zone 2 video comes from the video input sheet 3

buffer it is terminated on this sheet then fed to both the
OSD chip IC900 and the OSD insert multiplexer (Pixel
Switch)IC902. Characters are generated by the OSD and
this signal is present on the second input to the pixel
switch. Both of the signal are sync tip clamped by
transistors Q900, Q901, this means that their DC levels at
the input to the pixel switch should be about the same.
The fast blanking signal from the OSD controls the

position of the pixel switch. Fast blanking is high when
OSD characters are being generated this causes the pixel
switch to change to the output from the OSD chip. The
pixel switch IC902 has a video buffer output and a gain of
two. This buffered output is fed back to the Video board
(sheet 3) and out via the Zone 2 connector.
The vertical sync output of the sync separator IC901 is

used to determine if the incoming video is PAL or NTSC
so that the correct clock can be provided to the OSD chip.
! Vertical sync 50Hz = PAL 17.73447MHz

! Vertical sync 60Hz = NTSC 14.31818MHz
L922 Video Board Parts List Issue 3.2


C304 2L210 Capacitor SM 0805 NPO Ceramic 5% 100V 1N0
C349 2KA315 Capacitor Boxed Polyester 5mm Pitch 5% 100VDC 15N





CP1 2L110 Capacitor SM 0805 NPO Ceramic 5% 100V 100P
CP2 2L110 Capacitor SM 0805 NPO Ceramic 5% 100V 100P
CP3 2J210 Capacitor SM 0805 X7R Ceramic 10% 50V 1N
D400 3CW34V7 Zener Diode 0.25W Surface Mount BZX84C4V7 SOT-23 Package
D401 3CW34V7 Zener Diode 0.25W Surface Mount BZX84C4V7 SOT-23 Package
HS1000 F004 HEATSINK BLACK TO220 23.7 degC/W
IC200 5V7625 IC MUX VIDEO ROHM BA7625 DIP-16 PACKAGE
IC203 5V7623 IC VIDEO BUFFER ROHM BA7623F SO-8 PACKAGE
IC300 5B5244 Opamp EL5244CS SO-8 Package
IC302 5V5730 IC OSD ST STV5730A SO-28 package
IC303 5B5244 Opamp EL5244CS SO-8 Package
IC304 5V4581 IC Video Sync Separator 50% slice SO-8 Package
IC305 5K74125T IC QUAD BUFFER 74HCT125D SMT

IC306 5K7404 IC HEX INVERTER 74HCU04D SMT
IC308 5K74123 IC DUAL RETRIGGERABLE MONOSTABLE WITH RESET 74HC123D PLASTIC SO-16
IC400 5M393AD IC COMPARATORLM393AM SO-8 PACKAGE
IC401 5M393AD IC COMPARATORLM393AM SO-8 PACKAGE
IC500 5K4053 IC TRIPLE 2 CHANNEL ANALOGUE MUX 74LV4053D SMT
IC502 5K7408 IC QUAD 2-INPUT AND GATE 74HC08D SM
IC503 5V4331 IC VIDEO MUX 300MHZ EL4331CS SO-16
IC505 5V4331 IC VIDEO MUX 300MHZ EL4331CS SO-16
IC506 5A4332 IC VIDEO MUX TRIPLE 300MHZ SO-16 package
IC605 5K74125T IC QUAD BUFFER 74HCT125D SMT
IC607 5TG550R SPDIF OPTICAL RX TOSLINK GP1FA550RZ
IC608 5TG550R SPDIF OPTICAL RX TOSLINK GP1FA550RZ
IC701 5K74244T IC OCTAL 3 STATE BUFFER 74HCT244D SMT
IC900 5V5730 IC OSD ST STV5730A SO-28 package
IC901 5V4581 IC Video Sync Separator 50% slice SO-8 Package
L400 7D327 Inductor 27mH 5% SCREENED
L401 7D327 Inductor 27mH 5% SCREENED
L601 7E101 Common Mode Choke 1000R@100MHz
PCB L922PB BLANK PCB AV8 VIDEO BOARD

Q302 4D17H Transistor BFS17H SOT23 Package
Q400 4B180 Transistor BD180 TO126 Package
Q417 4AFMMT597 Transistor FMMT597 SOT23 Package
Q418 4AFMMT597 Transistor FMMT597 SOT23 Package
Q426 4D10KP Transistor MMUN2111LT1 SOT23 Package


R461 1E147 Resistor Carbon Film 1W 5% 470R



R1002 1C856 Resistor Carbon Film 2W 5% 5R6
SC1 E870MC SHIELD EMC TOP-VIDEO PCB FMJ AV8
SC2 E869MC SHIELD EMC VIDEO PCB FMJ AV8
SK200 8D221 PHONO SKT SINGLE GOLD
SK209 8K8022B CON 1.00MM VERTICAL FFC 22WAY FMN SERIES
SK400 8D233 CON PCB JACK 3.5MM STEREO
SK401 8K9009M CON DTYPE HORIZ 9WAY MALE WITH BOARDLOCK
SK402 8D304 SKT JACK DUAL 3.5MM STEREO
SK403 8D304 SKT JACK DUAL 3.5MM STEREO
SK404 8D233 CON PCB JACK 3.5MM STEREO
SK500 8D225 PHONO SKT 4-WAY GOLD
SK601 8D232 PHONO SKT 2 WAY VERT GOLD INDIVIDUAL GNDS
SK700 8K8022B CON 1.00MM VERTICAL FFC 22WAY FMN SERIES
SK701 8D2272 CON SVHS MINI DIN UNSCREENED
SKP1 8K2005 CON CT SERIES VERTICAL 5WAY
SKP2 8D301 CON PCB STEREO JACK
SW402 A1501 SWITCH TACT SDT SERIES
X300 7X022 Crystal 17.73447MHz low profile HC49
X301 7X020 Crystal 14.31818MHz low profile HC49
L922 AV8 Video Circuit
VID TOP.SCH
VID TOP.SCH
REF HOLES
SUB BOARD FIXINGS H/P BOARD FIXINGS
FIX5 FIX9 FIX10 FIX14 FIX11 FIX13 FIX12 FIX16 FIX6 FIX7 FIX8 FIX15
FIXING HOLE 3.5 FIXING HOLE 3.5 FIXING HOLE 3.5 FIXING HOLE 3.2 FIXING HOLE 3.5 FIXING HOLE 3.2 FIXING HOLE 3.5
FIXING HOLE 3.5 FIXING HOLE 3.5 FIXING HOLE 3.5 FIXING HOLE 3.5
FIXING HOLE 3.5
C109 C110 C114
C111 C113 C112
C100 C101
1N 0805 1N 0805 CHASSIS
1N 0805 1N 0805
1N 0805 1N 0805 1N 0805 1N 0805
CHASSISB DGND VGND
DGND VGNDA CHASSISA HPCHASSIS
MAIN BOARD FIXINGS
FIX17 FIX1 FIX2 FIX3 FIX4
FIXING HOLE 3.5 FIXING HOLE 3.5 FIXING HOLE 3.5 FIXING HOLE 3.5 FIXING HOLE 3.5
C104 C105 C106 C107

1N 0805 1N 0805 1N 0805 1N 0805
VGND CHASSIS
TL1 TL2 TL3

TOOLING TOOLINGTOOLING
DRAWING TITLE 02_E163 WAF 8/08/02 IC701 CHANGED FROM 74LV244D TO 74HCT244D 3.2
DD4 PS PCB DD5
PCB MATERIAL
AV8 Video PCB Icons + Mech parts 02_E112 AJD 6/06/02 Updated R431 and 430 to improve the IR reciever reliability. 3.1.0
Photo Strip PCB Update Box
FR4, 1 OZ Cu
FD_1 FD_2 FD_3 FD_4 FD_5 FD_6 FD_7 FD_8 Mods to pass THX (video levels, clocks, black clamp) and board outline.
Filename: L922CT_3.2.Sch 02_E103 MJT 15/05/02 3.0
23425
FR4_1OZ PHOTO_STRIP UPDATE_BOX Sch symbol for 3.5mm jack (scart ctrl) corrected and connections swapped.
L922PB
FIDUCIALFIDUCIALFIDUCIALFIDUCIALFIDUCIALFIDUCIALFIDUCIALFIDUCIAL Notes: 02_E053 MJT 26/02/02 FINAL RELEASE MODS ADDED BEFORE PRODUCTION 2.0
A & R Cambridge Ltd. 02_E029 WAF 31/1/02 PRODUCTION ISSUE FOR ATE 1.0
Waterbeach
Cambridge CB5 9PB Contact Engineer: Andrew Dutton Contact Tel: (01223) 203200 Printed: 8-Aug-2002 Sheet 1 of 11 DRAWING NO. L922CT
L922 AV8 Video Circuit
VID RGB YUV video mux VID On Screen Display
VID RGB YUV video mux.SCH VID On Screen Display.Sch
OSD R
OSD R OSD R
OSD G
OSD G OSD G
OSD B 4 SKP2
OSD B OSD B
OSD Y 5
OSD Y L
CLAMP_ON SKP1
CLAMP_ON
RGB MUTE 1 2
RGB MUTE SYNC ON GREEN LHC
OSD G TTL 2 3
OSD G TTL OSD G TTL RHC
OSD B TTL 3 1
OSD B TTL OSD B TTL
BLACK CLAMP 4
BLACK CLAMP COMP SYNC HPSKT
CHAR OUT 5 6
CHAR OUT CHAR OUT
Y/G 2V 7
Y/G 2V Y/G 2V R
FAST BLANKING BLACK CLAMP AMPCT5
FAST BLANKING BLACK CLAMP
RGB/YUV INPUT SEL 1 CP1 CP2 CP3
RGB/YUV INPUT SEL 1 1N 0805
RGB/YUV INPUT SEL
RGB/YUV INPUT SEL
OSD RGB/YUV SEL
OSD RGB/YUV SEL
100P NPO 0805 100P NPO 0805
VID SVideo mux
VID SVideo mux.sch
HPCHASSIS
OSD RGB/YUV SEL PHONES SKT BOARD
RGB/YUV INPUT SEL
RGB/YUV INPUT SEL 1
SYNC ON GREEN
SYNC ON GREEN
OSD MUX A
OSD MUX A OSD MUX A
OSD MUX B
OSD MUX B OSD MUX B
OSD MUX C
OSD MUX C OSD MUX C
OSD MUX D
OSD MUX D OSD MUX D
OSD MUX E
OSD MUX E OSD MUX E
RGB MUTE
Zone2 OSD CLK
Zone2 OSD CLK
VIDEO SERIAL DATA
VIDEO SERIAL DATA
VIDEO SERIAL CLK
VIDEO SERIAL CLK SVIDEO Y
VIDEO SVID LATCH
VIDEO SVID LATCH
PAL NTSC
PAL NTSC
OSD VIDEO IN PRESENT ZONE2 PAL NTSC
OSD VIDEO IN PRESENT ZONE2 PAL NTSC
VSYNC
FAST BLANKING
VIDEO SERIAL DATA
Comp Video 2V VIDEO SERIAL DATA
VIDEO SERIAL CLK
OSD CVBS VIDEO SERIAL CLK
VIDEO OSD CS
OSD Y VIDEO OSD CS
SVIDEO Y
SVIDEO Y OSD C
SVIDEO C
SVIDEO C
SVIDEO MUTE
SVIDEO MUTE
SK0
SCART CTRL 0 VID SPDIF RXTX
SK1
SCART CTRL 1 VID SPDIF RXTX.Sch
SK2
SCART CTRL 2
SK3
SCART CTRL 3
SK4
SCART CTRL 4
SK5
SCART CTRL 5
SK6 VIDEO SVID LATCH
SCART CTRL 6
VIDEO ZONE2 CS
OSD C
PAL NTSC
ZONE2 PAL NTSC
VID Svideo CVBS OSD insert
VID Svideo CVBS OSD insert.Sch
VIDEO SERIAL DATA VIDEO SERIAL DATA
OSD C VIDEO SERIAL CLK VIDEO SERIAL CLK
OSD Y SPDIF LATCH
OSD Y SPDIF LATCH SPDIF LATCH
OSD CVBS
OSD CVBS VIDEO SVID LATCH
Comp Video 2V
Comp Video 2V VIDEO ZONE2 CS
FAST BLANKING VIDEO OSD CS
FAST BLANKING VIDEO OSD CS
VSYNC
VSYNC
OSD VIDEO IN PRESENT
BLACK CLAMP
SVIDEO Y CLAMP_ON
SVIDEO Y CLAMP_ON
SVIDEO C ZONE2 ENABLE
SVIDEO C ZONE2 ENABLE
SVIDEO MUTE SPDIF ADC TX
SVIDEO MUTE SPDIF ADC TX SPDIF ADC TX
SPDIF_RXN
SPDIF_RXN SPDIF_RXN
SPDIF_GND SPDIF_GND
SPDIF_GND SPDIF_GND
VID Zone2 OSD TRIGGER
TRIGGER
VID Zone2 OSD.sch MAIN ZONE ENABLE
MAIN ZONE ENABLE
Zone2 OSD CLK TRIGGER ZONE2
Zone2 OSD CLK COMP SYNC TRIGGER ZONE2
VIDEO SERIAL DATA
VIDEO SERIAL DATA
VIDEO SERIAL CLK
VIDEO SERIAL CLK
VIDEO ZONE2 CS
VIDEO ZONE2 CS TRIGGER ZONE2 VID RC5 & TRIGGER
MAIN ZONE ENABLE VID RC5 & TRIGGER.sch
TRIGGER
ZONE2 ENABLE
Zone2 video OSD 2V RXDATA
Zone2 video OSD 2V Zone2 video OSD 2V RXDATA RXDATA
Zone2 video 2V TXDATA
Zone2 video 2V Zone2 video 2V TXDATA TXDATA
SIGGND
SIGGND SIGGND
DEMOD1
DEMOD1 DEMOD1
VSYNC ZONE2 DEMOD2
VSYNC ZONE2 VSYNC ZONE2 DEMOD2 DEMOD2
ZONE2 VIDEO IN PRESENT
ZONE2 VIDEO IN PRESENT ZONE2 VIDEO IN PRESENT
PROGRAM
PROGRAM PROGRAM
SK0
SCART CTRL 0
SK1
SCART CTRL 1
SK2
SCART CTRL 2
SK3
SCART CTRL 3
SK4
SCART CTRL 4
SK5
SCART CTRL 5
SK6
SCART CTRL 6
VID PSU
VID CVBS mux
VID PSU.SCH
VID CVBS mux.Sch
AV8 Video Board TOP 02_E112 AJD 6/06/02 Updated R431 and 430 to improve the IR reciever reliability.
Filename: VID TOP.Sch 02_E103 MJT 15/05/02 None to this sheet 3.0
23425 Notes: 02_E053 MJT 26/02/02 FINAL RELEASE MODS ADDED BEFORE PRODUCTION 2.0
Waterbeach
C254 NF C214
SK204
10N 0805 IC202 10N 0805
C259 NF PHONO1G
R213 EMC
16 1 VCR VIDEO
C273
IN1 VCR CVBS MUX Mon Out
+
150R 0805 R222 R205 TP203
Comp Video OSD 2V A CHASSISA
+
2U2 EL 12 14 C203
IN2 Vout1 P5VVA 39R 0805 1% 36R 0805 1%
Q203 470U EL 25V 1N 0805
C211 7 10 C227
IN3 Vout2 BC849B
SK200
PHONO1G 5 R215 Q200 10P SM 0805 TP204
IN4 MUTE 1 R208 BC849B
EMC 10N 0805 15
C239 CTL A 1K0 0805 1%
3 11 220R 0805 1%
TP200 IN5 CTL B VGNDA
CHASSISA 9
CTL C Q205
8
+
C200 CTL D R219 BC849B
VCR R200 2U2 EL 6
1N 0805 C215 C240 CTL E
75R 0805 2 220R 0805 1% VGNDA
GND
P5VVA
TP201
4 13 CVBS O/P x2
+
GND Vcc
10P SM 0805 2U2 EL
VGNDA C212 + C265 VGNDA
BA7625 C264 100U EL C216
100N 0805
10N 0805 VGNDA SK205
C255 10N 0805 PHONO1G
VGNDA VGNDA EMC
C274
R223 R206 TP205
10N 0805 CHASSISA
+
C260 IC200 C204
39R 0805 1% 36R 0805 1%
R214 P5VVA 470U EL 25V 1N 0805
16 1 MAIN VIDEO
C228
IN1 Main CVBS MUX Mon Out Q204
+
2U2 EL 150R 0805 BC849B Q201
12 14 R210 BC849B 10P SM 0805 TP209
IN2 Vout1
SK202 C213 R217
MUTE 2 220R 0805 1%
PHONO1G 7 10
IN3 Vout2 1K0 0805 1% VGNDA
EMC 10N 0805 Q206
C241 5 R220
TP202 IN4 BC849B
CHASSISA 15
CTL A 220R 0805 1% VGNDA
3 11
+
C201 IN5 CTL B

R201 2U2 EL 9
TAPE 1N 0805 C225 C245 CTL C
75R 0805 8
CTL D
6
TP206 CTL E VGNDA
2
+
GND C221
10P SM 0805 2U2 EL P5VVA
ZONE 2 O/P SK208
VGNDA C217 4 13
GND Vcc PHONO1G
10N 0805 EMC
+ C277 C275
10N 0805 BA7625 C269 100U EL R224 R212 TP210
Zone2 video OSD 2V A CHASSISA
+
C256 100N 0805
39R 0805 1% 36R 0805 1% C207
470U EL 25V 1N 0805
P5VVA C281
10N 0805 VGNDA VGNDA VGNDA
C261 Q207 47P NPO 0805
Q202 TP211
BC849B
R211 BC849B
+
ZONE2 MUTE R218 VGNDA

C218 220R 0805 1%
SK203 2U2 EL 1K0 0805 1%
Q208
PHONO1G R221 BC849B
EMC 10N 0805
C242 220R 0805 1% VGNDA
TP207
CHASSISA
+
C202 R203 2U2 EL

AV 1N 0805 C226 C246 VGNDA
75R 0805 IC201
TP208 R216
16 1 ZONE2 VIDEO
+
IN1 Zone 2 CVBS MUX Mon Out

10P SM 0805 2U2 EL 150R 0805
VGNDA C219 12 14
IN2 Vout1
7 10
IN3 Vout2
10N 0805
C257 5
IN4
15
CTL A
3 11
IN5 CTL B
10N 0805 9
C262 CTL C
8
CTL D
6
CTL E
2
+
GND
2U2 EL P5VVA
4 13
C220 GND Vcc
SK206 C250
+ C278
PHONO1G C270
BA7625 100U EL
EMC 10N 0805 100N 0805
C243 10N 0805
TP214
CHASSISA C252
+
VGNDA VGNDA VGNDA R204 Comp Video 2V A
+
C205 R207 2U2 EL
SAT 1N 0805 C229 C247 75R 0805
75R 0805
470U EL 25V
TP215
+
10P SM 0805 2U2 EL C251

VGNDA C223
10N 0805
10N 0805 C253
C258
Zone2 video 2V A
+
10N 0805 470U EL 25V
C263 P5VVA
IC203
IC204 P5VVA
C222
+
8 16
2U2 EL GND VCC 1 8 SK201
GND OUT1
C224 VCR O/P PHONO1G
13
SK207 OE C272 2 7 10N 0805 EMC
VIDEO SERIAL DATA A 14 IN1 OUT2 C209
PHONO1G DS 100N 0805
VIDEO SERIAL CLK A 11 R202 TP212
EMC 10N 0805 SHcp(DATA) 3 6 CHASSISA
+
C244 10 IN2 OUT3 C208
MR 75R 0805
TP216 VIDEO COMP LATCH A 12 1N 0805
CHASSISA STcp(LATCH) 4 5 470U EL 25V
VGNDA IN3 Vcc C210
+
C206 15 47P NPO 0805

R209 2U2 EL Q0
DVD 1N 0805 C230 C248 1 P5VVA TP213
75R 0805 VGNDA Q1 BA7623F
2
Q2
TP217 3
Q3 VGNDA
+
4 + C279
10P SM 0805 2U2 EL Q4 C271
5 100U EL
VGNDA C238 Q5 100N 0805
6
Q6
7
Q7
10N 0805 SK209 VGNDA
TP218 9
VIDEO SERIAL DATA A 1 Q7OUT
2
TP219 74HCT595D
VIDEO COMP LATCH A 3
VGNDA VGNDA
4
TP220
VIDEO SERIAL CLK A 5
6
TP221
Zone2 video OSD 2V A 7
P5VVA
8
TP222
Zone2 video 2V A 9
IC205 P5VVA SC1
10
TP224 8 16 E870MC
Comp Video OSD 2V A 11 GND VCC
E870MC
12
P5VVA TP225 13
Comp Video 2V A 13 OE C249
14
1
2
3
4
5
6
7
8
9
14 DS 100N 0805
TP226 11
15 SHcp(DATA)
10
16 MR
12
17 STcp(LATCH)
VGNDA CHASSISA
+ C280 18
C282 C237 C235 C233 C231 15
100U EL 19 Q0
100N 0805 TP223 1 MUTE 1
20 VGNDA Q1
2 MUTE 2
21 Q2
C236 C234 C232 3 ZONE2 MUTE
VGNDA 22 Q3
4 DRAWING TITLE 02_E163 WAF 8/08/02 IC701 CHANGED FROM 74LV244D TO 74HCT244D 3.2
10P SM 0805 VGNDA Q4
FFC22V1MM Q5
5
6
AV8 CVBS mux 02_E112 AJD 6/06/02 Updated R431 and 430 to improve the IR reciever reliability. 3.1
Q6
7
Q7
Filename: VID CVBS mux.Sch 02_E103 MJT 15/05/02 None to this sheet 3.0
10P SM 0805 10P SM 0805
10P SM 0805
10P SM 0805
10P SM 0805 VGNDA
10P SM 0805
Q7OUT
9
74HCT595D
Waterbeach
P5VV
P5VV
R343
4K7 0805
P5VV
L304
70R@100MHz
Q304
BFS17H
C327 C329 D300

100N 0805 100N 0805
Q302
VGND VGND BFS17H C332
100N 0805
P5VV
L305
70R@100MHz BAV99W DUAL SM
P5VV
VGND
C347
C328 C330 OSD Y
+
C346 100N 0805 100N 0805 OSD Y
R341
C362 100R 0805 10N 0805 10U EL
Comp Video 2V C348
Comp Video 2V
VGND ON SCREEN DISPLAY (OSD) OSD CVBS
+
+
OSD CVBS
2U2 EL OSD / SYNC SEP SEL VGND
1U0 EL
C363 IC301 IC302
Y/G 2V Q300 C366 1 28 C331
Y/G 2V R301 YOUT YIN
16 1 BC859B 2 27 OSD C
+
IN1 Mon Out VIDEOIN VIDEOOUT1 OSD C
2U2 EL 3 26
+
75R 0805 RES VIDEOOUT2
12 14 2U2 EL 4 25 100N 0805 P5VV
C364 IN2 Vout1 FTR CIN
R307 5 24
AVDD COUT
SVIDEO Y 7 10 75R 0805 6 23
SVIDEO Y IN3 Vout2 DVDD LESCREEN
VGND 7 22
+
CSYNC LECHAR Q301

2U2 EL 5 R321 R349 8 21 R354 R355
IN4 XTALIN AGND
15 NF 9 20 2k7 0805 2k7 0805 BLACK CLAMP R346 R347 R348
2M2 0805
30K 0805
C365 CTL A XTALOUT DGND
3 11 VGND 10 19 47K 0805 47K 0805 10K 0805
IN5 CTL B MUTE BAR
OSD CVBS 9 R344 11 18
CTL C DATA CO
8 12 17
+
5K6 0805
680P NPO 0805
CTL D C350 CLK FB
2U2 EL 6 13 16
CTL E 220P NPO 0805 CSN B
2 14 15 R357 VGND VGND VGND VGND
15N PE 5%
GND C307 R G
R336 P5VV 1K0 0805 DTRANN SM
100R 0805 4 13 NF C349 STV5730A
GND Vcc
100N 0805
R350 R345 R356
C335
+ C344 33R 0805 4K7 0805 1K0 0805
BA7625 C334 100U EL VGND VGND
100N 0805 R358
680R 0805 C336
VGND 100N 0805
VGND VGND VGND
VGND
OSD VIDEO IN PRESENT VGND VGND VGND

VIDEO SERIAL DATA
VIDEO SERIAL DATA
OSD MUX A VIDEO SERIAL CLK
OSD MUX A VIDEO SERIAL CLK
OSD MUX B VIDEO OSD CS
OSD MUX B VIDEO OSD CS
OSD MUX C R313 RGB OSD VIDEO
OSD MUX C
OSD MUX D R312 8K2 0805 IC300B
OSD MUX D
OSD MUX E 6K8 0805 5
OSD MUX E R338
R311 7 OSD R
R303 OSD R
8K2 0805 6 75R 0805
0R0 0805 IC502C EL5244 SM
OSD_SYNC 9 R317 R339 OSD G
OSD G
8 15K 0805 75R 0805
R309 10
680R 0805 C308 R340 OSD B
74HC08 SM IC300A OSD B
NF 680P NPO 0805 3 75R 0805
R300 NF 1
PAL CLOCK
680K 0805 1% 2
IC305A EL5244 SM
SYNC ON GREEN
VGND
IC306C IC306B 74HCT125 SM
C355
5 6 R361 R304 3 4 R302 2 3 R365 R366 R367
TP301
NF NF NF
3K3 0805
3K3 0805
3K3 0805
33R 0805 4K7 0805 330R 0805 IC303A
10N 0805 C333 C338 C339 3
1
74HCU04 SM 74HCU04 SM
1
SYNC ON GREEN
Improve return path for these clock signals. 2
IC305B EL5244 SM
74HCT125 SM
C303 220P NPO 0805 220P NPO 0805 220P NPO 0805
R359 5 6 R316 VGND
4M7 0805 3K3 0805 1%
4
IC306F 100P NPO 0805 R319

X300
C405 330R 0805
13 12
33P NPO 0805
17.73447MHZ#A NF
74HCU04 SM C305
VGND 47P NPO 0805
C351 C352 IC305C
27P NPO 0805 27P NPO 0805 74HCT125 SM
VGND
9 8
VGND VGND
10
R306
680K 0805 1% CHAR OUT
CHAR OUT
FAST BLANKING
FAST BLANKING
NTSC CLOCK OSD B TTL
IC305D OSD B TTL
OSD G TTL
IC307C IC307B Improve return path for these clock signals. 74HCT125 SM OSD G TTL
C340 C301 R315
5 6 R362 R305 3 4 R308 12 11 R318 Zone2 OSD CLK 0R0 0805
TP300 Zone2 OSD CLK
33R 0805 4K7 0805 330R 0805 3K3 0805 1% NF
10N 0805
13
74HCU04 SM 74HCU04 SM 100P NPO 0805

IC307F C404 COMP SYNC
33P NPO 0805 COMP SYNC To Microcontroller
13 12 VSYNC
VSYNC
NF P5VV
R360 74HCU04 SM
VGND P5VV
R314 C302
4M7 0805 R364 R310
PAL NTSC R363 0R0 0805
33R 0805 100N 0805 1K0 0805
33R 0805 NF
X301
16
ZONE2 PAL NTSC
IC308 VGND
C342 1
VCC
100N 0805 1A
14.31818MHZ#A IC304 15
1RCEXT C304
2
1B 1N NPO 0805
1 8 14
C353 C354 CS OP Vcc 1CEXT
VGND 3 1
22P NPO 0805 22P NPO 0805 100N 0805 C341 1RD R320
2 7 13 BLACK CLAMP
C VID IP OE OP 1Q BLACK CLAMP
4 330R 0805
1Q C306
VGND VGND 3 6 74HC123D
VS OP Rset 100P NPO 0805
MONOSTABLE 12
2Q
4 5 5
GND BURST OP 2Q
11 VGND
2RD
6 2
R368 C343 2CEXT
EL4581CS 10
680K 0805 1% 100N 0805 2B
P5VV P5VV P5VV 7
2RCEXT
GND
100N 0805 100N 0805 100N 0805 9
L300 L301 L302 2A
C357 C359 C361 SYNC SEPERATOR
IC306A IC307A
74HC123D SM
8
IC303B 1 2 1 2
5 P5VV C356 C358 C360
7 100N 0805 100N 0805 100N 0805 VGND VGND
VGND 6 VGND
IC306D IC307D
8
EL5244 SM IC300C IC303C

14
14
VGND VGND VGND 9 8 9 8

VS
VS
+ C345
14
GND
GND
100U EL C337 C300

100N 0805 100N 0805
74HCU04 SM 74HCU04 SM DRAWING TITLE 02_E163 WAF 8/08/02 IC701 CHANGED FROM 74LV244D TO 74HCT244D 3.2
EL5244 SM EL5244 SM IC305E
AV8 On Screen Display
4
IC306E IC307E
74HCT125 SM
7
IC307G IC306G 02_E112 AJD 6/06/02 Updated R431 and 430 to improve the IR reciever reliability. 3.1
11 10 11 10
7
VGND R302,R308 now 330R (was 3k3). C348 now 1u (was 10u). C404,C405 now NF.
Filename: VID On Screen Display.Sch 02_E103 MJT 15/05/02 3.0
23425
C305 now 47p (was 10p). R310 now 1k (was 330R). C304 now 1N (was 100p).
VGND VGND
Notes: 02_E053 MJT 26/02/02 FINAL RELEASE MODS ADDED BEFORE PRODUCTION 2.0
VGND
VGND VGND
Waterbeach
P5VV P5VV
R708
SYNC TIP CLAMP 4K7 0805
D702
Q705 C728
Q700
DTRANN SM BFS17H
BLACK CLAMP
BLACK CLAMP C732
Q701 100N 0805 10N 0805
S-Video Out
BFS17H C730
R713 R705 TP700 SVHS1V-TCS
+
BAV99W DUAL SM 39R 0805 1% 36R 0805 1%
VGND
470U EL 25V
C736 C712 VGND C701
A1
SK701
10P SM 0805
A5
+
A3 Y
10U EL 100N 0805 IC700
C729 A4 NA6
OSD Y 3
OSD Y C719 A1 C
1 TP701 CHASSIS
OUT1
SVIDEO Y 4
A2
SVIDEO Y B1 10N 0805
+
OSD C 10U EL 6 C731 C700
OSD C A2 R714 R706 1N 0805
C714 8
+
OUT2
SVIDEO C 5 39R 0805 1% 36R 0805 1% TP702
SVIDEO C B2
470U EL 25V
OSD CVBS 100N 0805 12 C702
OSD CVBS C720 A3 10P SM 0805
9
OUT3
Comp Video 2V 11 Q706
B3
+
1U0 EL 16 P5VV R716 VGND
A/B 100N 0805
14
VCC
R702 R703 R704 15 C715 + C733 220R 0805 1%
VCC BC849B
150R 0805 160R 0805 330R 0805 C713 10U EL
7
GND Q702
10 C716 + C734 VGND
GND
100N 0805 2 13 10U EL R700
47K 0805
10K 0805
47K 0805
GND VEE P5VV
VGND Q704 220R 0805 1%
R711
R709
R712
VGND VGND VGND EL4332CS 100N 0805 BC849B
N5VV Q707 BC849B
R717 BC849B
FAST BLANKING A = H = OSD B = L = DIRECT VGND
FAST BLANKING VGND
VGND VGND VGND 220R 0805 1%
VGND
Q703
Ensure orientation is sensible R701 BC849B
R715
1K0 0805 1%
SK700 220R 0805 1%
22 TP703 VIDEO SERIAL DATA
21
20 TP704 VIDEO COMP LATCH R710
VGND
19 0R0 0805
18 TP705 VIDEO SERIAL CLK
17
16 TP706 Zone2 video OSD 2V
Zone2 video OSD 2V
15
14 TP707 Zone2 video 2V
Zone2 video 2V
13
12 TP708 Comp Video OSD 2V Comp Video OSD 2V
11
10 TP709 Comp Video 2V
Comp Video 2V
9 P5VV
8 TP726 SVIDEO MUTE
SVIDEO MUTE
7
6 + C718
5 TP710 C703 C707 C709 100U EL
C705
4 C711
3 10P SM 0805
C704 C706 C708 C710
2 VGND
10P SM 0805
10P SM 0805
10P SM 0805
10P SM 0805
10P SM 0805
10P SM 0805
10P SM 0805
10P SM 0805
1 VGND
FFC22V1MM
CHASSIS
P5V
C717
IC701 100N 0805
10 20
GND VCC
1
1OE
EMC CAPACITORS TO CHASSIS 19 DGND
2OE
SK702
C727A 100PX4 SM 30 TP711 DGND 2 18 VIDEO SERIAL DATA
1A0 1Y0 VIDEO SERIAL DATA
C727B 100PX4 SM 29 4 16 VIDEO SERIAL CLK
1A1 1Y1 VIDEO SERIAL CLK
C727C 100PX4 SM 28 TP712 6 14 VIDEO COMP LATCH
1A2 1Y2
C727D 100PX4 SM 27 8 12 VIDEO SVID LATCH
1A3 1Y3 VIDEO SVID LATCH
C726A 100PX4 SM 26 TP713 17 3 SPDIF LATCH
2A0 2Y0 SPDIF LATCH
C726B 100PX4 SM 25 TP714 15 5 VIDEO ZONE2 CS
2A1 2Y1 VIDEO ZONE2 CS
C726C 100PX4 SM 24 TP715 13 7 VIDEO OSD CS
2A2 2Y2 VIDEO OSD CS
C726D 100PX4 SM 23 TP716 11 9
2A3 2Y3
C725A 100PX4 SM 22 TP717
C725B 100PX4 SM 21 TP718 ZONE2 VIDEO IN PRESENT 74HCT244D
C725C 100PX4 SM 20 TP719 OSD VIDEO IN PRESENT
C725D 100PX4 SM 19 TP720 PROGRAM
PROGRAM
C724A 100PX4 SM 18 TP721 VSYNC DGND
VSYNC
C724B 100PX4 SM 17
C724C 100PX4 SM 16 TP722 VSYNC ZONE2
VSYNC ZONE2
C724D 100PX4 SM 15
C723A 100PX4 SM 14 TP723 COMP SYNC
COMP SYNC
C723B 100PX4 SM 13 SPDIF_GND
SPDIF_GND
C723C 100PX4 SM 12 TP725 SPDIF_RXN
SPDIF_RXN
C723D 100PX4 SM 11
C722A 100PX4 SM 10 TP727 RXDATA
RXDATA
C722B 100PX4 SM 9 TP728
SIGGND
C722C 100PX4 SM 8 TP729 TXDATA
TXDATA
C722D 100PX4 SM 7
C721A 100PX4 SM 6 TP730 DEMOD1
DEMOD1
C721B 100PX4 SM 5
C721C 100PX4 SM 4 TP731 DEMOD2
DEMOD2
3
C721D 100PX4 SM 2 TP732 SPDIF ADC TX
SPDIF ADC TX
1
CHASSISB R707
FFC30V SM
22R 0805
C735
DGND VGND
100N 0805 DRAWING TITLE 02_E163 WAF 8/08/02 IC701 CHANGED FROM 74LV244D TO 74HCT244D 3.2
AV8 Svideo CVBS OSD Insert 02_E112 AJD 6/06/02 Updated R431 and 430 to improve the IR reciever reliability. 3.1
Filename: VID Svideo CVBS OSD insert.Sch 02_E103 MJT 15/05/02 R702 now 150R (was 75R). R703 now 160R (was 75R). 3.0
Waterbeach
P5VV P5VV P5VV
R906
4K7 0805
Q902
BFS17H
Q900 Q903
BFS17H 100N 0805
D902
Q901 BFS17H
BFS17H
C911
BAV99W DUAL SM
VGND
C913 IC902
3 Long track
+
C912 A1
1
OUT1 Zone2 video OSD 2V
1U0 EL 4
B1
+
1U0 EL 6
A2
R909 8
R901 OUT2
47K 0805 5
47K 0805 B2
P5VV
L900 12
A3
70R@100MHz 9
OUT3
11
VGND B3
VGND P5VV
R910 L = DIRECT = 0 H = OSD = 1 16
C902 C904 A/B
330R 0805 14
100N 0805 100N 0805 C915 VCC
15 + C919
100P NPO 0805 VCC C901 10U EL
Long track
VGND VGND 7 100N 0805

GND
VGND 10
GND
P5VV 2 13
GND VEE
L901
70R@100MHz VGND EL4332CS
VGND VGND
C903 C905
100N 0805 100N 0805
ON SCREEN DISPLAY (OSD)

VGND + C918
P5VV C917 10U EL VGND
IC900 100N 0805
C900 1 28
R902 YOUT YIN
Zone2 video 2V 2 27 N5VV
Zone2 video 2V VIDEOIN VIDEOOUT1
3 26 R916 R917
+
39R 0805 RES VIDEOOUT2

2U2 EL 4 25 2K7 0805 2K7 0805
FTR CIN
R903 5 24
AVDD COUT
43R 0805 6 23
DVDD LESCREEN
7 22
CSYNC LECHAR
R907 R911 R912 8 21
C920 XTALIN AGND
9 20 R919
2M2 0805
5K6 0805
30K 0805
XTALOUT DGND
VGND NF 10 19 C907 1K0 0805
MUTE BAR
680P NPO 0805
NF 11 18
DATA CO 100N 0805
12 17 R918
C916 CLK FB
13 16 1K0 0805
220P NPO 0805 CSN B
14 15
15N PE 5%
R G
R920
C914 STV5730A 680R 0805 C908
R908 100N 0805
4K7 0805
VGND VGND
Zone2 OSD CLK VGND VGND

Zone2 OSD CLK
VGND VGND VGND

VIDEO SERIAL DATA
VIDEO SERIAL DATA
VIDEO SERIAL CLK
VIDEO SERIAL CLK
VIDEO ZONE2 CS
VIDEO ZONE2 CS VSYNC ZONE2
VSYNC ZONE2
R905
0R0 0805
P5VV NF
R914 R915
33R 0805 33R 0805
NF
C906
IC901 100N 0805
1 8
CS OP Vcc
C909 VGND
100N 0805 2 7
C VID IP OE OP
3 6
VS OP Rset
4 5
GND BURST OP
R904
EL4581CS 680K 0805 1% C910
100N 0805
SYNC SEPERATOR
VGND VGND
AV8 Zone2 OSD 02_E112 AJD 6/06/02 Updated R431 and 430 to improve the IR reciever reliability. 3.1
R902 now 39R (was 75R). R903 now 43R (was 75R).
Filename: VID Zone2 OSD.sch 02_E103 MJT 15/05/02 3.0
23425
C912, C913 now 1u (was 10u).
Waterbeach
P3V3
TP1000
6U8H RADIAL
L1003
SK1000 P12V
1 TP1007
P12V
2
DGND
3 + C1002
N12V
4 TP1008 DGND 470U EL 25V
DGND TP1006
5 L1000 P5VV 6U8H RADIAL
P5V TP1002 TP1009
6 DGND + C1001
DGND L1002
7 6U8H RADIAL 100N 0805 470U EL 25V DGND
P3V3
8 + C1007
DGND
C1010 1M0 10V
N12V
AMPCT8 TP1001
C1005A C1005B C1005C C1005D C1006A C1006B C1006C C1006D TP1004 VGND
1000PX4 SM 1000PX4 SM 1000PX4 SM 1000PX4 SM 1000PX4 SM 1000PX4 SM 1000PX4 SM 1000PX4 SM L1001 P5V
TP1003
6U8H RADIAL
100N 0805 + C1008
C1011 1M0 10V
CHASSIS
DGND TP1005 DGND
C1012
100N 0805
C1013
100N 0805
C1014
100N 0805
VGND DGND
DGND
+ C1004
R1001 10U EL
1K2 0805 1%
+ C1009
10U EL C1000 HS1000 D1001 R1000 + C1003
1N4003
A
100N 0805 390R 0805 470U EL 25V

ADJ
R1002 TP1010
I O
Vin Vout
5R6 2W CF
N12V
IC1000 TO220HS23REG
LM337T
N5VV
D1000 1N4003
AV8 Power Supply 02_E112 AJD 6/06/02 Updated R431 and 430 to improve the IR reciever reliability. 3.1
Filename: VID PSU.Sch 02_E103 MJT 15/05/02 None to this sheet 3.0
Waterbeach
P5VV
SC2
E869MC
VGND R519 R520 INSERT BLACK LEVEL ON UV or E869MC
47R 0805 C515 4K7 0805 BACKGROUND COLOUR (BLUE) FOR CHARACTERS ON UV
100N 0805
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
IC501A
12
1Y0
14
1Z CHASSIS
13
1Y1
SELECT RGB OR YUV
2
2Y0
15 IC500A
2Z
1 OSD R 12
2Y1 OSD R 1Y0
14 R/V
1Z
5 13
3Y0 1Y1
4
3Z
3 OSD G 2
3Y1 OSD G 2Y0
15 G/Y
2Z
IC502A 11 OSD Y 1
1S OSD Y 2Y1
OSD B TTL 1 IC502B 10 6
OSD B TTL 2S INH
3 4 9 OSD B 5
R500 IC504A 3S OSD B 3Y0
2 6 4 B/U
4K7 0805 C513 3Z
1 2 5 74LV4053 SM 3
100N 0805 R522 OSD G TTL 74HC08 SM 3Y1
VGND
330R 0805 74HC08 SM VGND 11
74HCU04 SM IC504B 1S
10 6
2S INH
VGND CHAR OUT 3 4 OSD RGB/YUV SEL 9
CHAR OUT OSD RGB/YUV SEL 3S
N5VV
0=RGB 1=YUV 74LV4053 SM
74HCU04 SM
VGND
R502 R501 R503
75R 0805 75R 0805 75R 0805
VGND VGND VGND

R508 Y/G 2V
SK501C Y/G 2V
TP503 75R 0805
4 R/V 1
PHONO4SPLIT
TL 6
TP501
SK500A
C571 10N 0805
TP504
1 R/V 2 R/V
TP507
EMC TR 3 10N 0805 C570
C542 C505
R507 R509 5 SK501D
+
CHASSIS TP502 C572
C522 C504 R504 R505 10U EL 39R 0805 1% 36R 0805 1%
C503 IC503 470U EL 25V BL (GND pin 6)
+
10P SM 0805 3 IC505 10P SM 0805 PHONO4SPLIT
A1 C546 10N 0805
10N 0805 10P SM 0805 75R 0805 75R 0805 1 3
OUT1 A1 VGND
4 1
B1 OUT1
4
B1
VGND 6
+
A2 C573 10U EL
8 6
OUT2 A2
5 8
B2 OUT2
5 C574
B2 10U EL
12
A3
9 12 IC506 EL4332CS
+
OUT3 A3
11 9 3
SK502C B3 OUT3 A1 C569 10N 0805
11 1
TP505 B3 C543 10N 0805 OUT1
4 G/Y1 16 4
A/B B1
P5VV R535 R536 R537 16 R538 R539 R540 G/Y
A/B C568 TP509
TL 6 14 15 220R 0805 220R 0805 220R 0805 P5VV 220R 0805 220R 0805 220R 0805 6 C506 SK502D
TP500 PD VCC A2 R515 R510
14 15 8 5
+
PD VCC OUT2
7 5 39R 0805 1% 36R 0805 1%
SK501A GND B2
10 7 470U EL 25V BL (GND pin 6)
TP506 GND GND
1 G/Y2 2 13 VGND 10 VGND 12 10P SM 0805 PHONO4SPLIT
GND VEE GND BLACK LEVEL CLAMP A3
2 13 9
GND VEE FOR Y/G, U/B AND V/R OUT3
EMC TR 3 EL4331CS 11 VGND
B3
EL4331CS
CHASSIS TP513 VGND FAST BLANKING 16
C508 C510 A/B
R512 R514 VGND Q511 14
C527 VCC
P5VV P5VV DTRANN SM 15
10N 0805 VCC
10P SM 0805 10P SM 0805 Q500 Q512
75R 0805 75R 0805 + C537 + C557 R529 R506 R530 7
C554 C541 DTRANN SM DTRANN SM GND
47U EL 35V 47U EL 35V 47K 0805 47K 0805 47K 0805 10
100N 0805 100N 0805 GND
2 13
GND VEE C567 10N 0805
VGND + C531 + C532
VGND 47U EL 35V C524 VGND 47U EL 35V C525 P5VV
100N 0805 100N 0805 TP516 B/U
C566 SK502B
VGND VGND R516 R517 C511
2
+
N5VV N5VV + C563
47U EL 35V C556 39R 0805 1% 36R 0805 1%
SK502A 100N 0805 470U EL 25V BR (GND pin 3)
TP514
1 B/U 1 10P SM 0805 PHONO4SPLIT
+ C564 VGND Q502
TP511 FAST BLANKING 47U EL 35V C561 BC849B VGND
EMC TR 3
100N 0805
CHASSIS R521
SK500C
N5VV 220R 0805 1%
TP515
4 B/U 2
TL 6
VGND Q503
TP512 BC849B
C507 C509 R511 R513
C526 R527
10N 0805 220R 0805 1%
P5VV Q506
10P SM 0805 10P SM 0805 75R 0805 75R 0805 BC849B
VGND Q501 R523 VGND

IC502D R518
BLACK CLAMP 12 RGB MUTE BC849B 220R 0805 1%
BLACK CLAMP RGB MUTE
11 R525 1K0 0805 1%
RGB/YUV INPUT SEL 13 330R 0805 Q504
RGB/YUV INPUT SEL C501 BC849B
RGB/YUV INPUT SEL 1
74HC08 SM 100P NPO 0805 VGND
RGB/YUV INPUT SEL 1 R528
CLAMP_ON
CLAMP_ON
VGND 220R 0805 1%
Q507
BC849B
P5VV P5VV
TP520 R524
SK500B 2 R/V 3 VGND
PHONO4SPLIT 220R 0805 1%
BR (GND pin 3)
16
16
IC501B
Q505
VDD
VDD
R531 7 IC500B 7 R534 VGND BC849B

VEE VEE
GND
GND
C538 75R 0805 C517 C519 220R 0805 1%

10P SM 0805 100N 0805 100N 0805
8
74LV4053 SM
74LV4053 SM VGND
VGND C518 VGND C520 VGND
100N 0805 100N 0805
TP521
SK501B 2 G/Y3 VGND VGND
PHONO4SPLIT BR (GND pin 3)

N5VV N5VV
TP522 P5VV P5VV

SK500D 5 B/U 3
PHONO4SPLIT BL (GND pin 6)

14
14
IC502E
IC504E IC504F IC504C IC504D DRAWING TITLE 02_E163 WAF 8/08/02 IC701 CHANGED FROM 74LV244D TO 74HCT244D 3.2
VCC
R532 R533
GND
C539 C540 75R 0805 75R 0805 11 10 13 12 5 6 9 8

C555
100N 0805
C516
100N 0805
AV8 RGB YUV Video Mux 02_E112 AJD 6/06/02 Updated R431 and 430 to improve the IR reciever reliability. 3.1
10P SM 0805 10P SM 0805
7
IC504G 74HC08 SM
74HCU04 SM 74HCU04 SM 74HCU04 SM 74HCU04 SM Filename: VID RGB YUV video mux.SCH 02_E103 MJT 15/05/02 None to this sheet 3.0
23425
74HCU04 SM
VGND IC502C is on sheet 4
VGND VGND
VGND
Waterbeach
C834
VCR S-Video Out

100N 0805
C848
R800 TP805
C845 NF
+
75R 0805
470U EL 25V
100N 0805 C828 C808
A1
C869 NF 10P SM 0805 SK802
A5
A3 Y
100N 0805 IC800 IC802
+
A1
SK800 C818 A4 NA6
2U2 EL C835
R803 C
A5 TP801 16 1 1 8 CHASSIS
Y A3 C820 IN1 S VID Y MUX Mon Out GND OUT1
+
150R 0805 SVHS1V-TCS
A2
A4
VCR A6 N TP802
2U2 EL 12 14 2 7 100N 0805
C IN2 Vout1 IN1 OUT2 C849 C802
CHASSIS
+
R801 TP806
2U2 EL 7 10 3 6 1N 0805
+
SVHS1V-TCS
A2
C800 IN3 Vout2 IN2 OUT3 TP807
R808 R810 C830 P5VV 75R 0805
1N 0805 75R 0805 1% C806 75R 0805 1% C807 5 4 5 470U EL 25V
10P SM 0805 IN4 IN3 Vcc C809
TP800 10P SM 0805 15
CTL A 10P SM 0805
100N 0805 3 11 + C851
IN5 CTL B C833
C858 NF 9 BA7623F 100U EL
CTL C 100N 0805
8 R812
CTL D
6 75R 0805 1% VGND
CTL E
VGND 100N 0805 2
C871 NF GND
P5VV
4 13
GND Vcc
+
2U2 EL + C850 VGND VGND VGND VGND
BA7625 C832 100U EL
100N 0805 C854
C846
IC803 100N 0805
VGND VGND VGND C856
100N 0805 C829 R806
1 8 SVIDEO Y
+
C870 GND OUT1 SVIDEO Y
IC806 150R 0805
2 7 470U EL 25V
100N 0805 IN1 OUT2
+
A1
SK801 C819 R802 C855

2U2 EL 16 1 R807
IN1 S VID VCR Y MUX Mon Out 3 6 SVIDEO C
A5 TP803 150R 0805 IN2 OUT3 SVIDEO C
Y A3 C821 P5VV 160R 0805
12 14
+
A4 IN2 Vout1 4 5 100N 0805
TAPE A6 N TP804
2U2 EL IN3 Vcc C857
C
CHASSIS 7 10
+
IN3 Vout2
+
+ C853
SVHS1V-TCS 2U2 EL
A2
BA7623F C844 100U EL

C801 R809 R811 C831 5
IN4 R819 100N 0805 470U EL 25V
1N 0805 75R 0805 1% C810 75R 0805 1% C813 15
10P SM 0805 CTL A 75R 0805 1%
10P SM 0805 3 11
TP808 IN5 CTL B
100N 0805 9
CTL C
C860 8
CTL D
6
CTL E
2
GND VGND VGND VGND VGND
VGND 100N 0805 P5VV
C873 4 13
GND Vcc
+
+ C879
2U2 EL BA7625 C862 100U EL
100N 0805
C859
VGND VGND VGND

100N 0805
C872 C836
IC801
P5VV
+
100N 0805 16 1 R805

A1
SK803 2U2 EL C822 IN1 S VID VCR C MUX Mon Out IC804 P5VV
150R 0805 8 16
A5 TP811 12 14 GND VCC
Y A3 C824 IN2 Vout1
+
A4 13
AV A6 N TP812
2U2 EL 7 10 OE C842
C IN3 Vout2 VIDEO SERIAL DATA 14
CHASSIS VIDEO SERIAL DATA DS
+
VIDEO SERIAL CLK 11 100N 0805

SVHS1V-TCS 2U2 EL 5 VIDEO SERIAL CLK SHcp(DATA)
A2
C803 IN4 10
R813 R815 C838 15 MR
1N 0805 C811 C814 CTL A VIDEO SVID LATCH 12
75R 0805 1% 75R 0805 1% 3 11 VIDEO SVID LATCH STcp(LATCH)
10P SM 0805 IN5 CTL B VGND
10P SM 0805 9
TP809 CTL C 15
100N 0805 8 Q0
CTL D 1
C861 6 Q1
CTL E 2
2 Q2
GND 3
P5VV Q3
4
VGND 100N 0805 4 13 Q4
C875 GND Vcc 5
Q5
6
+ C880 Q6 SCART CTRL 6
C866 VGND 7
BA7625 Q7 SCART CTRL 5
+
100U EL
2U2 EL 100N 0805
9
C863 Q7OUT
P5VV
74HCT595D
VGND VGND VGND
100N 0805 C837
C874 IC807
IC805 P5VV
R804 8 16
100N 0805 16 1 GND VCC
+
A1
SK804 C823 IN1 S VID C MUX Mon Out

2U2 EL 150R 0805 13
A5 TP813 12 14 OE C847
Y A3 C825 IN2 Vout1 14
DS
+
A4 11 100N 0805
SAT A6 N TP814
2U2 EL 7 10 SHcp(DATA)
C IN3 Vout2 10
CHASSIS MR
+
12
SVHS1V-TCS 2U2 EL 5 STcp(LATCH)
A2
C804 IN4 VGND

R814 R816 C839 15
1N 0805 C812 C815 CTL A 15
75R 0805 1% 75R 0805 1% 3 11 Q0 SCART CTRL 4
10P SM 0805 IN5 CTL B 1
10P SM 0805 9 Q1 SCART CTRL 3
TP810 CTL C 2
100N 0805 8 Q2 SCART CTRL 2
CTL D 3
6 Q3 SCART CTRL 1
C865 CTL E 4
2 Q4 SCART CTRL 0
GND 5 RGB/YUV INPUT SEL
P5VV Q5 RGB/YUV INPUT SEL
6 RGB/YUV INPUT SEL 1
VGND 4 13 Q6 RGB/YUV INPUT SEL 1
100N 0805 GND Vcc VGND 7 OSD RGB/YUV SEL
C876 Q7 OSD RGB/YUV SEL
+ C852
C843 9
BA7625 100U EL Q7OUT
+
100N 0805
2U2 EL 74HCT595D
P5VV
VGND VGND VGND
C864
IC808 P5VV
8 16
100N 0805 C840 GND VCC
C877
13
OE C868
14
100N 0805 DS
+
A1
SK805 11 100N 0805

2U2 EL C826 SHcp(DATA)
10
A5 TP816 MR
Y A3 12
STcp(LATCH)
+
A4 VGND
DVD A6 N TP817
2U2 EL C827
C 15 OSD MUX A
CHASSIS Q0 OSD MUX A
+
1 OSD MUX B
SVHS1V-TCS 2U2 EL Q1 OSD MUX B
A2
C805 2 OSD MUX C

R817 R818 C841 Q2 OSD MUX C
1N 0805 C816 C817 3 OSD MUX D
75R 0805 1% 75R 0805 1% Q3 OSD MUX D
10P SM 0805 4 OSD MUX E
TP815
10P SM 0805 Q4 OSD MUX E
5 SYNC ON GREEN
100N 0805 Q5 SYNC ON GREEN
6 RGB MUTE
C867 Q6 RGB MUTE
VGND 7 SVIDEO MUTE
Q7 SVIDEO MUTE
9
VGND 100N 0805 Q7OUT
C878
74HCT595D
+
2U2 EL
AV8 SVideo Mux 02_E112 AJD 6/06/02 Updated R431 and 430 to improve the IR reciever reliability. 3.1
Filename: VID SVideo mux.sch 02_E103 MJT 15/05/02 R806 now 150R (was 75R). R807 now 160R (was 75R). 3.0
Waterbeach
R618 R621 R622
47K 0805 680K 0805 1% 680K 0805 1%
IC603A IC603B IC603C IC603D
IC600A
C614 12 1 2 R619 3 4 R620 5 6 9 8 R624 SPDIF_RXN
R605 1Y0 SPDIF_RXN
14 3K3 0805 3K3 0805 100R 0805
1Z
560R 0805 1% 13
1Y1 74HCU04 SM 74HCU04 SM 74HCU04 SM 74HCU04 SM C629 SPDIF_GND
10N 0805
2 33P NPO 0805
2Y0
SK600A 15
PHONO4SPLIT TP601 2Z IC603E IC603F
1 1
2Y1 R625
11 10 13 12
TAPE
EMC TR 3 5 100R 0805 DGND
3Y0
4
TP600 3Z 74HCU04 SM 74HCU04 SM
CHASSIS 3
3Y1
C600 TP602
2 11 SPDIF SEL 7 P5V
CD 10N 0805 SK600B 1S 100N 0805
C615 6 10 SPDIF SEL 6
R606 INH 2S
BR (GND pin 3) 9 SPDIF SEL 5
PHONO4SPLIT 3S C605
560R 0805 1%
10N 0805 74LV4053 SM
R600 R601
14
C624 75R 0805 C625 DGND
75R 0805 100P NPO 0805 100P NPO 0805 IC603G
74HCU04 SM
IC601A
12 R623 SPDIF_GND
7
1Y0
DGND DGND DGND 14 0R0 0805
1Z
13 DGND
1Y1
2
2Y0
C616 15
R607 2Z
1
2Y1
560R 0805 1%
10N 0805 5
3Y0
4
3Z
3
TP605 3Y1
AV SK600C 4
11 SPDIF SEL 4
1S
PHONO4SPLIT TL 6 6 10 SPDIF SEL 3
INH 2S
TP604 9 SPDIF SEL 2
3S
PHONO4SPLIT
74LV4053 SM
5 TP609
TUNER SK600D
C618
BL (GND pin 6) R608
560R 0805 1%
10N 0805
C602 R603 R604 IC602A
10N 0805 C626 75R 0805 C627 12
100P NPO 0805 1Y0
14 P5V
100P NPO 0805 1Z
CHASSIS 75R 0805 13
1Y1
2 R611
2Y0
DGND DGND DGND 15 1K0 0805 1%
2Z
1
2Y1
5
3Y0
4
3Z
C617 3 R612
R609 3Y1 C619 + C632
1K0 0805 1%
SK601 11 SPDIF SEL 1 10N 0805 10U EL
TP606 560R 0805 1% 1S
10N 0805 6 10
DVD INH 2S
9
TP603 3S
T R602
PHONO2G IND GND 75R 0805 C628 74LV4053 SM
DGND 100P NPO 0805 DGND
B
TP607 IC605A
out DGND
74HCT125 SM
DGND C604
TP608 R626 3 2
1
680R 0805
R613
100N 0805
1
L601 100R 0805
C603
4
100P NPO 0805
L CM CHOKE SM SN102
DGND
C631 IC605B
L600
10N 0805 74HCT125 SM
C633 DGND
C634 R627 6 5
10N 0805 R610
100P NPO 0805 10K 0805 680R 0805
C630
4
CHASSIS CHASSIS CHASSIS
100N 0805
P5V SPDIF LOOP
DGND
R630
10R 0805
+ C622
C606 IC605C
74HCT125 SM
100N 0805 10U EL
R628 8 9
1
680R 0805
VCC DGND DGND C620
10
TP610 R614
3
VCR O/P
560R 0805 1% P5V
GND 10N 0805 100N 0805
IC607
2
GP1FA550RZ C608
IC605D
DGND
74HCT125 SM
R629 11 12 SPDIF ADC TX DGND
14
SPDIF ADC TX
P5V 680R 0805 IC605E
13
R631
10R 0805
7
74HCT125 SM
+ C623 P5V SPDIF ADC
C607 10U EL
100N 0805 IC606 P5V DGND
8 16
GND VCC
1
P5V
VCC DGND DGND C621 13
TP611 R617 OE C613
3 IC604 P5V 14
SAT O/P DS 100N 0805
560R 0805 1% 8 16 VIDEO SERIAL CLK 11
GND VCC VIDEO SERIAL CLK SHcp(DATA)
GND 10N 0805 10
MR
IC608 13 SPDIF LATCH 12
2
OE C612 SPDIF LATCH STcp(LATCH)

GP1FA550RZ VIDEO SERIAL DATA 14 DGND
VIDEO SERIAL DATA DS 100N 0805
DGND VIDEO SERIAL CLK 11 15 PAL NTSC
VIDEO SERIAL CLK SHcp(DATA) Q0 PAL NTSC
10 DGND 1 ZONE2 PAL NTSC
MR Q1 ZONE2 PAL NTSC
SPDIF LATCH 12 2 MAIN ZONE ENABLE
SPDIF LATCH STcp(LATCH) Q2 MAIN ZONE ENABLE
DGND 3 TRIGGER
Q3 TRIGGER
15 SPDIF SEL 1 4
Q0 Q4
DGND 1 SPDIF SEL 2 5
Q1 Q5
2 SPDIF SEL 3 6 ZONE2 ENABLE
Q2 Q6 ZONE2 ENABLE
3 SPDIF SEL 4 7 CLAMP_ON
Q3 Q7 CLAMP_ON
4 SPDIF SEL 5
Q4
5 SPDIF SEL 6 9
Q5 Q7OUT
6 SPDIF SEL 7
Q6
7 TRIGGER ZONE2 74HCT595D
Q7 TRIGGER ZONE2
9
Q7OUT
74HCT595D
P5V P5V P5V
IC600B C609 C610 C611 CHASSIS

16
16
16
74LV4053 SM 100N 0805 100N 0805 IC602B 100N 0805 C601

1N 0805 DRAWING TITLE 02_E163 WAF 8/08/02 IC701 CHANGED FROM 74LV244D TO 74HCT244D 3.2
74LV4053 SM
VDD
VDD
VDD
VEE
7 IC601B
VEE
7
VEE
7 AV8 SPDIF RXTX 02_E112 AJD 6/06/02 Updated R431 and 430 to improve the IR reciever reliability. 3.1
GND
GND
GND
74LV4053 SM
Filename: VID SPDIF RXTX.Sch 02_E103 MJT 15/05/02 None to this sheet 3.0
23425
8
DGND DGND DGND
DGND
Waterbeach
12V 100mA
P12V
P12V
R413 R414
6R8 0805 1% 6R8 0805 1%
Q413 Q409
BC859B BC859B
P5V
Q411 Q412
+ C423 R436
R432 R433 100U EL 10K 0805
10K 0805 10K 0805
TP401
IC400B BD180 PNP TO-126 R400 BD180 PNP TO-126 R405 DGND Q405
SK402B 6 4K7 0805 4K7 0805 BC859B
TOP - B Carrier Filter 7 SK403B
TP400 R448 R452
4 5 TOP - B
R461 TP403
1K0 0805 100K 0805 R406 R407 4
5 LM393A SM 10K 0805 10K 0805 C429
6 L400 470R 1W CF 5
R430 D400 22P NPO 0805
27MH R456 R453 6
JACK STEREO DUAL 3.5MM C428 4V7 350MW SM C433 1K8 0805 100K 0805 R435 TP404 JACK STEREO DUAL 3.5MM
TP402 680P PP DGND DGND DGND 10K 0805
22P NPO 0805
R416
C400 10K 0805 C401
1N 0805 Carrier Demodulator 1N 0805
Q408
470R 0805 C424 R415
CHASSIS DGND R458 P5V BC849B
10N 0805 1K5 0805 10K 0805 1%
DGND DGND CHASSIS
DGND R434
10K 0805
IC400A
3 Q407
1 Demod1 R441 BC849B
R440 DEMOD1
2 10K 0805
10K 0805 P5VV
LM393A SM Q404
DTRANN SM
R450 MAIN ZONE ENABLE R417
C415 MAIN ZONE ENABLE R408
1K0 0805 10K 0805 1% SW402
1N 0805 10K 0805
PROGRAM
PROGRAM
Q406 PROGRAM
TACTSW A1501
ZONE2 ENABLE
ZONE2 ENABLE
R447
10K 0805
DGND
DTRANN SM
P5V
VGND
12V 100mA R438 R439

10K 0805 10K 0805 DGND P12V
11
TP407
IC401B SK401
EMC
SK402A 6 R412 DTYPE 9 WAY MALE BOARDLOCK
BOTTOM - A Carrier Filter 7 10R 0805 1
TP405 R449 R454
1 5 Q415 6
TP408
1K0 0805 100K 0805 BC859B RXDATA 2
RXDATA
2 LM393A SM 7
TP409
3 L401 Q417 TXDATA 3
R431 D401 TXDATA
SCRN1 27MH R457 R455 FMMT597 8
C430 4V7 350MW SM C434 1K8 0805 100K 0805 4
SCRN2 22P NPO 0805 680P PP 9
TP410
EMC R421 SIGGND 5
TP406 SIGGND
JACK STEREO DUAL 3.5MM 10K 0805
Carrier Demodulator
EMC
470R 0805 C425 C431 C432 C416
DGND R459 P5V
10
10N 0805 1K5 0805 VGND 22P NPO 0805 22P NPO 0805 1N 0805
C417 TP412
1N 0805 DGND R446
10K 0805 Q427
IC401A DTRANP SM CHASSIS
3 D402
CHASSIS 1 Demod2 5V6 400MW
R445 DEMOD2
2
10K 0805 Q429
LM393A SM DTRANP SM
Q426
R451 Drive of RGBSTAT and SPARESTAT have been swapped DTRANP SM
1K0 0805 C418 over to allow RGBSTAT output to be either 1V, 12V or Q421
1N 0805 VGND. Q419
DTRANN SM P12V
N.B. RGBSTAT requires a 1V signal into a 75 Ohm load. DTRANN SM
R418
SCART CTRL 4 SCART CTRL 5 SCART CTRL 6
R419 10R 0805
JACK STEREO 3.5MM JY039 10K 0805 Q420 Q416
SK400 CVBSSTAT DTRANN SM BC859B
DGND
R422
10K 0805 Q418
RGBSTAT FMMT597
VGND R423
C1102 C1100 C1101 10K 0805
P12V 10N 0805 10N 0805 10N 0805
P12V
CHASSIS
R420 Q410 R409 Q428 Q430 VGND
R464 Q402 R401 10R 0805 BC859B 4K7 0805 DTRANP SM DTRANP SM
10R 0805 BC859B 4K7 0805 D403 D404
10V 400MW 5V6 400MW
Q431 Q432
Q401 R410 DTRANP SM DTRANP SM
Q400 R402 4K7 0805
4K7 0805
TRIGGER OUTPUT Q422 Q424
APPROX 11.4 DC DTRANN SM DTRANN SM
SK403A 60mA MAX CURRENT BD180 PNP TO-126 Q414
JACK STEREO DUAL 3.5MM BD180 PNP TO-126 Q403
TRIGGER ZONE2
R411 TRIGGER ZONE2 SCART CTRL 0 SCART CTRL 1 SCART CTRL 2 SCART CTRL 3
BOTTOM - A + C403
TP414 R404 TRIGGER 10K 0805 JACK STEREO 3.5MM JY039
1 10U EL R424 Q423 Q425
10K 0805 DTRANN SM SK404 CVBSSTAT2 10K 0805 DTRANN SM DTRANN SM
2 + C426 DTRANN SM R425
3 TP413 10U EL 10K 0805
SCRN1 SPARESTAT
SCRN2 C420 DGND

EMC 1N 0805 DGND VGND
TP415
R403 C1104 C1103 C1105
100R 0805 10N 0805 10N 0805 10N 0805
CHASSIS
C419 CHASSIS
1N 0805 C402
1N 0805 P5V P5V
CHASSIS DGND
CHASSIS
8
IC401C
IC400C
LM393A SM C421 LM393A SM C422
100N 0805 100N 0805 DRAWING TITLE 02_E163 WAF 8/08/02 IC701 CHANGED FROM 74LV244D TO 74HCT244D 3.2
AV8 RC5 Trigger
4
02_E112 AJD 6/06/02 Updated R431 and 430 to improve the IR reciever reliability. 3.1
Corrected JY039 socket schematic symbol, changed schematic to
Filename: VID RC5 & TRIGGER.sch 02_E103 MJT 15/05/02 3.0
23425
keep PCB the same.
DGND DGND
Waterbeach
Phase Locked
Loop
Board
L948
Contents
! Component overlay
! Parts list
! Circuit diagrams
AV8 Phase Locked Loop Board The phase comparator output PC2 generates a charge pulse
if the two signals are not exactly in phase and this pulse is
filtered and integrated by the opamp circuit IC5. IC5 runs
from +/- 12V rails so that the control voltage range can be
Introduction increased from 5V at the output of the phase comparator to
Refer To Block Diagram approximately 20V (+/- 10v) at the output of the opamp.
The increase voltage range allows a much greater
The phase locked loop performs a comparison between the capacitance range to be achieved on the varicaps D1 and
incoming master clock from the crystal semiconductors D2. IC5 pin 3 is biased to 2.5 volts so that the 0 to 5V
SPDIF receiver chip CS8415A and a locally derived input range can be converted to a positive and negative
master clock from an xtal based Voltage controlled output voltage.
oscillator (VCXO).
IC5 Loop filter.
The comparison is made at Fs (44.1 or 48 KHz) rather than 0V on the input = 10V on the output and 5V on the input
the master clock frequency (256xFs) as this improves the = -10V on the output
low frequency noise rejection of the circuit. The micro
controller on the main digital PCB (L896) knows what the The DC control voltage from the output of IC5 pin 6 is fed
incoming frequency is and can select the appropriate Xtal to the input of the varicaps D1 and D2. C31 and C35
oscillator using the control lines XTAL11.2896 and XTAL provide an AC ground for the oscillator circuit.
12.288. R10,R11,C33,C40 and R12,R13,C38,C41 create a filtered
negative 12V bias for the diode so that a maximum
The phase comparison is used to dump or source current voltage of 22V (12V +10V) from opamp and a minimum
from an integrating circuit which filters the pulses and of 2V (12V –10V) can be present on the varicap.
converts the charge to a voltage to control the VCXO.
The oscillator is a collpits type, the gain is provided by the
When charge is dumped onto the integrator the voltage RF transistor Q1 and Q2. The oscillator can be turned on
decreases (as it inverts) and this in turn reduces the reverse and off by the digital transistors Q3 and Q5 this removes
bias across the voltage control capacitor (Varicap). the load from the emitter of the RF transistors. The output
Reducing the reverse bias makes the depletion region in of the oscillator is via the capacitors C50 and C51 after the
the diode become smaller increasing the capacitance. capacitors the signal is biased to the threshold point of the
following gates IC3A and IC3C. The gates amplify the
Increasing the capacitance increases the load capacitance signal then the signal is fed back to the input of the loop to
on the xtal oscillator and thus reduces the frequency at the divider IC IC2 and to the input of a second buffer. The
which the crystal oscillates. (The circuit works in the second buffer is so that the micro can switch between the
opposite manner if charge is sourced off of the integrator) original clock and the phase locked clock buffer. This is
This is the method by which frequency lock is achieved. achieved by IC3B and IC3D and the output (phase locked
The phase of the circuit is arbitrary as it uses two dividers or bypass) is fed back to the main digital PCB L896.
that generate the Fs signals.
Q4 in the bypass feed is used to mute the input to IC3D
The bypass circuit feeds the clock from the CS8415A when the circuit is phased locked. This is to reduce any
direct to the rest of the circuits in the event of any of the cross talk from the original input master clock and the de-
following conditions. jittered phase locked master clock.
! Phase locked loop cannot lock to the incoming
signal (i.e. it is not at Fs = 44.1 or 48KHz) Lock detection is performed using the PC1/PCP out
! To much jitter on the signal that it goes outside (PIN2) of IC4 the phase comparator. This signal goes low
the +/- 150PPM tolerance whenever there is any phase error between the two
! When the loop is actively locking onto signal incoming signals so it can be used to determine if the
signal is in lock. When the signal is in lock this is always
In the event that the circuit is knocked out of lock for any high or has very small variations only due to tiny phase
reason more than three times after the DSPs on the main error corrections. If the signals go out of lock the signal
board have been reset it defaults to staying in bypass. This goes low and the capacitor C12 is discharged fast via the
is to prevent the situation where the master clock is diode D3, to charge the cap up again the signal has to pass
repeatedly lost. through the resistor R15 so the circuit is biased towards
indication out of lock very quickly and only showing lock
when the signal has been high for some time. As the
Description output of the PCP is a 5V signal and the Schmitt trigger
IC7 is a 3.3V part a potential divider is used to reduce this
Refer to circuit diagram L948 sheet 1 voltage to a maximum of 2.5V by R15 and R25. The
Schmitt trigger cleans up the edge of this lock detection
The master clock from the digital PCB L896 comes in on
signal and buffers it to be fed back to the micro controller.
pin 2 of SK3 goes to both the divider IC1 and to the
bypass circuit IC6. The divider divides by 256 and the
When the micro detects a lock signal it waits a further 3
clock at Fs then goes to the Comp input of the Phase
seconds to make sure the lock is stable then checks the
comparator IC4.
lock signal again before switching from the bypass circuit
to the phase locked clock.
As the integrator inverts the polarity of the control voltage
the inputs on the Phase comparator are swapped over so
that the comparison input is used for the main signal and Specification Range
the signal input is used for the comparison input. This
corrects the polarity of the complete control loop. Lock range 44.1 KHz 11.2896 MHz +/-
150PPM
The sig input on the phase comparator is fed from the Lock range 48 KHz 12.288MHz +/-
second divider IC2. IC2 divides the output of the voltage 150PPM
controlled xtal oscillator by 256 so that it is also at Fs.
L948 Phase Locked Loop Board Issue 1.0


D1 3E1530 Diode VARICAP KV1530
D2 3E1530 Diode VARICAP KV1530
IC3 5K74125 IC QUAD BUFFER 74HC125D SMT
IC4 5F9046AD IC PLL 74HCT9046AD SMT
IC5 5B071CD Opamp TL071CN SO-8 Package
IC6 5KA1U04 IC SINGLE INVERTER SN74AHC1GU04DBVR DBV
IC7 5K7414 IC HEX INVERTING SCHMITT TRIGGER 74HC14 SMT
L1 7B810 Inductor Surface Mount 1U0
PAD1 E802AP PAD DAMPING 15x6x3MM SORBOTHANE
PAD2 E802AP PAD DAMPING 15x6x3MM SORBOTHANE
PB L948PB BLANK PCB AV8 PHASE LOCKED LOOP PCB

X1 7X042 Crystal 11.2896MHz GOLLEDGE 7X042
X2 7X043 Crystal 12.288 MHz
+12VD
SP1 L2
SK1
1 Q_1 IR RX 1U0H SM
2 Q_2 SUPPORT PAD
C34 C6
3 Q_3 10N 0805 100N 0805
4 Q_4 LOCKDETECT
5 Q_5 XTAL/BYPASS* DGND IR RX SUPPORT PAD
6 Q_6 XTAL12.288 PAD1 DGND DGND
7 Q_7 XTAL11.2896 SORBOTHANE R17
15K 0805 1%
8 Q_8 HALF PAD
+5VD 7.5 X 6 X 3 mm
C23 C24 C25 C26 C27 C28 SORBO HALF PAD E802AP
AMPCT8 C1 C2 100P NPO 0805 100P NPO 0805 100P NPO 0805 100P NPO 0805 100P NPO 0805 100P NPO 0805
100N 0805 100N 0805
Lay this crystal flat to PCB +3V3D
R1 KV1530 VARICAP
100K 0805 1% Q1
D1 C32 X1
R3 BFS17H
CNTRL
DGND 100K 0805 1% R4
10N 0805 120K 0805 1%
11.2896MHZ HC49 30PF
C31 R10 C46 220P NPO 0805

10N 0805 47K 0805 1% IC3A
+5VD R2 + C29
100K 0805 1% C5 74HC125 SM
L1 C50
10U EL SG 100N 0805 DGND + C40 R14 2 3 R24
C33 10U EL 10K 0805 1% R19
1U0H SM 10N 0805 DGND 33R 0805 1%
C3 C4 220P NPO 0805
1
100N 0805 100N 0805 33R 0805 1%
IC1 DGND DGND DGND R11

47K 0805 1% C48
8 16 DGND DGND R22 R5
GND VCC 220P NPO 0805 2K2 0805 1% 100K 0805 1%
D3
TR? 9
TR? 7 IC7E IC7A
6 BAS16W SM -12VD DGND DGND
10 TR? 5 10 11 2 1 R15 DGND
CP TR? 2 10K 0805 1%
TR? 3
TR? 74HC14D 74HC14D Q3
11 MR 4 R30 R25 C12 DTRANN SM
TR? 10K 0805 100N 0805
TR? 13 33R 0805 +5VD XTAL11.2896
12 R31
TR? 14 NF +12VD
33R 0805 L4
TR? 15 R32 NF R20
TR? 1 + C30 DGND DGND IC7B
33R 0805 33R 0805 1%
TR? R62 10U EL SG C10 1U0H SM C11
NF 100N 0805 3 4 DGND
74HCT4040 SM 33R 0805 100N 0805
R63 NF C13 +12VD
74HC14D
DGND 33R 0805 DGND DGND DGND 100N 0805
IC4 SP2 L5
16 PHASE COMP 1 DGND IR RX

VCC GND 1U0H SM
SUPPORT PAD
IC5 C37 C15
3 COMP IN DGND 10N 0805 100N 0805
7
SK3 14 SIG IN PC1/PCP OUT 2 3
1 Q_9 6 IR RX SUPPORT PAD
2 Q_10 +5VD 15 13 2 PAD2 DGND DGND
3 L3
RB PC2 OUT SORBOTHANE R18
4
4 Q_11 C54 C55 HALF PAD
15K 0805 1%
TL071SM
5 R6 7.5 X 6 X 3 mm
1U0H SM 100K 0805 1% VCO
C8 C9
100N 0805 100N 0805 6 C1A SORBO HALF PAD E802AP
AMPCT5 DGND DGND 7 C1B VCO OUT 4
IC2 11 C14 Lay this crystal flat to PCB +3V3D
8 16 DGND DGND 10P SM 0805 10P SM 0805
12 R1 10 KV1530 VARICAP
DGND GND VCC 9 R2 DEM OUT 100N 0805
D2 C36 X2 Q2
VCO IN R7 BFS17H
TR? 9 5 INH GND VCO 8
7 R90 -12VD DGND R8
TR? 100K 0805 1%
10N 0805 12.288MHZ HC49 30PF 120K 0805 1%
100N 0805
TR? 6
C7 C52 C53 10 5 74HCT9046AD
CP TR? 22K 0805 1% C35 R12
2 47K 0805 1%
TR? 3 10N 0805 C47 IC3C
CNTRL 10P SM 0805 10P SM 0805
11 MR TR? 4 R64 DGND DGND DGND 220P NPO 0805
C51
74HC125 SM
TR? R16 R26
TR? 13 33R 0805 DGND + C41
10K 0805 1%
9 8
R65 C38 10U EL R21
TR? 12 NF C58 10N 0805 DGND 33R 0805 1%
14 33R 0805 R92 220P NPO 0805
10
TR? R66 33R 0805 1%
15 NF 47K 0805
TR? 1 10U NP R13
33R 0805 47K 0805 1%
TR? R67 NF C49 R23 R9
220P NPO 0805 2K2 0805 1% 100K 0805 1%
74HCT4040 SM 33R 0805 C56
R68 NF
33R 0805
DGND 220N PE -12VD DGND DGND
DGND
C57
Q5
DTRANN SM
22N PE XTAL12.288
IC7C
5 6 DGND
IC3B
74HC125 SM
74HC14D
5 6 R28
+3V3D 33R 0805 1%
4
L6
IC7D
1U0H SM 9 8
C16 C17
100N 0805 100N 0805
74HC14D
DGND DGND IC3D

IC6
74HC125 SM
5
2 4 R91 12 11 R29
1K0 0805 33R 0805 1%
3
13
74AHC1GU04 SM
DGND Q4
DTRANN SM
XTAL/BYPASS*
PB
PCB DGND
L948PB
PD1 PD2 PD3

TOOLING TOOLING TOOLING
FD_1 FD_2 FD_3
FIX7 FIX902 FIX9 FIX1

FIDUCIAL FIDUCIAL FIDUCIAL FIXING HOLE 3.5 FIXING HOLE 3.5 FIXING HOLE 3.5 FIXING HOLE 3.5 +3V3D +3V3D
FD_4 FD_5
L7
FIDUCIAL FIDUCIAL
1U0H SM
C62
SK2 CNTRL PSU
14
14
IC7F C59 C60 C61 C64 100N 0805 C39 C22
1 P1 10N 0805 100N 0805
P12V 2 13 12 10N 0805 10N 0805 10N 0805 10N 0805 IC3E
DGND 3 IC7G DGND
N1 74HC125 SM
N12V 4 74HC14D
DGND DGND
DGND 74HC14D
5 L8 +5VD L10 +12VD
7
P5V P2
DGND 6 DGND
7 +1 +3 DGND
P3 6U8H RADIAL 6U8H RADIAL
P3V3 8 + C42 + C44 DGND DGND
DGND1 C18 C20
DGND 100N 0805 10U EL 10U EL
100N 0805
DGND2 DGND4 DRAWING TITLE
AMPCT8
C65 C66
10N 0805
C67
10N 0805
C68
10N 0805
C69
10N 0805
C70
10N 0805
C71
10N 0805
C72
10N 0805
DGND DGND AV8 Phase Locked Loop
10N 0805 L9 +3V3D L11
23425
+2 -1 Filename: L948ct_1.0.sch
6U8H RADIAL 6U8H RADIAL
C19
+ C43
C21
-12VD
10U EL C45 Notes:
100N 0805 100N 0805 + 10U EL
PSU DGND3 DGND5 A & R Cambridge Ltd. 02_E100 WAF 8/5/-2 PRODUCTION ISSUE 1.0
DGND Pembroke Avenue ECO No. INITIALS DATE DESCRIPTION OF CHANGE ISSUE
Waterbeach
Cambridge CB5 9PB Contact Engineer: EngName A.Dutton Contact Tel: (01223) 203240 tel No Printed: 9-May-2002 Sheet 1 of 1 DRAWING NO. L948CT
Mechanical
Assembly
Contents
! General assembly
parts list
! Phono card upgrade

assembly parts list
AV8 General Assembly Parts List
ITEM 230V 115V 100V SILVER BLACK DESCRIPTION WHERE USED QTY
1 E101AY E101AYB COVER PLATE ASSEMBLY 1

2 E839AY E839AYB VOLUME KNOB ASSEMBLY 1
3 E850PM E850PMB FMJ MAINS BUTTON 1
4 E919AY E919AYB FASCIA ASSEMBLY 1
HA4V06B SCREW MACHINE M4x6mm PAN TORX ST STEEL BLACK
5 HA4V06S SCREW MACHINE M4x6mm PAN TORX ST STEEL NICKEL COVER TO CHASSIS 4
6 8A016 IEC INLET 1
7 E040AY REAR PANEL ASSEMBLY 1
8 E041AY PHONO CAN ASSEMBLY 1
9 E042AY POWER CAN ASSEMBLY 1
10 E800RS MAINS IEC LEAD 1
11 E806PK POLY BAG VENTILATED 415x535MM 350 GAUGE TO PACKAGE UNIT 1
12 E816CH CHASSIS 1
13 E873MC DAMPING PLATE CHASSIS FLOOR 1
14 E877MC POWER CAN LID 1
15 E879SL PRODUCT CONFIGURATION CONTROL LABEL OUTSIDE OF CHASSIS WALL 1
16 E887PM DiVA POWER BUTTON ADAPTER 1
17 E905PK PLAIN OUTER CARTON FMJ AV8 1
18 E906PK INTERNAL PRINTED CARTON FMJ AV8 1
19 E907PK CARDBOARD PARTITION FOR MAINS LEAD FMJ AV8 INSIDE INTERNAL CARTON 1
20 E908PK PAIR OF CAPS (TOP AND BOTTOM) FMJ AV8 1
21 E919MC DIGITAL PCB SHIELD 1
22 E935MC FOOT (TURNED) 4
23 E936SL FMJ AV8 CARTON LABEL ON INNER AND OUTER PACKING CARTON 2
24 E942SL SHOCK WARNING LABEL ON TOP OF E877MC 1
25 F219 TWIST LOCK CABLE CLIP ON TOP OF DIGITAL PCB EMC SHIELD 2
26 F224 BLACK DOME BLANKING PLUG MM/MC HOLE ON REAR PANEL 1
27 F225 BUMPON FOOT (3M) STICKS TO RECESS IN FOOT 4
28 F226 EMC GASKET (250mm) ALONG TOP EDGE OF SUB-PANEL 1
29 H030 18mm M3 MALE-FEMALE PILLAR ABOVE & BELOW PHASE LOCK LOOP PCB 8
30 H038 38mm M3 FEMALE-FEMALE PILLAR BETWEEN AUDIO AND VIDEO PCB 5
31 H039 38mm M3 MALE-FEMALE PILLAR DIGITAL PCB 12
BETWEEN AUDIO AND VIDEO PCB
32 H041 22mm M3 MALE-FEMALE PILLAR BETWEEN VIDEO AND TOP VIDEO PCB 2
33 HA3V06A SCREW MACHINE M3x6mm PAN TORX STEEL ZINC-PLATE CLEAR 60
34 HA3V10B SCREW MACHINE M3x10mm PAN TORX-SLOT STEEL ZINC-PLATE BLACK IEC INLET 2
35 HA4A12B SCREW MACHINE M4x12mm PAN SUPA STEEL ZINC-PLATE BLACK REAR PANEL EARTHING STUD 1
36 HA4V06S SCREW MACHINE M4x6mm PAN TORX ST STEEL NICKEL CHASSIS EARTHING STUD 1
37 HE6V06B SELF-TAPPING N06x6mm PAN TORX-SLOT STEEL ZINC-PLATE BLACK SUB-PANEL TO CHASSIS 8
THRO’ CHASSIS INTO DAMPING PLATE
38 HF4V09B SCREW SELF-TAPPING-SEMS N04x9mm PAN TORX-SLOT STEEL ZINC-PLATE 62
BLACK
39 HJ3A00F NUT NYLOC M3 STEEL ZINC-PLATE CLEAR IEC INLET 2
40 HJ4A00A NUT FULL M4 STEEL ZINC-PLATE CLEAR REAR PANEL EARTH 1
41 HJ4C00D NUT WAISTED M4 BRASS CLEAR REAR PANEL EARTH 1
42 HJ9A01E NUT HALF M9 STEEL ZINC-PLATE CLEAR VOLUME KNOB 1
43 HL3IB WASHER INT-SHAKEPROOF M3 STEEL ZINC-PLATE BLACK IEC INLET SCREWS 2
44 HL4SB WASHER INT-SHAKEPROOF M4 STEEL ZINC-PLATE BLACK SIDE OF CHASSIS (1) AND REAR PANEL EARTH (2) 3
45 L816RC REMOTE CONTROL AV8 1
46 L896AY AV8 DIGITAL PCB ASSEMBLY 1
47 L897AY PSU PCB ASSEMBLY HORIZONTAL & VERTICAL PCB’S 1
48 L898AY AV8 DISPLAY PCB ASSEMBLY 1
49 L921AY AV8 AUDIO PCB ASSEMBLY INCLUDES AUXILIARY SNAP-OFF PCB 1
50 L922AY AV8 VIDEO PCB ASSEMBLY INCLUDES SNAP-OFF TOP VIDEO & HEADPHONE PCB 1
51 L922CA 22-WAY FLEX FOIL 100mm VIDEO - TOP VIDEO PCB 2
AUDIO - DIGITAL
52 L923CA 8-WAY AMP CT 120mm AUDIO – DIGITAL (2) 4
PHASE LOCK LOOP - DIGITAL PCB (1)
VIDEO – HORIZ POWER (1)
53 L925CA 8-WAY AMP CT 280mm AUDIO PCB - AUX SNAP-OFF PCB (1) 3
PHASE LOCK LOOP - HORIZ POW PCB (1)
DIGITAL – POWER (1)
54 L926CA 7-WAY AMP CT 350mm DIGITAL - HORIZONTAL POWER PCB 1
55 L927CA 6-WAY AMP CT 100mm AUDIO TO HORIZ POWER 1
56 L928CA 6-WAY AMP CT 600mm DIGITAL - HORIZONTAL POWER PCB 1
57 L929CA 4-WAY AMP CT 220mm DIGITAL - VERTICAL POWER PCB 1
58 L930CA 5-WAY AMP CT 250mm HEADPHONE PCB - AUDIO PCB 1
59 L931CA 30-WAY FLEX FOIL 190mm VIDEO - DIGITAL PCB 2
DIGITAL - DISPLAY PCB
60 L933CA 5-WAY AMP CT 100mm AUDIO - DIGITAL 2
PHASE LOCK LOOP - DIGITAL PCB
61 L939CA POWER LOOM IEC INLET 1
62 L948AY PHASE LOCK LOOP PCB 1
63 P3020 GRIP-SEAL POLYTHENE BAG 254X356 CLEAR 180 GAUGE FOR REGISTRATION CARD, ENVELOPE AND HANDBOOK 1
64 SH000 REGISTRATION CARD IN POLY BAG P3020 1
65 SH000A ENVELOPE IN POLY BAG P3020 1
66 SH099 AV8 HANDOOK (MULTI-LANGUAGE) IN POLY BAG P3020 1
67 SH116 L816RC CR80 REMOTE HANDBOOK 1
68 SH119 REAR PANEL CONNECTOR FITTING INSTRUCTIONS 1
69 SM631 SELLOTAPE PACKING 0.2m
70 U015 BLANK BAR-CODE LABEL REAR PANEL (WHERE INDICATED), OUTSIDE WALL OF CHASSIS, REGISTRATION CARD, 6
OUTER CARTON LABEL & INNER CARTON LABEL (WHERE INDICATED), AIWA’S RECORDS.
AV8 Phono Card Upgrade General Assembly Parts List
ITE 230V 115V 100V SILVER BLACK DESCRIPTION WHERE USED QTY
M
1 L870AY PHONO PCB 1
2 H031 20mm M3 FEMALE-FEMALE PILLARS 3
3 HF4V09B TORX SCREW NO.4x9m + WASHER REAR PANEL 1
4 HA3V06A M3x6mm SCREW INTO PILLARS 6
5 L925CA 8-WAY AMP CT 240mm 1
6 P2C03 WHITE CARD OUTER SLEEVE 1
7 P1A30 BLUE ACCESSORY CARTON 1
8 P2C02 CARD INSERT FOR PHONO PCB 1
9 E941RS HANDBOOK AND ADDENDUM ASSEMBLY PLACE IN INSERT 1
10 E933SL PHONO LABEL PLACE ON CARTON 1
11 SM631 SELLOTAPE FOR OUTER SLEEVE 0.2m
12 P3004 POLY BAG SELF SEAL (6” x 9”) FOR PILLARS, SCREWS & CABLE 1
ARCAM
All parts can be ordered via spares@arcam.co.uk
Pembroke Ave, Waterbeach, Cambridge, CB5 9PB, ENGLAND

TEL: +44(0) 1223 203 203 FAX: +44(0) 1223 863 384

AV8 Service Manual Issue2 Complete

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Service Manual AV8

Phono board L870

Digital board L896

PSU board L897

Display board L898

Audio board L921

Video board L922

Phase Locked Loop board L948

L896 Digital Board

02_E101 IC906 EEPROM changed from 5G24LC08 to 5G24LC16

L897 Power Supply Board

L898 Display Board

02_E081 R128 changed from 22K (1M322) to 33K (1M333)

L922 Video Board

02_E103 Change of PCB routing

L948 Phase Locked Loop Board

Summary Issue 1.0 to 2.0

! Front & rear view

AV8 PREAMP PROCESSOR

THX EFFECT MODE

DESIGNED & MADE REMOTE DIGITAL INPUTS HIGH QUALITY VIDEO

Video inputs and outputs

! AV8 Loader software

THX Ul2: 13.0 DTS –ES: 15.0 Front Panel IR Rx

Exit this menu Engineering Menu 2

RC5 Code Zone 1

RC5 Code Zone 2

If, after programming the AV8 the unit displays

! How to assemble the

3. Assemble the power socket to rear panel before

5. N.B. If a phono card is to be fitted then you do not fit

Part No. Description Qty

Part No. Description Reference Qty

Part No. Description Qty

Connect L930CA from audio board (SK917) to the headphone

Part No. From To Part No. Description Qty

Part No. From To Part No. Description Qty

The amplifier is a small signal class A voltage feedback

Both of these differential stages are designed to have as

SW100 switches between MM and MC. Two poles of the

The DC offset is controlled by a non-inverting servo built

The output is class A buffered by a dual mirror follower

Closed loop stability is achieved with C16, C117, giving

Designator Part Description

Designator Part Description

PCB1 DRAWING TITLE

100R MF C108 100P PPW 12

R120 R121 + C107

100R MF 100P PPW 9

R220 R221 + C207

The clock for the DSP is generated from the Micro-controller

Each of the supplies that is used passes through a LC filter to

PSU Sync signal

Voltage set and VFD HT shut down

To prevent anode stripping when the heater is switched off the

Three regulators are used to provide secondary regulation for

Designator Part Description

Designator Part Description

Designator Part Description

Designator Part Description

Designator Part Description

Designator Part Description

Designator Part Description