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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO.

12, DECEMBER 2010

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A 1.2-V 10-W NPN-Based Temperature Sensor in 65-nm CMOS With an Inaccuracy of 0.2 C (3 ) From 70 C to 125 C
Fabio Sebastiano, Student Member, IEEE, Lucien J. Breems, Senior Member, IEEE, Ko A. A. Makinwa, Senior Member, IEEE, Salvatore Drago, Student Member, IEEE, Domine M. W. Leenaerts, Fellow, IEEE, and Bram Nauta, Fellow, IEEE
AbstractAn NPN-based temperature sensor with digital output has been realized in a 65-nm CMOS process. It achieves a batch-calibrated inaccuracy of 0.5 C (3 ) and a trimmed inaccuracy of 0.2 C (3 ) over the temperature range from 70 C to 125 C. This performance is obtained by the use of NPN transistors as sensing elements, the use of dynamic techniques, i.e., correlated double sampling and dynamic element matching, and a single room-temperature trim. The sensor draws 8.3 A from a 1.2-V supply and occupies an area of 0.1 mm2 . Index TermsCMOS analog integrated circuits, sigma-delta modulation, smart sensors, temperature sensors.

I. INTRODUCTION EMPERATURE sensors are used in a wide range of commercial applications, ranging from the control of domestic appliances and industrial machinery to environmental monitoring. Fabrication costs can be reduced by implementing the sensors in standard digital CMOS processes. This enables the co-integration of the read-out electronics, so that a digital temperature reading can be directly provided to, for instance, a microcontroller. An additional motivation for the development of CMOS temperature sensors in deep-submicron technologies has come from their use in the thermal management of microprocessors [1][4]. Although this requires an accuracy of only a few degrees centigrade, other applications are more demanding, e.g., the compensation of CMOS frequency references [5], [6] or MEMS oscillators [7]. CMOS temperature sensors with an inaccuracy of less than 0.1 C over the military temperature range have been demonstrated in a mature technology (0.7- m CMOS) [8], [9]. They are usually based on the temperature dependency of PNP transistors and achieve high accuracy by employing a single-temperManuscript received April 21, 2010; revised July 12, 2010; accepted August 19, 2010. Date of publication October 11, 2010; date of current version December 03, 2010. This paper was approved by Guest Editor Gyu-Hyeong Cho. This work was supported by the European Commission in the Marie Curie Project TRANDSSAT-2005-020461. F. Sebastiano, L. J. Breems, S. Drago, and D. M. W. Leenaerts are with NXP Semiconductors, Eindhoven, The Netherlands (e-mail: fabio.sebastiano@nxp. com). K. A. A. Makinwa is with the Electronic Instrumentation Laboratory, Delft University of Technology, Delft, The Netherlands. B. Nauta is with the IC Design Group, CTIT Research Institute, University of Twente, Enschede, The Netherlands. Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/JSSC.2010.2076610

ature trim as well as precision circuit techniques, such as offset cancellation, dynamic element matching (DEM) and curvature correction.1 The same sensing principle has been employed in temperature sensors in 65 nm [3] and 32 nm [10], but these only achieved inaccuracies of about 5 C. This lack of accuracy is mainly due to the non-idealities of parasitic PNP transistors in deep-submicron technologies. Other sensing principles have been proposed for deep-submicron applications, such as the use of thermistors [1], the measurement of ring oscillator frequency [1] or MOS-transistor leakage [2]. These approaches require either multi-temperature trimming, or suffer from inaccuracies of a few degrees centigrade even over temperature ranges much narrower than the standard military or industrial temperature ranges. Sensors based on inverter delay have been proposed as good candidates for VLSI integration because of their compact layout. However, in a 0.35- m CMOS prototype, a two-temperature trimming was necessary to achieve an inaccuracy of 0.4 C to 0.6 C over the range from 0 C to 90 C [11]. Furthermore, the sensors power supply sensitivity was quite high: about 10 C/V at room temperature, which is two orders of magnitude worse than that of PNP-based sensors. This paper describes the design of a temperature sensor in 65-nm CMOS [12]. The aim was to demonstrate that accurate low-power low-voltage temperature sensors can still be designed in deep-submicron CMOS processes. Precision circuit techniques already adopted for larger feature-size processes have been employed, together with deep-submicron-specic techniques, such as the use of NPN bipolar transistors as sensing elements. In this way, a batch-calibrated inaccuracy of and a (single-temperature) trimmed inaccuracy of 0.5 C from 70 C to 125 C have been achieved. 0.2 C The sensors principles of operation are presented in Section II, while its main sources of inaccuracy and the techniques used to overcome them are described in Section III. The circuit details are presented in Section IV; experimental results are shown in Section V and conclusions are drawn in Section VI. II. PRINCIPLE OF OPERATION The sensing principle of a bandgap (or bipolar-transistor-based) temperature sensors is depicted in Fig. 1. The
1Throughout the paper, the terms batch-calibration or correction (curvature correction, nonlinear correction) refer to the adjustment of all samples in the same manner and by the same amount.

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Fig. 1. Principle of operation of the temperature sensor and temperature dependence of voltages in the sensor core.

Fig. 2. Simplied cross section of (a) a substrate PNP and (b) a vertical NPN in CMOS technology.

sensors core consists of a pair of matched bipolar transistors (diode-connected PNPs) biased by two currents with ratio , and . to produce two temperature-dependent voltages The base-emitter voltage of one transistor and the difference can be approximated as in base-emitter voltages (1)

(2) where is the Boltzmanns constant, is the absolute temperis the bias current and ature, is the electron charge, is the saturation current of the transistor. is proportional to absolute temperature (PTAT) and independent of process and bias conditions. can be fed to an analog-to-digital converter (ADC) to produce a digital temperature reading. As shown in Fig. 1, a PTAT digital output can then be generated by combining and as follows [13]: (3) in this work). and using the appropriate scale factor ( An output in degree Celsius can then be obtained by scaling: (4) where and [13].

Fig. 3. Bipolar transistors congurations to generate V PNP and (b) a vertical NPN.

using (a) a substrate

III. SOURCES OF INACCURACY A. Non-Idealities of Bipolar Transistors CMOS temperature sensors are usually based on substrate PNPs [3], [8][10], [14]. As shown in Fig. 2(a), these consist of a p+ drain diffusion (emitter), an n-well (base) and the silicon substrate (collector) and are available in most CMOS processes. Since the silicon substrate is usually tied to ground, the PNP must be biased via its emitter [Fig. 3(a)]. While (1) is valid for , it is this conguration under the approximation possible to derive [13]

(5)

and are emitter and base currents and where is the current gain of the transistor. The nite current gain and . The its spread affect both the curvature and the spread of additional curvature can be compensated for by using standard -curvature compensation (see Section III-D), methods for but the additional spread directly impacts the sensors accuracy. As can be understood from (5), this effect is negligible for high but becomes increasingly signicant as decreases [8]. The current gain of the substrate PNPs available in several CMOS processes is reported in Fig. 4. It approaches unity in deep-submicron processes, making it difcult to implement accurate temperature sensors with these devices. As an alternative, parasitic NPN transistors can be employed, which can be directly biased via their collectors. Lateral NPN transistors in CMOS technology have been used in temperature sensors [15] characteristic deviates from (5) due to varbut their ious extra non-idealities [13]. A better option is the vertical NPN [16], [17], which consists of an n+ drain diffusion (emitter), a p-well (base) and a deep n-well (collector), all standard features in deep-submicron processes [Fig. 2(b)]. Their only disadvantage is a higher sensitivity to packaging stress compared to vertical PNPs [18]. As shown in Fig. 3(b), a vertical NPN can be biased via its collector, while the required base current can be easily provided by a feedback amplier. The resulting base-emitter voltage will then be independent of the transistors current gain. Moreover, the transistors drain voltage is xed by the feedback amplier, making the collector current insensitive to supply voltage variations. It should also be noted that this circuit can tolerate lower supply voltages than a diode-connected PNP. With reference to Fig. 3(a), this requires a minimum supply voltage equal to the and the current sources headroom. Since can be sum of

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Fig. 5. Principle of operation of the charge-balancing converter. Fig. 4. Current gain of substrate PNP transistors versus the minimum gate length for various CMOS processes (data from [13] and several design manuals).

as high as 800 mV at the lower bound of the military temperature range 55 C and a certain headroom is required to ensure current source accuracy, the minimum supply voltage can easily exceed 1.2 V. For the NPN circuit in Fig. 3(b), however, the supply voltage primarily has to accommodate the sum of the 0.3 V and of the curNPNs saturation voltage rent sources headroom. Although it must also ensure the functionality of the branch, comprising the base-emitter junction and is ensured by the amplier, that supplies , the accuracy of the feedback loops gain and consequently the amplier does not require much headroom. The minimum supply voltage can thus be signicantly lower than in the case of a diode-connected PNP. This is a signicant advantage in deep-submicron designs, which must operate at supply voltages of 1.2 V or lower. B. ADC Accuracy and Quantization Noise The digital output in (3) can be obtained by connecting the bipolar core to the charge-balancing converter shown in Fig. 5 [19]. Here, a bias circuit generates a supply-independent current . Scaled copies of this current bias a pair of vertical NPNs at a collector current ratio and a third NPN with a current . The resulting voltages and constitute the ADC. The ADC integrates when inputs of a 1st-order and integrates when . Thanks the bitstream to the negative feedback, the average input of the integrator is equal to zero, i.e., the integrated charge is balanced, which can be expressed as (6) where the bitstream average is . From (6) it follows that the resulting satises (3). In the practical implementation of the charge-balancing converter, a sensitive point is the implementation of the amplication factor . An integer factor is usually adopted, so that it can easily be realized by an array of matched elements, e.g., capacitors [8]. The limit to the accuracy of is therefore determined by the matching of these elements, requiring the use of dynamic element matching techniques that add to the complexity and area of the sensor. Alternatively, the factor can be realized by multiple integrations during the phase. This is depicted in Fig. 6(a)

. The amplier in Fig. 5 is removed from for the case , is integrated in the system of Fig. 5 and when successive cycles. When , is integrated in a single cycles. At the end of the cycles, the comparators output is updated. With this solution, a single element , but the drawback is that the can be used to implement conversion speed is traded for accuracy. This is because times more cycles are used to obtain an accurate multiplication factor. The comparator is sampled only after a single integration for the phase or after a series of integrations for the phase. An additional improvement in resolution can be achieved if the comparator is sampled more rapidly, e.g., after every integration, as shown in Fig. 6(b). Note that this is equivalent to . The effectiveness of this apmultiple integrations with proach is demonstrated by Matlab simulation of the 1st-order converter with and . The results are shown in Fig. 7, where the peak quantization error over the temperature range from 70 C to 125 C is plotted versus conversion time. In the simulation, the length of the different phases required by the circuit described in Section IV has been used,2 i.e., respecphase and the phase, 390 s and tively, for the and 70 s and 100 s for . The value 100 s for has been chosen since it corresponds to a simple circuit implementation (see Section IV-D). , then in (3) will no It should be noted that if longer be temperature independent and the bitstream average will no longer be PTAT. A digital back-end (similar to the one in [10]) is then required to compute a PTAT output, according to the relation (7) where is the value required in (3) to obtain a PTAT output, and is the value actually used in the charge-balancing converter. It can be concluded that, for the same conversion time, using a smaller value of results in lower quantization error, thanks to the increased granularity of the charge-balancing process. The only drawback is the need for a digital back-end to implement the nonlinear correction described by (7). However, in a deep2With reference to the symbols used in Section IV-D, for , the bs phase is the same as in the case , while the length in the bs phase has been assumed equal to T T s s s.

= 18 =1 =2 =0 + ( 0 1) = 50 + 17 1 20 = 390

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Fig. 6. Integrator output and output bitstream of a fragment of the temperature conversion of the system in Fig. 5 for different values of ; the dashed lines . (b) . indicate the sampling of the comparator. (a)

=6

=1

Fig. 8. Block diagram of the temperature sensor.

perature-independent. Any systematic residual nonlinearity can then be compensated for by digital post-processing. A full conversion then consists of the following steps: , as 1) the charge-balancing converter is operated with explained in Section III-B; 2) the output bitstream is decimated to obtain (8) 3) a PTAT ratio is computed: (9)
Fig. 7. Simulated peak quantization error over the temperature range from 70 C to 125 C versus conversion time for different values of .

4) The residual nonlinearity in is compensated for with the help of a compensating polynomial. IV. CIRCUIT IMPLEMENTATION A block diagram of the sensor is shown in Fig. 8. The circuit , the bipolar front-end design of the bias circuit generating are described in detail in the following sections, and the together with the choice of the bias currents for the bipolar core.

submicron CMOS technology, this requires little extra chip area or power dissipation. C. Process Spread Since accurate current references are not available in CMOS, is derived by forcing a well-dened voltage, e.g., , across a resistor. However, due to the spread of this resistor and of the biased transistor will still spread. the spread of , the As shown in [20], this spread is PTAT in nature, and can be cancelled simply by trimming the bias current used to generate , i.e., by trimming in Fig. 5 [8]. In this way, a singlepoint trim is enough to compensate for process. D. Nonlinearity of In the previous sections, the temperature behavior of has shows a slight nonbeen considered to be linear. In practice, linearity mainly consisting of a second-order term [21]. Over the military temperature range, this can be as large as 1 C [8]. The nonlinearity in can be compensated for by making , the temperature coefcient of the denominator of (3), i.e., slightly positive [19]. This can be accomplished by slightly incompared to the value required to make temcreasing

A. Current Level in the Bipolar Core The bias currents of the NPN transistors in the bipolar core are constrained by several requirements, such as accuracy, noise and conversion speed. For low collector currents, the approximation used in (1) is not valid anymore and must be expressed as

(10) Thus, the bias current must be signicantly larger than the saturation current in order to obtain an accurate PTAT voltage, es-

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pecially at higher temperatures, since increases rapidly with temperature and can reach pico-Ampere levels at 125 C. is impaired by For large bias currents, the accuracy of the parasitic resistances and in series with the emitter may be and the base junction respectively. In this case expressed as (11) (12) (13) (14) and are the base and emitter currents of where and is the equivalent series resistance [13]. Typical values and are typically in the order of 100 and 10 , for respectively. Considering that the current gain is commonly will be in the lower than 10 in deep-submicron processes, order of some tens of Ohms, leading to a non-negligible temperature error for bias currents higher than a few hundred nano-Amperes. non-PTAT. The additional terms in (10) and (14) make Moreover, those terms will give rise to extra spread, due to and . Fig. 9 shows the simthe process spread of , spread on the temperature reading for ulated effect of the NPN transistors available in the adopted technology with m m emitter area, with the added assumption that the a is 20%. Since no accurate spread models for spread in the parasitic resistances and saturation currents were available, these parameters were kept constant. The maximum allowable error (dashed line in Fig. 9) due to spread should be less than 10% of the target inaccuracy. It can be seen that several pairs meet those requirements. of the design parameters and and A larger is preferable, because it implies a larger consequently more relaxed requirements on the ADC. A larger bias current is also advantageous since it results in less noise. and at Based on these considerations, room temperature have been chosen. B. Bias Circuit and are biased In the bias circuit (Fig. 10), transistors ) with a 2:1 by a low-voltage cascode mirror ( and current ratio, forcing a PTAT voltage across polysilicon resistor and making the emitter current of supplyare tied independent. The gates of the cascode transistors . The cascade of and provides to ground the base currents for and in a conguration similar to that can be derived shown in Fig. 3(b). The bias current by generating and summing copies of the collector current and the base current of . If the current gains of and were equal and consequently held for their base could be obtained by mirroring the drain current currents, with a gain of 1/3 and adding it to a copy of . However, of since is a (weak) function of collector current, a replica circuit
Fig. 9. Maximum temperature error over the military range due to spread in V for different bias current and bias currents ratio n.

is used to bias the matched transistor with the same collector current of and obtain an accurate copy of through . and (through and ) are then summed Copies of at the input of a low-voltage current mirror [22]. Unlike PNP-based bias circuits [8], [9], [14], the circuit in Fig. 10 does not need low-offset ampliers. This is because the and resistor loop comprising the base-emitter junctions of can be directly realized with NPNs but not with substrate PNPs. In the presented circuit, the function of the feedback ampliers and the low-voltage current mirror is only to equalize their collector-base voltages. Thus, their offset specications are relaxed. However, since the base currents are relatively large , and the transconductance of and is rather low, the common-source buffers and are used to reduce the and . The collector voltage voltages present at the input of , obtained by biasing with a copy of . is set to and are implemented as current-mirror-loaded pMOS differential pairs with tail currents of 340 nA at room temperature. Their respective feedback loops are stabilized by Miller and the associated zero-cancelling resistors capacitors . is a current-mirror OTA [23] with a pMOS input pair. The associated feedback loop is stabilized by Miller capacitor . This is kept reasonably small (1 pF), by using a low bias current (8 nA) combined with a mirror attenuation of 10 to keep the OTAs effective transconductance low. The bias and are thus currents of the ampliers are scaled copies of approximately PTAT and supply-independent. Thanks to the use of NPNs and of the feedback loops, the circuit is able to work at low supply voltages and low temperatures. Simulation shows that, for the adopted process, the effect is less than 300 ppm/V down to a of supply variations on 800 mV). supply voltage of 1.2 V at 70 C (for which Due to the self-biasing nature of the circuit, a start-up circuit generates a current in is required. The long transistor at the the order of few tens of nA, which is lower than the correct operation point for any operating condition and process corner. This current is compared to by the current comparator comprising , and . If is larger than , i.e., if is mirthe circuit has not yet started up, the difference and used to start-up the circuit. The start-up rored by current is delivered to the bases of , to resistor and

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Fig. 10. Schematic of the bias circuit.

Fig. 11. Schematic of the bipolar core and of the 61 ADC.

as bias currents of (not shown in the schematic), which would otherwise be off because of the low . The injection makes the currents in all the branches increase and of becomes larger than reach the stable operation point. When , the current in is zero and the start-up circuit is disabled. C. Bipolar Core and are In the bipolar front-end (Fig. 11), transistors unit current sources , whose biased by an array of . The switches controlled current (50 nA) is derived from and can be congured to generate a differential by output equal to either or . If is high and is low, the base-emitter junction of is shorted is switched off to prevent and the drain current of . In this any voltage drop over the switch driven by

. When both are condition, high, the switches connected to the current source array are set to and either at a :1 or at a 1: collector current ratio, bias or . so that, respectively, either Because and are not required at the same time, only two bipolar transistors are employed rather than the three shown in Fig. 5. needs to be integrated, the accuracy of the 1: When current ratio and, hence, that of is guaranteed by a bitstream-controlled dynamic element matching (DEM) scheme, which is used to swap the current sources in a way that is uncor-integration related with the bitstream [8]. In successive cycles, a different current source is chosen from the array to sources provide the unit collector current, while the other provide the larger collector current. Mismatch errors in the current sources are thus averaged out without introducing in-band

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intermodulation products. Another source of error is the misand , which can be expressed as mismatch match between and . This misof their saturation currents, respectively, match can cause errors when generating and can be canmodulator in the following way. celled by operating the , as explained in the following section, When integrating are biased so two phases are employed: in the rst phase, that and is integrated; in the second are biased so that and phase, is integrated. The net integrated differential charge is then (15) (16) (17) where the superscripts (1) and (2) refers to the voltages in the rst and second phase phase, respectively. is adjusted, as To trim the sensor at room temperature, explained in Section III-C: the collector current of or can be coarsely adjusted via of the current sources, while the th is driven by a digital modulator to provide a ne trim [8]. are loaded by the input capacitors of The bases of . Care must be taken to ensure stable operation of the the for any bias of the collector current. Taking loops around into consideration only one of them, the loop is comprised of , and . Miller compensation three cascaded stages, , with resistive cancellation of the positive zero is introduced , so that the cascade of and behaves like a around two-stage Miller compensated amplier. The gain-bandwidth can be approximated as product (18) where and are the transconductance and collector cur. To ensure enough phase margin for the loop, the rent of frequency of the poles associated with and must be , i.e., that for the largest . larger than the worst-case (a current-mirror loaded differential pair) is then biased (equal to 400 nA with a PTAT tail current derived from at room temperature), so that its associated pole, proportional to its transconductance, moves to higher frequencies for higher and consequently temperatures, i.e., the conditions at which are larger. The third pole due to the impedance and capacitance at the drain of is brought to high frequency by . The impedance of that adding the diode-connected bipolar node could have been lowered also by adding a diode-connected MOS transistor, but the use of a diode-connected bipolar is more and form a curadvantageous for two reasons. Firstly, tracks , so that rent mirror and the collector current of , and thus the third pole, are larger the transconductance of for a higher . Secondly, for a xed current consumption, a higher transconductance can be usually achieved by a BJT rather than with a MOS. For a xed bias current , this is true if

(19) where is the MOS subthreshold slope factor, and a MOS in weak inversion has been assumed, i.e., in the operation region with highest transconductance-to-current ratio. is typically between 1.2 and 1.6 ( 1.5 for the devices Since . used in this work) [24], a BJT is more efcient for D. Sigma-Delta ADC A rst-order modulator (Fig. 11) is used to sample the voltages produced by the bipolar core. The modulator implements the charge-balancing principle described in Section II, as can be understood from the example waveforms shown in Fig. 12. The modulators switched-capacitor integrator is reset at the beginning of each temperature conversion. The opamp is based on a two-stage Miller-compensated topology and achieves a minimum simulated gain of 93 dB (over process and temperature variations) with a PTAT bias current (3 A at room temperature). Correlated double sampling (CDS) is used to reduce its offset and 1/f noise [25]. During phase , the opamp is congured as a unity-gain buffer and the signal plus offset and icker noise are sampled on input capacitors pF. In the second phase , the offset and low frequency noise are cancelled and the charge on the input . Since capacitors is dumped on integrating capacitors the modulator must operate at 1.2 V, the voltage swing at the output of the integrator was scaled down by choosing . Furthermore, as shown in the timing diagram in Fig. 12, when , only one BJT is biased is integrated, instead and only one base-emitter voltage of previous work [8], [9]. Since a charge proporof the is integrated when as shown in (17), tional to the ratio between the charge integrated for and is equal to . The factor 2 results in an equivalent in the charge-balancing conversion, as mentioned factor , in Section III-B. However, this choice means that when a -dependent common-mode voltage will also be integrated. Imbalances in the fully differential structure of the integrator, such as mismatch in the parasitic capacitances to ground at the inverting and non-inverting input of the opamp, can result in a nite common-mode-to-differential-mode charge gain, leading to error in the output. To minimize the total integrated common-mode voltage, the sign of the input common-mode cycles, by setting voltage is alternated in successive either and in (period A in Fig. 12), or and in (period B). As shown in Fig. 12, a longer settling time is required when and one input of the modulator must switch between, say, is being integrated, than when one of the inputs 0 V, when and when is being must switch between, say, integrated. To minimize the conversion time, the length of each when the phase of the integrator are chosen equal either to or to when the input input switches between 0 and and . switches between

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Fig. 12. Timing diagram and waveforms of a fragment of the temperature conversion; periods when bs

= 1 are shown in gray (A and B).

Fig. 13. Chip microphotograph.

V. EXPERIMENTAL RESULTS The temperature sensor (Fig. 13) was fabricated in a baseline TSMC 65-nm CMOS process, and was packaged in a ceramic DIL package. As shown in Fig. 13, the active area measures 0.1 mm and it is dominated by the capacitors of s integrator. All transistors employed in the design the are thick-oxide high-threshold devices with a minimum drawn length of 0.28 m, in order to avoid any problem due to gate leakage, which may be signicant at high temperatures. In spite of the use of high-threshold device, the sensor can still operate from a 1.2-V supply, from which it draws 8.3 A at room temperature. The supply sensitivity is 1.2 C/V at room temperature, which demonstrates the low-voltage capability of the proposed NPN-based sensor. The off-chip digital back-end decimates the output of the modulator and compensates for the nonlinearity. , the modulators bitstream average is limited, With varying between 0.05 and 0.18 over the temperature range from 70 C to 125 C. To exploit this, a decimation lter was instead used instead of a traditional sinc lter, as this results

Fig. 14. Measured temperature error (with batch calibration.

63 limits) of 12 samples after

in less quantization error over this limited range. The digital nonlinear correction described in Section III-D has been applied off-line, using a sixth-order polynomial for the correction of residual nonlinearities. The conversion rate of the sensor is s, s) at which it 2.2 Sa/s (6000 bits, obtains a quantization-noise-limited resolution of 0.03 C. A set of devices was measured over the temperature range from 70 C to 125 C. After digital compensation for systematic nonlinearity, the inaccuracy (Fig. 14) was 0.5 C ( , 12 devices). This improved to 0.2 C ( , 16 devices) after trimming at 30 C (Fig. 15). A summary of the sensors performance and a comparison to the state-of-the-art for CMOS temperature sensors is reported in Table I. The sensors untrimmed accuracy is 10 times better than previous designs in deep-submicron CMOS and both its batch-calibrated and trimmed accuracy are comparable with sensors realized in larger-feature-size processes. Furthermore,

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TABLE I COMPARISON WITH PREVIOUSLY PUBLISHED CMOS TEMPERATURE SENSORS

The resolution is limited by quantization noise and hence it is not a statistical quantity. [2] E. Saneyoshi, K. Nose, M. Kajita, and M. Mizuno, A 1.1 V 35 m 35 m thermal sensor with supply voltage sensitivity of 2 C/10%Supply for thermal management on the SX-9 supercomputer, in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2008, pp. 152153. [3] D. Duarte, G. Geannopoulos, U. Mughal, K. Wong, and G. Taylor, Temperature sensor design in a high volume manufacturing 65 nm CMOS digital process, in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Sep. 2007, pp. 221224. [4] C. Poirier, R. McGowen, C. Bostak, and S. Naffziger, Power and temperature control on a 90 nm Itanium-family processor, in IEEE ISSCC Dig. Tech. Papers, Feb. 2005, pp. 304305. [5] F. Sebastiano, L. Breems, K. Makinwa, S. Drago, D. Leenaerts, and B. Nauta, A low-voltage mobility-based frequency reference for crystal-less ULP radios, IEEE J. Solid-State Circuits, vol. 44, no. 7, pp. 20022009, Jul. 2009. [6] M. Kashmiri, M. Pertijs, and K. Makinwa, A thermal-diffusivity-based frequency reference in standard CMOS with an absolute inaccuracy of 0.1% from 55 C to 125 C, in IEEE ISSCC Dig. Tech. Papers, Feb. 2010, pp. 7475, 75a. [7] D. Rufeux, F. Krummenacher, A. Pezous, and G. Spinola-Durante, Silicon resonator based 3.2 W real time clock with 10 ppm frequency accuracy, IEEE J. Solid-State Circuits, vol. 45, no. 1, pp. 224234, Jan. 2010. [8] M. Pertijs, K. Makinwa, and J. Huijsing, A CMOS smart temperature sensor with a 3 inaccuracy of 0.1 C from 55 C to 125 C, IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 28052815, Dec. 2005. [9] A. Aita, M. Pertijs, K. Makinwa, and J. Huijsing, A CMOS smart temperature sensor with a batch-calibrated inaccuracy of 0.25 C (3) from 70 C to 130 C, in IEEE ISSCC Dig. Tech. Papers, Feb. 2009, pp. 342343. [10] H. Lakdawala, Y. Li, A. Raychowdhury, G. Taylor, and K. Soumyanath, A 1.05 V 1.6 mW 0.45 C 3 -resolution 61-based temperature sensor with parasitic-resistance compensation in 32 nm CMOS, IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 36213630, Dec. 2009. [11] P. Chen, C.-C. Chen, Y.-H. Peng, K.-M. Wang, and Y.-S. Wang, A time-domain SAR smart temperature sensor with curvature compensation and a 3 inaccuracy of 0.4 C + 0.6 C over a 0 C to 90 C range, IEEE J. Solid-State Circuits, vol. 45, no. 3, pp. 600609, Mar. 2010. [12] F. Sebastiano, L. Breems, K. Makinwa, S. Drago, D. Leenaerts, and B. Nauta, A 1.2 V 10 W NPN-based temperature sensor in 65 nm CMOS with an inaccuracy of 0.2 C (3 ) from 70 C to 125 C, in IEEE ISSCC Dig. Tech. Papers, Feb. 2009, pp. 312313. [13] M. A. P. Pertijs and J. H. Huijsing, Precision Temperature Sensors in CMOS Technology. Dordrecht, The Netherlands: Springer, 2006. [14] K. Souri, M. Kashmiri, and K. Makinwa, A CMOS temperature sensor with an energy-efcient zoom ADC and an inaccuracy of 0.25 C (3 ) from 40 C to 125 C, in IEEE ISSCC Dig. Tech. Papers, Feb. 2009, pp. 310311. [15] P. Krummenacher and H. Oguey, Smart temperature sensor in CMOS technology, Sensors and Actuators A: Physical, vol. 22, no. 13, pp. 636638, Jun. 1989. [16] J. P. Kim, W. Yang, and H.-Y. Tan, A low-power 256-Mb SDRAM with an on-chip thermometer and biased reference line sensing scheme, IEEE J. Solid-State Circuits, vol. 38, no. 2, pp. 329337, Feb. 2003.

Fig. 15. Measured temperature error (with trimming at 30 C.

63 limits) of 16 samples after

it is capable of sensing much lower temperatures, while operating from a 1.2-V supply. VI. CONCLUSIONS This paper describes a temperature sensor realized in a 65-nm CMOS process with a batch-calibrated inaccuracy of 0.5 C and a trimmed inaccuracy of 0.2 C from 70 C to 125 C. This represents a 10-fold improvement in accuracy compared to previous deep-submicron temperature sensors, and is comparable with that of state-of-the-art sensors implemented in larger-feature-size processes. These advances are enabled by the use of vertical NPN transistors as sensing elements, the use of precision circuit techniques, such as dynamic element matching and dynamic offset compensation, and a single roomtemperature trim. In particular, the use of NPNs, rather than the PNPs of previous work, enables low-temperature 70 C sensing while operating from a low supply voltage (1.2 V). Such NPNs can be made without process modications by exploiting the availability of deep N-well diffusions in most deep-submicron CMOS processes. This work demonstrates that an accurate sensor can still be designed in advanced deep-submicron CMOS process. REFERENCES
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[17] K. Szajda, C. Sodini, and H. Bowman, A low noise, high resolution silicon temperature sensor, IEEE J. Solid-State Circuits, vol. 31, no. 9, pp. 13081313, Sep. 1996. [18] J. Creemer, F. Fruett, G. Meijer, and P. French, The piezojunction effect in silicon sensors and circuits and its relation to piezoresistance, IEEE Sensors J., vol. 1, no. 2, pp. 98108, Aug. 2001. [19] G. Meijer, R. V. Gelder, V. Nooder, J. V. Drecht, and H. Kerkvliet, A three-terminal intergrated temperature transducer with microcomputer interfacing, Sensors and Actuators, vol. 18, no. 2, pp. 195206, Jun. 1989. [20] G. Meijer, G. Wang, and F. Fruett, Temperature sensors and voltage references implemented in CMOS technology, IEEE Sensors J., vol. 1, no. 3, pp. 225234, Oct. 2001. [21] G. C. Meijer, Thermal sensors based on transistors, Sensors and Actuators, vol. 10, no. 12, pp. 103125, Sep. 1986. [22] F. You, H. Embabi, J. Duque-Carrillo, and E. Sanchez-Sinencio, An improved tail current source for low voltage applications, IEEE J. Solid-State Circuits, vol. 32, no. 8, pp. 11731180, Aug. 1997. [23] R. J. Baker, H. W. Li, and D. E. Boyce, CMOS Circuit Design, Layout, and Simulations. New York: IEEE, 1997, p. 637. [24] A. Pouydebasque, C. Charbuillet, R. Gwoziecki, and T. Skotnicki, Renement of the subthreshold slope modeling for advanced bulk CMOS devices, IEEE Trans. Electron Devices, vol. 54, no. 10, pp. 27232729, Oct. 2007. [25] C. Enz and G. Temes, Circuit techniques for reducing the effects of op-amp imperfections: Autozeroing, correlated double sampling, and chopper stabilization, Proc. IEEE, vol. 84, no. 11, pp. 15841614, Nov. 1996.

Ko A. A. Makinwa (M97SM05) received the B.Sc. and M.Sc. degrees from Obafemi Awolowo University, Nigeria, in 1985 and 1988, respectively. In 1989, he received the M.E.E. degree from the Philips International Institute, The Netherlands, and in 2004, the Ph.D. degree from Delft University of Technology, The Netherlands. From 1989 to 1999, he was a Research Scientist with Philips Research Laboratories, Eindhoven, The Netherlands, where he worked on interactive displays and on front-ends for optical and magnetic recording systems. In 1999, he joined Delft University of Technology, where he is now an Antoni van Leuwenhoek Professor in the Faculty of Electrical Engineering, Computer Science and Mathematics. His main research interests are in the design of precision analog circuitry, sigma-delta modulators, smart sensors and sensor interfaces. This has resulted in one book, 14 patents, and over 110 technical papers. Dr. Makinwa is on the program committees of several international conferences, including the European Solid-State Circuits Conference (ESSCIRC) and the IEEE International Solid-State Circuits Conference (ISSCC). At such conferences, he has presented several invited talks and tutorials. He has also served as a guest editor of the IEEE JOURNAL OF SOLID-STATE CIRCUITS (JSSC). He is a corecipient of several best paper awards, including one from the JSSC, one from the ESSCIRC, and three from the ISSCC. In 2005, he received a Veni Award from the Netherlands Organization for Scientic Research and the Simon Stevin Gezel Award from the Dutch Technology Foundation. He is a Distinguished Lecturer of the IEEE Solid-State Circuits Society and a Fellow of the Young Academy of the Royal Netherlands Academy of Arts and Sciences.

Fabio Sebastiano (S10) was born in Teramo, Italy, in 1981. He received the B.Sc. (cum laude) and M.Sc. (cum laude) degrees in electrical engineering from the University of Pisa, Italy, in 2003 and 2005, respectively. In 2006, he received the Diploma di Licenza from Scuola Superiore SantAnna, Pisa, Italy. In 2006, he joined NXP Semiconductors Research in Eindhoven, The Netherlands, working toward the Ph.D. degree in collaboration with Delft University of Technology. His main research interests are ultra-low-power radios for wireless sensor networks, fully integrated crystal-less frequency references and sensor interfaces. Mr. Sebastiano is co-recipient of the 2008 ISCAS Best Student Paper Award.

Salvatore Drago (S10) received the M.Sc. degree (cum laude) in electrical engineering from the University of Catania, Italy, in 2003. From 2004 to 2006 he was with Synapto s.r.l. in Catania, Italy, where he worked on EM modelling of embedded passives and interconnections in PCBs. In 2006 he joined NXP Semiconductors Research in Eindhoven, The Netherlands as a Marie Curie Fellow, where he is working toward the Ph.D. degree in collaboration with the University of Twente, The Netherlands. His research interests include ultra-low-power radio and RF integrated circuit design. Mr. Drago was a corecipient of the 2008 ISCAS Best Student Paper Award.

Lucien J. Breems (S97M00SM07) received the M.Sc. degree (cum laude) and the Ph.D. degree in electrical engineering from the Delft University of Technology, The Netherlands, in 1996 and 2001, respectively. From 2000 to 2007 he was with Philips Research, Eindhoven, The Netherlands, and in 2007 he joined NXP Semiconductors where he currently leads a research team working on sigma-delta A/D converters. Since 2008 he has been a Lecturer at the Delft University of Technology on the topic of sigma-delta modulation. He published a book, Continuous-Time Sigma-Delta Modulation for A/D Conversion in Radio Receivers (Kluwer, 2001). His research interests are in the eld of mixed-signal circuit design. Dr. Breems is a member of the technical program committees of the International Solid-State Circuits Conference (ISSCC) and the Symposium on VLSI Circuits, and was a technical program committee member of the IEEE International Symposium on Low Power Electronics and Design from 2004 to 2007. Since 2009 he has served as Associate Editor of the IEEE JOURNAL OF SOLIDSTATE CIRCUITS, and he has served as Guest Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II (20082009). He is a recipient of the ISSCC 2001 Van Vessem Outstanding Paper Award.

Domine M. W. Leenaerts (M94SM96F2005) received the Ph.D. degree in electrical engineering from the Eindhoven University of Technology, Eindhoven, The Netherlands, in 1992. From 1992 to 1999, he was with Eindhoven University of Technology as an Associate Professor with the Micro-electronic Circuit Design group. In 1995, he was a Visiting Scholar with the Department of Electrical Engineering and Computer Science, University of California, Berkeley. In 1997, he was an Invited Professor at Ecole Polytechnique Federale de Lausanne, Switzerland. From 1999 to 2006 he was a Principal Scientist with Philips Research Laboratories, Eindhoven, where he was involved in RF integrated transceiver design. In 2006, he moved to NXP Semiconductors, Research as a Senior Principal Scientist. He has published over 150 papers in scientic and technical journals and conference proceedings, and holds several US patents. He has coauthored several books, including Circuit Design for RF Transceivers (Kluwer, 2001). Dr. Leenaerts served as IEEE Distinguished Lecturer in 20012003 and served as an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I (20022004), and since 2007 has been am Associate Editor of the IEEE JOURNAL OF SOLID-STATE CIRCUITS. During 20052008 he was the IEEE Circuits and Systems Society Member representative in the IEEE Solid-State Circuits Society Administrative Committee, on which he is now an elected member. He is a Distinguished Lecturer of the IEEE Solid-State Circuits Society. He serves currently on the Technical Program Committee of the European Solid-State Circuits Conference, the IEEE Radio Frequency Integrated Circuits (RFIC), and IEEE International Solid-State Circuits Conference (ISSCC).

SEBASTIANO et al.: A 1.2-V 10- W NPN-BASED TEMPERATURE SENSOR IN 65-nm CMOS

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Bram Nauta (M91-SM03-F07) was born in Hengelo, The Netherlands, in 1964. In 1987 he received the M.Sc. degree (cum laude) in electrical engineering from the University of Twente, Enschede, The Netherlands. In 1991 he received the Ph.D. degree from the same university on the subject of analog CMOS lters for very high frequencies. In 1991 he joined the Mixed-Signal Circuits and Systems Department of Philips Research, Eindhoven, The Netherlands, where he worked on high-speed AD converters and analog key modules. In 1998 he returned to the University of Twente, as a full Professor heading the IC Design group, which is part of the CTIT Research Institute. His current research interest is high-speed analog CMOS circuits. He is also a

part-time consultant in industry. In 2001 he co-founded Chip Design Works. His Ph.D. thesis was published as a book: Analog CMOS Filters for Very High Frequencies (Springer, 1993) and he received the Shell Study Tour Award for his Ph.D. work. From 1997 until 1999 he served as Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II, ANALOG AND DIGITAL SIGNAL PROCESSING. After this, he served as Guest Editor, Associate Editor (20012006), and from 2007 to 2010 as Editor-in-Chief of the IEEE JOURNAL OF SOLID-STATE CIRCUITS. He is also a member of the technical program committees of the IEEE International Solid-State Circuits Conference (ISSCC), the European Solid State Circuit Conference (ESSCIRC), and the Symposium on VLSI Circuits. He was a corecipient of the ISSCC 2002 and 2009 Van Vessem Outstanding Paper Award. He has been a Distinguished Lecturer of the IEEE and an elected member of the IEEE-SSCS AdCom, and is an IEEE Fellow.

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