IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-15, NO.

3, JUNE 1980

331

Analysis and Characterization of the Depletion-Mode IGFET

YOUSSEF A. ELMANSY, MEMBER,lEEE

A bstractUsing simple charge-voltage relationships, a four-terminal model is developed for the depletion-mode IGFET. Various conditions which can coexist at the surface, such as accumulation, depletion, and inversion, are taken into account. The implanted channel is approximal.ed by a box profile. The b~ic model elements, namely, the soirrcedraih transport current and the various charging currents, are explicitly given in terms of known processing data and implanted channel pararm etelrs. Deviee threshold voltage, drain saturation voltage, and conditions for surface inversion are explicitly given as a function of these parameters.

I. INTRODUCTION

EPI_,ETION-mode IGFETs are normally fabricated by introducing impurity ions of the opposite type to the starting substrate to form a shallow layer underneath the gate of the device. This layer can be achieved by ion implantation, diffusion, epitaxial growth, or otherwise. Ion implantation is the most commonly used method because exact control of the number of impurity atoms and their distribution is essential for reproducible device characteristics. To produce afi n-channel depletion-mode device in a standard NMOS process, n-t ype impurities are selectively introduced into the p-type stiu-ting material. If an n-doped polysilicon gate is used, the re:wdting device will have a negative threshold voltage and is capable of conduction with zero voltage between the gate afid the source. The use of these devices was originally Iimited to load elements in enhancement-depletion logic in order to decrease th,e power-delay product [1], [2]. In such a case, the source and the gate are tied together and the device approximates a Recently [3], [4], depletion-mode devices current source. hive become widely used in more general configurations to utilize their superior qualities such as high mobility and low surface generated 1/f noise. Also, the same device with appropriate implant conditions is the basic element in bulk-channel charge-coupled device technology. To account for these various modes of operation, a general model which is explicitly related to known processing information, device geometry, and properly handles the nonlinear dc and charging current components is essential. Initially, the current behavior of the device was described by an enhancement surface device model with a threshold voltage shifted as a function of the number of impurities implanted in the channel. Such modeling is adequate for lightly doped
Mmuscript received June 20, 1979; revised December 12, 1979. The author was with Bell-Northern Research, Ottawa, Ont., Canada. He is now with the Intel Corporation, Aloha, OR 97005.

shallow implanted channels where the devices are used as load elements. More accurate analysis to account for the finite thickness of the implanted channel has been performed by Edwards and Marr [5]. A simpler version of the analysis was carried out by Huang and Taylor [6] where the effects of the ftiite channel thickness are represented by an average semiconductor capacitance in series with the gate oxide capacitance. For a heavily implanted deep channel, the device cannot be turned off by applying a gate voltage due to the formation of a surface inversion layer which causes the gate to lose control over the channel. A device operating in this mode was described by Verbracken et al. [7] where the substrate is used as the input signal terminal to utilize the high gain obtainable for this configuration. More recently, accurate analysis has been presented by Haken [8] wherein siniple measurements performed on an IGFEr to determine the implanted layer properties relevant to buried-channel charge. coupled device applications were used. In all these analyses, charging currents in the device were mostly ignored atid only experimental characterization and semiquantitative description of device capacitances were attempted [9], [10]. The present work therefore has the following objectives. 1) Development of a physical model that uses basic process. ing information and covers all regions of device operation except the subthreshold region. 2) Modeling the charging currents in the device in a manner that can be directly implemented in a circuit analysis program. 3) Using model parameters that are easily and systematically obtained from a simple and small number of measurements of device terminal parameters. In Section H, the dc and charging current elements of the model are derived from basic charge densities in the device. This results in all the elements required for an equivalent circuit representation. Device terminal characteristics that are useful in defining the implanted region parameters are discussed in Section III. Finally, some of the experimental results and discussion of such results are given in Section IV. II. ANALYSIS

A. ChargeDensities
Two cross sections of an n-channel device in the direction of channel current flow and in the lateral direction are shown schematically in Fig. 1 with basi,c coordinate and voltage definitions. The boundmies of the two space-charge regions which modulate the conducting channel are illustrated. The depletion width of the p-n junction formed by the channel and the substrate is controlled by the channel voltage. The conditions $00.75 @ 1980 IEEE

0018-9200/80/0600-0331

332

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-15, NO. 3, JUNE 1980

(a)

o Ss i

hp-:ub,t~---j
&
Field G * Oxide )

4
In

-iaN

(b)
.x

Fig. 1. Device cross sections showing coordinates, device dimensions, and voltage definitions (a) in the direction of current flow and (b) in the lateral direction.

Fig. 2. An elemental section of the device at a position along the channel where the surface is depleted. Also shown is the charge and potential distribution in the direction normal to the surface.

in the surface space-charge region are due to the combined effects of the gate and channel voltages. These conditions range from accumulation of electrons at the surface for a positive gate voltage to the existence of a p-type surface inversion layer at a large negative gate voltage. Fig. 2 $hows an ele. mental section of the device at a position y, together with the charge and potential distribution in the direction perpendicular to the surface. 1 The implanted layer is approximated by a rectangle of height JV and width Xi. Later, we discuss a Using the gradual method for defining these parameters. channel approximation (GCA), we can write for the charge density Qm in the channel
Qin=-Qi+Qj+Q.

e is the permittivity voltage

of silicon,

Vm = V+ @B, V is the channel source and drain, and @B = @fn +

at any point between

@fp is the p-n junction equilibrium barrier height. V t~es the values Vs and ~d, while VW takes the values ~m~ and ~~d at the source Q. takes between
Q,=

and drain terminals, the following values

respectively. depending

The component on the relationship potentials:

the gate and channel electrostatic

- h) %g>
VTI ~

Co(hg

~m
Vmg G Vm

accumulation depletion inversion 1 (4)

= qNX~ = qNX~m

V&< VT~

(1)

wherez C. is the gate oxide capacitance per unit area,

where the various charge density (per unit surface area) components are defined as follows. The implanted layer charge density is given by Qi = qNXi. The p-n junction space-charge density
Qj = @xj = KE % Qj is given by

Vmg = Vg- vf~+ o~

where Vg is the applied gate voltage
Vfb = @fg+@fn &

(2)

co

(3)

and VTI is the threshold for surface inversion given as

where2

K~ = ~W,
NE. NAN NA +N
1The distributions shown correspond to a position where the surface is not inverted. 2AU voltages are with respect to the neutral substrate region. Vm is the electrostatic potential of the channel with respect to neutral substrate, while V is the corresponding voltage of the channel defined consistently with the externally applied voltages V& Vd, and V . Such a definition makes the gradients of both Vm and V equal, t i erefore causing the diffusion components of channel current to be zero.

where

The surface space-charge region thickness is given by X$= K~(<Vm

- V&+ Vc - w)/qN

(5a)

where Vc = qNe/(2C~ ). When inversion occurs at the surface, the space-charge region X, attains a maximum value X& given by

EL-MANSY

: DEPLETION-MODE

IGFET

333

It is implied

here that once an inversion layer is formed at the to the p-substrate and therefore has as the substrate.3 is valid at any point along the Whether all the conlayer, As the

Implant Implant Substrate

Dose = 1,9 x 1012 Depth

cm-z

x (M

surface, it is connected the same potential

Xl = 0.63 Micron = 1.9 x 1015 cm-3

4
07 t

Dopfng

The set of equations (l)-(4) ditions mentione<i

surface between the source and the drain. in (4) actually depend on the number the thickness gate voltage face region encountered. is reduced of impurities below

occur in a given device will in the implanted

of that layer, and the channel voltage. the flat beco]mes depleted

band value, the suris

.=oi2F=?zl=}(xi-xJ

and one of two conditions

1) The value of Qm in (1) becomes zero before the threshold for inversion is reached, and in this case the channel or punches through and is cutoff 2) Inversion

occurs at the surface first and in this case the 3.

~
-12 -10 -8 -6 -4 -2 246

channel does not punch through. To illustrate these points, the surface space-charge region thickness X~ and the lower channel boundary depth (Xi - Xi) are plotted in Fig. 3 for a specified device. For channel voltages below 6 V, inversion conditiQps occur first, while for channel voltages greater than ?r equal to 6 V, the channel punches throu@,, The channel voltage V can be any vaIue along the channel including the source and drain boundaries. The above relations (l)-(5) can therefore be used at these
o

Vg(v)
Fig. Variation of surface and p-n junction space-charge region widths.

A value Vp = O is used.

Oxnh
Gate

hmlmted Lw6r Vmd

Subs,,.te

boundaries to def@e basic device parameters. Specifically, we now use the mobile charge density along the channel together with the source and drain boundary conditions to evaluate various device terminal parameters representative of performance characte~stics and relevant to model formulation. B. Channel Current and Conductance Neglecting be written Id= diffusion current, the channel (drain) current can as (refer to Fig. 1) (6)
(cl (bl

cl

(d

VW -

Vnw

dVm -@#Qm - dy between source and drain v~d Qm dVm J vln~

/ Vnw

integrating

Vlnf I

rd=~

-/lw

(7)

[d) 0 .

where W and L are the width respectively. Substituting

and the length

of the device,
Vnw

for Qm from (1) into (7), we obtain

(.I
.

DraNIBoundary

where KE = fifi

and F5 is the contribution

of the sur-

Fig. 4. Potential

distributions

in

the gate,

oxide,

and semiconductor is

face space-charge region to the current defined as Vmd Fs = Jv Q, dVm .

ms

regions of the device at source and drain boundaries. In all the plots,
source and drain voltages are kept constant, while the gate voltage changed from a large negative value (a) to a large positive value (e).

(9) function for the different situations ranging from inversion to accumulation (all along the surface), with reference to the conditions of(4). 1) Inversion Along the Entire Surface [Fig. 4(a)J: This condition exists for gate voltages satisfying the inequa$t y Vmg <
(Kiv/CO) ~.

The function

F5 takes different

values depending

on the con-

ditions existing at the surface; see Fig. 4. We now evaluate this

3 me inver$ion ~yer is connected to the

substrate via the field reidon

characteristics up to

implant which high frequencies.

results

in frequency-independent

ln this case, Q, compri8es the positive ions

334

IEEE

JOURNAL

OF SOLID-STATE

CIRCUITS,

VOL.

sc!-15,

NO.

3, JUNE

1980

existing within -KN fi

the surface depletion

layer and is given by Q~ =

and Fs is Fs = Co

while - V;j?). (9a) (

F~ = +KN(V;~

V;d 2

V;s - v~g vmd - co ~ - vmg vm, . )( )

(%)

2) Inversion at Source, Depletion at Drain [Fig. 4(b)J: This condition exists for gate voltages in the range

-(a= <v--(%=
The surface in this case is inverted at the source end and up to a point V1~. depleted. Q.=KNm =KN[/~,g) + VC - ~] along the surface where the potential Beyond Therefore, Q$ is given by is given by Vm = this pc~int and up to the drain, the surface is

It should be noted that for terms arising from accumulation of electrons at the surface, i.e., those terms in (9d) and (9e) with a premultiplier Co, a surface mobility value should be used in place of the bulk mobility. As will be shown later in the results, the surface mobility required to fit the measured region, some For values is about one-half the bulk value. Depending on the parameters of the implanted outlined of the conditions above may not be encountered.

example, for shallow implants, covered by conditions

inversion may not occur at the

surface, and in this case, the whole range of device currents is

vm~ < Vm < v[~

VID < Vm < Vma

3), 4), and 5) above. Such would be the isolated from the

case also if the surface region is completely substrate. Differentiating

where VID = ( Co VmiT/KN)2 is the potential of the point separating the invertedl section from the depleted section and

the drain current with respect to the terminal correspondgate These are defined as drain conducconductance g~ = 3rd/3V,, and substrate transconduc-

voltages results in four small-signal conductance ing to the four terminals. tance tance
C.

gd = 3rd/3V&
gmb = -(gal + &

source
+%).

transconductance

gm = 3rd/3Vg,

Charging Current and Capacitance Components

. ~ KN [V~# - V~~ + (Vmd - Vmg + Vc)3/2 - (fiD 3) Depletion - V&+ Along Vc)3/2 - w(V& the Entire fiD)] . (9b)

To formulate the charging current model [11] of the device, we need only consider the charge components that give rise to gate and substrate charging currents. charge neutrality of the device. This is due to the overall

Surface [Fig.

4(c)]: ~/Co)<

In this

case, the gate potential is in the range -(KN & < vm~. The charge Q~ is
Qs =

The charge density on the gate at any point along the channel is given by Qg = -Q, CO(J%g - J%)

KN(~ng
FS is

VC- m)
=
-Q,. -q~xs

Vmg> Vm

accumulation

and the function

FS = ~ KN [(Vmd - Vmg + Vc)3/2 - (Vm, - Vmg + Vc)3/2

- % (Vmd - VmS)]. at Source, Depletion (9C) at Drain [Fig. 4(d)l: is in the range Vm~ < = co Vg

VT1 < Vmg < Pm depletion

(lo) 1

Vmg< v~~
contributing

inversion

4) Accumulation This condition

and the charge density current is Qb = -Qj

to a substrate charging

exists for a gate potential,

V~g < Vmd, and Q. is given by Q,= CO(Vm - Vmg) =KN(~Wg The function Fs=Co ~ + Vc - &)

Vmg> Vm
VT1 < Vmg < Vm
Q.Qg

accumulation depletion inversion

1

V*. < Vm < Vmg

Vmg < Vm < Vmd.

=
-Qj

-Qj

vmg<vTZ

Fs is then given by

(11) Using (6), the total gate and substrate charges are given by

V&

- Co ~

v;.
- VmSVmg )

QG=W

+ # KN

[( md

- Vmg + - Vmg)].

Vc)siz - Vy
(9d) Surface /Fig. 4(e)J: The and

L
Qg @ = ~

v~d Vmr J Qg Qm dvm

fi(vmd

5) Accumulation

Along

the Entire

=*FG Id

-/.lw2

(12)

gate potential for this condition The charge Q. is then

is always greater than Vmd.

QB.

Q.= co(vm -

~mg)

-j-w -/.fw md .. Qz)Qrn ~Jk = Id Id ~m~

.FB.

(13)

EL-MANSY:

DEPLETION-MODE

IGFET

335

?G
Cgs

s
. \

ypf?$F .,\
\

\
(a) (b) -$@~

L3
Fig. 5. Equivalent circuit of the device showing the transport current Id and the various capacitance components.

TIS

The gate and substrate written as

charging current

components

can be

[ v.,-

..

dQG ig=~=Cg~

d(Vg - V.) dt

+ Cgd

d( Vg- Vd) dt

dVg + C@ dt
(14)

(c)

Fig. 6. Behavior of device threshold voltages as a function of source-

and

substrate voltage. (a) Threshold for inversion. (b) Cutoff threshold. (c) Combined plot.

d(- ~) dQ~ =Cbs~+&~ lb dt

where

d(- Vd)

d(-vg) + Cbg dt

~15) 1) Threshold Voltages: As discussed earlier, there exist two parameters; the gate voltage required to completely turn the device off is denoted as VT and the threshold for surface inversion as VTI~. The threshold voltage VT is obtained by equating Qw at the source end to zero to obta~ (the source is taken as the reference terminal)
vT= v@-@%+

(16a) where the subscripts k and j refer to the device terminals b, d, as Fkj = bFk/% s, and g and the function Fkj is defined The six capacitance components provide all the information required to implement the charging currents in the device in a circuit analysis program. The configuration used is illustrated in Fig. 5 where the two capacitive current sources il and iz represent the asymmetry of the gate and substrate regions of the device. These two sources are given by [11 ] (16b) The division of the sources between source and drain terminals is carried out in proportion to a combination of the other four components in a manner similar to that for enhancement devices discussed in detail in [11 ]. To illustrate the simplicity of the approach, an example is given in the Appendix to derive all the model components for one of the regions of operation, namely, inversion along the surface. Other regions of operation can be treated in a similar manner to complete the model. Such a model has been derived and implemented in a circuit simulator. 111. DEVICE THRESHOLD AND SATURATION VOLTAGES Insight is provided into the dependence of the device characteristics upon the various processing parameters (e g., implant dose, implant depth, oxide thickness) by considering the influence of these parameters on the gate threshold voltage and the saturation voltage.

NE

@imsa.
cl

(17)

The threshold for inversion at the source is (18) where Cl = Co/(l + CO/C~), CZ = CO/(1 +
E/Xi.

(CO/2

Cj)),

ml

ct

Of course, the relevant threshold is used depending on the implanted layer parameters and bias conditions. If VT is plotted as a function of ~, a straight line is obtained as shown in Fig. 6(a). The slope and intercept of such a line provide the information on the implanted layer parameters and surface conditions (flat band voltage). The slope of the plot is a function of NE and Cl and both depend on the implanted region thickness Xj. Thus, knowledge of the starting material doping N~ and the oxide thickness XO enables the extraction of Xi. The intercept of such a line gives the flat band voltage (since Qi and G are known). For hew doses with a large Xi) the device cannot be turned off without the use of source-substrate voltage. In such a case, the slope of the VTZScume at Vm. = O gives the doping N, and the intercept is simply (Vfb); see Fig. 6(b). 4 In general, for heavy implanted
4 lf instead the substrate k taken as a reference, then a Plot of the 12 threshold for inversion ( VTZS+ Vs) versus ( Vs+ @JB) would be a straight line.

336

IEEE JOURNAL OF SOLID-STATE CIRCUITS,

VOL.

SC-15,

NO. 3, JUNE

1980

devices, the two thresholds VT and VTIs are obtainable depending on the range of applied Vm~. In this case, shown in Fig. 6(c), enough information can be obtained to extract the dose Qi and the substrate doping IV. As was mentioned earlier, the finite thickness of the implant changes the threshold equation in two ways. First, the substrate body coefficient is increased due to the smaller capacitance Cl as compared to C. (note that AJE is reduced from NA, but the net result is an increase of the term @~). Second, the threshold is shifted by an amount Qi/C2 which for a finite Xi is larger than Qi/CO. This could be seen more clearly by rewriting
&=&

-20.5

- -18

V*= 6V

c,

c.

()
~+g

2Ci

-14

-12

-10

-8 vgv~

-6 (v)

-4

-2

02

This shows that an implant thickness of about three times the oxide thickness would produce a 50 percent error if the simple Qi/CO voltage shift is used instead of the exact value given above. Two limiting cases of the threshold equation are of interest due to their simplicity and their practical significance. a) Very shallow implants: Xi ~ O, N ~ CO. In this case, Ci+~and Cl= Cz=CO. Thus, VT becomes (19) which is the standard enhancement device threshold shifted by the implant contribution (- Qi/CO). Note that in this case Vfb should be replaced by (V~b + +B) where V~b is the flat band voltage of the enhancement device, and OB would correspond to the usual 2@f term in the enhancement device threshold expression. b) Intrinsic substrates, N_ + O. For intrinsic substrates, the VT expression reduces to

Fig. 7. Drain saturation voltage as a function of gate and source voltages. Device parameters used are the same as in Fig. 3. If the drain end is inverted,
KNc+KEa=Qi

then the alternate

expression

(22)

is used instead. In this case, the gate is screened from the channel by the inversion layer and Vmp becomes independent of the gate voltage. A typical behavior of vd=t as a function of Vg and V$ is shown in Fig. 7 with the relevant process information as given in Fig, 3. In many situations, the linear part in the Vds,t curve can be expressed as

J&atVg- Vp =

(23)

This becomes an exact relationship for the case of an intrinsic substrate and starts deviating from linearity as the substrate doping increases. IV. RESULTS AND DISCUSSION

Measurements were performed on devices with a wide range of implant conditions. Results from two representative de(20) vices are presented. The first has a light shallow implant which l+%. z is typical of what can be obtained from an E/D NMOS process. This relation is useful for lightly doped substrates (> 100 ~ The second uses a heavier implant dose, thereby covering the cm). It still shows that the effect of Qi on VT should be various regions of operation from inversion to accumulation accounted for properly. at the surface. 2) Device Saturation Voltage: This is defined as the drain 1) Experimental Results: Results of comparing the drain voltage at which the drain current reaches its maximum value current-gate voltage characteristics of the device with shallow for a fixed gate voltage. For the one-dimensional treatment implant to model prediction are illustrated in Fig. 8. AS with no velocity saturation effects, this is equivalent to setting shown in the figure, for gate voltages higher than the source Qn = O at the drain end of the channel. Using the expression voltage, the surface is accumulated and a reasonable matching of (1) for Qm and replacing Vn by V&, we obtain between model and experiment is achieved only by using a surface mobility value lower than the bulk channel value. In K~[~(VmP - V.g) + Vc - ~] +KE== Qi (21) this particular case, a surface mobility of about 50 percent of where the drain saturation voltage is the bulk value is required. The implanted region parameters were obtained following the procedure outlined in Section Vd sat = Vnp - @B III. Even though this device is only 8 ~ long, it has exhibited very little evidence of short channel effects. which can be solved for Vmp as a function of Vng. This produces an approximately linear relationship. Such a relation is A set of dc and small-signal characteristics of the heavily valid as long as the surface region at the drain is depleted. If implanted device is shown in Fig. 9. The parameters for this device are as given in Fig. 3. In Fig. 9(a), the drain current as the region is accumulated, the device cannot be pinched off.

v~=vf+ ()

EL-MANSY: DEPLETION-MODE IGFET

337

2.4 -

I y=

I 100

I ,

2.0 L~

1.6 z L
_= 1.2 _

Dose = 5.5x 1011 cm2 Xl = 0.23 micron NA =4x .,.,,

..-_. Exp.

1014 C~3

0.8 _ 0.4

P , I 0.6 I

3.6

3.0

2.4

1.8 1.2

0.6

Vg v~ (v)
Fig. 8. The drain current-voltage characteristics of a lightly implanted device covering the depletion and accumulation regions. The need for
using a surface mobility is illustrated,

ld (/M)
se Model
q EXP.

V$ = Ov
9
q

q *

**

Model eExP,

48

vdv~=lov

v~v~=5v

Iv

1 40

---t\

V$= Ov

-16

-12

-8

-4

4
Vd

8 (V)

12

16

*:
-16 -14 -12 -10 -8 -6 -4 -2 0

Vg V$(v)
(a)

Vgv$
(b)
Model
q

w)

Cg (Pf) 12-

q 

Model
q EXP,

A
y

36
q

qEXP.

430 ~

10-

v~v~=5v - 24 Z $ x - 18 E m
q

8- -

- 12 4V - 6 t. t
-16

~ . .

(b

2.T

1 -14 -12 -10 -8 -6 -4 -2

, 0

~
-12 -9 -6 12

Vg-v, (v)
(c)

Vg (v)

(d) Fig. 9. Device characteristics for a heavily implanted device. Parameters of the implanted region are given in Fig. 3. (a) Drain current Id. (b) Substrate transconductance gmb. (c) Gate transconductance gm. (d) Gate capacitance Cg

338

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-15, NO. 3, JUNE 1980 I I

I I I I I I
Dose = 5X 1071 a 1,000 t G. D Vad =03/! = 15V

of both gate and drain voltages is illustrated. As can be seen, the device cannot be turned off by applying a gate voltage for small values of source to substrate voltages (up to 6 V). Thus, a plot of the type shown in Fig. 6(c) would characterize the parameter VTI~ up to a source voltage of 6 V than the parameter VT for higher VJ values. The role played by the surface inversion layer in screening the channel from the gate or alternatively making the substrate terminal more effective in modulating the channel is illustrated in Fig. 9(b) and (c). The behavior of the substrate transconductance g~b under various conditions depends strongly on whether an inversion layer exists at the surface and whether the device is operating in saturation. The following points can be made regarding the behavior of gmb [refer to Fig. 9(b)]. a) If the surface is depleted or accumulated, then g~b is independent of Vg since the signal applied to the substrate terminal does not affect the surface space-charge region. b) As the gate voltage is decreased to cause inversion at the source end, the channel is now modulated from both sides and gmb starts to increase. Further decrease of gate voltage causes the inversion layer to propagate towards the drain, thereby increasing g~b. This continues until the whole length of the channel is inverted, at which point g~b reaches a maximum value. c) If the drain end is pinched off, the voltage at the drain end of the channel ( VmP) becomes a function of Vg and thus reduces as Vg is decreased (see Fig. 7). This results in a reduction of ~~b (e.g., the two curves corresponding to ~ =4,6 V) until the source end inverts ( V~= 4 V) where g~b rises agtin or the device is cut off (~ = 6 V). Similar points can be made regarding the behavior of the gate transconductance gm shown in Fig. 9(c). The difference here is that the inversion layer plays an opposite role, i.e., once it starts to form, it screens the channel from the signal on the gate and results in a sharp drop in gm. In Fig. 9(d), the total gate capacitance is shown as a function of gate-substrate voltage. This figure illustrates the various modes of operation for the device as the gate voltage is changed from a large negative voltage to a large positive voltage. Since the source and drain voltages are equal, the conditions existing at the surface are uniform from the source to the drain. At a large negative gate voltage, the implanted region is fully depleted all the way between the source and the drain, and the surface conditions are adequate for the creation of an inversion layer. Thus, the total gate capacitance is equal to the gate-to-substrate component which is the oxide capacitance. As the gate voltage increases, the inversion layer disappears and the gate-to-substrate capacitance is now the series combination of oxide capacitance, implanted layer capacitance, and p-n junction (formed by the implanted region and the substrate) capacitance. Further increase in the gate voltage causes the channel to start forming, which gives rise to the sudden increase in the capacitance due to the two capacitance components C@ and Cgd. The channel starts widening as the gate voltage increases and the surface space-charge region thickness reduces, resulting in a gradual increase in Cgs and Cgd. Finally, the surface region thickness becomes zero and

a function

0,800

1+
cgd
+B

0,800 1

c~
)i, 1

( b s

0,400

1
0,200

%b o r 2 4 6 8 10 12 14 16

(a)
1,200 I I I I I

Dow 1,000 ;e % xl v~~

= 2X 1012 =0611 = I!!v

0,800

0,600

0,400

G 0,200

0 0 2 & 6 8 10 12 14 ?6

? ,200 I

1,000>

%,

0,800 c1

C9S 0,EL70

0,400

0.200

Cb,

ox 0

I
2

I 4

I 6

I 8

I 10

d 12

1 ?4 ?6

(c) Fig. 10. A plot of capacitance components contributed by load device at the output node of an inverter as a function of the voltage at that node (a) for a lightly implanted device, (b) for a heavily implanted device, and (c) for an enhancement device.

EL-MANSY:DEPLETION-MODEIGFET the surface becomes accumulated, in which case the sum of C@ and Cgd reaches the oxide capacitance again. 2) Discussion: Some of the advantages of using a depletionmode device as the load element in an inverter configuration are high channel mobility, low surface-generated noise, and close resemblance to a current source. In addition to these, the depletion-mode device contributes only small capacitance loading at the output node. This would be the case for proper matching of the process parameters and the voltage used. In Fig. 10(a), the various capacitance components contributed to the output node by a load device having a low implant dose are shown. It is obvious that as long as the device is operating ~ the saturation mode, it contributes less than 20 percent of the gate oxide capacitance. However, once in the linear region, the component C@ increases rapidly towards half of the oxide capacitance. The same type of plot is shown in Fig. 10(b) for a larger implant dose and deeper channel. In this case, the device enters the linear region at relatively lower voltages and the loading of the output mode is more severe. To illustrate these advantages, Fig. 1O(C) shows the contribution of a saturated enhancement device to the output node which is approximately 70 percent of the oxide capacitance of the device over most of the voltage range. V. CONCLUSIONS A nonlinear dc and charging current model for the depletionmode IGFET has been presented. The model is defined in terms of basic processing related parameters which can be obtained from a simple set of terminal measurements. A systematic procedure for deriving the various capacitance components of the model has tieen presented which is computationally very efficient and directly usable in circuit simulation progryrrs. The device model describes device operation in all voltage ranges and all surface conditions. Measurements are presented on various dc and small-signal parameters. Finally, it is shown that the contribution of the device capacitance to the output node capacitance is one of the important factors to be considered when designing a process to ensure that the load device is operating in the saturation mode over most of the voltage range covered by the output node. APPENDIx DERIVATION OF MODEL PARAMETERS As an example to illustrate the systematic approach to deriving the various dc and capacitance parameters, we apply these formulas to some of the regions of operations. Consider the case where inversion exists along the whole surface where we have
Qm = -Qi+(KE Qg = Co%g +KN)~

~-say Therefore, Id= $

[Qi(Vmd - Vm.) - ; (KE +KN) (U% -

%/?)1
(A4)

FG = - QiCOVm~(Vmd - Vms) + ~
(v;& v~$),

CO vmg(~~

+ Kiv)

(A5)

FB = ~ Qi(KE +KN) (v~ti - v~f) - ; (KE + KN)2(V;d - V&) - FG.

The conductance
VW gd=~

(A6)

are written as
(KE + KN)

[Qi -

Jt%]

(A7) (A8)

gm=o g,= - $! [Qi- (KE +KN)

gb = f V# ]

(A9)

(KE +KN) (V~fi - V#).

(A1O)

The derivatives of the charge functions are

FG~ = FGD = -

/,lw CO

mg&

1( 1(

) )

(Al 1)

/.Jw CO mggd ~

(A12)

FGB =(COId - co Vmggb)

and

1()
/.lw

(A13)

FBS G(KN +KE) V~/gS

/(

>W ~
/.lw

- FGS - FGD

(A14)

FBD (KN +KE) V~~ gd

/0

(A15)

FBG = -FG/Vmg.

(A16)

The six capacitance components can then be constructed using (16) and the relevant expressions for each capacitance component. ACKNOWLEDGMENT The author wishes to acknowledge the many stimulating discussions with his colleagues at BNR. Special thanks are due to A. R. Boothroyd for his contributions to t~s work and for constructive c@icism of the manuscript. The comments made by the reviewers of the paper improved the clarity of the presentation for which the author is grateful. REFERENCES [1] L. Forbes, n-channel ion-implanted enhancement/depletion FET circuit and fabrication technology; IEEE J. Solid-State Circuits, vol. SC-8, pp. 226-230, June 1973. [2] F. F. Fang and H. S. Rupprecht, High performance MOS integrated circuits using ion-implantation technique: IEEE J. So2idState Circuits, vol. SC-10, pp. 205-211, Aug. 1975.

(Al) (A2)

and Qh = -(KE +KAT)c

- CoVm,.

(A3)

340

IEEE JOURNAL OF SOLID-STATECIRCUITS, VOL. SC-15, NO. 3, JUNE 1980 of ion-implanted buried-channel MOSFETS, Solid-State Electron., vol. 22, pp. 47-54, 1979.

[3] El. J. Hosticka et al., MOS sampled data recursive filters using switched capacitor integrators, IEEE J. Solid-State Circuits, VOL 6 SC-12, pp. 00-608, Dec. 1977. [4] See, for example, 1978 IEEE ISSC Dig. Tech. Paper-s: a) E. M. Blaser and D. A. Conrad, FET logic configuration, pp. 14-15. b) R. W. Knepper, Dynamic depletion mode: An E/D MOSFET circuit method~ pp. 16-17. c) R. A. Blouschild et al., An NMOS voltage reference; pp. 50-51. [5] J. R. Edwards and G. Mar~, Depletion-mode IGFET made by deep ion-implantation; IEEE Trans. Electron Devices, VOLED20, pp. 283-289, Mar. 1973. [6] J. S. Huang and G. W. Taylor, Modeling of an ion-implanted silicon-gate depletion-mode IGFET, IEEE Trans. Electron Devices, vol. ED-22, pp. 9951000, Nov. 1975. [7] C. G. Verbracken et al., Impurity profiie determination and DC modeling of the JIGFET, IEEE Trans. Electron Devices, vol. ED-24, pp. 723-730, June 1977. [8] R. A. Haken, Analysis of the deep depletion MOSFET and the use of the DC characteristics for determining bulk-channel chargecoupled device parameters: Solid-State Electron., vol. 21, pp. 753-761,1978. [9] A. M. Mohsen and F. J. Morris, Measurements on depletionrnode field-effect transistors and buried channel MOS capacitors for the characterization of bulk transfer charge-coupled devices: Solid-State Electron., vol. 18, Pp. 407-416,1975. [10] G. Lubberts and B. C. Burkey, Capacitance and doping profiles

[11] J. A. Robinson, Y. A. E1-Mansy,and A. R. Boothroyd, A generrd four-terminal charging-current model for the insulated-gate field-effect transistor~ Solid-State Electron., VOL22, 1979.

Youssef A. E1-Mrmsy (S71-M74) was born in Egypt on March 8,1945. He received the B.SC. and M.SC.degrees, both in electrical engineering, from Alexandria University, Alexandria, Egypt, in 1966 and 1970, respectively, and the Ph.D. degree in electronics from Carleton University, Ottawa, Ont., Canada, in 1974. From 1966 to 1970 he was a Teaching and Research Assistant at Alexandria University where he was involved in research in the area of network synthesis and filter theory. Since 1970 he has been engaged in research on semiconductor device modeling and characterization, From 1974 to 1979 he was with Bell Northern Research, Ottawa, Ont., Canada, initially as a member of the Scientific Staff working on MOS device modeling and CCD device characterization for signal processing, and later as a Manager for a group responsible for device amdysis, characterization, cicuit, and process simulation. In 1979 he joined Intel Corporation, Aloha, OR, where he is currently involved in technology development.

Computer

Analysis and Modeling of Injection-Coupled Synchronous Logic (ICSL) Gates

N. FRIEDMAN, C. A. T. SALAMA, AND P. M. THOMPSON

Abstr~ctThis paper discusses the computer analysis and modeling of injection-coupied synchronous logic (ICSL) gates. A lumped circuit model is developed taking into account the layout and dimensions of the gate. The model is suitable for analysis using a standard computer program such as SPICE. Equations for the static and dynamic model psrarnet:rs including partial base currents, collector cukents, current gains, tr~$sit times, and depletion capacitances are developed in terms of physical dimensions and prQcess parameters. The perfokrnance of the model is successfully tested against experimental results over a wide range of injection currents. .

DATA INPUT (INJECTOR C0t4TROL

p ~ = -41
+V
INJECTOR Ij

?/

INPUT)

INTRODUCTION gate based on a modified 12L injector was described recently [1]. In this structure, in addition to the regular 12L base input, an injector control input tied to the collector of the p-n-p transistor is provided as shown in Fig. 1. The usefulness of the modified injector structure was demonlogic new

Fig. 1. Schematic diagram of a four-collector symmetric ICSL gate. strated in the design of comparators and synchronous logic circuits [1] . The new structure was shown to offer considerable reduction in area (75 percent) as compared to standard 12L in the fabrication of synchronous logic elements while providing the same power X delay product. The basic gate can operate in two modes: the quiescent-

Manuscript received August 10, 1979; revised January 30, 1980. This work was supported by the National Science and Engineering Research Council of Canada. N. Friedman and C. A. T. Salama are with the Department of Electrical Engineering, University of Toronto, Toronto, Ont., Canada. P. M. Thompson is with Thompson Foss Inc., Ottawa, Ont., Canada. 001$ -9200/80/0600

-0340$ 00.75 @ 1980 IEEE