GNMT - NTL (For Print) - 10-2010

Nguyn Tun Linh BM KTMT Khoa in t i hc k thut cng nghip Thi Nguyn
K thut ghp ni my tnh
Thng 5/2010
Nguyn Tun Linh BM KTMT Khoa in T
Bi ging mn hc: K thut ghp ni my tnh

CHNG 1. I CNG V K THUT GHP NI MY TNH ............. 6
1.1. 1.2.
1.2.1 1.2.2 1.2.3
Cu trc chung ca h thng ................................................................................. 7 Yu cu trao i tin ca my vi tnh i vi mi trng bn ngoi ..................... 8
Yu cu trao i tin vi ngi iu hnh ................................................................8 Yu cu trao i tin vi thit b ngoi trong h o lng iu khin ...................8 Yu cu trao i tin trong mng my tnh ...............................................................8
1.3.
1.3.1 1.3.2
Dng v cc loi tin trao i gia my vi tnh v thit b ngoi (TBN) ............... 8
Dng tin (s) ............................................................................................................8 Cc loi tin ...............................................................................................................9
1.4.
1.4.1 1.4.2
Vai tr v nhim v ca khi ghp ni (KGN) ..................................................... 9

Vai tr ......................................................................................................................9 Nhim v ..................................................................................................................9
1.5.
1.5.1 1.5.2
Cu trc chung ca mt h ghp ni my tnh .................................................... 11

Cu trc ng tn hiu ca KGN vi My tnh ...................................................11 Cu trc chung ca mt khi ghp ni ..................................................................11
1.6.
1.6.1 1.6.2 1.6.3
Chng trnh phc v trao i tin cho khi ghp ni ......................................... 12

Lp trnh hp ng (assembly) ................................................................................12 Lp trnh Pascal......................................................................................................13 Lp trnh C/C++ .....................................................................................................13
CHNG 2. GIAO TIP VI TN HIU TNG T .................................. 15

2.1. 2.2.
2.2.1 2.2.2 2.2.3 2.2.4
Khi nim tn hiu analog v h o lng iu khin s .................................... 16 Chuyn i tn hiu s sang tng t DACs ...................................................... 16
Cc tham s chnh ca mt DAC ...........................................................................17 DAC chia in tr (Resistive Divider DACs) .......................................................18 DAC trng s nh phn (Binary Weighted DACs) ................................................18 DAC iu bin rng xung (PWM DACs) ........................................................19
2.3.
2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6
Chuyn i tn hiu tng t - s ADC: ............................................................. 20

Cc tham s chnh ca mt ADC ...........................................................................20 B bin i AD theo hm dc................................................................................21 A/D xp x tim cn ...............................................................................................22 Tch phn sn dc ................................................................................................23 Flash ADC .............................................................................................................24 Mt s vi mch ADC thng dng ..........................................................................25
M t chc nng ca cc chn: ........................................................................... 27
CHNG 3. TH TC TRAO I D LIU CA MY TNH ................. 30

3.1. 3.2.
3.2.1 3.2.2 3.2.3
Cc ch trao i d liu ca my vi tnh ........................................................ 31 Trao i tin ngt vi x l..................................................................................... 32

Cc loi ngt ca my PC ......................................................................................32 X l ngt cng trong IBM - PC: ..........................................................................35 Lp trnh x l ngt cng:......................................................................................37
3.3.
3.3.1 3.3.2 3.3.3
Trao i tin trc tip khi nh ............................................................................ 39

C ch hot ng: ..................................................................................................39 Hot ng ca DMAC: ..........................................................................................39 Chip iu khin truy nhp b nh trc tip DMAC 8237 .....................................40
CHNG 4. GHP NI QUA RNH CM M RNG ................................ 45

4.1. 4.2. t vn ............................................................................................................ 45 Bus PC ................................................................................................................. 47
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4.3. 4.4. 4.5.

4.5.1 4.5.2
Bus ISA (16 bit) .................................................................................................. 47 Bus PCI ............................................................................................................... 50 Ghp ni qua khe cm m rng .......................................................................... 50
Mt s c im ca Card ISA ............................................................................. 50 Gii m a ch v kt ni Bus d liu .................................................................. 50
CHNG 5. GHP NI TRAO I TIN SONG SONG ................................ 53

5.1. 5.2.
5.2.1 5.2.2
Khi ghp ni song song n gin ..................................................................... 53 Cc vi mch m, cht (74LS245, 74LS373)..................................................... 55
Vi mch m 74LS245: ......................................................................................... 55 Vi mch cht 74LS373: ......................................................................................... 55
5.3.
5.3.1 5.3.2 5.3.3 5.3.4
Vi mch PPI 8255A ............................................................................................ 56

Gii thiu chung .................................................................................................... 56 Cc lnh ghi v c cc cng v cc thanh ghi iu khin ................................... 57 Cc t iu khin ................................................................................................... 57 Ghp ni 8255A vi My tnh v TBN ................................................................. 62
5.4.
5.4.1 5.4.2 5.4.3 5.4.4
Ghp ni song song qua cng my in ................................................................. 65

Ghi thiu chung ................................................................................................... 65 Cu trc cng my in ............................................................................................. 66 Cc thanh ghi ca cng my in: ............................................................................ 67 EPP - Enhanced Parallel Port ................................................................................ 69
CHNG 6. GHP NI TRAO I TIN NI TIP ...................................... 75

6.1. 6.2.
6.2.1 6.2.2 6.2.3
t vn ........................................................................................................... 75 Yu cu v th tc trao i tin ni tip: .............................................................. 76

Yu cu: ................................................................................................................. 76 Trao i tin ng b: Synchronous ....................................................................... 77 Trao i tin khng ng b - Asynchronous: ........................................................ 77
6.3.
6.3.1 6.3.2
Truyn thng ni tip s dng giao din RS-232: .............................................. 78

Qu trnh truyn mt byte d liu: ........................................................................ 79 Cng ni tip RS 232 ............................................................................................ 79
6.4.
6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 6.4.7
Giao tip USB ca my PC: ............................................................................... 96

Gii thiu chung. ................................................................................................... 96 M t h thng USB .............................................................................................. 97 Giao din vt l ..................................................................................................... 99 S im danh ....................................................................................................... 104 Cc kiu truyn USB ........................................................................................... 104 Giao thc USB .................................................................................................... 105 Khun dng cc gi tin ........................................................................................ 108
CHNG 7. GIAO TIP VI CC THIT B NGOI VI C BN ......... 111

7.1.
7.1.1 7.1.2
Giao tip vi bn phm v chut ....................................................................... 112

Bn phm ............................................................................................................. 112 Chut ................................................................................................................... 117
7.2. 7.3.
7.3.1 7.3.2
Giao tip PC Game ........................................................................................... 118 Monitor v card giao din ho ..................................................................... 120
Nguyn l hin nh trn monitor ......................................................................... 120 Card giao tip ha........................................................................................... 121
Gii thiu mn hc
Tn mn hc: Giao tip my tnh K thut ghp ni my tnh (Computer Interfacing) Mc tiu: Trang b cho sinh vin cc kin thc c bn v ghp ni my tnh v vai tr ca ghp ni my tnh trong cc h thng t ng. Nghin cu cc giao tip c bn ca my tnh vi cc thit b ngoi vi nh: cc khe cm (ISA, PCI, ..), cc cng vo ra (LPT, COM, USB,). Thit k v xy dng cc h thng ghp ni my tnh p ng cc yu cu c th t ra trong thc t. Ng Din Tp, K thut ghp ni my tnh, NXB KHKT, Ng Din Tp, o lng v iu khin bng my tnh, NXB KHKT Nguyn Mnh Giang, K thut ghp ni my vi tnh, NXB Gio dc, 2 tp. Xun Tin, K thut lp trnh iu khin h thng, NXB KHKT Ng Din Tp, Lp trnh ghp ni my tnh trong Windows, NXB KHKT
Ti liu tham kho [1]. [2]. [3]. [4]. [5].
Chng 1: i cng v k thut ghp ni my tnh
CHNG 1. I CNG V K THUT GHP NI MY TNH

Mc tiu: Hiu c cu trc tng quan ca h vi x l; V tr, chc nng v cu trc chung ca khi ghp ni trong trong mt h thng my tnh trong o lng iu khin. Xc nh c yu cu, cc thnh phn v lp trnh iu khin cho khi ghp ni Tm tt chng:
-
Cu trc chung ca h thng Yu cu trao i tin ca my vi tnh i vi mi trng bn ngoi Dng v cc loi tin trao i gia my vi tnh v thit b ngoi (TBN) Vai tr v nhim v ca khi ghp ni (KGN) Cu trc chung ca mt h ghp ni my tnh Chng trnh phc v trao i tin cho khi ghp ni
1.1. Cu trc chung ca h thng

My vi tnh hay h vi x l u c cu trc chung do Von Newman xut gm khi x l trung tm (CPU), b nh (Memory) v cc cng vo/ra (I/O), nh hnh 1.1. Ngoi ra, My tnh cn cn phi trao i d liu vi mi trng bn ngoi, v d nh giao tip vi ngi s dng qua bn phm, mn hnh, trao i d liu vi cc thit b ngoi vi thng dng, cc thit b ngoi trong h o iu khin, v cc My tnh khc trong mng. Do cc khi ghp ni (KGN) thit b ngoi vi c xy dng, gm: KGN cc thit b vo chun nh bn phm, chut, KGN cc thit b ra chun nh mn hnh, my in, KGN cc b nh ngoi chun nh cng, CD, KGN vi cc my tnh khc trong mng nhiu my tnh KGN vi h vi iu khin, vi x l KGN vi h o iu khin
Hnh 1.1. Cu trc ca h ghp ni my tnh vi thit b ngoi vi Trong : VXL: Vi x l RAM: Random Access Memory B nh trong RAM ROM: Read-only Memory B nh trong ROM BGN: B ghp ni, khi ghp ni CN: Cng nghip K: iu khin c bit trong h o lng - iu khin, My tnh nhn d liu trng thi vt l ca h thng (nhit , p sut, in p, dng in) di dng tn hiu in, t u d cc b cm bin (sensor), b chuyn i (tranducer), b pht hin (detector). V
Nguyn Tun Linh BM KTMT Khoa in T 7
My tnh cn nhn thng tin v trng thi sn sng hay bn ca thit b o. My tnh sau a tn hiu chp nhn trao i d liu vi TBNV, thu thp v x l d liu, tnh ton cc tn hiu iu khin a ra cc c cu chp hnh (cc van ng m, cc rle trong mch in, cc mch ng lc iu tc ng c in), hay a ra cc thng s k thut cho thit b. Ngoi ra, My tnh cn cn lu tr d liu trn cng, a compact (CD-ROM) tra cu lc cn, hin th kt qu o di dng bng s liu, dng th hay hnh v ho trn mn hnh.
1.2. Yu cu trao i tin ca my vi tnh i vi mi trng bn ngoi

1.2.1 Yu cu trao i tin vi ngi iu hnh Ngi iu hnh trao i thng tin vi my tnh thng qua cc thit b nhp/xut c bn nh chut, bn phm, mn hnh. Vic trao i c thc hin thng qua mt giao din trn mn hnh my tnh. Trng thi hot ng ca h thng c th hin trn giao din, ngi s dng tc ng vo h thng qua giao din ny s dng cc thit b nhp nh chut, bn phm, Vic trao i thng tin vi ngi s dng cn m bo nhanh, chnh xc ng thi phi thun tin, an ton cho ngi s dng. 1.2.2 Yu cu trao i tin vi thit b ngoi trong h o lng iu khin Trong h o lng iu khin, my tnh nhn d liu trng thi vt l ca h thng (nhit , p sut, in p, dng in,..) di dng tn hiu in, t cc b cm bin (sensor), b chuyn i (transducer), b pht hin (detector), v my tnh cn nhn thng tin v trng thi sn sng hay bn ca thit b. My tnh sau trao i d liu vi thit b ngoi vi, thu thp v x l d liu, tnh ton cc tn hiu iu khin a ra cc c cu chp hnh (cc van ng m, cc r le trong mch in, cc mch ng lc iu tc ng c in,..) hay a ra cc thng s thit lp ch hot ng cho thit b. Ngoi ra my tnh cn lm nhim v lu tr d liu tra cu, thng k hoc hin th kt qu trng thi hot ng ca thit b di dng th hay cc hnh v trc quan. 1.2.3 Yu cu trao i tin trong mng my tnh Mt my tnh trong mng cn trao i tin vi nhiu ngi s dng mng, vi nhiu my vi tnh khc, vi nhiu thit b ngoi nh: cc thit b u cui, cc thit b nh ngoi, cc thit b lu tr v biu din tin.
1.3. Dng v cc loi tin trao i gia my vi tnh v thit b ngoi (TBN)
1.3.1 Dng tin My tnh ch trao i tin di dng s vi cc mc logic 0 v 1
Thit b ngoi li trao i tin vi nhiu dng khc nhau nh dng s, dng k t, dng tng t, dng m tn hnh sin tun hon 1.3.2 Cc loi tin My tnh a ra thit b ngoi mt trong 3 loi tin: Tin v a ch: l cc tin ca a ch TBN hay chnh xc hn, l a ch cc thanh ghi (register) ca khi ghp ni i din cho TBN. Tin v lnh iu khin: l cc tn hiu iu khin khi ghp ni hay TBN nh ng m thit b, c hoc ghi mt thanh ghi, cho php hay tr li yu cu hnh ng, v.v.. Tin v s liu: l cc s liu cn a ra cho thit b ngoi. My tnh nhn tin vo t TBN v mt trong hai loi tin: Tin v trng thi ca TBN: l tin v s sn sng hay yu cu trao i tin, v trng thi sai li ca TBN. Tin v s liu: l cc s liu cn a vo My tnh
1.4. Vai tr v nhim v ca khi ghp ni

1.4.1 Vai tr Khi ghp ni nm gia My tnh v TBN ng vai tr bin i v trung chuyn tin gia chng
Ngun Ngun nhn Ngun pht Ngun nhn
MVT
Ngun nhn Ngun pht Ghp ni ng dy MVT Ngun nhn Ghp ni ng dy TBN
TBN
Ngun pht
V tr v vai tr ca khi ghp ni
1.4.2 Nhim v Phi hp v mc v cng sut tn hiu - Mc tn hiu ca My tnh thng l mc TTL (0V 5V) trong khi TBN c nhiu mc khc nhau, thng thng cao hn ( 15V, 48V) hay mc in cng nghip (220V/380V hoc ln hn) - Cng sut ng tn hiu My tnh nh (c chc mA), trong khi cng sut cn cho TBN thng rt ln, c bit trong cng nghip.
Do KGN phi bin i in p v khuch i cng sut cho ph hp gia my tnh v thit b. Pha my tnh thng dng cc vi mch 3 trng thi ghp ni tn hiu vo/ra. u vo/ra s mc tr khng cao khi khng c trao i d liu, c lp thit b vi my tnh, hn ch tiu th cng sut ng tn hiu v bo v my tnh.
Phi hp v dng d liu: Trao i tin ca My tnh thng l song song dng s, c th truyn theo 8, 16 hoc 32 bit, ca TBN i khi l ni tip hoc ch yu l tn hiu tng t Phi hp v tc trao i tin My tnh thng hot ng vi tc cao (tn s ln ti hng GHz) trong khi thit b thng hot ng chm hn nhiu. Do cn phi thc hin ng b v mt tc . Vic ny thng c s kt hp gia phn cng v phn mm. Trn KGN phi c b nh m m d liu gia my tnh v thit b. KGN nhn t my tnh v lu d liu b nh m ri truyn cho thit b theo nhp chm ca thit b, gii phng cho my tnh lm nhim v khc (phc v thit b khc, x l d liu hoc iu khin hin th,..) Tng t, KGN nhn d liu t thit b v ch my tnh c d liu vo. Phi hp v phng thc trao i tin m bo trao i tin mt cch tin cy gia My tnh v TBN, cn c KGN v cch trao i tin din ra theo trnh t nht nh. Vic trao i tin do my tnh khi xng (1) My tnh a lnh d khi ng TBN hay khi ng KGN (2) My tnh c tr li sn sng trao i hay trng thi sn sng ca TBN. Nu c trng thi sn sng mi trao i tin, nu khng, ch v c li trng thi (3) My tnh trao i khi c thy trng thi sn sng Vic trao i tin do TBN khi xng: (1) gim thi gian ch i trng thi sn sng ca TBN, My tnh c th khi ng TBN ri thc hin nhim v khc. Vic trao i tin din ra khi: (2) TBN a yu cu trao i tin vo b phn x l ngt ca KGN, a yu cu ngt chng trnh cho My tnh (3) Nu c nhiu TBN a yu cu ng thi, KGN sp xp theo u tin nh sn, ri a yu cu trao i tin cho My tnh (4) My tnh nhn yu cu , sa son trao i v a tn hiu xc nhn sn sng trao i (5) KGN nhn v truyn tn hiu xc nhn cho TBN (6) TBN trao i tin vi KGN v KGN trao i tin vi My tnh (nu a tin vo) (7) My tnh trao i tin vi TBN qua KGN (nu a tin ra)
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1.5. Cu trc chung ca mt h ghp ni my tnh

1.5.1 Cu trc ng tn hiu ca KGN vi My tnh Bt c KGN no cng ni vi My tnh v TBN c cc nhm sau Nhm ng tn hiu a ch A0 - An - Cc tn hiu ny c gii m trong cc KGN chn cc TBN cn lin lc vi My tnh - Tp hp cc tn hiu ny to thnh bus a ch (Address bus) Nhm ng tn hiu iu khin - ng tn hiu c, ng tn hiu vit truyn lnh c (RD) hay vit cho KGN. - ng tn hiu hi thoi t chc phi hp hnh ng gia My tnh v KGN, m bo s hot ng nhp nhng, tin cy gia chng nh: Hi - tr li Yu cu (t KGN vo My tnh) v chp nhn (t My tnh ra KGN) : yu cu ngt INTR v chp nhn ngt INTA - ng tn hiu lnh iu khin KGN hay TBN Nhm ng tn hiu nhp thi gian Nhm ng tn hiu in p ngun 1.5.2 Cu trc chung ca mt khi ghp ni
Lnh c A0 - An Gii m a ch lnh Lnh vit Cc lnh chn chip (CS)
Phi hp ng dy thit b ngoi
Phi hp ng dy my tnh
ng dy my tnh (System bus)
ng dy thit b ngoi
Yu cu (INTR) Xc nhn (INTA) Lnh c
X l ngt
Yu cu A Yu cu B iu khin A iu khin B
Thanh ghi trng thi Lnh vit
cm ngt
Thanh ghi iu khin
DO0 - DOn
Thanh ghi m vit

Lnh vit
DO0 - DOn
DI0 - DIn
Thanh ghi m c
Lnh c
DI0 - DIn
Cu trc chung khi ghp ni
Khi phi hp ng tn hiu My tnh Phi hp mc v cng sut tn hiu vi bus My tnh. Thng dng vi mch chuyn mc, vi mch cng sut C lp ng tn hiu khi khng c trao i tin
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Khi gii m a ch - lnh: Nhn cc tn hiu t bus a ch, cc tn hiu c, ghi, cht a ch (ALE), t hp thnh cc tn hiu c, ghi v chn chip cho tng thit b ca KGN v TBN. Cc thanh ghi m Thanh ghi iu khin ch Thanh ghi trng thi hay yu cu trao i ca TBN Thanh ghi m s liu ghi Thanh ghi m s liu c Khi x l ngt Ghi nhn, che chn yu cu trao i tin ca TBN. X l u tin v a yu cu vo My tnh Khi pht nhp thi gian Pht nhp thi gian cho hnh ng bn trong KGN hay cho TBN. i khi ng b, khi cn nhn tn hiu nhp ng h (clock) t bus my tnh Khi m thit b ngoi Bin i mc tn hiu, cng sut v bin i dng tin Khi iu khin : iu khin hot ng ca khi nh pht nhp thi gian, ch hot ng
1.6. Chng trnh phc v trao i tin cho khi ghp ni

Mi khi ghp ni cn c mt chng trnh phc v trao i tin, cc chng trnh ny thng vit di dng cc chng trnh con, tp hp cc chng trnh con iu khin thit b thng c cung cp km vi thit b thng qua cc th vin. Cc th vin ny c th c ng gi vi nhiu dng khc nhau nh th vin lp trnh (.h, .lib), th vin lin kt ng (.dll), cc iu khin ActiveX (.ocx), cc device driver. Vi chng trnh phc v trao i tin, cn c cc thao tc sau: Khi ng KGN Ghi che chn v cho php ngt c trng thi TBN Ghi s liu ra c tin s liu C th xy dng chng trnh iu khin bng nhiu ngn ng lp trnh v mi trng lp trnh khc nhau nh: Assembly, Pascal, C/C++, Visual C, Visual Basic, Trong ti liu ny ch yu cung cp cc phng php lp trnh bng cc ngn ng bc thp v trong mi trng DOS. 1.6.1 Lp trnh hp ng (assembly) Xut d liu t bin data ra cng c a ch address: mov dx, address mov ax, data out dx, ax
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V d: mov dx, 300H mov ax, F0H out dx, ax Nhp s liu t cng a ch address vo bin data mov dx, address in ax, dx mov data, ax data, address l s nh phn 16 bit. c/ghi thanh ghi: 1.6.2 Lp trnh Pascal c thanh ghi: <bi n> := port[ a ch Ghi vo thanh ghi Port[ a ch Lp xa bit: Lp bit: Port[$301]:=port[$301] OR $02; {L p C1} Xa bit: Port[$301 ]:=port[$301] AND $EF; {Xa C4} Kim tra bit: kt:=port[$300] AND $04; {ki m tra bit S2} kt = 0 S2 = 0 kt 0 S2 = 1 1.6.3 Lp trnh C/C++ c/ghi thanh ghi: c thanh ghi: <bi n> = inp ( a ch Ghi vo thanh ghi outp (< a ch Lp xa bit:
thanh ghi];
thanh ghi] := <Gi tr >;
thanh ghi);
thanh ghi>,<Gi tr >)
Lp bit: Outp (0x301,inp (0x301)||0x02);{L p C1} Xa bit: Outp (0x301,inp (0x301) && 0xEF); {Xa C4} Kim tra bit: kt:=inp (0x300) && $04; {ki m tra bit S2} kt = 0 S2 = 0 kt 0 S2 = 1
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Chng 2: Giao tip tn hiu tng t
CHNG 2. GIAO TIP VI TN HIU TNG T

Mc tiu: Cung cp cc kin thc c bn v giao tip gia my tnh vi tn hiu tng t trong cc h thng o lng v iu khin. Tm hiu cu trc, nguyn l hot ng ca cc loi vi mch bin i tn hiu tng t -s (ADC/DAC) v ng dng ca chng.
Tm tt chng: Khi nim tn hiu analog v h o lng iu khin s Chuyn i tn hiu s sang tng t DACs Chuyn i tn hiu tng t - s ADC:
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Khi nim tn hiu tng t v h o lng iu khin s Vic s dng phng php s trong x l thng tin v iu khin ang ngy cng hiu qu v thun li. Tuy nhin hu ht cc tn hiu trong th gii thc li l tn hiu dng tng t (analog). Do bt k h thng no mun x l cc tn hiu thc t bng phng php s th n phi c kh nng chuyn i cc thng tin tng t thnh dng s v ngc li. Thao tc thng c thc hin bng cc thit b ADC (Analog to Digital Converter) v DAC (Digital to Analog Converter).
Hnh 2.1: M hnh h thng x l tn hiu tng t bng phng php s H thng x l tn hiu tng t bng phng php s ni chung l mt h lai, trong s liu tng t s c truyn, lu tr , hay x l bng phng php s nh cc b vi x l s. Trc khi s l, tn hiu tng t phi c chuyn thnh tn hiu s nh b chuyn i tn hiu tng t sang s (ADC). Kt qu ca php x l s c chuyn ngc li thnh dng tng t nh b chuyn i tn hiu s thnh tng t (DAC).
2.1. Chuyn i tn hiu s sang tng t DACs

Mt b chuyn i tn hiu s thnh tng t DAC l mt dng c bit ca mt b gii m. N gii m tn hiu s u vo v chuyn thnh tn hiu tng t u ra. Bng chn l ca n c th c dng nh sau: Hnh 2.2: Bng gi tr chn l ca mt DAC
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2.1.1 Cc tham s chnh ca mt DAC Tham s n v Gii thch y l s bit m DAC x l. Nu DAC c n bit th gi tr in phn gii p u ra c th phn thnh n trng thi c gi tr cch u Bit (revolution) nhau. Mi gi tr tng ng vi mt m s u vo. S bit n cng cao th DAC c phn gii cng ln Gii in p tham chiu (Vref) FSR V Ch ra mc in p ln nht v nh nht c th c s dng nh in p tham chiu t bn ngoi
L chnh lch gia thay i gi tr ip p ra thc t vi phi tuyn vi LSB thay i in p ra l tng trong trng hp u vo s phn hay thay i mt bit LSB , hay d thay i gia hai gi tr s k (Non-Linearity, %Vref nhau Differential - DNL) VD: +/- 1 LSB; +/- 0.001% FSR phi tuyn tch L sai s ln nht gia u ra vi ng thng ni gia im 0 phn (Nonv im ton thang (gi tr ln nht ca thang o) ngoi tr sai Linearity, Integral LSB s im khng v sai s ton thang INL) hay chnh xc tng i VD: +/-1 LSB typ.; +/- 4 LSB's max. (Relative Accuracy) L chnh lch gia gi tr tng t ln nht v nh nht m Gii u ra tng DAC c th cung cp t hay gii ton V thang VD: -3V to +3V, Bipolar Mode Mc in p logic cao u vo, Vih (Logic "1") Logic Input Voltage, Vil (Logic "0") in p ngun dng (+Vs) in p ngun m Analog Negative Power Supply (-Vs) in p mc logic dng (+VL) in p mc logic m (-VL) V L in p nh nht ca tn hiu s u vo DAC m bo c nhn l mc logic 1 VD: 2.4 V min. L in p ln nht ca tn hiu s u vo DAC m c nhn l mc logic 0" VD: : 0.8 V max L di in p c th dng lm ngun cung cp dng cho DAC VD: +4.75V min.; +5.0V typ.; +13.2V max. L di in p c th s dng lm ngun cung cp m cho DAC VD: -13.2V min.; -5V typ.; -4.75V max. L di in p c th s dng cho mc logic dng ca DAC: VD: +4.75V min.; +5.0V typ.; +13.2V max. L di in p c th s dng cho mc logic dng ca DAC VD: -13.2V min.; -5V typ.; -4.75V max.
V V V
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2.1.2 DAC chia in tr DAC theo phng php chia in tr (Resistive Divider DAC) c l l kiu DAC n gin nht. DAC kiu ny s dng mt chui in tr mc ni tip vi nhau to ra mt tp cc gi tr in p cch u nhau gia +Vref v Vref. Tn hiu s u vo xc nh tn hiu in p no c ni vi b khuch i thng qua cc cc b chuyn mch. Mc d phng php chia in tr c th d hiu, nhng n tr nn km hiu qu vi cc b DAC c phn gii cao. Mi bit thm vo cho phn gii ca DAC i hi tng gp i s in tr v cng tc. V d nh vi DAC 12 bit th phi cn ti 4095 in tr v 4096 cng tc.
Hnh 2.3: DAC chia in tr 2.1.3 DAC trng s nh phn Khi phn gii ca DAC t ti 6 hay 7 bit, kin trc thang in tr thng cho mt phng php hiu qu hn Phng php ny cho ta li ch chnh l chng tit kim din tch vi mch. Chng hn nh mt DAC 9 bit ch cn 1 in tr v 1 cng tc thm vo so vi DAC 8 bit
Hnh 2.1DAC trng s nh phn
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2.1.4 DAC iu bin rng xung Phng php DAC iu bin rng xung (Pulse width modulation PWM) l phng php rt n gin v hu nh hon ton s dng phng php s, s dng rt t mch tng t PWM iu chnh in p u ra s dng chui xung tn s cao vi rng xung c th thay i c thay i cng sut u ra di xung cng ln th in p u ra cng gn vi in p ti a (VOH) ca DAC, v ngc li di xung ngn nht tng ng vi in p ti thiu (VOL) Tn hiu u ra s c a qua mt b loc thng thp to tn hiu analog
Hnh 2.2: DAC iu bin rng xung DAC dng PWM cng kh thu c DAC vi phn gii cao, bi v c phn gii cao, DAC phi iu chnh chui xung theo cc khong thi gian rt nh. iu yu cu phi c mt xung clock (master clock) vi tn s rt cao iu khin rng xung V d vi DAC 16 bit, cn c phn gii theo thi gian bng 1/65536 ln chu k chui xung. V xung tn hiu cn phi a qua b lc thng thp to ra tn hiu tng t, tn s xung i hi phi gp nhiu ln ( thng thng l gp 100 ln) tn s cao nht ca tn hiu tng t u ra. Do mt b DAC 16 bit cho cc ng dng x l m thanh c bng thng 20kHz cn c mt b to xung clock c tn s l 65536 x 100 x 20000 = 131 GHz. R rng rng tn s ny l khng th t c vi cng ngh hin nay
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2.2. Chuyn i tn hiu tng t - s ADC:

Tn hiu trong th gii thc thng dng tng t (analog), nn mch iu khin thu thp d liu t i tng iu khin v (thng qua cc cm bin) cng dng tng t. Trong khi , b iu khin ngy nay thng l cc P, C x l d liu dng s (digital). V vy, cn phi chuyn i tn hiu dng tng t thnh tn hiu dng s thng qua b bin i AD. Gii php thng dng a tn hiu tng t vo x l bng cc b x l s l dng b chuyn i tn hiu tng t sang s (analog-to-digital converter - ADC). Hnh di l mt v d cho mt b ADC n gin. u vo cho b ny l hai tn hiu: mt tn hiu tham chiu (reference) v tn hiu cn chuyn i. N c mt u ra biu din mt t m dng s 8 bit. T m ny vi x l c th c v hiu c
C nhiu phng php bin i AD khc nhau, y ch gii thiu mt s phng php in hnh. 2.2.1 Cc tham s chnh ca mt ADC Tham s phn gii Resolution Sai s tuyn tnh vi phn Non-Linearity, Differential (DNL) Sai s tuyn tnh tch phn Non-Linearity, Integral (INL) Di in p tng t u vo hay di ton thang (Analog Input Range or Full-Scale Range)
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n v Bits Bits (with no missing codes)
Gii thch Nu mt ADC c n bit, th phn gii ca n l 2n , c ngha l s trng thi hay s m c th s dng chia u vo analog. S bit cng cao th phn gii cng ln v cng phn bit c nhiu trng thi Vi mi ADC, tn hiu s bin i theo tng bit LSB. chnh lch gia cc gi tr l tng c gi l phi tuyn vi phn. Example of an Actual Spec: 10 Bits min Hm truyn ca mt ADC l mt ng thng ni t im 0 ti im ton thang. Sai s ln nht ca mt m s vi ng thng ny c gi l sai s tch phn ca ADC Example of an Actual Spec: +/- 2 LSB's max L chnh lch gia gi tr tng t ln nht v nh nht ng vi ADC c th VD:0V to +10 V, Unipolar Mode; -5V to +5V, Bipolar Mode
LSB
Thi gian chuyn i sec (Conversion Time) Ngun nui dng (+ Power Supply V+) Ngun nui m - Power Supply (V-) V
Thi gian cn thit ADC hon thnh mt ln chuyn i VD: 15 sec min.; 25 sec typ.; 40 sec max. Di in p c th s dng lm ngun nui dng cho ADC VD: +4.5V min.; +5.0V typ.; +7.0V max. Di in p c th s dng lm ngun nui m cho ADC VD: -12.0V min.; -15V typ.; -16.5V max.
2.2.2 B bin i AD theo hm dc
u vo analog vA
+ OPAMP -
Clock
EOC
Start
So snh vAX Reset vA Khi chuyn i hon tt, counter ngng m EOC
tC
Kt qu digital
Hnh 2.3: Bin i ADC theo hm dc y l b bin i n gin nht theo m hnh b bin i tng qut trn. N dng mt counter lm thanh ghi v c mi xung clock th gia tng gi tr nh phn cho n khi vAX vA. B bin i ny c gi l bin i theo hm dc v dng sng vAX c dng ca hm dc, hay ni ng hn l dng bc thang. i khi n cn c gi l b bin i AD loi counter. Hnh trn cho thy s mch ca b bin i AD theo hm dc, bao gm mt counter, mt b bin i DA, mt OPAMP so snh, v mt cng AND cho iu khin. u ra ca OPAMP c dng nh tn hiu tch cc mc thp ca tn hiu EOC. Gi s vA dng, qu trnh bin i xy ra theo cc bc : - Xung Start c a vo reset counter v 0. Mc cao ca xung Start cng ngn khng cho xung clock n counter. - u vo ca b bin i DA u l cc bit 0 nn p ra vAX = 0v. - Khi vA > vAX th u ra ca OPAMP (EOC) mc cao.
Start
vAX
...
B bin i DA
Counter
Clock
Khi Start xung mc thp, cng AND c kch hot v xung clock c a vo counter. Counter m theo xung clock v v vy u ra ca b bin i DA, vAX, gia tng mt nc trong mt xung clock Qu trnh m ca counter c tip tc cho n khi vAX bng hoc vt qua vA mt lng vT (khong t 10 n 100v). Khi , EOC xung thp v ngn khng cho xung clock n counter. T kt thc qu trnh bin i. Counter vn gi gi tr va bin i xong cho n khi c mt xung Start cho qu trnh bin i mi.
T ta thy rng b bin i loi ny c tc rt chm ( phn gii cng cao th cng chm) v c thi gian bin i ph thuc vo ln ca in p cn bin i. 2.2.3 A/D xp x tim cn y l b bin c dng rng ri nht trong cc b bin i AD. N c cu to phc tp hn b bin i AD theo hm dc nhng tc bin i nhanh hn rt nhiu. Hn na, thi gian bin i l mt s c nh khng ph thuc gi tr in p u vo.
u vo analog vA
+ OPAMP START
Clock n v iu khin ... Thanh ghi MSB LSB ... B bin i DA vAX
n bit thp k Sai
Xa tt c cc bit
So snh
Start EOC
Bt u MSB Set bit = 1 VAX > VA ? Sai Xong ht bit ? ng Qu trnh bin i kt thc v gi tr bin i nm trong thanh ghi END ng Clear bit = 0
S mch v gii thut nh sau : S mch tng t nh b bin i AD theo hm dc nhng khng dng counter cung cp gi tr cho b bin i DA m dng mt thanh ghi. n v iu khin sa i tng bit ca thanh ghi ny cho n khi c gi tr analog xp x p vo theo mt phn gii cho trc. 22
Chuyn i n bit cn n bc Cn c tn hiu Start v End

Thi gian chuyn i thng thng: 1 to 50 ms phn gii thng thng 8 to 12 bits
2.2.4 Tch phn sn dc B bin i loi ny l mt trong nhng b c thi gian bin i chm nht (thng l t 10 n 100ms) nhng c li im l gi c tng i r khng dng cc thnh phn chnh xc nh b bin i AD hoc b bin i p sang tn s. Nguyn tc chnh l da vo 20 qu trnh np v x tuyn tnh ca 18 16 t vi dng hng. u tin, t 14 Vin c np trong mt khong thi 12 10 gian xc nh t dng in khng 8 6 i ng vi in p vo vA. V 4 2 vy, cui thi im np, t s c 0 0 2 4 6 8 10 12 14 16 mt in p t l vi in p vo. Time Counting time Cng vo lc ny, t c x tuyn tnh vi mt dng hng rt ra t in p tham chiu chnh xc vref. Khi in p trn t gim v 0 th qu trnh x kt thc. Trong sut khong thi gian x ny, mt tn s tham chiu c dn n mt counter v bt u m. Do khong thi gian x t l vi in p trn t lc trc khi x nn cui thi im x, counter s cha mt gi tr t l vi in p trn t trc khi x, tc l t l vi in p vo vA.
Start Conversion
Voltage accross the capacitor
Start Conversion
S R
Enable
IN
C o u nt
N-bit Output
Oscillator
Cl k
Hnh 2.4: ADC tch phn theo sn dc Ngoi gi thnh r th b bin i loi ny cn c u im chng nhiu v s tri nhit. Tuy nhin thi gian bin i chm nn t dng trong cc ng dng thu thp d liu i hi thi gian p ng nhanh. Nhng i vi cc qu trnh bin i chm (c qun tnh ln) nh l nhit th rt ng xem xt n.
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2.2.5 Flash ADC Bin tn hiu c so snh vi mt tp 2n gi tr tham kho (refference) o lng trc tip vi 2n-1 b so snh (comparator) Hiu sut thng thng: 4 ti 10 -12 bits 15 - 300 MHz Tiu th nng lng ln ng dng trong s ho dng sng tn hiu
Hnh 2.5: ADC flash B bin i loi ny c tc nhanh nht v cng cn nhiu linh kin cu thnh nht. C th lm mt php so snh: flash AD 6-bit cn 63 OPAMP, 8-bit cn 255 OPAMP, v 10-bit cn 1023 OPAMP. V l m b bin i AD loi ny b gii hn bi s bit, thng l 2 n 8-bit. V d mt flash AD 3-bit : Mch trn c phn gii l 1V, cu chia in p thit lp nn cc in p so snh (7 mc tng ng 1V, 2V, ) vi in p cn bin i. u ra ca cc OPAMP c ni n mt priority encoder v u ra ca n chnh l gi tr digital xp x ca in p u vo. Cc b bin i c nhiu bit hn d dng suy ra theo mch trn.
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2.2.6 Mt s vi mch ADC thng dng Hin nay, trn th trng c rt nhiu loi IC chuyn dng cho b bin i ADC. Di y l loi IC rt hu dng v c s dng nhiu trong thc t. 3.1 B bin i ADC 0809 y l loi bi mch ADC ch to da trn k thut ADC xp x lin tip. S chn: c im cu to: Thang in tr 256 R vi ng chuyn mch analog. Thanh ghi xp x lin tip. B multiplexing. B cht a ch ng vo. B gii m. B m ng ra. Tt c nhng vi mch trn c tch trn mt chip CMOS n khi v khng i hi cc linh kin ph khc mc thm bn ngoi.
U1 26 27 28 1 2 3 4 5 12 16 10 9 7 IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 REF+ REFCLK OE EOC ADC0809 START ALE D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 17 14 15 8 18 19 20 21 25 24 23 6 22
Ti mi thi im ch c th mu 1 trong 8 knh analog vo qua mch phn knh 3 sang 8. S khi:
START 8 BIT AD Control a timing 8 analog input 8 chanel multiplexing analog switch CLOCK EOC
8 digital output
SAR
Tri-state output Latch buffer
Switches tree 3 bit Address Address Latch And decoder Address Latch enable
256 Register Ladder REF+ REF OE
Vcc
GROUND
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c im k thut ca ADC 0809: ADC0809 c tc bin i nhanh, sai s lng ha thp v cng tiu tn thp. Ngun cung cp 5v DC, in p chun 5v DC. Thi gian chuyn i l 100s. C 8 knh analog ng vo. in p ng vo t 0 n 5V. Tn s xung CLOCK t 10 1280KHz. Nguyn tc hot ng : Ti mt thi im, 1 trong 8 ng vo analog c chuyn i. Vic chn ng vo c xc nh bi 3 ng a ch A, B, C thng qua b phn knh 3 sang 8. Qua trnh chuyn i c bt u khi 3 ng a ch c chn v khi xung START v xung ALE bt ln mt. Khi , ALE cht a ch knh c chn v s a tn hiu vo b so snh, xung START bt u thc hin vic chuyn i, EOC mc 0, bus d liu trng tng tr cao. Sau khong thi gian 100s, qu trnh chuyn i kt thc, tn hiu analog c chuyn thnh 8 bit d liu s ng ra. Lc ny xung EOC bt ln 1 v d liu c a vo vng m. a d liu t vng m ln bus, phi t xung OE ln 1. Nh b m 3 trng thi nn d dng kt ni vi data bus ca CPU. Gin thi gian:
CLOCK START ALE AD ANALOG INPUT
OE EOC DATA Tri - state
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Cc s liu k thut: phn gii : Dy ng in tr vo : Trong iu kin :
K = 5/256 = 0.196V
Vcc = Vref (+) = 5V Vref (-) = GND CLK = 640 KHz th tng tr vo t 1 2.5 K. Mc logic ca tn hiu ra :Trong iu kin 4.75V Vcc 5.5V th mc in p logic 1 l V Vcc 0.4 v mc in p logic 0 l V 0.45v Tc chuyn i : 100s Cng sut tiu tn : 15 mW. ADC ICL7109:
ICL7109CPL l b bin i AD 12-bit dng n phin, bin i theo phng php tch phn hai dc, cng vi cc bit ch cc tnh, bit bo qu thang o c th giao tip vi P, C theo hai cch : - Ghp trc tip vo bus : thng qua chn chn chip, hai chn cho php xut byte cao, byte thp. - Ghp theo chun cng nghip UART : c ng dng trong truyn nhn d liu t xa, ng ra c bin i v a n mt UART trong ch bt tay, trao i d liu ni tip. ICL7109CPL c chnh xc cao, tri nhit nh hn 1V/0C. c ng dng trong nhiu trong nhng h thng thu thp d liu do gi thnh thp, cng sut tiu tn v dng phn cc nh. Cc c im ch yu nh sau : - Pha zero-integrator gip khi phc qu ti nhanh. - Loi b vng tr v nhiu. - Ci tin kh nng li bus. - Ng ra 3 trng thi. - UART ch bt tay giao tip ni tip. - C sn ngun tham chiu chun. - 30 ln bin i trong 1 giy. - Khi n, cng ngh CMOS c cng sut thp M t chc nng ca cc chn: GND : Ni t. STATUS : ng ra. Khi mc cao, b bin i ang trong pha integrate hoc pha de-integrate cho n khi d liu c cht. Khi mc thp, b bin i ang pha auto-zero hoc de-integrate sau khi d liu c cht. POL : bit ch cc tnh (polarity), nu mc cao, ch ra rng tn hiu vo l p dng.
OR : bit ch qu thang (over-range), nu mc cao, ch ra rng ng vo vt qu gii hn cho php. B1B12 : ng ra ba trng thi, l cc bit d liu tng ng. TEST : ng vo, khi TEST = 1 th ADC hot ng bnh thng, TEST = 0 th tt c bit d liu ra u mc cao, cn khi khng kt ni th cc cht ng ra b m c cho php. Trong hot ng bnh thng : ni TEST ln +5v. LBEN : ch trc tip (MODE = 0 v CE/LOAD = 0) th LBEN l ng vo, khi mc tch cc s cho php xut byte thp; ch bt tay (MODE = 1) th LBEN l ng ra, c chc nng l c byte thp. HBEN : ch trc tip (MODE = 0 v CE/LOAD = 0) th HBEN l ng vo, khi mc tch cc s cho php xut byte cao; ch bt tay (MODE = 1) th HBEN l ng ra, c chc nng l c byte cao. CE/LOAD : ch trc tip, l ng vo, khi tch cc s cho php xut ra 12 bit d liu B1B12, POL, OR nu LBEN, HBEN tch cc. ch bt tay, l ng ra strobe. MODE : ng vo, khi mc thp : ADC hot ng ch trc tip, cn khi mc cao : ADC hot ng ch bt tay. OSC IN : ng vo ca b dao ng. OSC OUT : ng ra ca b dao ng. OSC SEL : ng vo, dng chn b dao ng. ICL 7109 c mt b dao ng vi 3 ng, n c th hot ng vi b dao ng RC hay dao ng thch anh, cng c th hot ng vi ngun xung clock bn ngoi. Nu chn OSC SEL h (c pullup ko ln) hay ni vi mc cao th xung clock s ly t b dao ng RC bn ngoi. Khi , xung clock s cng pha, cng tn s vi tn hiu trn chn BUF OSC OUT v tn s xung clock tnh theo cng thc :
f = 0.45 RC
in tr nn chn l 100K, t chn sao cho khong thi gian ca 2048 chu k xung clock gn vi mt bi s tch phn ca 50Hz loi tr nhiu 50Hz, nhng khng nn nh hn 50pF. Nu chn OSC SEL c ko xung mc thp th xung clock ly t dao ng thch anh bn ngoi c tn s t 1MHz n 5MHz. Tn s xung clock bn trong khi s bng tn s ca tn hiu trn chn BUF OSC OUT chia cho 58. BUF OSC OUT : ng ra ca b dao ng c m, tin dng lm ngun xung clock cho cc IC khc.
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RUN/HOLD : sau khi pha autozero hon tt trong khon thi gian nh nht, cn c mt xung ln cao t nht 200ns tc ng vo chn RUN/HOLD bt u mt qu trnh bin i. Tuy nhin cn ch rng nu c bt k xung no xut hin trong qu trnh bin i hay trong vng 2048 chu k xung clock sau khi chn STATUS xung thp s b b qua. Nu ICL 7109 ang vo thi im kt thc pha autozero, mt qu trnh bin i s c bt u v chn STATUS s ln cao trong vng 7 chu k xung clock sau khi RUN/HOLD ln cao. Thm vo , bt u v kt thc mt qu trnh bin i, chn ny cng c th c s dng cc tiu thi gian bin i. Bi v mt qu trnh bin i bnh thng s tn mt 8192 chu k xung clock, trong ring pha de-integrate ly mt 4096 chu k xung clock v c lp vi in p vo. Nhng nu sau khi STATUS xung thp, RUN/HOLD xung thp theo th ICL 7109 s nhy tc thi n pha autozero hn l phi mt ton b 4096 chu k xung clock cho pha de-integrate. SEND : ng vo, bo hiu rng thit b bn ngoi chp nhn d liu khi ADC hot ng ch bt tay. Ni ln +5v nu khng s dng. V- : ngun m cho ICL 7109, thng ni n -5v. REF OUT : ng ra in p tham chiu, thng nh hn V+ l 2,8v. BUF : ng ra b khuch i m. AZ : c ni n t CAZ. INT : c ni n t CINT. COMMON : chn chung ca tn hiu tng t. IN LO : cc m ca in p vo vi sai. IN HI : cc dng ca in p vo vi sai. REF IN+ : ng vo dng ca in p tham chiu. REF CAP+ : cc dng ca t tham chiu. REF CAP- : cc m ca t tham chiu. REF IN- : ng vo m ca in p tham chiu. V+ : Vcc (5v).
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Chng 3: Th tc trao i tin ca my vi tnh
CHNG 3. TH TC TRAO I D LIU CA MY TNH

Mc tiu: Trnh by cc kin thc c bn v cc th tc trao i d liu s dng gia my tnh v cc thit b ngoi vi. Nguyn l, u nhc im v ng dng ca mi loi th tc trao i d liu. Lp trnh khi to v iu khin cho mi th tc.
Tm tt chng: Cc ch trao i d liu ca my vi tnh Trao i tin ngt vi x l Trao i tin trc tip khi nh
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3.1. Cc ch trao i d liu ca my tnh

Ch trao i tin ca My tnh vi thit b ngoi Trao i tin theo ch chng trnh S trao i tin c VXL iu khin theo mt trong hai loi lnh sau Cc lnh vo (IN) hay ra (OUT). Cc lnh chuyn (MOV) gia thanh ghi A v thanh ghi m s liu ca KGN c a ch nh xc nh. Trao i tin trc tip b nh Sau khi VXL c khi ng, s trao i tin hon ton do KGN iu khin thay cho VXL v cc cng vo ra ca VXL trng thi in tr cao (VXL b c lp). Lc ny, KGN iu khin mi hot ng ca b nh M v KGN, c th l: Pht a ch cho khi nh hoc TBN. Pht lnh c (/RD) hay ghi (/WR) s liu. Cc s liu c, ghi c trao i gia khi nh M va TBN thng qua cc thanh ghi m ca KGN.
Chng trnh
Th tc trao i tin trong ch chng trnh ch trao i tin theo chng trnh, c th trao i tin theo mt trong ba phng php sau: - Trao i ng b - Trao i khng ng b hay hi trng thi (Polling) - Trao i theo ngt chng trnh 1. Trao i ng b Sau khi khi ng TBN, My tnh khng cn quan tm ti TBN c sn sng trao i tin hay khng m a lun cc lnh trao i tin ( c vo, ghi ra hay truyn s liu ). Phng php trao i tin ny ch c thc hin khi: - TBN lun sn sng trao i tin. - Tc trao i tin ca My tnh v S TBN lun ph hp nhau hoc TBN trao i tin nhanh. nh gi: - u im: Nhanh, khng tn thi gian ch i - Nhc im: Thiu tin cy, b mt tin v c th c s c lm TBN cha sn sng trao i. 2. Trao i khng ng b hay hi trng thi (Polling) Trnh t trao i din ra nh sau: - My tnh a tin iu khin TBN.
Trao i tin
Chng trnh
TBN sn sng ? Trao i tin
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My tnh ch v kim tra trng thi sn sng trao i tin ca TBN bng cch: o c tin v trng thi sn sng ca TBN. o Kim tra trng thi sn sng. Nu cha, My tnh li c v kim tra trng thi sn sng. - My tnh trao i tin vi TBN. Phng php trao i ny thc hin khi tc trao i tin ca TBN chm so vi My tnh
3.2. Trao i tin ngt vi x l

Phng php trao i tin ny khc phc nhc im ca cc phng php trn. Trnh t nh sau: (1) My tnh ang thc hin chui lnh ca mt chng trnh no . (2) TBN c yu cu trao i tin, s gi tn hiu yu cu trao i tin ( yu cu ngt INTR) (3) My tnh (c th l VXL ) a tn hiu chp nhn (xc nhn ngt INTA) (4) Chng trnh chnh b ngt, My tnh chuyn sang chng trnh con phc v ngt tc l chng trnh con trao i tin cho TBN yu cu. (5) Chng trnh chnh li tip tc thc hin ch b ngt. 3.2.1 Cc loi ngt ca my PC Cc loi ngt Ngi ta chia ngt thnh hai loi: ngt cng v ngt mm Ngt cng: cn gi l ngt ngoi v do nguyn nhn bn ngoi. VXL c cc li vo dnh cho ngt ngoi. Khi c tn hiu vo li vo ny, chng trnh VXL ang thc hin s b dng. Ngt NMI ( Non maskable Interrupt) - Ngt khng che c : Khi c ngt ny, VXL dng chng trnh sau lnh ang thc hin, thanh ghi a ch lnh (IP) v thanh ghi ch th flag c lu gi, 2 bit IF (Interrupt Flag) va TF (Trap Flag) b xo v 0 cm ngt ngoi tip theo v khng c by. Mun cho php hay khng cho php ngt ny xy ra, chng ta dng mt triger (flip flop) mc li vo ngt trc khi a vo li vo ngt NMI. Ngt INTR: o Ngt ny c cho php hay cm ngt bng cch lp hay xo bit IF ca thanh ghi flag. Lp bi lnh STI (Set Interrupt), xo bi lnh CLI (Clear interupt) o Thng c ni vi li ra yu cu ngt ca vi mch x l u tin ngt (8214, 8259). Ngt reset :
Chng trnh Chng trnh con phc v ngt
Ngt
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Ngt mm: (hay ngt bn trong do lnh ca chng trnh) do VXL gp cc lnh gy ra ngt hoc tnh hung c bit khi thc hin lnh (ngt logic) v ngt ca h iu hnh. - Ngt do lnh: l ngt khi thc hin cc lnh CALL, HLT, INT - Ngt logic hay cc ngoi tr: xy ra khi gp cc tnh hung c bit sau: o Chia mt s cho 0 o Trn ni dung thanh ghi hay b nh o Thc hin tng bc (vector 1) o im dng ( Break point) chng trnh do ngi dung chng trnh s dng nh trc (Vect 3) - Ngt ca h iu hnh: l cc ngt do h iu hnh quy nh phc v trao i tin ca cc TBN (bn phm, my in, vv) nh INT 10, INT 16, INT 21, .v.v..) Ngt ca My tnh PC (8086, 80286 ) Cc ngt khng hon ton c lin kt vi cc thit b ngoi. H VXL 8086 cung cp 256 ngt, a phn trong s chng l ch phc v nh ngt phn mm. H 8086 c mt bng vecter ngt gi a ch ca cc chng trnh phc v ngt. Mi a ch l 4 byte. Trong cc my PC, ch c 15 ngt dnh cho phn cng v 1 ngt khng che c. Phn cn li c s dng cho cc ngt phn mm v cc b x l ngoi l. B x l ngoi l l cc chng trnh tng t nh ISR nhng x l cc ngt khi xut hin li. V d nh vector ngt u tin gi a ch ca ngoi l Divide by Zero (li chia cho 0). Khi xut hin li ny VXL nhy sang a ch 0000:0000 v thc hin chng trnh c a ch lu y. INT IRQ Common Uses (Hex) 00 - 01 Exception Handlers 02 03 - 07 08 09 0A 0B 0C 0D 0E 0F 10 - 6F 70 Non-Maskable IRQ Exception Handlers Hardware IRQ0 Hardware IRQ1 Hardware IRQ2 Hardware IRQ3 Hardware IRQ4 Hardware IRQ5 Hardware IRQ6 Hardware IRQ7 Software Interrupts Hardware IRQ8 Non-Maskable IRQ (Parity Errors) System Timer Keyboard Redirected Serial Comms. COM2/COM4 Serial Comms. COM1/COM3 Reserved/Sound Card Floppy Disk Controller Parallel Comms. Real Time Clock
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71 72 73 74 75 76 77 78 - FF
Hardware IRQ9 Hardware IRQ10 Hardware IRQ11 Hardware IRQ12 Hardware IRQ13 Hardware IRQ14 Hardware IRQ15 Software Interrupts
Redirected IRQ2 Reserved Reserved PS/2 Mouse Math's Co-Processor Hard Disk Drive Reserved -
Th tc x l (p ng) ngt chng trnh Khi c mt tin hiu yu cu ngt chng chnh a vo chn yu cu ngt (INTR), qu trnh ngt chng trnh c din ra theo cc bc sau: Lu gi tin v trng thi ca VXL lc c tn hiu yu cu ngt v ni chng trnh b gin on. VXL gi tn hiu xc nhn hay cho php ngt INTA v c vector ngt. Chuyn sang chng trnh phc v ngt. Tr v ch chng trnh chnh b ngt v tip tc thc hin chng trnh . Lu gi tin v ch b ngt chng trnh: cui mi chu trnh lnh, VXL 8086 ( cng nh 80286) kim tra xem c yu cu ngt no gi ti khng. Nu c yu cu, VXL tin hnh lu tr tin v ni b ngt chng trnh ( dng lnh PUSH vo vng nh ngn xp m a ch ch th bi thanh ghi SP). Cc tin l: - Thanh ghi c Flag FR (Flag Register) - Con tr lnh IP (Instruction Pointer) - Thanh ghi on lnh CS (Code Segment register) Gi tn hiu cho php (xc nhn ) ngt v c vector ngt: Sau khi lu tr tin v v tr b ngt ca chng trnh chnh, VXL gi tn hiu xc nhn ngt INTA (Interrupt Acknowledge) cho KGN ca TBN. Tu cch t chc ngt v to vector ngt, VXL s dng tn hiu ny c vector ngt tng ng ca KGN vo thanh ghi cha A. VXL c ni dung ca nh c a ch l vector ngt bit c a ch u tin ca chng trnh con phc v ngt ( chng trnh trao i tin). Thc hin chng trnh con phc v ngt l chng trnh m a ch lnh u tin nm trong nh c a ch l vector ngt. Kt thc chng trnh con ny, c lnh tr v (RET - return) VXL tip tc thc hin chng trnh chnh. Tip tc thc hin chng trnh chnh:
34 Nguyn Tun Linh BM KTMT Khoa in T
Sau khi gp lnh tr v (RET), VXL tin hnh c v hi phc cc tin ca VXL lc b ngt chng trnh ghi nh ch ngt chng trnh (bng lnh POP cc nh ngn xp). Qua trnh c ra ny xy ra ngc li vi qu trnh ghi vo (o quy lut LIFO Last In First Out) v ni dung ca: Thanh ghi con tr lnh (IP) tr v lch (offset) ca a ch lnh tip theo ca chng trnh chnh b ngt trong mng nh lnh (CS). Thanh ghi mng lnh (CS) v a ch on u tin ca vng nh dnh cho chng trnh chnh b ngt. Thanh ghi flag lc b ngt chng trnh. 3.2.2 X l ngt cng trong IBM - PC: VXL 80x86 c 3 chn dng cho ngt cng l: INTR: Interrupt Request NMI: NonMaskable Interrupt /INTA: Interupt Acknowledge INTR l tn hiu u vo yu cu ngt ca VXL v n c th che hay cho php thng qua lnh CLI (Clear Interrupt) v STI (Set Interrupt) NMI tng t INTR nhng khng che c bng lnh INTR v NMI c th c kch hot t bn ngoi bng cch ni vo in p 5V vo chn tng ng ca VXL. Nh vy VXL ch c kh nng phc v mt yu cu ngt cng t TBN. m rng kh nng phc v ngt ngoi IBM - PC s dng thm vi mch x l ngt cng lp trnh c PIC (Programmable Interrupt Controller) 8259. S dng PIC 8259 ni vo chn INTR c th m rng s lng ngt cng ln n 64
RAM ROM
System bus
INT
INT /INTA
VXL
Interrupt Controller
IR7 . . . IR0
KGN1 ...
KGN8
Reset
NMI C ch th c hi n ng t c ng
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Vi mch x l ngt 8259 S khi:

IN T
D0 D7 B m d liu
Logic iu khin
A0
Logic c/ghi ng dy ni
Thanh ghi phc v (ISR)
Gii quyt u tin (PR)
Thanh ghi yu cu ngt
IR0 . . . . IRn
CAS0 CAS1 CAS2
B so snh v ni tng
Thanh ghi che ngt (IMR)
S khi 8259
Cc chn: IR0 IR7 (Chn 18 25) D0 D7 (Chn 11 4) A0 (chn 27) CS (Chn 11) WR (chn 2) RD ( chn 3) CAS0 2 (Chn 12,13,15) SP (chn 16) l ch (Master). (Slave) INTA (chn 26) INT (chn 17) Cu trc PIC 8259
: Cc li vo yu cu ngt : Cc bit s liu (2 chiu) : a ch chn thanh ghi lnh : Chn vi mch (chip select) : Li vo lnh ghi : Li vo lnh c : Li vo mc ni tng : Trong ch khng m, nu
SP = 1 th 8259
SP = 0 th l t : Li vo xc nhn ngt : Li ra yu cu ngt chng trnh
Thanh ghi yu cu ngt IRR (Interrupt Request Register): ghi tm mc ngt (IR0 IR7) t TBN. Thanh ghi Ngt ang phc v ISR (In Service Register): ghi mc ngt ang s dng. Thanh ghi mt n ngt IMR (Interrupt Mask Register). Mch logic gii quyt u tin PR (Priority Resolver)
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Khi logic iu khin: x l ngt, a yu cu (INT) v xc nhn ngt (INTA) B m ng tn hiu s liu: m ghi vo cc thanh ghi v m c cc s liu t cc thanh ghi. Logic iu khin c/ghi: to cc tn hiu ghi v c cc thanh ghi m. B m ni tng/so snh: chn cc vi mch 8259 t trong mt vi mch 8259 ch. i vi IBM - PC, 2 PIC c s dng m rng ra 15 ngt cng. PIC1 qun l u vo ngt IRQ0 - 7, PIC2 dnh cho IRQ8 - 15. PIC2 c ni tng ?ln PIC1 qua ng IRQ2 (Do nu ta chn ngt IRQ2 th ton b IRQ 8 - 15 cng b che.
Port 20H INT IR0 IR1 IR2 Pri PIC IR3 : INT /INT IR7 CAS0-2 Port A0H IR0 IR1 Sec PIC IR2 INT : CAS0-2 /INT IR7 IRQ1 IRQ8 IRQ9 IRQ1 : IRQ0 IRQ1 IRQ3 : IRQ7
MPU
/INT
S ghp ni ni tng PIC trong IBM - PC

3.2.3 Lp trnh x l ngt cng: Trong my IBM - PC c 2 PIC c nh v ti cc a ch l PIC1 - 20H, PIC2 A0H. Cc PIC c khi to bi BIOS, do ta ch cn quan tm ti 2 lnh khi lm vic vi chng. Lnh th nht tc ng vo t iu khin OCW1 thit lp vic che ngt Nu mun che ngt no th ta xo bit tng ng vi ngt v 0. T iu khin OCW1 c gi ti a ch base + 1. Lnh th 2 l lnh End of Interrupt (EOI). Lnh ny c gi ti PIC khi kt thc chng trnh con x l ngt reset PIC. Lnh EOI c gi ti PIC bng cch ghi gi tr 20H vo thanh ghi c a ch base. Cu trc chung ca mt chng trnh c s dng phng php vo ra bng ngt vit bng Pascal nh sau: program <Tn chng trnh>;
uses Crt, Dos; const {PIC Constants} PIC1 = $20; PIC1_OCW1 = $21; PIC2 = $A0; PIC2_OCW1 = $A1; var OldVector: procedure; {$F+} procedure MyISR; interrupt; var begin ... {Chng trnh i u khi n vo/ra d ... ` Port[MasterPIC] := EOI; end; {$F-}
li u}
{Chng trnh chnh} BEGIN {Thi t l p vector ng t} GetIntVec ($0C,@OldVector); {Lu vector ng t c} SetIntVec ($0C,Addr (MyISR)); {Thay vector ng t} Port[MasterOCW1] := Port[MasterOCW1] and $EF;{cho php ng t IRQ3} . . . {Chng trnh chnh} . . . SetIntVec ($0C,@OldVector); {Tr l i vector ng t c} Port[MasterOCW1] := Port[MasterOCW1] or $10; {Che ng t IRQ3} END.
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3.3. Trao i tin trc tip b nh

Phng php trao i d liu theo chng trnh s chm do:
- VXL phi gii m v thc hin lnh. - Trao i d liu thc hin tng byte thng qua thanh ghi AX ca VXL K thut vo/ra DMA (Direct Memory Access) l phng php truy nhp trc tip ti b nh.
Data Bus
HOLD VXL
DREQ DMAC MEMORY Disk Controller
HLDA
DACK
Address Bus Control Bus (IOR, IOW, MEMR, MEMW) Hot ng ca DMAC
3.3.1 C ch hot ng: VXL khi to TBN. TBN khi xng vic truyn s liu bng cch s dng cc thng tin cung cp bi VXL thng qua qu trnh khi to. Khi d liu c truyn trc tip gia TBN v b nh thng qua s iu khin ca b iu khin DMA (DMAC). 3.3.2 Hot ng ca DMAC: Khi to: Trc khi a DMAC vo hot ng, Phi c chng trnh khi to cho n. Qu trnh khi to s cung cp cho DMAC thng tin cn thit hot ng. l cc thng tin nh: a ch bt u ca khi d liu, kch thc khi d liu, chiu c/ghi d liu, s hiu cng ca TBN. Hot ng: Xt trng hp truyn mt khi d liu t b nh ra TBN. (1) Bc 1: TBN yu cu DMA bng cch t tn hiu DREQ ln mc cao (2) Bc 2: DMAC t tn hiu mc cao vo chn HRQ (Hold Request) gi tn hiu yu cu treo bus cho VXL, bo cho VXL bit DMAC cn s dng bus.
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(3) Bc 3: VXL kt thc chu k bus hin ti, chuyn cc cng ghp ni vi bus sang mc tr khng cao v tr li yu cu DMA bng tn hiu mc cao chn HDLA ( Hold Acknoledge) bo cho DMAC c quyn s dng bus (4) Bc 4: DMAC kch hot tn hiu DACK bo cho TBN bit n s bt u iu khin vic truyn d liu. (5) Bc 5: DMAC bt u truyn d liu t b nh ti TBN nh sau: DMAC t a ch ca byte u tin ca khi d liu ln bus a ch Kch hot tn hiu /MEMR c byte d liu t b nh ln bus d liu t a ch ca cng TBN ln bus a ch Kch hot tn hiu IOW ghi byte d liu ang c trn bus d liu ra TBN Gim gi tr m v tng gi tr a ch Lp li qu trnh trn cho ti khi gi tr m bng 0. (6) Sau khi qu trnh DMA kt thc, DMAC xo gi tr HRQ xung mc thp, tr quyn iu khin bus cho VXL.
3.3.3 Chip iu khin truy nhp b nh trc tip DMAC 8237 DMAC 8237 c th thc hin truyn d liu theo 3 kiu: kiu dc (t b nh ra thit b ngoi vi), kiu ghi (t thit b ngoi vi n b nh) v kiu kim tra. Khi Timing and Control (nh thi v iu khin): To cc tn hiu nh thi v iu khin cho bus ngoi (external bus). Cc tn hiu ny c ng b vi xung clock a vo DMAC (tn s xung clock ti a l 5 MHz). Khi Priority encoder and rotating priority logic (m ho u tin v quay mc u tin): DMAC 8237A c 2 m hnh u tin: m hnh u tin c nh (fixed priority) v m hnh u tin quay (rotating priority). Trong m hnh u tin c nh, knh 0 s c mc u tin cao nht cn knh 3 c mc u tin thp nht. Cn i vi m hnh u tin quay th mc u tin khi khi dng ging nh m hnh u tin c nh nhng khi yu cu DMA ti mt knh no d c phc v th s c t xung mc u tin thp nht. Khi Command Control (iu khin lnh): Gii m cc thanh ghi lnh (xc nh thanh ghi s c truy xut v loi hot ng cn thc hin).
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Cc thanh ghi: DMAC 8237A c tt c 12 loi thanh ghi ni khc nhau:
Chc nng cc chn ca 8237A: CLK (Input): tn hiu xung clock ca mch. Tn hiu ny thng c ly t 8284 sau khi qua cng o.
CS (Input): thng c ni vi b gii m a ch. RESET (Input): khi dng 8237A, c ni vi ng RESET ca 8284. Khi Reset th thanh ghi mt n c lp cn cc phn sau b xo: Thanh ghi lnh Thanh ghi trng thi Thanh ghi yu cu Thanh ghi tm Flip-flop du/cui (First/Last flip-flop) READY (Input): ni vi READY ca CPU to chu k i khi truy xut cc thit b ngoi vi hay b nh chm. HLDA (Hold Acknowledge) (Input): tn hiu chp nhn yu cu treo t CPU DRQ0 DRQ3 (DMA Request) (Input): cc tn hiu yu cu treo t thit b ngoi vi DB0 DB7 (Input, Output): ni n bus a ch v d liu ca CPU IOR , IOW (Input, Output): s dng trong cc chu k dc v ghi EOP (End Of Process) (Input,Output): bt buc DMAC kt thc qu trnh DMA nu l ng vo hay dng bo cho mt knh bit l d liu chuyn xong (Terminal count TC), thng dng nh yu cu ngt CPU kt thc qu trnh DMA. A0 A3 (Input, Output): chn cc thanh ghi trong 8237A khi lp trnh hay dng cha 4 bit a ch thp. A4 A7 (Output): cha 4 bit a ch HRQ (Hold Request) (Output): tn hiu yu cu treo n CPU DACK0 DACK3 (DMA Acknowledge) (Output): tn hiu tr li yu cu DMA cho cc knh. AEN (Output): cho php ly a ch vng nh cn trao i ADSTB (Address Strobe) (Output): cht cc bit a ch cao A8 A15 cha trong cc chn DB0 DB7 MEMR , MEMW (Output): dng dc / ghi b nh. Cc thanh ghi ni: Cc thanh ghi ni trong DMAC 8237A c truy xut nh cc bit a ch thp A0 A3
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Chng 3: Th tc trao i tin ca my vi tnh Bit a ch A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 a ch X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 XA XB XC XD XE XF Chn chc nng Thanh ghi a ch b nh knh 0 Thanh ghi m t knh 0 Thanh ghi a ch b nh knh 1 Thanh ghi m t knh 1 Thanh ghi a ch b nh knh 2 Thanh ghi m t knh 2 Thanh ghi a ch b nh knh 3 Thanh ghi m t knh 3 Thanh ghi trng thi / lnh Thanh ghi yu cu Thanh ghi mt n cho mt knh Thanh ghi ch Xo flip-flop u/cui Xo ton b cc thanh ghi / c thanh ghi tm Xo thanh ghi mt n Thanh ghi mt n R/W? R/W R/W R/W R/W R/W R/W R/W R/W R/W W W W W W/R W W
a ch cc thanh ghi ni dng ghi / c a ch:
Knh 0
/IOR 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
/IOW 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
A3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
A1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
Thanh ghi a ch c s v a ch hin hnh a ch hin hnh B m c s v b m hin hnh B m hin hnh a ch c s v a ch hin hnh a ch hin hnh B m c s v b m hin hnh B m hin hnh a ch c s v a ch hin hnh a ch hin hnh B m c s v b m hin hnh B m hin hnh a ch c s v a ch hin hnh a ch hin hnh B m c s v b m hin hnh B m hin hnh
R/W? W R W R W R W R W R W R WR WR
a ch cc thanh ghi trng thi v iu khin:

/IOR 1 0 1 1 1 1 1 0 1 0 1 0
Thanh ghi /IOW A3 A2 A1 A0 0 1 0 0 0 Ghi thanh ghi lnh 1 1 0 0 0 c thanh ghi trng thi 0 0 0 0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 0 1 1 0 0 0 1 1 1 1 1 0 1 0 1 1 0 0 1 1 a ch c s v a ch hin hnh a ch hin hnh B m c s v b m hin hnh B m hin hnh Ghi thanh ghi yu cu Ghi thanh ghi mt n Ghi thanh ghi ch Xo flip-flop u/cui Xo tt c cc thanh ghi ni
Mch 8237A-5 cha 4 knh trao i d liu DMA vi mc u tin lp trnh c. 8237A-5 c tc truyn 1 MBps cho mi knh v 1 knh c th truyn 1 mng c di 64 KB. c th s dng mch DMAC 8237A, ta cn to tn hiu iu khin nh sau:
Tn hiu iu khin cho h thng lm vic vi DMAC 8237A Tn hiu AEN t 8237A dng cm cc tn hiu iu khin t CPU khi DMAC nm quyn iu khin bus.
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Chng 4: Rnh cm m rng
CHNG 4. GHP NI QUA RNH CM M RNG

Mc tiu: Trnh by cc vn v ghp ni my tnh vi thit b ngoi vi thng qua cc khe cm (slot) ca my tnh PC. Cu trc, nguyn l v cch ghp ni ca cc khe cm thng dng nh ISA, PCI. Tm tt chng: t vn Bus PC Bus ISA (16 bit) Bus PCI Ghp ni qua khe cm m rng
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t vn Khi bn lun v cu trc my tnh ta thng cp n cc cu trc bus, cc ng dn bus nh bus d liu, bus iu khin , v.v. Cc rnh cm m rng l mt dng th hin bng phn cng ca bus trn bn mch chnh, trn c th cm thm cc card m rng thay i hoc nng cp cu hnh ca my tnh. S ra i ca cc loi rnh cm m rng gn lin vi s pht trin ca k thut my tnh. T trc n nay c n 8 kiu bus m rng c s dng cho my tnh c nhn. Vic phn loi cc bus m rng da trn s cc bit d liu m chng x l ng thi. l cc bus: - Bus PC (Cn gi l ISA 8 bit) S chn khe cm ISA 8 bit - Bus ISA (16 bit) Pha mch in Pha linh kin - Bus PC/MCIA (16 bit) GND B01 A01 /IOCHCK - Bus VESA local (32bit) Reset B02 A02 D7 + 5V B03 A03 D6 - Bus SCSI (16/ 32 bit) IRQ2 B04 A04 D5 - Bus EISA (32 bit) - 5V B05 A05 D4 - Bus MCA (32 bit) DREQ2 B06 A06 D3 - Bus PCI (32/ 64 bit) - 12V B07 A07 D2 D tr B08 A08 D1 - Bus AGP (32/ 64 bit)
+ 12V GND /MEMW /MEMR /IOW /IOR /DACK3 DERQ3 /DACK1 DREQ1 /DACK0 CLK IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 /DACK2 TC ALE + 5V OSC GND B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 D0 /IOCHRDY AEN A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
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4.1. Bus PC
Bus PC l loi bus xut hin trn my tnh PC/XT u tin nn c gi lun l bus PC. Loi bus ny tn dng kin trc ca b VXL Intel 8088, nn c mt bus d liu 8 bit v ngoi v bus a ch 20 bit. Rnh cm ni vi bus PC c 62 chn cho php cm vo mt card m rng lm t mch in 2 mt. V trn bus ny c 8 bit d liu c truyn ng thi nn bus PC cn c gi l bus PCI 8 bit Tc truyn ca bus PC c c nh 4.77 MHz i vi bus ISA 8 bit ta cn quan tm n mt s ng tn hiu chnh sau: Tn hiu Hng M t A0 - A19 I/O 20 ng tn hiu a ch dng nh a ch cho b nh v cc thit b ngoi vi D0 - D7 I/O 8 ng tn hiu to thnh BUS d liu cho vi x l, b nh v cc thit b ngoi vi Reset Out Sau khi bt my tnh hoc sau khi khi ng li, ng dn Reset s kch hot trong thi gian ngn a card c cm vo n mt trng thi ban u xc nh. /IOW Out Input/Output/Write: Tn hiu ny s kch hot khi truy nhp ghi ln mt card m rng. Mc thp ch ra rng cc d liu c gi tr ang ch a ra bus d liu. Cc d liu c n nhn bng sn trc /IOR Out Input/Output/Read: Mc thp ca ng dn a ch ny bo hiu s truy nhp c trn mt card m rng. Trong thi gian ny cc d liu c gi tr cn phi sp xp sau c n nhn bng sn trc AEN Out Address Enable ng dn iu khin AEN dng phn bit chu trnh truy nhp DMA v chu trnh truy nhp b vi x l. mc cao DMA gim st qua bus a ch v bus d liu. ng dn c hiu lc mc thp. ng dn ny cn phi c s dng cho qu trnh gii m a ch bi card m rng.
4.2. Bus ISA (16 bit)

Do cch t chc rnh cm nh vy nn mt card PC vn c th cm vo mt khe cm ca bus ISA. Card ISA rt ph bin bi v chng th hin tnh nng u vit i vi hu ht cc ng dng ghp ni. Cc linh kin c s dng trn card u rt r, cho nn trn thc t vic ghp ni bng cc card m rng ISA t ra l cng ngh qua th thch v ng tin cy. T tn gi cho thy : y l loi bus c kin trc theo tiu chun cng nghip (ISA: Industry standard architecture). Trong cc ti liu gi bus PC l bus ISA 8 bit th loi bus ny thng c phn bit r l ISA 16 bit. Cng ty my tnh IBM pht trin bus ISA (kin trc theo chun cng nghip) dng cho my tnh AT (Advanced Technology) da trn b vi x l 80286. im mnh r nt ca bus ny l c th cho
php cng mt lc x l hoc trao i vi 16 bit d liu. bo m tnh tng thch vi bus PC, cc nh thit k b xung rnh cm th hai thng hng vi rnh cm PC 8 Bit, trn c cha 8 bit d liu v 4 ng dn a ch. Nh vy, bus ISA c mt bus d liu 16 bit v chnh v l i khi bus ISA cn c gi r l ISA 16 bit phn bit vi 8 bit. Ngoi ra bus ISA cn c mt bus a ch 24 bit, cho php nhiu nht l 16 Mbyte b nh c th nh a ch c v ging nh bus PC n s dng tc ng h c nh, nhng khc v gi tr, c th l bng 8,33MHz. Nh vy tc truyn d liu cc i l 2 byte (16 bit) trong mi chu k gi nhp, cho ra mt lu lng cc i l 16 MB/giy. Trong cc my tnh c tn s gi nhp chy nhanh hn 8 MHz, bus ISA chy chm hn nhng phn cn li ca my tnh.Do cch t chc rnh cm nh trn nn mt card PC vn c th cm c vo trong rnh cm ca bus ISA. Cc card ISA rt ph bin bi v chng th hin tnh nng u vit i vi hu ht cc ng dng ghp ni. Cc linh kin c s dng trn card u rt r, cho nn trn thc t vic ghp ni bng card m rng ISA t ra l cng ngh qua th thch v ng tin cy. Nhng ng dng tiu biu c th k l: Card vo/ra ni tip v song song, card ni mng v card m thanh. C cc tip im c b tr trn hai mt, c nh s l A,B,C,D. Cc ng a ch: S ng a ch trong cc my tnh l khc nhau, cc XT c 20 ng a ch,cc my AT c 24 ng a ch t A0 (A23 tuy nhin cc ng A20 (A23 dng cho vic qun l,nn thc t cc ng a ch cn li l A0 ( A19 Cc ng t A0 ( A19 i ra t my tnh hot ng mc th cao, cc ng ny c dng a ch ho b nh hay thit b vo ra .A0 l cc bit gi tr nh nht (LSB) ,A19 c gi tr cao nht (MSB) cc ng ny c iu khin nh VXL trong chu trnh bus c v vit b nh hay cng vo ra. Ngoi ra chng cn c iu khin nh logic xm nhp trc tip vo b nh trong chu trnh DMA. B vi x l qua vic s dng cc lnh in v out c th a ch 64Kbyte a ch cng vo ra nhng thit k PC khng cho php s dng ton b cc a ch ny v cng vo ra chim cc nh t 300h 3FFh nn ch c 10 bit thp nht ca ng a ch l c s dng a ch ca thit b v a ch cng vo ra. Nh vy ch cc ng a ch A0-A19 l c s dng cho vic gii m a ch cc thit b v a ch cng vo ra. Bit 9 l mt bit c ngha c bit: -Khi bit ny khng tch cc h ch cho php s liu t cc thit b ngoi vi v cc thit b vo ra trong Mainboard trao i vi n khi bit 9 l khng tch cc chng chim a ch t 000h 0FFh . Khi 9 bit tch cc l cc bit cho php s lu c ghi c t cc cng vo ra ca khe cm chng chim cc a ch 300h 3FFh. iu ny c ngha l vi cng vo 1024 a ch c chia lm 2 phn 512 a ch dng cho Mainboard v 512 a ch dng cho khe cm. Cc ng s liu:
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Cc ng ny chuyn s liu gia VXL vi cng vo ra v b nh .S lng cc ng bus s liu quyt nh s bit c th truyn ng thi n hoc i t b nh. Cc my XT c 8 ng s liu D0 ( D7 c ngha l c th truyn 1 byte. My AT cos 16 ng s liu D0 ( D15 tc c th truyn ng thi 2 byte. Cc ng s liu D0 ( D15 l cc ng 2 chiu c th hot ng mc th cao .D0 l (LSB), D15 l (MSB) khi VXL a ra chu trnh bus n iu khin bus ti a ch ca nh hay cng vo ra xc nh, iu khin hng truyn ni nhn s liu. Khi chu trnh ghi bt u s liu trn bus l s liu s c ghi vo b nh hay cng vo ra .S liu phi n nh trc sn tng ca tn hiu iu khin IOW v MEMW . Sn tng ca cc tn hiu ny thng dng to nhp cho s liu trn bus s liu ghi vo b nh hoc cc thanh ghi ca cng vo ra. Trong chu trnh s liu a ch nh hay a ch thanh ghi cng vo ra s liu phi t ln bus s liu trc sn tng ca tn hiu iu khin IOW v MEMW . Mc ch ca chu trnh l a s liu ra mt trong cc a ch nh hoc cng vo ra. Tn hiu cho php cht a ch ALE y l tn hiu ra c iu khin nh b iu khin bus n c ch rng bus a ch by gi n nh c th bts u chu trnh bus. Tn hiu ny dng cht thng tin a ch t bus a ch hoc bus s liu ca b ca VXL. Tn hiu ALE ng b vi chu trnh knh ca Bus khi n bt u chu trnh Bus cc a ch ca b VXL c vi sn gim ca tn hiu ALE. Tn hiu cho php a ch AEN . Tn hiu ny c s dng bo cho b VXL v cc thit b t cc knh vo/ra cho php truyn DMA c thc hin khi ng ny tch cc. B iu khn DMA iu khin Bus a ch cc ng c lch v ghi s liu. Tn hiu c cng vo/ra .
Tn hiu ny hot ng mc thp cng l tn hiu ra t my tnh c iu khin bi b iu khin Bus.Nh tn hiu ny thit b vo ra t s liu ln bus s liu v bo cho cng vo ra bit chu trnh bus ca VXL lc ny l chu trnh c. Cng vo ra v a ch trong bus a ch (l a ch ca cng vo ra) phn ng li bng cch t s liu ca chng ln bus s liu. V tn hiu ny hot ng mc thp nn cng vo ra cn phi nh s liu trn bus s liu m bo cho VXL nhn c s liu. Tn hiu ghi ca cng vo ra.
Tn hiu ny hot ng mc th thp c iu khin t b iu khin bus. N ch ra rng chu trnh ca bus ca h VXL l chu trnh ghi ca cng vo ra. a ch trong bus a ch l a ch ca cng vo ra.
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Khi tn hiu ny mc th thp th s liu trong bus s liu n nh nh vy cng s liu cn phi to nhp hay cht bng vic s dng sn tng ca tn hiu ny. Khi xut hin chu trnh ca bus tn hiu ny quy nh bi b iu khin DMA. Sau tn hiu /IOW c dng vit s liu ln bus s liu t b nh. Cng vo/ra c chn nh tn hiu.
4.3. Bus PCI

Cng ty Intel xy dng nn mt tiu chun ghp ni mi c tn l bus cc b PCI (Peripheral Component Interconnection - Kt ni cc thnh phn ngoi vi) hay thng gi tt l bus PCI, dng cho b x l Pentium. Bus ny cho php truy nhp rt nhanh ti b nh, b iu khin a, card m thanh, card ho. Vi mch ghp ni dng cho bus ny l chip PCI 82430 cho php ghp ni trc tip vi bus. Mt s c im chnh: - Bus PCI truyn d liu bng tc ca ng h h thng cho php truyn d liu vi tc cao hn nhiu so vi bus ISA. - C th hot ng vi 64 bit - Tc ti a t c l 264 Mbyte/s - Rnh cm PCI c mt chn cao hn do vy khng tng thch vi cc card ISA.
4.4. Ghp ni qua khe cm m rng

4.4.1 Mt s c im ca Card ISA Kch thc ln nht ca cc card ISA 8 bit l: Chiu cao: 106,7 mm (hay 4.2 inch) Chiu di 333.5 mm ( hay 13.13 inch) Chiu dy - k c linh kin - 12.7 mm (hay 0.5 inch) Cc ng tn hiu ca khe cm b tr c 2 pha, v vy card m rng bao gi cng phi l bn mch in 2 mt. 4.4.2 Gii m a ch v kt ni Bus d liu i vi my PC vng a ch 300 - 31FH c d tnh dnh ring cho card m rng cm thm vo. Cc ng a ch s dng i vi vng ny l A0 - A9. Trn mt card m rng thng c nhiu khi chc nng nh b bin i tng t/s ADC, b bin i s - tng t DAC, khi xut nhp d liu s, iu khin hin th, .v.v. . Cc khi ny c trao i di nhng a ch khc nhau t my tnh. Do , trn card m rng phi c thm mt b gii m a ch. B gii m a ch c nhim v so snh a ch trn bus a ch ca my tnh vi cc a ch c thit lp trc cho cc khi chc nng ca card m rng. Khi a ch c s thng nht vi khi no th khi tng ng s c kch hot thng qua mt ng tn hiu logic t u ra ca b gii m. Khi c kch hot, khi mi c th tin hnh s trao i thng tin vi my tnh.
B gii m a ch 74HC688 so snh cc ng dn a ch A2 - A9 xem c thng nht vi a ch thit lp trc ca card m rng bng chuyn mch DIP. 74HC688 so snh cc cp bit xem c ging nhau khng. Khi cc cp ng nht thi s to ra mt tn hiu mc thp u ra. Ngoi ra khi gii m cn phi quan tm n ng tn hiu AEN (Address ENable). ng ny cho bit CPU hay DMAC ang chim quyn s dng bus. Khi tn hiu ny mc thp th card m rng mi c s dng cc bus. Tn hiu AEN c a ti u vo /G ca 74HC688 cho php b gii m hot ng. Cc ng tn hiu A0, A1, IOR, IOW cng c s dng trong b gii m bng cch kt hp vi cc IC cng logic AND, OR v vi mch gii m 74HC138 to thnh cc ng iu khin c ghi cho tng khi chc nng trn card B gii m logic ng thi m nhn vai tr iu khin b m bus 2 chiu 74HC245. B ny ni cc ng dn d liu ca rnh cm PC vi cc ng dn ca card m rng. Cch ghp ni ny rt quan trng, nh vy m cc mc tn hiu trn ng dn d liu khng b nh hng. N c cha 8 vi mch m vi cc li ra 3 trng thi trao i thng tin gia cc ng dn bus d liu theo 2 hng. Hng truyn d liu c xc nh bng chn DIR: DIR = 0, d liu c chuyn t B sang A. Vic chuyn hng d liu cho php qun l n gin bng tn hiu /IOR. Ta c th ni trc tip ra chn DIR. Qua m bo b m ch cho php d liu a vo t bn
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ngoi a ln bus d liu ca my tnh khi PC thc hin mt qu trnh truy nhp c (/IOR = 0)
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Chng 5: Ghp ni trao i tin song song
CHNG 5. GHP NI TRAO I TIN SONG SONG

Mc tiu: Trnh by cc kin thc c bn v ghp ni v trao i d liu qua cc giao din song song. Tm hiu cc giao din song song t c bn n nng cao v cu trc, nguyn l hot ng, cch ghp ni v lp trnh iu khin cho cc giao din ny.
Tm tt chng: Khi ghp ni song song n gin Cc vi mch m, cht (74LS245, 74LS373) Vi mch PPI 8255A Ghp ni song song qua cng my in
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Khi ghp ni song song n gin Cng vo n gin: Gm mt b gii m a ch - lnh v cc cng vo 3 trng thi a trc tip s liu song song t thanh ghi m s liu t TBN vo ng tn hiu s liu (D0 - Dn) ca My tnh
A0 - An RD D0 D1 D2 D3 DI0 DI1 DI2 DI3 Gii m a ch
S ca vo n gin
Cng ra n gin: Cng c b gii m a ch - lnh, nhng c thm cc thanh ghi cht s liu ra ghi s liu a ra t My tnh. Li ra c th c thm s 3 trng thi c lp TBN vi bus ca My tnh
A0 - An Gii m i ch
WR D Q C D1 D Q C D2 D Q C D3 D Q C DO3 DO2 DO1 DO0
D0
Ca ra n gin khng c i thoi
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5.1. Cc vi mch m, cht (74LS245, 74LS373)

5.1.1 Vi mch m 74LS245:
Inputs DI G R L L H L H X
Function A bus B bus Outputs A=B B=A Z
Outpu Input t Input Output High Impedance
Vi mch 74LS245 cho tn hiu vo ra 2 chiu dng m s liu trong my tnh PC/XT (VXL 8086). Vi mch ny c 2 ng iu khin chnh, tn hiu /G l tn hiu cho php vi mch hot ng, khi /G mc cao, cc chn d liu ca vi mch trng thai tr khng cao. Tn hiu DIR xc nh chiu truyn d liu. DIR = 1 d liu c truyn t A sang B, ngc li, khi DIR = 0 d liu c truyn t B sang A 5.1.2 Vi mch cht 74LS373:
Vi mch bao gm cc vi mch cht v cc vi mch cng 3 trng thi. Vi mch ny thng c dng cht a ch trong my PC/XT v cht d liu trong cc ng dng ghp ni my tnh. C 2 ng tn hiu iu khin l /OE v LE. Tn hiu /OE l tn hiu cho php hot ng ca vi mch. Khi /OE mc cao, cc cng ca vi mch trng thi tr khng cao. Tn hiu LE l tn hiu cho php cht, tn hiu ny tch cc mc dng. i vi 74LS373, khi LE mc cao, tn hiu a vo t cng D c a ra cng Q. Khi LE chuyn sang mc thp, tn hiu cng Q c cht li.
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5.2. Vi mch PPI 8255A

5.2.1 Gii thiu chung Vi mch vo ra song song lp trnh c PPI (Programable Parallel Interface) 8255 do hng Intel ch to. Ngoi kh nng cho php to mt giao din song song lp trnh c ghp ni vi my tnh, n cn c th hot ng vi cc ch khc nhau v kh nng lp xo bit cng C cho i thoi. Vi mch 8255 ny rt thng dng, thng c trong cc my tnh PC/XT, PC/AT v cc thit b trao i tin khc.
iu khin nhm A
Cng A 8
IO
D0 - D7
PA0 - PA7 Cng C na cao 4
m s liu
IO
PA7 - PA4
iu khin lgic c ghi
A1 A0 Reset
iu khin nhm B
Cng C na thp 4
IO
PA3 - PA0
Cng B 8
IO
PA0 - PA7
S khi ca PPI 8255A Vi mch gm: - B m s liu trao i tin v s liu hai chiu gia PPI v bus ca my tnh. - B logic iu khin c vit: tc l b gii m a ch lnh cho cc thanh ghi m v thanh ghi iu khin. Phn ghp ni vi TBN c: Cng A: thanh ghi m s liu (8 bit), vo hoc ra tu theo chng trnh khi pht Cng B: thanh ghi m s liu (8 bit), vo hoc ra tu theo chng trnh khi pht Cng C: Chia lm 2 na, cao v thp Tu theo ch s dng cho bi t iu khin cng C c th c dng - Trao i s liu vo hoc ra - iu khin hoc i thoi vi TBN v VXL khi cng A v B ch xc lp v xo tng bit PCi
- iu khin hoc i thoi vi TBN v VXL khi cng A v B ch 1 v 2 Cc mch iu khin ni b: C cc khi iu khin (nhm A, nhm B) cc cng A, B v C. 5.2.2 Cc lnh ghi v c cc cng v cc thanh ghi iu khin Vi t hp cc tn hiu a ch (A0, A1), chon vi mch (CS), v cc lnh c ghi (RD, WR) ca VXL, ta c cc lnh ghi c khc nhau cho cc cng (A, B, C ) v thanh ghi iu khin nh bng 3.2, to ra s di chuyn s liu gia ng tn hiu s liu, cc cng v thanh ghi iu khin. Nh vy, vi mch 8255 c c im l khng c lnh c thanh ghi trng thi m dng lnh c c ng C khi vi mch ch 1 v 2, cn ch 0, khng c trng thi. A1 0 0 1 1 0 0 1 1 X A0 0 1 0 1 0 1 0 1 X
CS
RD
WR
Lnh (ca VXL) c cng A c cng B c cng C Ghi cng A Ghi cng B Ghi cng C Thanh ghi iu khin
0 0 0 0 0 0 0 0 1
0 1 1 0 1 1 1 1 X
1 1 1 1 0 0 0 0 X
Trng thi in tr cao Cc lnh ca 8255A
Chiu di chuyn s liu (vi VXL) Cng A -> D0 - D7 Cng B -> D0- D7 Cng C -> D0- D7 Khng c gi tr D0 - D7 -> Cng A D0 - D7 -> Cng B D0 - D7 -> Cng C D0 - D7 -> Thanh ghi iu khin Khng c trao i d liu
5.2.3 Cc t iu khin T iu khin thit lp ch :

Control Word (T iu khin)
D7
Mode Flag 1 = Active
D6
D5
D4
D3
D2
D1
D0
Nhm B Nhm A
Cng C cao
1 = Li v o 0 = Li ra
Cng C thp
Cng B
Cng A
Mode
1 = Mode 1 0 = Mode 0
Mode
00 = Mode 0 01 = Mode 1 0X = Mode 2
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T iu khin lp xo bit:
D7
D3
D2
D1
D0
C lp/xo 0: xo 1: lp
0: Lp xa bit
Bit PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
D3 0 0 0 0 1 1 1 1
D2 0 0 1 1 0 0 1 1
D1 0 1 0 1 0 1 0 1
T IU KHIN LP XO BIT CA VI MCH 8255
Ch 0
WR, RD Port B I/O PB0 - PB7
D0 - D7 8255A Port C I/O PC0 - PC3 I/O PC4 - PC7
A0, A1, CS Port A I/O PA0 - PA7
Ch ny cn c gi l ch vo/ra c s v: - Cc cng A, B, v 2 na ca cng C c s dng c lp vi nhau - Cc cng c th l cng vo hoc ra tu t iu khin ch ghi vo thanh ghi iu khin - S liu ra c cht - S liu vo khng c cht - Khng c tn hiu i thoi vi VXL cng nh TBN. Nu mun c tn hiu i thoi, phi dng cc bit ca cng no ( thng l cng C) cc lp ln 1 v sau l xo v 0 bng cch ghi s liu hoc bng cch xc lp/ xo mt bit PCi ca cng C bi t iu khin vi D7 = 0. Khi cng C phi thit lp ch ra. - Lp xo tng bit ca cng PC - ch 0, ngi ta c th dng cc bit PCi ca cng C lp (t ln 1) v xo (xo v 0) iu khin hoc i thoi vi TBN. Mun vy phi ghi li lnh vi D7 = 0 vo thanh ghi iu khin ca 8255A sau khi ghi li iu khin ch .
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Ch 1:
Port B I/O
PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
Port A I/O
INTRB
PB0 - PB7
INTRA
Ca vo Ca ra
IBFB STBB OBFB ACKB
STBA IBFA I/O I/O I/O
I/O PA0 - PA7
ACKAOBFA
i thoi ca B
i thoi ca A
Ch ny cn gi l ch vo ra c i thoi vi cc bit cng C. Chia thnh 2 nhm. Nhm A gm cng A trao i s liu v na C cao (PC3 PC7) i thoi vi VXL v TBN. Nhm B gm cng B trao i s liu v na C thp (PC0 PC2) i thoi vi VXL v TBN. Chiu v ch 1 ca cng A v B do t iu khin quyt nh, cn cc tn hiu i thoi PCi cn ph thuc chiu cng vo hay ra ca cng A, B PC0 lun l tn hiu ra INTRB: tn hiu yu cu ngt chng trnh cho B PC3 lun l tn hiu ra INTAA: tn hiu yu cu ngt chng trnh cho A PC2 lun l tn hiu vo, nhn cc tn hiu yu cu STBB v xc nhn /ACKB ca thit b ngoi cho cng B chung cho c 2 chiu vo hay ra. Cn na A, nu l cng vo, PC4 nhn /STBA ca thit b ngoi v PC6 nhn /ACK ca thit b ngoi nu cng A l cng ra. Cc bit cn li ca cng C l vo hay ra tu t iu khin ch Ch ra: Mi khi d liu c ghi ra cng, tn hiu /OBF chuyn sang mc tch cc 0 thng bo cho TBN bit d liu c cht cng ra v sn sng cho TBN c. Khi c c d liu, TBN kch hot tn hiu /ACK cho bit c d liu, khi tn hiu /OBF c t ng chuyn v mc cao. /OBF (Output Buffer Full): L tn hiu ra thng bo cho TBN bit d liu c cht cng ra A hoc B.
/ACK (Acknowledge): Tn hiu xc nhn bo v t TBN lm cho chn OBF chuyn ln mc cao. Tn hiu ny thng bo cho 8255 bit TBN nhn d liu.
Cng A: Ch 1, chiu
INTR: Tn hiu ny thng thng dng ngt VXL mi khi TBN gi li tn hiu /ACK INTE (Interrupt Enable): Bit ni, dng cho php hay cm tn hiu INTR. INTEA c lin kt vi PC6 nu cng A hot ng ch ra. PC4 nu ch vo INTEB lin kt vi PC2 vi c chiu ra v vo ca cng B Ch vo: /STB: Chn nhn tn hiu xung cht. Khi c mt xung mc thp tc ng vo chn ny, d liu a t TBN vo 8255 s c cht cng vo. IBF: Khi tn hiu /STB tch cc tn hiu IBF s c chuyn sang mc cao, bo cho TBN bit 8255 cht d liu cng vo. Tn hiu ny s tr v mc thp khi VXL c tn hiu ang cht cng (khi tn hiu /RD tch cc) INTR: Tn hiu ngt VXL, tch cc khi /STB chuyn sang mc cao. Khi c tn hiu /RD tn hiu ny s thi tch cc. Ch 2:
Cng A: Ch 1, chiu
Port B I/O
PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
Port A I/O
INTRA
PB0 - PB7
I/O (Ch 0) i thoi (Ch 1)
STBA IBFA
ACK OBFA
PA0 - PA7 (2 chiu)
Ca B c th ch 0 hoc 1
Ca A ch i thoi 2 chiu
Ch ny ch dng cho cng A vi vo ra hai chiu v cc bit PC3 PC7 dng lm tn hiu hi thoi. Cng B lc ny c th hot ng ch 0 hoc 1, chiu vo hay ra c th t bng t iu khin. V d: Gi thit ta cn thit lp: PPI hot ng ch 0. Cng A vo, B ra, C cao vo, C thp ra. -> Ta c gi tr ca t iu khin l 98H Cng B hot ng ch 1, vo. Cng A hot ng ch 0, ra. Cng C cao ra, cng C thp khng quan tm
- > Gi tr t iu khin: 87H hoc 86H T trng thi Thng thng khi s dng 8255 ch 1 v 2, ta thng dng phng php iu khin bng ngt chng trnh. Tuy nhin ta c th s dung phng php hi vng trng thi bng cch c cng C bit c trng thi hot ng ca 8255. Do ta c th coi a ch cng C trong ch 1 v 2 l a ch ca thanh ghi trng thi ca 8255. c thanh ghi trng thi ny, ta c th bit c cc thng tin sau: C yu cu ngt chng trnh trao i tin ca cc cng A (INTRA) hay B (INTRB) Cc thanh ghi m s liu vo c s liu (IBFA=1, IBFB=1) Cc thanh ghi m ra c s liu (/OBFA = 0, /OBFB = 0) Hoc ring vi ch 2, khi c ngt xy ra, ta cn phi c t trng thi bit c nguyn nhn gy ra ngt l do 8255 nhn c d liu hay gi c d liu c cc hot ng tng ng. 5.2.4 Ghp ni 8255A vi My tnh v TBN S ghp ni cng vo ra theo chng trnh vi VXL v TBN nh hnh di. PPI 8255A t gia VXL v TBN, ng vai tr trung chuyn tin gia VXL v TBN qua cc ng tn hiu ca My tnh v TBN.
INTR
D0 D7
D0 D7 INTR INTR 8 PA0 PA7
Reset
RST
VXL A0
A1
Gii m a ch
8255 A
PC 8
TBN
A2 - An
PA0 PA7
Ghp ni 8255A vi MVT v TBN
Phn ghp ni vi My tnh Cc tn hiu v s liu (data bus) D0 D7, a ch thp (A0,A1), lnh c (RD), lnh ghi (WR) c ni thng vi cc li vo tng ng ca PPI 8255A Tn hiu /CS (Chip Select) ca PPI c ni vi b gii m cc a ch cao (A2 An) ca VXL Cc tn hiu ra yu cu ngt chng trnh (INTRA , INTRB) ca 8255 c ni vo li vo INTR ca VXL qua mt vi mch logic OR
Phn ghp ni vi thit b ngoi: Tu thuc loi TBN, s bit ca ng tn hiu s liu v phng thc trao i tin m ta c cch mc ng tn hiu khc nhau. Ch 0: Ba ng tn hiu PA, PB, PC u c dng trao i s liu hoc tin v iu khin v trng thi mt cch bnh ng vi nhau v tu la chn. ch ny c th: o Khng cn i thoi gia 8255 v TBN, ch c trao i s liu trn 1 trong 3 cng o Nu cn tin v iu khin hay c trng thi ca TBN ta s dng thm cc cng khc cho mc ch ny ngoi cng trao i s liu Ch 1: Ch c hai cng A,B trao i s liu c lp nhau, cn cc ng PCi ca cng PC dng hi thoi cho cc cng A,B trn. Cc ng ny c chiu v vai tr xc nh do khng th thay i. Ch 2: Ch cho cng PA vi s liu vo/ra hai chiu. Cc bit ca PC cng c vai tr v chiu xc nh cc ch bt tay (i thoi), gia 8255 v TBN ch trao i hai tn hiu hi p m thi Mt s ng dng ghp ni 8255 vi thit b ngoi: Mch ghp ni 8255 ch 0: hnh 4.x gii thiu cch ghp ni 8255 vi my in qua cng PA c chiu ra, v ghp ni vi mt b bin i tng t - s qua cng PB c chiu vo. Cng C c dnh cho cc tn hiu i thoi. Trong : Na C thp l cng vo, c trng thi ca my in v ADC PC0 cho trng thi my in bn (busy) PC1 cho tn hiu ACK ca my in PC2 Cho tn hiu EOC (End of Convertion) ca ADC Na C cao a ra cc tin v iu khin PC4 a ra tn hiu cht d liu cho my in PC5 a ra tn hiu Start cho ADC.
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Chng 5: Ghp ni trao i tin song song D0 D7 8 PA0 PA7 D0 D7 PC0 PC1 Reset RST PC4 /ACK Busy Data Strobe PB0 PB7 EOC Start
INTR
My in
VXL A0
A1
Gii m a ch
8255 A
PC3 PC5
ADC
A2 - An
Ghp ni 8255A vi MVT v TBN ch 0
Ghp ni 8255 ch 1:
INTR
D0 D7
D0 D7 PC3 PC0 PA /ACK Busy Data Strobe PB
Reset
RST
My in
VXL A0
A1
Gii m a ch
8255 A
A2 - An
EOC Start
ADC
Ghp ni 8255A vi MVT v TBN ch 1
Chng trnh trao i tin cho 8255A Tu theo cch mc v TBN, chng trnh cn c cc khi lnh c bn sau: 1. Khi to: l lnh ghi vo thanh ghi iu khin ca 8255 vi a ch thp A0, A1 = 11 ti t iu khin. Cc bit t iu khin ny c xc nh bi: - Ch ca cc cng - Chiu (vo/ra) ca cc cng 2. iu khin TBN: Cn a ni dung ca cc bit cho cc cng dng iu khin TBN. Nu ch 1,2 cc bit nay l cc bit PCi ca i thoi, ta khng cn phi vit lnh a gi tr ra na. Cn trng hp ch 0 ta c th dng mt trong hai cch sau: - Lp/ xo tng bit PCi ca cng PC - a tin ra cc bit ca cc cng 3. c v kim tra trng thi: - Cc lnh c vo o Thanh ghi trng thi nu cng dng ch 1, 2 o Mt cng bt k ch 0 dng ghi trng thi ca TBN.
Lnh v logic (AND) chn cc bit khng cn kim tra Lnh so snh (CMP) vi cc gi tr 1 ca bit Lnh tr v v tr c lnh c trng thi nu kt qu so snh khng ng trng thi cn xt 4. Trao i s liu: - a s liu vo (IN v VXL h 86) hay chuyn s liu MOV (ca VXL 8085) - a s liu ra (OUT ) hay chuyn s liu MOV -
5.3. Ghp ni song song qua cng my in

5.3.1 Gii thiu chung Cng my in l giao din thng c s dng nhiu nht trong cc ng dng ghp ni my tnh n gin, do tnh ph cp v n gin trong vic ghp ni v iu khin cng vi yu cu ti thiu v thit b phn cng thm vo. Cng ny cho php a vo ti 13 bit v a ra 12 bit song song, trong c 4 ng iu khin, 5 ng bo trng thi v 8 ng d liu. Trong hu nh bt k PC no ta cng c th tm thy cng my in pha sau. u ni ny c dng DB 25 chn (gic ci female).
Cc cng song song gn y c chun ho theo chun IEEE 1284 a ra nm 1994. Chun ny m t 5 ch hot ng ca cng my in nh sau: 1. Ch tng thch (Compatibility mode) 2. Ch Nibble 3. Ch Byte 4. Ch EPP 5. Ch ECP Ch c s (hay cn gi l Centronics mode) c bit n t lu. Ch ny ch cho php a d liu theo mt chiu ra (output), vi tc ti a 150kB/s. Mun thu d liu (input) ta phi chuyn sang ch Nibble hay Byte. Ch Nibble c th cho php a vo 4 bit song song mt ln. Ch Byte s dng tnh nng song song hai hng ca cng my in a vo mt byte. a ra mt byte ra my in ( hoc cc thit b khc) trong ch c s, phn mm phi thc hin cc bc sau:
(1) Vit d liu ra cng my in (ghi vo thanh ghi d liu) (2) Kim tra my in c bn khng, nu my in bn, n s khng chp nhn bt c d liu no, do d liu ghi ra lc s b mt (3) Nu my in khng bn, t chn Strobe (chn 1) xung thp (mc 0), bo vi my in l c d liu trn ng truyn ( chn 2 - 9) (4) Sau ch 5 micro giy v t chn Strobe ln cao (mc 1). Ch m rng (EPP) v nng cao (ECP) s dng cc thit b phn cng tch hp thm vo thc hin v qun l vic i thoi vi thit b ngoi. ch ny cho phn cng kim tra trng thi my in bn, to xung strobe v thit lp s bt tay thch hp. Do ch cn s dng mt lnh vo ra trao i d liu nn gip tng tc thc hin. Khi cng ny c th a d liu ra vi tc 1 2 MB/s. Ngoi ra ch ECP cn h tr s dng knh DMA v c thm b m FIFO. 5.3.2 Cu trc cng my in Chun IEEE 1284 a ra 3 u ni dng cho cng my in. Dng A (DB25) c th thy hu ht cc my PC, dng B (36 chn) thng thy my in, v dng C, 36 chn, ging dng B nhng nh hn, c cc thuc tnh in tt hn v c thm 2 ng tn hiu dnh cho cc thit b i mi sau ny. Hng Thanh S hiu Tn M t chn (In/Out) ghi 1 nStrobe In/Out Control Byte c in 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 - 25 Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 nAck Busy Paper-Out / Paper-End Select nAuto-Linefeed nError / nFault nInitialize nSelect-Printer / nSelect-In Ground Out Out Out Out Out Out Out Out In In In In In/Out In In/Out In/Out Gnd Data Data Data Data Data Data Data Data Status Status Status Status Control Status Control Control ng d liu D0 - D7
Xc nhn (Acknowledge) My in bn Ht giy ( Paper Empty) La chn ( Select ) T np giy ( Auto Feed) Li t li my in
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nXXXX: Tch cc mc thp Bng s chn ca cng my in Tn hiu ra ca cng my in thng cc mc logic TTL. Address 378h - 37Fh 278h - 27Fh Cng LPT 1 LPT 2
Khi khi ng BIOS gn a ch cho cc cng my in v lu thng tin a ch ny trong b nh a ch cho bng di: a ch bt u 0000:0408 0000:040A 0000:040C 0000:040E 5.3.3 Cc thanh ghi ca cng my in: 1. Thanh ghi d liu (Data Register) a ch Tn Read/Write Base + Data 0 Port Write S hiu bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 M t Data 7 Data 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 M t a ch c bn cng LPT1 a ch c bn cng LPT2 a ch c bn cng LPT3 a ch c bn cng LPT4
a ch c s (Base address) thng gi l cng d liu (Data port) hay Thanh ghi d liu (Data Register) thng s dng a d liu ra cc chn tn hiu ( Chn 2 9). Thanh ghi ny thng l thanh ghi ch ghi. Nu ta c d liu cng ny ta s thu c gi tr m ghi ra gn nht. Nu cng my in l hai chiu th ta c th thu gi liu vo t cng ny. 2. Thanh ghi trng thi ( Status Register): a ch Base + 1 Tn Status Port Read/Write Read Only S hiu bit Bit 7 Bit 6 M t Busy Ack
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Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Paper Out Select In Error IRQ (Not) Reserved Reserved
Thanh ghi trng thi l thanh ghi ch c. Bt k d liu no ghi ra cng ny u b b qua. Cng trng thi c to bi 5 ng tn hiu vo (Chn 10, 11, 12, 13, 15), mt bit trng thi ngt IRQ v 2 bit dnh. Ch rng bit 7 (Busy) l u vo tch cc thp, ngha l khi c mt tn hiu +5V chn 11, bit 7 s c gi tr logic 0. Tng t vi bit 2 (nIRQ) nu c gi tr 1 c ngha l khng c yu cu ngt no xut hin. 3. Thanh ghi iu khin ( Control Register): a ch Tn Base + Control 2 Port Read/Write Read/Write S hiu bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 M t Unused Unused Enable Bi-Directional Port Enable IRQ Via Ack Line Select Printer Initialize Printer (Reset) Auto Linefeed Strobe
Thanh ghi iu khin c d nh l ch ghi. Khi mt my in c ni vi my tnh, 4 ng iu khin s c s dng. l cc ng Strobe, Auto Linefeed, Inittialize v Select Printer, tt c u l u ra o tr ng Initialize. Bit 4 v 5 l cc bit iu khin ni. Bit 4 cho php ngt v bit 5 cho php cng d liu c chiu vo. Lp bit 5 cho php thu d liu vo qua ng Data0 7. 4. Thanh ghi iu khin m rng ECR (Extended Control Register ): a ch Base + 402H Bit Function 7:5 Selects Current Mode of Operation 000 Standard Mode 001 Byte Mode 010 Parallel Port FIFO Mode 011 ECP FIFO Mode
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100 EPP Mode 101 Reserved 110 FIFO Test Mode 111 Configuration Mode ECP Interrupt Bit DMA Enable Bit ECP Service Bit FIFO Full FIFO Empty
4 3 2 1 0
5.3.4 EPP - Enhanced Parallel Port Cng song song nng cao (EPP) c thit k bi s lin kt gia cc hng Intel, Xircom & Zenith Data Systems. Cng EPP ban u c m t theo chun EPP 1.7 v sau l chun IEEE 1284 ra i nm 1994. EPP c hai chun: EPP 1.7 v EPP 1.9. C mt vi s khc nhau gia cc chun ny nn c nhng nh hng ti cc thao tc x l ca thit b. EPP c tc truyn d liu tiu chun l t 500KB/s ti 2MB/s. iu ny t c do cc thit b phn cng ti cc cng to ra tn hiu bt tay (tn hiu mc ni, hi thoi) chng hn nh tn hiu stroble, thay cho s dng phn mm x l chng, nh trong ch SPP. EPP c s dng rng ri hn ECP. EPP khc vi ECP ch cng EPP pht ra cc tn hiu v iu khin tt c qu trnh truyn d liu gia n v thit b ngoi vi. Bn cnh th ECP li yu cu thit b ngoi vi c s hi thoi tr li bi mt tn hiu mc ni. iu ny l khng mm do cho vic thit lp mt lin kt logic v nh vy cn c mt b iu khin chuyn dng hoc mt chip ngoi vi ECP. Cc c trng phn cng EPP Khi s dng ch EPP, mt tp cc tc v khc nhau (c tn tng ng) c sp xp trn mi ng dy tn hiu. Cc tn hiu ny c ch ra trong bng 4. Chng s dng cc tn chung trong SPP v EPP trong cc bng m t v cng song song v cc ti liu. iu ny c th lm cho n rt kh ch r chnh xc nhng g ang xy ra. Do tt c cc ti liu y u s s dng tn theo EPP. SPP Signal Strobe Data 0-7 Ack Busy EPP IN/OUT Signal Write Out
Pin 1 2-9 10 11
Function Mc thp th hin mt chu k ghi, mc cao ch nh l ang c Data Bus. Hai chiu Interrupt Line. Ngt xut hin sn dng ca xung S dng cho bt tay. Mt chu k EPP c th bt
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Data 0-7 In-Out Interrupt In Wait In
u khi mc thp, kt thc mc cao 12 13 14 15 16 17 Paper Out Spare /End Select Auto Linefeed Error/fault Initialize Select Printer Spare Data Strobe Spare In In Out In Spare Khng s dng trong bt tay EPP Spare Khng s dng trong bt tay EPP Khi mc thp, ch nh l ang truyn d liu Spare Khng s dng trong bt tay EPP Reset - Tch cc thp Khi mc thp, ch nh ang truyn i ch Ground
Reset Out Address Out Strobe Ground GND
18-25 Ground
B ng 1 S s p x p cc chn c a EPP. Cc tn hiu Paper Out, Select v Error khng c nh ngha trong tp cc tn hiu bt tay ca EPP. Cc tn hiu ny c th c s dng tu theo s nhu cu ca ngi s dng. Trng thi ca cc c tn hiu ny c th c xc nh ti bt k thi im no bng cc kim tra cc bit ca thanh ghi trng thi. ng tic l khng c u ra d tr no cho s dng cho mc ch khc. Cc thanh ghi trong ch EPP Ch EPP c mt tp cc thanh ghi mi, trong c 3 thanh ghi c t ch SPP Address Base + 0 Base + 1 Base + 2 Base + 3 Base + 4 Base + 5 Base + 6 Base + 7 Port Name Data Port (SPP) Status Port (SPP) Control Port (SPP) Address Port (EPP) Data Port (EPP) Undefined (16/32bit Transfers) Undefined (32bit Transfers) Undefined (32bit Transfers) Read/Write Write Read Write Read/Write Read/Write -
Qu trnh bt tay ca EPP thc hin mt chu k truyn d liu hp l khi s dng EPP, chng ta phi tun th th t bt tay ca EPP. Do phn cng lm tt c mi vic nn cc tn hiu bt tay ny ch c s dng cho phn cng ca chng ta m khng c s dng cho phn mm nh trong trng hp vi SPP. khi to cho mt chu k EPP, phn mm ch cn thc hin mt thao tc vo/ra khi to cho thanh ghi EPP. Chi tit v vn ny s ni c th sau.
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EPP Data Write Cycle 1. Chng trnh ghi d liu vo thanh ghi d liu EPP (Base+4) 2. /Write c xo v 0. (Cho bit ang c mt thao tc ghi) 3. D liu c t ln ng truyn d liu (2 9). 4. /Data Strobe c kch hot nu /Wait ang mc thp (Sn sng bt u mt chu k mi) 5. My tnh ch tn hiu xc nhn th hin bi /Wait chuyn sang mc cao 6. Ngng kch hot /Data Strobe 7. Chu k ghi d liu EPP kt thc Qu trnh ghi a ch EPP (Address Write Cycle) 1. Chng trnh ghi gi tr a ch vo thanh ghi a ch EPP (Base+3) 2. /Write c xo v 0. (Cho bit qa trnh ghi) 3. Gi tr a ch c t ln ng truyn d liu (2 7). 4. /Address Strobe c kch hot nu /Wait ang mc thp (Sn sng bt u) 5. My tnh ch tn hiu xc nhn ng vi /Wait t ln mc cao (TBN c a ch xong) 6. Tn hiu /Address Strobe ngng tch cc 7. Chu k gi a ch EPP
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Chu k c d liu EPP 1. Chng trnh ra lnh c thanh ghi d liu EPP (Base+4) 2. /Data Strobe c kch hot nu /Wait ang mc thp (Sn sng mt chu k mi) 3. My tnh ch tn hiu xc nhn (/Wait chuyn sang mc cao) 4. D liu c c t cc chn tn hiu ca cng 5. Ngng kch hot tn hiu /Data Strobe . Chu k c a ch EPP 6. Kt thc chu k c d liu
1. Program reads EPP Address Register (Base+3) 2. nAddr Strobe is asserted if Wait is Low (OK to start cycle) 3. Host waits for Acknowledgment by nWait going high 4. Data is read from Parallel Port Pins 5. nAddr Strobe is deasserted 6. EPP Address Read Cycle Ends
Ch : Nu s dng EPP 1.7 (trc IEEE 1284) tn hiu Strobes cho d liu v a ch c th c dng xc nhn s bt u ca mt chu k ri ca trng thi i. EPP 1.9 s ch bt u mt chu k i mc thp. C EPP 1.7 v EPP 1.9 chuyn tn hiu i (strobe) ln mc cao kt thc chu k. Cc thanh ghi s dng trong ch EPP Cng EPP cng c mt tp cc thanh ghi mi. Tuy nhin c 3 thanh ghi l k tha ca cng SPP. Bng sau cho thy cc thanh ghi c v cc thanh ghi mi. Address
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Port Name
Read/Write
Base+0 Data Port (SPP) Base+1 Base+2 Base+3 Base+4 Base+5 Base+6 Status Port (SPP) Control Port (SPP) Address Port (EPP) Data Port (EPP) Undefined (16/32bit Transfers) Undefined (32bit Transfers) B ng 2: EPP Registers
Write Read Write Read/Write Read/Write -
Base+7 Undefined (32bit Transfers)
Nh ta c th thy, 3 thanh ghi u l ging ht cc thanh ghi trong tp thanh ghi ca cng SPP v chc nng cng l ging. V th nu ta s dng mt cng EPP ta c th a d liu ra thanh ghi d liu (Base+0) ging nh ta thc hin vi SPP. Nu ta kt ni vi mt my in v s dng ch ph hp, th ta phi kim tra xem cng c bn khng, tip theo ta c th to xung strobe v kim (Ack) tra thng qua vic ghi/c thanh ghi iu khin v trng thi. Nu mun truyn thng vi mt thit b tng thch EPP th tt c cng vic ta phi lm l gi d liu ra thanh ghi d liu EPP (EPP Data Register) ti a ch Base+4 v cng my in s sinh ra tt c cc tn hiu bt tay cn thit. Tng t nh vy, nu mun gi mt a ch ti thit b, ta s dng thanh ghi a ch EPP (EPP Address Register) ti a ch Base+3. C thanh ghi a ch v d liu u c th c v ghi, do c d liu t thit b ta c th s dng cng mt thanh ghi. mc d, card my in phi khi pht mt chu k c vi tn hiu Data Strobe hoc Address Strobe u ra. Thit b ngoi vn c th a ra tn hiu yu cu c qua ng tn hiu yu cu ngt v ISR (chng trnh con phc v ngt) s thc hin cng vic c. Cng trng thi c mt s thay i nh. Bit 0 l d tr i vi tp thanh ghi ca SPP th gi y n l bit Time-out EPP. Bit ny s c lp khi xut hin mt Time-out EPP. S kin ny xy ra khi ng tn hiu nWait l khng c xc nhn tr li trong khong 10S (gi tr ny tu thuc vo cng khc nhau) ca tn hiu IOR hoc IOW. Cc tn hiu IOR v IOW l cc tn hiu c v ghi thit b (I/O Read v I/O Write) trn bus ISA. Ch EPP c gin thi gian rt ph thuc vo gin thi gian ca bus ISA. Khi thc hin mt chu k c, cng phi m nhn trch nhim iu khin ph hp cc tn hiu hi thoi Read/Write v tr li d liu nh trong chu k bus ca ISA. Tt nhin qu trnh ny khng ng thi vi chu k bus ISA, v th cng s dng tn hiu iu khin IOCHRDY (I/O Channel Ready) trn bus ISA cho bit trng thi i cho n khi hon thnh chu k bus. By gi ta c th tng tng rng nu mt qu trnh c hoc ghi EPP c bt u nu nh khng c thit b ngoi vi no ni
vo th s ra sao? Cng s khng bao gi nhn c mt tn hiu xc nhn (nWait) v th m c c mt yu cu cho trng thi i, my tnh phi thc hin mt vng lp kim tra., do n duy tr vic gi tn hiu yu cu v ch kt thc trng thi wait, v my tnh s b treo. V vy m EPP thc hin mt kiu kim tra watchdog m thi gian time out l xp x 10S. Ba thanh ghi: Base+5, Base+6 v Base+7 c th c s dng cho cc thao tc c/ghi 32 bits d liu nu nh cng c h tr cho n. iu ny c th lm gim cc thao tc vo/ra ca ta. Cng song song c th chi truyn d liu 8 bits ti mt thi im cho nn bt k mt word 16 hay 32 bits c ghi ti cng song song s c chia thnh cc byte v c gi qua 8 bit d liu ca cng song song. Lp trnh cng my in trong ch EPP. EPP ch c 2 thanh ghi chnh v mt c trng thi time-out, chng ta c th thit lp chng nhng g? Trc khi ta c th bt u bt k mt chu k EPP bng vic c v ghi ti thanh ghi d liu v thanh ghi a ch th cng phi c cu hnh mt cch ng n cho ch lm vic ca n. Trong trng thi ri, cng EPP cn phi c cc tn hiu nAddress Strobe, nData Strobe, nWrite v nReset trng thi khng tch cc ( mc cao). Mt vi cng yu cu ta phi lp cc bit ny trc khi thc hin mt chu k bus EPP. V vy nhim v u tin ca chng ta l khi to mt cch th cng cc tn hiu ny bng vic s dng cc thanh ghi ca SPP. C th l ghi gi tr xxxx 0100 ti thanh ghi iu khin khi to. Trn mt vi card, nu cng song song c t trong ch nhn, th mt chu k ghi EPP s khng th thc hin c. V vy n s t bit phi t cng vo ch ra trc khi s dng EPP. Vic xo bits 5 ca thanh ghi iu khin cn phi c thc hin trc. Bit time-out ca EPP EPP: Khi bit ny c lp, cng EPP c th khng m bo ng chc nng ca n, s lun lun c gi tr 0FFh t c chu k a ch v chu k d liu. Bit ny nn c xo cc thao tc c tin cy v n phi lun c kim tra.
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CHNG 6. GHP NI TRAO I TIN NI TIP

Mc tiu: Trnh by cc kin thc c bn v ghp ni v truyn thng ni tip ni chung v qua giao din ni tip ca my tnh ni ring. Trnh by cu trc, nguyn l hot ng, nguyn tc ghp ni v lp trnh ca cc giao din ni tip ca my tnh nh cng COM, USB,
Tm tt chng: t vn Yu cu v th tc trao i tin ni tip: Truyn thng ni tip s dng giao din RS-232: Giao tip USB ca my PC:
6.1. t vn
Mt trong nhng k thut ghp ni c s dng rng ri l k thut ghp ni TBN qua cng ni tip - Qua cng ni tip c th ghp ni chut, modem ngoi, my in, b bin i A/D, cc thit b o lng, - Cc cch ghp ni ny s dng phng php truyn thng tin (d liu) theo kiu ni tip. cc bit d liu c truyn ni tip nhau trn mt ng tn hiu duy nht. Ti mt thi im ch c mt bit d liu c truyn trn ng tn hiu. - Truyn thng ni tip c u im l cn t ng tn hiu, c th s dng mt ng truyn, mt ng nhn. Thng tin thu nhn l tin cy, tuy nhin tc truyn l chm. - Chun RS232 c xy dng thnh chun chnh thc dnh cho truyn thng ni tip, do hip hi cc nh cng nghip in t EIA (Electronic Industries Association) nm 1962. Chun ny cho php truyn vi tc cc i 19.600 bit/s vi khong cch nh hn 20 m - Sau ra i mt s chun nh RS422, RS449, RS485 c tc truyn v khong cch cho php xa hn. Vd: RS422: Tc truyn 10Mbit/s, khong cch >1000m
6.2. Yu cu v th tc trao i tin ni tip:

6.2.1 Yu cu: Khi khong cch gia hai thit b trao i tin l rt ln, vic s dng phng php truyn tin song song s i hi chi ph tn km v ng tn hiu ng thi cng kh khn trong vic chng nhiu trn ng truyn. Do vi vic truyn tin khong cch xa v yu cu v tc khng ln th phng php truyn tin ni tip c s dng. Truyn thng ni tip cn thm cng on gia cng tn hiu chuyn tn hiu song song thnh tn hiu ni tip gi i, sau phi chuyn t tn hiu ni tip thnh song song ni nhn. Vic gia cng tn hiu ny cng tn mt khon chi ph nhng cng gim hn nhiu so vi truyn thng song song. Cc thit b u cui trong lin kt ni tip c th l cc loi thit b khc nhau nhng chng phi thng nht vi nhau v cc quy tc v giao thc cng nh nh dng d liu. S thng nht ny m bo d liu c gi ti bn nhn v bn nhn c th hiu c d liu . Phn ny s trnh by v nh dng d liu v giao thc truyn d liu s dng trong truyn thng ni tip, v s ch trng hn ti phng php truyn thng khng ng b do c dng trong chun RS232 ca cng ni tip COM Trong truyn tin ni tip, ti mt thi im ch c mt bit d liu c truyn i v cc bit d liu c truyn tun t nhau. Mt lin kt gia hai bn c th s dng hai ng d liu truyn theo hai hng ring bit hoc c th s dng chung mt ng d liu truyn theo c hai hng vo cc thi im khc nhau. Vic truyn thng s dng chung mt ng tn hiu cho c hai hng gi l truyn bn song cng (Half76 Nguyn Tun Linh BM KTMT Khoa in T
duplex) cn trng hp s dng hai ng tn hiu ring cho hai hng cho php truyn ng thi c hai hng th c gi l truyn song cng y (Full-duplex). Trong my tnh PC, lin kt ni tip s dng dng Full-duplex. C mt tn hiu phi c trong truyn tin ni tip l tn hiu xung ng h (clock). Tn hiu ny gip iu khin dng d liu. Bn gi v bn nhn s dng tn hiu ny quyt nh khi no gi v nhn mi bit. C hai phng php truyn thng ni tip l truyn thng ng b (Synchronous) v truyn thng khng ng b (Asynchronous). Vi mi loi th cch s dng tn hiu clock l khc nhau. 6.2.2 Trao i tin ng b: Synchronous Trong truyn thng ng b, hai bn truyn thng s dng chung mt ng tn hiu clock. Tn hiu ny c pht ra bi mt bn hoc bi mt thit b pht xung ng b ring. Tn hiu ng b ny c th c tn s thay i hoc c mt chu k khng xc nh. Ngha l mi bit truyn i c xc nh ti mt thi im khi c s thay i mc tn hiu ca tn hiu clock. Bn nhn cng s dng s thay i mc xc nh khi no th c bit d liu gi ti. Th d nh bn nhn s cht d liu gi ti khi xut hin sn ln ca xung clock hay l s thay i mc tn hiu t thp ln cao. Truyn ng b bn nhn khng cn phi bit trc tc trao i tin m ch cn qua tm ti tn hiu ng b pht trn ng tn hiu ng b. Truyn thng ng b rt hu ch khi truyn khong cch gn bi n cho php truyn thng vi tc cao. Tuy vy vi khong cch xa, vic truyn thng ng b l khng kh thi do n i hi c thm mt ng tn hiu clock, nh vy cn mt ng dy thm vo, hn na s d b nhiu trn ng truyn. Mi khi tin ng b thng gm nhiu byte, cc khi c nh du bi cc byte nh du khung tin, cc byte ny c gi tr l 16H ( m ASCII ca ch Sync) Truyn thng ng b phi thc hin lin tc, khi khng c d liu cn truyn th bn pht vn tip tc phi truyn cc d liu trng duy tr s ng b. Truyn thng ng b thc hin kim tra li bng phng php s d vng (chia tng tin ca khung cho mt a thc - gi l a thc sinh). S d ca php chia c ghi vo mt byte FCS ( Frame Check Sum). pha thu, cng tnh tng t v so snh kt qu. Nu bng nhau th tin truyn khng b li. 6.2.3 Trao i tin khng ng b - Asynchronous: Trong truyn thng khng ng b, ng truyn s khng cn c thm mt ng tn hiu clock bi v mi bn c b pht xung ng b ca ring n. lm c nh vy, hai bn phi thng nht mt tn s xung chung, v tt c cc xung clock phi khp nhau mt mc no . Mi byte truyn i s bao gm mt bit Start ng b xung ng h gia hai bn v mt bit Stop nh du kt thc byte c truyn. Cng RS232 ca my PC s dng nh dng khng ng b truyn thng vi cc thit b ngoi nh modem, my in cng nh truyn thng vi my tnh khc. Tuy rng cng RS-232
c th s dng phng php truyn ng b nhng phng php truyn khng ng b vn thng c s dng nhiu hn. Vic truyn thng s dng phng php khng ng b khng cn phi thc hin lin tc. Trong trng thi ngh, ng tn hiu truyn tin s c trng thi tng ng vi mc tn hiu ca bit Stop. Qu trnh truyn thng khng ng b s dng mt s nh dng khc nhau. Thng dng nht l dng 8-N-1. Trong mi byte d liu gi i bao gm mt bit Start, tip theo l 8 bit d liu, bt u bng bit 0 ( hay bit LSB) v kt thc bng mt bit Stop. K t N trong 8-N-1 c ngha l trong d liu truyn i khng c bit chn l (Parity bit). Bit chn l c s dng nh mt phng php kim tra li truyn mt cch n gin. Bit chn l c th l bit Chn hoc bit L. Bit chn c ngha l bit parity c t l chn hay l sao cho s cc bit c gi tr 1 trong cc bit d liu bao gm c bit Parity l mt s chn, v ngc li vi Parity l. Khi bn nhn nhn c byte d liu n s kim tra tnh gi tr parity ca byte c nhn, sau so snh vi bit parity trong byte va nhn. Nu khng trng nhau c ngha l c li xy ra trn ng truyn. Bn nhn s thng bo li bn gi truyn li byte d liu . S bit d liu truyn i trong mt ln truyn c th l t 5 n 8 bit tu theo tng ng dng. Nu truyn k t ASCII th ta truyn 7 bit, nu truyn gi tr nh phn (truyn file) th s dng 8 bit. S bit stop cng l mt tham s cn quan tm. S 1 trong 8-N-1 ch ra rng y ta s dng 1 bit Stop. S bit stop c th l 1,5 hoc 2 bit. Tham s rt quan trng trong qu trnh truyn thng l tc truyn d liu. Tc truyn l s bit c truyn trn ng dy trn mt n v thi gian, thng thng c tnh bng n v baud. Trong a s trng hp, n v ny tng tng ng vi n v bit trn giy (b/s). Vi nh dng 8-N-1, tc truyn mt byte d liu bng 1/10 tc truyn. Nu ta truyn vi tc 9600 baud th trong mt giy truyn c 960 byte.
6.3. Truyn thng ni tip s dng giao din RS-232:

Chng ta thy rng vic truyn thng ni tip i hi rt nhiu thao tc phi thc hin. Ta phi chuyn mt byte d liu t dng song song thnh dng ni tip (bi v hu ht cc h thng s u lm vic vi cc d liu dng song song). Tip theo ta phi to ra mt li tin theo ng nh dng cho trc bng cch thm cc bit Start, Stop, Parity ph hp. Sau ta mi truyn d liu i di dng ni tip. Cng ni tip ca my PC c mt vi mch chuyn dng iu khin truyn thng ni tip. Do , khi s dng cng RS-232 ca my PC truyn thng, tt c cng vic ca chng ta l gi byte d liu cn truyn ra thanh ghi d liu ca vi mch ny. Sau mi thao tc ca qu trnh truyn thng k trn s c vi mch thc hin da theo nhng thit lp trong qu trnh khi to.
6.3.1 Qu trnh truyn mt byte d liu: Trong trng thi ri, gi tr logic trn ng truyn lun bng 1. bo vic bt u truyn d liu, bn gi a gi tr logic 0 ln ng truyn trong khong thi gian bng di mt bit. Bit gi l bit Start. Khi truyn vi tc 300 baud, mt bit c di l 3,3 ms, trong khi vi tc 9600 baud th c di 0,1 ms. Ngay sau bit Start, bn truyn gi tip 8 bit d liu k tip nhau, bt u bng bit LSB. Tip sau bn truyn s gi tip mt bit c gi tr logic 1 ln ng truyn v duy tr trong khong thi gian t nht l di mt bit. Ngay sau hoc sau mt khong thi gian bt k, bit Start tip theo s c gi bt u truyn mt byte mi. 6.3.2 Cng ni tip RS 232 Cng ni tip c s dng truyn d liu hai chiu gia my tnh v ngoi vi, c cc u im sau: - Khong cch truyn xa hn truyn song song. - S dy kt ni t. - C th truyn khng dy dng hng ngoi. - C th ghp ni vi vi iu khin hay PLC (Programmable Logic Device). - Cho php ni mng. - C th tho lp thit b trong lc my tnh ang lm vic. - C th cung cp ngun cho cc mch in n gin Cc thit b ghp ni chia thnh 2 loi: DTE (Data Terminal Equipment) v DCE (Data Communication Equipment). DCE l cc thit b trung gian nh MODEM cn DTE l cc thit b tip nhn hay truyn d liu nh my tnh, PLC, vi iu khin, Vic trao i tn hiu thng thng qua 2 chn RxD (nhn) v TxD (truyn). Cc tn hiu cn li c chc nng h tr thit lp v iu khin qu trnh truyn, c gi l cc tn hiu bt tay (handshake). u im ca qu trnh truyn dng tn hiu bt tay l c th kim sot ng truyn. Tn hiu truyn theo chun RS-232 ca EIA (Electronics Industry Associations). Chun RS-232 quy nh mc logic 1 ng vi in p t -3V n -25V (mark), mc logic 0 ng vi in p t 3V n 25V (space) v c kh nng cung cp dng t 10 mA n 20 mA. Ngoi ra, tt c cc ng ra u c c tnh chng chp mch. Chun RS-232 cho php truyn tn hiu vi tc n 20.000 bps nhng nu cp truyn ngn c th ln n 115.200 bps.
Cc phng thc ni gia DTE v DCE: n cng (simplex connection): d liu ch c truyn theo 1 hng. Bn song cng ( half-duplex): d liu truyn theo 2 hng, nhng mi thi im ch c truyn theo 1 hng. Song cng (full-duplex): s liu c truyn ng thi theo 2 hng. nh dng ca khung truyn d liu theo chun RS-232 nh sau:
Start 0 D0 D1 D2 D3 D4 D5 D6 D7 P Stop 1
Khi khng truyn d liu, ng truyn s trng thi mark (in p -10V). Khi bt u truyn, DTE s a ra xung Start (space: 10V) v sau ln lt truyn t D0 n D7 v Parity, cui cng l xung Stop (mark: -10V) khi phc trng thi ng truyn. Dng tn hiu truyn m t nh sau (truyn k t A):
Hnh 4.1 Tn hiu truyn ca k t A Cc c tnh k thut ca chun RS-232 nh sau: Chiu di cable cc 15m i d liu cc i 20 Kbps Tc in p ng ra cc i 25V
in p ng ra c ti Tr khng ti in p ng vo nhy ng vo Tr khng ng vo
5V n 3K n 7K 15V 3V 3K n 7K
Cc tc truyn d liu thng dng trong cng ni tip l: 1200 bps, 4800 bps, 9600 bps v 19200 bps. S chn:
Hnh 4.2 S chn cng ni tip Cng COM c hai dng: u ni DB25 (25 chn) v u ni DB9 (9 chn) m t nh hnh 4.2. ngha ca cc chn m t nh sau: D25 D9 1 2 3 4 5 6 7 8 20 22 23 24 15 17 18 21 14 16 19 13 12 25 9 10
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Tn hiu TxD RxD RTS CTS DSR GND DCD DTR RI DSRD TSET TSET RSET LL RL STxD SRxD SRTS SCTS SDSRD TM
Hng truyn DTE DCE DTE DCE DCE DCE DTE DCE DCE DTE DCE DCE DCE DCE DTE DCE DTE DTE DTE DCE DTE DTE DCE DTE DTE DTE
3 2 7 8 6 5 1 4 9 -
DTE DCE DCE DTE DTE DCE DCE DTE DCE DTE
M t Protected ground: ni t bo v Transmitted data: d liu truyn Received data: d liu nhn Request to send: DTE yu cu truyn d liu Clear to send: DCE sn sng nhn d liu Data set ready: DCE sn sng lm vic Ground: ni t (0V) Data carier detect: DCE pht hin sng mang Data terminal ready: DTE sn sng lm vic Ring indicator: bo chung Data signal rate detector: d tc truyn Transmit Signal Element Timing: tn hiu nh thi truyn i t DTE Element Timing: tn hiu nh Transmitter Signal thi truyn t Signal Element d liu tn hiu nh thi Receiver DCE truyn Timing: truyn t DCE truyn d liu Local Loopback: kim tra cng Remote Loopback: To ra bi DCE khi tn hiu nhn t DCE li Transmitted Data Secondary Secondary Received Data Secondary Request To Send Secondary Clear To Send Secondary Received Line Signal Detector Test Mode Dnh ring cho ch test Dnh ring cho ch test
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Khng dng
Chng 6. Ghp ni trao i tin ni tip
Bng 1: D Type 9 Pin and D Type 25 Pin Connectors Chc nng ca cc chn Ch vit tt Tn y TD Transmit Data RD Receive Data CTS Clear to Send DCD Chc nng Serial Data Output (TXD) - u ra ca d liu Serial Data Input (RXD) - D liu c nhp vo Bo rng Modem sn sng trao i d liu. Khi no modem pht hin ra mt Carrier t mt Data Carrier modem kt thc khc ca phone line, th Line ny Detect tr thnh tch cc. Thng bo vi UART rng modem sn sng thit Data Set Ready lp mt mi lin kt . Data Terminal y l s i lp vi DSR. Bo vi Modem rng Ready UART sn sng lin kt . Request To Thng bo cho Modem rng UART sn sng Send trao i d liu. Tch cc khi modem pht hin c mt tn hiu Ring Indicator chung t ng in thoi
DSR DTR RTS RI
Null Modems Mt Null Modem c s dng ni cho hai DTE cng nhau. Nhng modem ny thng c s dng nh mt cch ni mng cho nhng tr chi hoc chuyn giao gia cc file my tnh s dng giao thc Zmodem Protocol, Xmodem Protocol, ... iu ny cng c th c s dng vi nhiu Microprocessor Development Systems (h thng pht trin b vi x l).
Hnh 1: S ni dy Null Modem Trn y l phng php u tin ca vic ni dy ca mt Null Modem. N ch yu cu 3 dy (TD, RD & SG) mc c xuyn thng qua v vy nh hng ln n chi ph s dng chy cp di. Nguyn l ca thao tc kh n gin. Mc tiu l lm cho my tnh cho rng n l mt modem hn l mt computer khc. Bt k d liu no c truyn t my tnh th nht phi c nhn bi mt my tnh khc do TD c ni vi RD. iu th hai my tnh phi c cng c cu nh vy th RD c ni ti TD. Tn hiu Signal Ground (SG) cng phi c ni chung cho c hai my tnh.
Data Terminal Ready (DTR) c ni vng vo chn Data Set Ready (DSR) v Data Carrier Detect (DCD) trn c hai my tnh. Khi chn Data Terminal Ready mc tch cc th chn Data Set Ready v chn Data Carrier Detect ngay lp tc tr thnh tch cc (active). Vo thi im ny my tnh cho rng Virtual Modem sn sng c ni v pht hin ra sng mang ca modem khc. V vn cn lo lng by gi l chn Request to Send v chn Clear To Send. Trong khi c hai my tnh giao thip vi nhau cng mt tc , v vy vic iu khin lung l khng cn thit do hai chn ny c ni vng vi trn mi my tnh. Khi my tnh mun gi d liu, n xc nhn s c mt ca chn Request to Send mc cao v khi n mc ni vi chn Clear to Send, lc ny ngay lp tc my tnh nhn c cu tr li rng n c th gi d liu v n thc hin ngay.
Hnh 2: S ni dy Loopback Plug Loopback plug thit b ny c th tr nn v cng d s dng khi vit nhng chng trnh truyn thng s dng cng ni tip RS232. N c th nhn v truyn nhiu tuyn ng cng nhau, v th m mi th c truyn ra ngoi ca cng ni tip th ngay lp tc nhn c bi cng cng . Nu chng ta ni thit b ny vi cng ni tip np vo Terminal Program, th bt c ci g chng ta nh my s ngay lp tc c hin ln trn mn hnh. Xin ch rng thit b ny cha c d nh cho vic s dng vi nhng chng trnh Chn on (Diagnostic Programs) v s c l khng lm vic. Bi v nhng chng trnh m chng ta yu cu khc nhau s bo cho Loop Back plug ci m c th thay i t chng trnh ny n chng trnh khc. Tc DTE / DCE Chng ta ni tm tt v DTE v DCE. Mt thit b u cui d liu (Data Terminal Device) tiu biu l mt my tnh v mt thit b truyn thng d liu (Data Communications Device) tiu biu l mt Modem. Ngi ta thng nhc n tc ca DTE to DCE hoc DCE to DCE. DTE to DCE l tc gia modem v my tnh ca chng ta, i khi c cp n nh l tc ca thit b cui ca chng ta. DTE to DCE cn phi chy mt tc nhanh hn tc ca DCE to DCE. DCE to DCE l s kt ni gia cc modem, i khi c gi l tc ng truyn.
Hu ht mi ngi ngy nay c nhng modem vi tc 28,8K hoc 33,6K. Bi vy chng ta cn phi ch i tc ca DCE to DCE cng nh tc ca modem l 28,8K hoc 33,6K. Suy cho cng v tc cao ca modem nn chng ta mong mun tc ca DTE to DCE s t n khong 115,200 BPS (Maximum Speed of 16550a UART). Nhng chng trnh truyn thng m chng ta s dng t tc cho DCE to DTE. Tuy nhin, chng ch c tc 9,6 KBPS, 14,4 KBPS ... v coi nh n l tc modem ca chng ta. Nhng modem ngy nay c th nn d liu vo trong chng (Data Compression). iu ny cng nh rt nhiu PK-ZIP nhng phn mm trong modem ca chng ta c th nn v gii nn d liu. Khi a ra ng cch thc chng ta c th mong i vic nn s truyn vi t l 1:4 hoc thm ch cn cao hn. T l nn d liu 1:4 l rt tiu biu cho vic nn d liu ca nhng file vn bn. Nu chng ta chuyn nhng file vn bn 28,8K (DCE-DCE), th khi modem nn n chng ta thc s ang chuyn 115,2 KBPS gia nhng computers v nh vy tc ca DCE-DTE l 115,2 KBPS. Nh vy d l l do ti sao tc ca DCE-DTE cn phi cao hn tc kt ni ca modem. Tuy nhin, hy khoan lm dng modem ca chng ta nu chng ta khng c nhng tc mong mun. l nhng t l nn cc i. Trong vi trng hp c bit nu chng ta c gng gi cho mt file nn, modem ca chng ta c th mt nhiu thi gian hn nn n, v vy chng ta c tc truyn chm hn tc kt ni ca modem. Nu iu ny xy chng ta nn c gng tt vic nn d liu ca chng ta li. Lc ny cn phi c nh trn nhng modem mi hn. Mt vi file nn d dng hn nhng file khc v vy bt k file no m nn n gin th t nhin s c mt t l nn cao hn. iu khin Lung (Flow Control) Nh vy nu tc ca DTE to DCE l nhanh hn gp vi ln tc ca DCE to DTE PC c th gi d liu ti modem ca chng ta ti 115,200BPS. Sm hay mun d liu s b mt khi b m b trn, trng hp ny iu khin lung s c s dng. iu khin lung c hai dng c bn, phn cng (hardware) hoc phn mm (software). iu khin lung bng phn mm (Software flow control), i khi c biu th nh Xon/Xoff s dng hai dng k t Xon v Xoff. Xon thng cho bit bi nhng k t ca ASCII 17 trong khi k t ASCII 19 c s dng cho Xoff. Nhng modem ch c mt b m nh v th khi my tnh ghi y n, Modem gi mt k t Xoff bo cho my tnh dng cng vic gi d liu. Khi modem trng cho nhiu d liu hn, n gi mt k t Xon v my tnh s gi nhiu d liu hn. Kiu iu khin lung th ny c nhiu li th rng n khng yu cu bt k tn hiu ring no nh nhng k t c gi qua nhng ng TD/RD. Tuy nhin mi k t yu cu lin kt chm mt 10 bits iu c th lm chm vic truyn thng li. iu khin lung phn cng (Hardware flow control) cng c bit nh iu khin lung RTS/CTS. N s dng hai dy trong cp ni tip ca chng ta hn l truyn thm nhng k t trong ng d liu ca chng ta.
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iu khin lung Phn cng cng c bit nh iu khin lung RTS / CTS. V vy iu khin lung phn cng (hardware flow control) s khng lm chm vic truyn thng li nh vic s dng Xon-Xoff thc hin. Khi my tnh mun gi d liu n s iu khin hot ng ca ng Request to Send. Nu modem c ch trng cho d liu ny, th modem s bng vic iu khin hot ng ca ng Clear to Send v my tnh bt u gi d liu. Nu modem khng rng th n s khng gi tn hiu cho Clear to Send. Vi mch iu khin truyn thng khng ng b van nng UART UART l vit tt ca Universal Asynchronous Receiver/Transmitter. a s cc card s c UART tch hp vo trong nhng mch in t chip khc m cng c th iu khin cng song song ca chng ta, cng games, floppy hoc a cng (hard disk drives) v tiu biu l nhng thit b giao tip vi ngi s dng. H vi mch 8250, bao gm 16450, 16550, 16650, & 16750 UARTS l nhng kiu thng thy trn PC ca chng ta. V sau chng ta s xem xt nhng kiu khc. Hnh 3: S Chn cho 16550, 16450 & 8250 UARTs
16550 l chip tng thch vi 8250 & 16450. Ch khc hai chn 24 v 29. Chn 24 trn 8250 l vic la chn chip ngoi m chc nng ch l vic ch bo ti nu chip hot ng hoc khng. Chn 29 khng c kt ni trn 8250/16450 UARTs. 16550 a vo hai chn mi trong n. l Transmit Ready v Receive Ready m c th thc thi vi DMA (Direct Memory Access). Nhng chn ny c hai kiu thao tc khc nhau. Mode 0 h tr vic chuyn giao n DMA trong khi mode 1 h tr Multi-transfer DMA. Mode 0 cng c gi l mode 16450. Mode ny c la chn khi b m FIFO c v hiu ho qua bit 0 ca FIFO Control Register hoc khi b m FIFO c cho php nhng DMA Mode Select = 0. (Bit 3 ca FCR) Trong mode ny RXRDY l tch cc mc thp khi t nht mt characters (Byte) c mt trong Receiver Buffer. RXRDY s khng hot ng mc cao khi khng c nhiu characters tn ti trong Receiver Buffer. TXRDY s hot ng mc thp khi khng c characters trong Transmit Buffer. N s khng hot ng mc cao sau khi characters/byte u tin c ti vo trong Transmit Buffer. Mode 1 l khi b m FIFO c kch hot v DMA Mode Select = 1. Trong mode 1, RXRDY s hot ng mc thp khi trigger level l reached hoc khi 16550 Time Out xy ra v s quay tr li trng thi khng hot ng khi khng c characters trong FIFO. TXRDY s c kch hot khi khng
c characters c mt bn trong Transmit Buffer v s khng c kch hot khi FIFO Transmit Buffer l hon ton Full. Chn Chn 1:8 Chn 9 Chn 10 Chn 11 Chn 12 Chn 13 Chn 14 Chn 15 Chn 16 Chn 17 Chn 18 Chn 19 Chn 20 Chn 21 Chn 22 Tn D0:D7 6.3.2.1.1.1.1.1 Li ghi ch
Chn 23
Chn 24 Chn 25 Chn 26 Chn 27 Chn 28 Chn 29 Chn 30 Chn 31 Chn 32 Chn 33 Chn 34 Chn 35
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Data Bus Receiver Clock Input. Tn s u vo ny cn phi cn RCLK bng vi receivers baud rate * 16 RD Nhn d liu (Receive Data) TD Truyn d liu (Transmit Data) CS0 Chip Select 0 - Active High CS1 Chip Select 1 - Active High nCS2 Chip Select 2 - Active Low Baud Output - Output from Programmable Baud Rate nBAUDOUT Generator. Frequency = (Baud Rate x 16) u vo External Crystal Input S dng cho Baud XIN Rate Generator Oscillator XOUT u ra External Crystal Output nWR Write Line Inverted (o) WR Write Line - Not Inverted (khng o) VSS Kt ni ti Common Ground RD Read Line - Inverted nRD Read Line - Not Inverted V hiu ho b phn iu khin (Driver Disable). Chn ny ri vo mc thp khi CPU c t UART. C th kt DDIS ni ti Bus Transceiver trong trng hp bus d liu c dung lng cao. nTXRDY Transmit Ready Xung a ch (Address Strobe). S dng nu tn hiu nADS khng n nh trong sut qu trnh c hoc ghi cycle A2 Address Bit 2 A1 Address Bit 1 A0 Address Bit 0 nRXRDY Receive Ready INTR Interrupt Output nOUT2 User Output 2 nRTS Request to Send nDTR Data Terminal Ready nOUT1 User Output 1 MR Master Reset
Chn 36 Chn 37 Chn 38 Chn 39 Chn 40
nCTS nDSR nDCD nRI VDD
Clear To Send Data Set Ready Data Carrier Detect Ring Indicator + 5 Volts
Bng 2: Pin Assignments for 16550A UART Tt c cc chn ca UARTs u thch hp vi TTL. Bao gm TD, RD, RI, DCD, DSR, CTS, DTR v RTS m tt c cc giao din trong l serial plug ca chng ta, typically a D-type connector. V vy RS232 Level Converters (m chng ta s ni c th sau) c s dng. Ci ny thng thng l DS1489 Receiver v DS1488 as PC has +12 and -12 volt rails m c th s dng bi nhng thit b ny. Trnh chuyn i RS232 s chuyn i tn hiu TTL vo trong RS232 Logic Levels. UART yu cu mt Clock chy. Nu chng ta xem xt card ni tip ca chng ta a common crystal tm thy cng l a 1.8432 MHZ hoc a 18.432 MHZ Crystal. crystal bn trong c kt ni ti chn XIN-XOUT ca UART s dng thm mt s thnh phn m gip crystal khi ng oscillating. Clock ny s c s dng cho chng trnh Programmable Baud Rate Generator l nhng giao din trc tip bn trong mch chuyn i thi gian ( transmit timing circuits) nhng khng trc tip bn trong mch receiver thi gian ( receiver timing circuits). i vi vic kt ni ngoi ny c lm t chn 15 (BaudOut) n chn 9 (Receiver clock in). Ch rng tn hiu clock s ti Baudrate*16. Registers ca cng ni tip Bng a ch v ngt ca cc cng COM Tn COM 1 COM 2 COM 3 COM 4 Bng 3: Bng a ch c s Trn l bng a ch c s. Chng lm vic trong a s cc PC.Ging nh cng LPT, d liu c s cho cc cng COM c th c t Vng D liu BIOS (BIOS Data Area). Start Address Function 0000:0400 COM1's Base Address 0000:0402 COM2's Base Address 0000:0404 COM3's Base Address 0000:0406 COM4's Base Address Bng 4: COM Port Addresses in BIOS Data Area; a ch 3F8 2F8 3E8 2E8 IRQ 4 3 4 3
Trn l bng cho thy a ch m chng ta c th tm thy a ch cc cng ni tip trong BIOS. Mi a ch s chim 2 bytes. Bng cc thanh ghi DLAB =0 =0 =1 =0 =1 Read/Write Write Read Read/Write Read/Write Read/Write Read Write Read/Write Read/Write Read Read Read/Write Abr. IER IIR FCR LCR MCR LSR MSR Register Name Transmitter Holding Buffer Receiver Buffer Divisor Latch Low Byte Interrupt Enable Register Divisor Latch High Byte Interrupt Identification Register FIFO Control Register Line Control Register Modem Control Register Line Status Register Modem Status Register Scratch Register
Base Address +0
+1 +2 +3 +4 +5 +6 +7
Bng 5: Bng cc thanh ghi Bit DLAB? Chng ta nn ch trong bng ca Register c ct DLAB. Khi DLAB thit lp 0 hoc 1 s c mt vi thay i ca thanh ghi. y l l do ti sao UART c th c 12 thanh ghi (bao gm c thanh ghi scratch) mc d ch c 8 cng a ch. DLAB l vit tt ca Divisor Latch Access Bit. Khi DLAB c t bng 1qua thanh ghi iu khin. Hai thanh ghi tr thnh sn c t chng ta c th t tc truyn thng ca chng. UART s c mt giao ng thch anh m cn phi dao ng xung quanh 1.8432Mhz. UART kt hp cht ch mt b chia bi b m 16 bit lm nhim v n gin l chia tn hiu clock gi n cho 16. Gi thit rng chng ta c tn hiu ng h 1.8432MHZ, m c th cho php chng ta c mt cc i, 115,200 hz bo hiu lm cho UART tr nn c kh nng truyn v nhn ti 115,200 Bits Per Second (BPS). iu l ph hp cho cc modem nhanh hn v cc thit b m c th iu khin tc , nhng nhiu thit b khng t c tc ny. Bi vy UART cn phi c thit lp hot ng vi tc thp hn thng qua hai thanh ghi cht gi tr chia tc . v d chng ta mun truyn thng ti 2400 BPS. Chng ta phi chia 115,200 bi 48 c th thc hin c 2400 Hertz Clock. Gi tr chia 48 trong trng hp ny, c ct gi trong hai thanh ghi cho php bi bit DLAB. Divisor ny c th l bt k s no m c th ct gi trong 16 bits (0 - 65535). UART ch c mt bus d liu 8 bit, v vy y l ni hai thanh ghi c s dng. Register u tin (Base + 0 khi DLAB = 1) ct gi byte thp trong khi register th hai (base + 1 khi DLAB = 1) ct gi byte cao ca gi tr chia.
Bn di l mt bng mt s tc v Divisor cht ca chng byte thp v byte cao. Ch rng tt c cc Divisor u c a vo h 16. Speed Divisor Divisor Latch High Byte Divisor Latch Low Byte (BPS) (Dec) 50 2304 09h 00h 300 384 01h 80h 600 192 00h C0h 2400 48 00h 30h 4800 24 00h 18h 9600 12 00h 0Ch 19200 6 00h 06h 38400 3 00h 03h 57600 2 00h 02h 115200 1 00h 01h Bng 6: Table of Commonly Used Baudrate Divisors Interrupt Enable Register (IER) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes Reserved Reserved Enables Low Power Mode (16750) Enables Sleep Mode (16750) Enable Modem Status Interrupt Enable Receiver Line Status Interrupt Enable Transmitter Holding Register Empty Interrupt Enable Received Data Available Interrupt
Interrupt Enable Register c th l mt trong nhng register n gin nht v d hiu trn UART. Thit lp bit 0 mc cao cho Received Data Available Interrupt m to ra mt ngt khi nhn register/FIFO cha d liu c bng CPU. Bit 1 cho php Transmit Holding Register Empty Interrupt. Ngt ny CPU khi b m truyn thng tin trng. Bit 2 cho php nhn ng ngt trng thi. UART s ngt khi nhn s chuyn i ng trng thi. Tng t nh vy i vi bit 3 th cho php ngt modem trng thi. Bit 4 n 7 th d dng hn. Chng c lu tr n gin . Interrupt Identification Register (IIR) Notes Bit 6 Bit 7 Bits 6 and 7 0 0 No FIFO Bit
0 1 FIFO Enabled but Unusable 1 1 FIFO Enabled Bit 5 64 Byte Fifo Enabled (16750 only) Bit 4 Reserved 0 Reserved on 8250, 16450 Bit 3 1 16550 Time-out Interrupt Pending Bit 2 Bit 1 0 0 Modem Status Interrupt Bits 1 and 2 0 1 Transmitter Holding Register Empty Interrupt 1 0 Received Data Available Interrupt 1 1 Receiver Line Status Interrupt 0 Interrupt Pending Bit 0 1 No Interrupt Pending Bng 8: Interrupt Identification Register interrupt identification register l register ch c (read only register). Bits 6 v 7 a ra trng thi FIFO Buffer. Khi c hai bit ny bng 0 th khng c FIFO buffers c kch hot. iu ny cn phi l kt qu duy nht chng ta s c 8250 hoc 16450. Nu bit 7 l tch cc nhng bit 6 l khng tch cc th UART c cho php b m ca n nhng li khng th dng c (it's buffers enabled but are unusable). iu ny xy ra trn 16550 UART khi c li trn FIFO buffer lm khng th dng c FIFO. Nu c hai bit l '1' th FIFO buffers l tch cc hon ton c th dng c. Bits 4 v 5 c lu tr. Bit 3 cho thy trng thi ca time-out interrupt trn 16550 or higher cao hn. cho nhy n Bit 0 m cho thy interrupt xut hin. Nu mt interrupt xut hin trng thi ca n s hin bi bits 1 v 2. Nhng ngt lm vic trng thi quyn u tin. Line Status Interrupt c quyn u tin cao nht, sau l Data Available Interrupt, tiip theo l Transmit Register Empty Interrupt v k l Modem Status Interrupt m c quyn u tin thp nht . First In/First Out Control Register (FCR) FIFO register l register ch ghi (write only register). Register ny c s dng iu khin FIFO (First In/First Out) buffers m c tm thy trn 16550 cao hn. Bit 0 cho php thao tc nhn v truyn ca FIFO. Ghi '0' ti bit ny s v hiu ho thao tc truyn v nhn ca FIFO, v vy chng ta phi loose ct tt c d liu trong FIFO buffers. Bit's 1 v 2 iu khin vic lm sch vic truyn hoc nhn ca FIFO. Bit 1 chu trch nhim cho b m nhn trong khi bit 2 chu trch nhim cho b m truyn. Thit lp nhng bit ny ln 1 s ch lm sch ni dung ca FIFO v s khng nh
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hng n thanh ghi. Hai bit ny s cng c xc lp li, v vy chng ta khng cn thit lp bit ny v 0 khi kt thc. Bit Notes Bit 7 Bit 6 Interrupt Trigger Level 0 0 1 Byte Bits 6 0 1 4 Bytes and 7 1 0 8 Bytes 1 1 14 Bytes Bit 5 Enable 64 Byte FIFO (16750 only) Bit 4 Reserved DMA Mode Select. Thay i trng thi ca chn RXRDY & Bit 3 TXRDY t mode 1 n mode 2. Bit 2 Clear Transmit FIFO Bit 1 Clear Receive FIFO Bit 0 Enable FIFO's Bng 9: FIFO Control Register Bit 3 cho php DMA la chn mode m c tm thy trn 16550 UARTs v cao hn. Bits 4 la bit d tr. Bits 6 and 7 c s dng thit lp triggering level on Receive FIFO. V d nu bit 7 c thit lp nn '1' v bit 6 c thit lp xung '0' th trigger level s thit lp vi 8 bytes. Khi c 8 bytes ca d liu trong receive FIFO th ngt Received Data Available c thit lp (See IIR). Line Control Register (LCR) Bit 7 1 Divisor Latch Access Bit Truy cp ti Receiver buffer, Transmitter buffer & 0 Interrupt Enable Register Bit 6 Set Break Enable Bits 3, 4 Bit 5 Bit 4 Bit 3 Parity Select And 5 X X 0 No Parity 0 0 1 Odd Parity 0 1 1 Even Parity 1 0 1 High Parity (Sticky) 1 1 1 Low Parity (Sticky) Bit 2 Length of Stop Bit 0 One Stop Bit 2 Stop bits for words of length 6,7 or 8 bits or 1.5 Stop 1 Bits for Word lengths of 5 bits. Bits 0 And Bit 1 Bit 0 Word Length
0 0 1 1
0 1 0 1
5 Bits 6 Bits 7 Bits 8 Bits
Bng 10: Line Control Register Line Control register thit lp nhng tham s c bn cho vic truyn thng. Bit 7 l Divisor Latch Access Bit (DLAB). Chng ta ni v chc nng ca n (Xem DLAB). Bit 6 thit lp cho php dng ( Break). Khi tch cc, ng TD i vo trng thi "Spacing" m nguyn nhn lm dng ( Break) vic nhn UART. Thit lp bit ny v '0' v hiu ho Break (Disables Break). Cc 3, 4 v 5 la chn parity. Nu chng ta nghin cu 3 bit ny, chng ta s thy rng bit 3 iu khin chn l (controls parity). l, nu n thit lp v '0' th khng c parity c s dng, nhng nu n thit lp ti '1' th parity c s dng. Nhy qua ti bit 5, chng ta c th thy rng n iu khin sticky parity. Sticky parity l n gin khi parity bit lun lun truyn v kim tra '1' hoc '0'. Bit ny c rt t thnh cng trong vic kim tra li nh nu 4 bit u tin c li nhng sticky parity bit cha vic thit lp bit thch hp, th mt parity li s khng cho kt qu. Sticky parity cao l s dng '1' cho parity bit, trong trng hp ngc li, sticky parity thp th s dng '0' cho parity bit. Nu bit 5 iu khin sticky parity, th s i hng bit ny khng phi cho kt qu bnh thng parity c cung cp bit 3 l s thit lp ln '1'. Parity l l khi bit parity pht tn hiu '1' hoc '0' v th m c mt s l cc bit 1 v ngc li. iu ny cung cp s kim tra li tt hn nhng vn khng phi l hon ho, v th CRC-32 c s dng thng xuyn cho sa li phn mm. Nu mt bit b li th c th pht hin li nh bit P, tuy nhin nu hai bit b lt theo mt cch no m n sinh ra parity bit th vic parity b li l khng th pht hin c. Bit 2 thit lp di ca nhng bit stop. Vic thit lp nhng bit ny v 0 s em li mt stop bit, tuy nhin nu thit lp n ln 1 s em li 1.5 hoc 2 stop bit ph thuc vo di d liu. Ch rng b nhn ch kim tra bit stop u tin. Bits 0 and 1 thit lp di s bit d liu. Thng thng th di l 8 bit. Modem Control Register (MCR) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
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Notes Reserved Reserved Autoflow Control Enabled (16750 only) LoopBack Mode Aux Output 2 Aux Output 1 Force Request to Send
Bit 0
Force Data Terminal Ready Bng 11: Thanh ghi Modem Control
Thanh ghi Modem Control l mt thanh ghi Read/Write. Bit 5,6 v 7 l bit d tr. Bit 4 kch hot ch loopback. Trong ch Loopback vic truyn thng ni tip ra ngoi c t vo trong trng thi Mark. u vo ni tip c ngng kt ni. Line Status Register (LSR) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes Error in Received FIFO Empty Data Holding Registers Empty Transmitter Holding Register Break Interrupt Framing Error Parity Error Overrun Error Data Ready
Bng 12: Line Status Register Thanh ghi trng thi ng truyn (line status register) l thanh ghi ch c. Bit 7 l bit error in received FIFO bit. Bit ny l bit cao khi c t nht mt li break, parity hoc framing xy ra trn mt byte m c cha trong FIFO. Khi bit 6 c thit lp, th c hai thanh ghi transmitter holding register v thanh ghi shift register trng. Thanh ghi UART's holding gi byte tip theo ca d liu s c gi n parallel fashion. Thanh ghi dch chuyn (shift register) c s dng chuyn i byte ni tip, v th m n cot th truyn trn mt ng. Khi bit 5 c thit lp, th ch thanh ghi transmitter holding register trng. V th s khc nhau gia hai bit l g? Khi bit 6 c thit lp, th thanh ghi transmitter holding v thanh ghi shift registers trng, khng c qu trnh chuyn i ni tip no xy ra v th phi khng c qu trnh hot ng no trn ng truyn d liu. Khi bit 5 c thit lp, th thanh ghi transmitter holding register trng, v th nhng byte khc c th dc gi n cng d liu, nhng vic chuyn i ni tip ang s dng thanh ghi dch chuyn (shift register) c th chim ch. break interrupt (Bit 4) xy ra khi ng d liu nhn c gi trong trng thi lgic '0' (Space) cho khong thi gian hn thi gian n dng n khi gi mt word y . Thi gian bao gm c thi gian cho start bit, data bits, parity bits and stop bits. A framing error (Bit 3) xy ra khi bit cui cng khng phi l stop bit. iu ny xy ra v mt li tnh ton thi gian. Thng thng chng ta s gp phi mt li framing error khi s dng mt null modem lin kt hai my tnh hoc protocol analyzer when speed at which data is being sent is different to that of what chng ta phi thit lp UART nhn n.
A overrun error thng thng xy ra khi chng trnh ca chng ta khng th c t cng nhanh. Nu chng ta khng c mt byte u vo ngoi ca thanh ghi nhanh (register fast enough), v byte khc nhn, th byte cui cng s b mt v mt li trn s xy ra. Bit 0 cho thy data ready, c ngha l mt byte c nhn bi UART v b m sn sng c. Modem Status Register (MSR) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes Carrier Detect Ring Indicator Data Set Ready Clear To Send Delta Data Carrier Detect Trailing Edge Ring Indicator Delta Data Set Ready Delta Clear to Send
Bng 13 : Modem Status Register Bit 0 ca modem status register cho thy delta clear to send, delta c ngha l mt s thay i bn trong, v vy delta clear to send ngha l c mt s thay i bn trong ng clear to send, t ln c cui cng ca thanh ghi ny. iu ny cng ng vi cc bits 1 v 3. Bit 1 cho thy s thay i bn trong ng Data Set Ready trong khi Bit 3 cho thy mt s thay i bn trong ng Data Carrier Detect. Bit 2 l Trailing Edge Ring Indicator ch bo rng c mt s bin i t trng thi thp n trng thi cao trn ng Ring Indicator. Bits 4 n bit 7 cho thy trng thi hin thi ca cc ng d liu khi c. Bit 7 cho thy Carrier Detect, Bit 6 cho thy Ring Indicator, Bit 5 cho thy Data Set Ready & Bit 4 cho thycc trng thi ca ng Clear To Send. Scratch Register scratch register khng s dng cho truyn thng nhng c s dng nh mt ni lu mt byte ca d liu. Vic s dng thc t ca n l xc nh UART l 8250/8250B hoc a 8250A/16450 v thm ch ci khng phi l chnh thc nh 8250/8250B khng bao gi c thit k cho AT v khng th hack bus speed.
6.4. Giao tip USB ca my PC:

6.4.1 Gii thiu chung. USB l mt giao tip cho php d liu truyn gia my tnh ch (host) v mt nhiu loi thit b ngoi vi ng thi. Thit b ngoi vi c cm vo c chia s bng thng ca USB thng qua giao thc da trn c ch lp lch v dng th bi
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(token). H thng bus ny cho php cc thit b c th cm vo, thit lp ch , s dng v rt ra trong khi host v cc TBNV khc vn ang hot ng 6.4.2 M t h thng USB Mt h thng USB c m t bao gm ba thnh phn chnh sau: Kt ni USB (USB interconnect) Cc thit b USB (USB devices) Ch USB (USB host)
Kt ni USB cho bit phng thc m cc thit b kt ni v truyn thng vi my ch (host). Bao gm nh sau: Cu trc lin kt bus (Bus Topology): M hnh lin kt gia cc thit b USB v host Cc quan h lp trong (Inter-layer Relationships): Cc tc v ca USB c thc hin theo tng lp trong h thng M hnh lung d liu (Data Flow Models): L cch m d liu di chuyn trong h thng gia cc i tc truyn thng Lp lch USB (USB Schedule): USB cung cp mt kt ni chia s. Vic truy nhp vo kt ni c lp lch c th h tr truyn thng ng thi v trnh xung t
Cu trc lin kt bus
V mt vt l USB l mt kin trc tng sao (tiered star) . Mt HUB ti trung tm ca mi sao, vi 7 bit a ch USB cho php qun l ti a 127 thit b ngoi vi y l con s mang tnh l thuyt bi khi c cng nhiu thit b u ni th tc truyn cng chm do di thng ca ton b bus b phn chia n tng thit b
Hnh 6.1: Cu trc tng sao ca USB
Ch USB ( host USB) Ch USB chnh l my tnh c nhn vi h iu hnh c kh nng qun l USB Mt mng USB ch c php c mt ch USB , my tnh s dng phn cng phn mm USB lm vic nh mt ch bus . My tnh nhn bit vic cm thm hay d b mt thit b ngoi vi khi ng qu trnh nh s v cc qu trnh truyn d liu khc trong bus. My tnh cng c trch nhim kim tra trng thi ,thng k hot ng v kim tra ghp ni in gia b iu khin ch v cc thit b USB ngoi vi. Thit b USB Cc thit b USB c chc nng t trong mng bus . Ta chia ra lm hai loi thit b USB : HUB
Mt hub ngoi c mt cng hng v my ch (upstream) v 4 cng ra thit b ghp ni (downstream) trong my PC cng c mt hub cm ngay trn bn mch chnh hub ny c gi l hub gc (roothub). Hub thng gm c mt b iu khin hub v mt b lp (repeater) mt hub c chc nng : chuyn mt cm USB thnh nhiu cm, nhn bit cc thit b mi c u vo , xo i mt thit b u ni vo bus nhng sau y c tho ra thc hin c vic ny c nhng trng thi bus c to ra theo cch c bit (da vo mc in p , ta khng cp n k thut ny y) C th ni tri tim ca hub chnh l vi iu khin USB 8x930 l loi vi iu khin 8 bit vi b nh v cng ngoi vi c cy bn trong vi iu khin ny c th x l c c 4 loi truyn d liu : iu khin, ngt ng b cch bit v khi. Truyn d liu gia thit b v my ch c thc hin thng qua mt cp im cui trong vi iu khin ny mi im cui c trang b mt b m FIFO pht v FIFO thu. Tu vo cc ng dng m ta cn cc FIFO c dung lng khc nhau Hot ng ca b iu khin USB c lp trnh thng qua cc thanh ghi chc nng c bit ., giao thc USB c cy bn trong ROM ca 8x930 v vy ngi lp trnh khng cn quan tm n vn ny Thit b chc nng
L cc thit b ngoi vi nh : chut, bn phm. Mn hnh, my qut, ADC, vi iu khin mi thit b chc nng ca bus u phi theo cc qui nh ca USB my ch c th nhn bit c chng. M i thi t b USB u c thi t k g m 3 ph n chnh : Phn giao din tun t SIE l vi mch chu trch nhim nhn v gi d liu theo chun USB Mt t hp gia phn cng v firmware nhn nhim v truyn d liu gia khi SIE v im cui ca thit b qua cc ng ng (pipe) thch hp ca chng
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Thnh phn th 3 l phn chc nng ca thit b ngoi vi
6.4.3 Giao din vt l Giao din vt l ca USB m t v mt in t v c kh ca kt ni USB
Chun v c kh (Mechanical):
Chun USB s dng cp 4 si truyn tn hiu v ngun nui. Tn hiu c truyn qua 2 dy cho mi on lin kt im im. C ba loi cp chnh Cp USB tc cao (high-speed) l 480 Mb/s. Cp USB tc (full-speed) l 12 Mb/s. Cp USB dnh cho truyn thng tc thp 1.5 Mb/s.
Cp USB high/full-speed
. Hnh 6.2 Cp dng cho USB USB quy nh hai loi u cm c gi l dng A v B. Hai loi ny ch khc nhau v kiu dng
Hnh 6.3: u cm USB dng A v B Chun v in t (Electrical)
Tn hiu ng h c truyn v gii m cng vi d liu. Phng php m ho bit l NRZI cng vi vic nhi bit m bo chnh xc trong truyn thng.
Chn 1 2 3 4
Tn gi VBUS DD+ GND
Mu dy Trng Xanh lc en
M t +5Vdc Dliu Dliu + Ni t
Qua cm USB pha sau my tnh c th ly ra in p +5v vi dng tiu th khong 100mA , trong mt s trng hp c th ly ra dng tiu th n 500mA Hai ng dn d liu D+ v D- l cc tn hiu vi sai vi mc in p bng 0/3,3V. in p ngun nui bus USB c th n +5.25 V V khi chu dng ti ln c th gim xung +4.2V, nu b sung mt vi mch n p c th to ra mt in p n nh +3.3V Ton b h thng c thit k sao cho khi chu dng ti ln in p ngun cng khng vt qu +4.2V. Khi thit b ghp ni cn dng ln hn 100mA cn xem xt k kh nng cung cp v chu ti ca cc linh kin trong my tnh. y cng chnh l mt trong cc u im ca USB l cc thit b chc nng c th ly ngun nui lun t host M c tn hi u: Chun USB quy nh mc ca tn hiu cho tng kiu truyn low-speed, full-speed v high-speed Low-/Full-speed Mc tn hiu Trng thi bus Ti pha pht (vo thi im kt thc thi gian bit) D+ > VOH (min) and D- < VOL (max) D- > VOH (min) and D+ < VOL (max) Ti pha nhn Yu cu (D+) - (D-) >200 mV v D+ >VIH (min) (D-) - (D+) > 200 mV Chp nhn c (D+) - (D-) >200 mV (D-) - (D+) > 200 mV
1 0
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v D->VIH (min) Trng thi ri: Lowspeed Full-speed Khng quan tm D- > VIHZ (min) v D+ < VIL (max) D+ > VIHZ (min) v D- < VIL (max) D+ and D-<VIL (max) for 10 ms D- > VIHZ (min) v D+ < VIH (min) D+ > VIHZ (min) v D- < VIH (min) D+ and D-<VIL (max) for 2.5 s
Reset
D+ and D-<VOL (max) for 10ms
Vi kiu truyn Low-/Full-speed, bn ngun phi m bo a ra c mc tn hiu ch ra ct 2 v bn nhn phi nhn ra trng thi ng ca ng truyn ng vi mc ct 3 Full-/High-speed Tr ng thi ng truy n Tn hi u sai phn Highspeed 1 M c tn hi u bn pha pht M c tn hi u m t chi u DC: VHSOH (min) D+ VHSOH (max) VHSOL (min) DVHSOL (max) M c tn hi u sai phn AC: A transmitter must conform to eye pattern templates called out in Section 7.1.2. M c tn hi u bn pha thu
See Note 2. Tn hi u sai phn Highspeed 0 DC Levels: VHSOH (min) DVHSOH (max) VHSOL (min) D+ VHSOL (max)
M c tn hi u sai phn AC signal at target connector must be recoverable, as defined by eye pattern templates called out in Section 7.1.2. See Note 2.
See Note 1. AC Differential Levels: A transmitter must conform to eye pattern templates called out in Section 7.1.2.
See Note 2. Tr ng thi r i Highspeed NA
AC Differential Levels: signal at target connector must be recoverable, as defined by eye pattern templates called out in Section 7.1.2. See Note 2. DC Levels: VHSOImin (D+, D-) VHSOImax See Note 1. AC Differential Levels: Magnitude of differential voltage is 100 mV See Note 3.
M ha v gi i m tn hi u: USB thc hin m ha theo phng php NRZI (Non Return to Zero Inverted) khi truyn mt gi tin. Vi phng php NRZI, bit 1 th hin bng s khng thay i v mc tn hiu trn ng truyn cn bit 0 th hin bng s thay i mc tn hiu.
Nh i bt (Bit Stuffing) m bo s chnh xc khi truyn tn hiu, chun USB thc hin nhi bit khi truyn cc gi tin. Mt bit 0 s c thm vo (nhi) sau mi 6 bit lin tc trong lung d liu trc khi m ha NRZI c thc hin. iu m bo cho bn nhn c th ng b ha tn hiu xung ng b sau mi 7 bit. Vic nhi bit c cho php bt u sau mu SYNC. Bit 1 cui ca mu ng b SYNC c m l bit u tin trong chui d liu. Bn nhn phi gii m d liu NRZI, pht hin ra bt nhi v b qua chng.
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im cui v ng ng
im cui l u ngun hay u pht ca mt thit b ngoi vi , mt thit b ngoi vi c th c nhiu im cui n ch ra d liu cn thit c dn ti u hoc cn phi n nhn t u , n lm cho thit b c nh a ch mt cch linh hot v d nh chut USB chng hn c mt im cui 0 , mt im cui 1. im cui 0 c s dng khi khi to cc d liu hu ch c b vi iu khin ghi trn mt khong cch nh trc tnh theo im cui 1 v t my PC c vo Mi im cui thit b thng tng ng vi mt FIFO ng vai tr trung gian gia cc cuc truyn , nhn d liu gia khi SIE v phn cn li ca thit b Mt ng ng l mt knh logic dn ti mt im cui trong mt thit b , ta c th hnh dung ng ng nh mt knh d liu c hnh thnh t mt dy dn ring l . Nhng trn thc t d liu c truyn trn ng ng di dng cc gi d liu trong mt khung truyn chim hng mili giy v c phn cng phn pht thng qua a ch im cui . Mt thit b c th s dng nhiu ng ng ng thi v th tc truyn d liu tng cng c nng ln . Ni cch khc ng ng l phn mm qun l im cui ca thit b USB , ta c th hiu chng l nhng knh phn mm c gi ln trong phn mm iu hnh USB v c nhim v truyn tin n nhng im cui ca thit b ngoi vi , mi thit b trong bus USB s cng chia gii tn qua mt giao thc khung truy nhp my ch.
Kt ni cc thit b USB
Khi c mt kt ni n HUB n s thng bo n my ch , my ch hi HUB xc nh nguyn nhn ca thng bo , HUB tr li bng vic nhn dng cng kt ni vi thit b USB . My ch cho php cng v nh a ch thit b USB vi mt ng ng iu khin bng cch s dng a ch mc nh USB, tt c cc thit b khi u ni vo ln u u c nhn mt a ch mc nh USB , Host xc nh xem thit b va c u ni l HUB hay thit b chc nng v gn cho thit b USB mt a ch duy nht My ch thit lp mt ng ng iu khin i vi thit b USB bng cch s dng a ch USB c gn v s 0 im cui. Nu thit b USB l mt hub th khi c mt thit b USB kt ni vo n qu trnh trn din ra lin tc Nu thit b USB l mt thit b chc nng th cc thng bo v vic kt ni s c phn mm USB gi ti phn mm my ch Loi b cc thit b USB Khi mt thit b USB c g b t mt trong s cc cng ca hub th hub t ng v hiu ho cng v cung cp mt thng tin cho host bo v vic loi b thit b ra khi bus. Sau y host s loi b cc s liu vit v thit b va d b Nu thit b USB d b l mt hub th qu trnh d b phi c thc hin vi tt c thit b USB m trc c u ni vo hub
6.4.4 S im danh Nh ta bit phn trc mt u im c bit ca bus USB l kh nng cm l chy ( Plug and Play) i vi thit b mi c u ni vo bus . Mun th h thng phi hot ng trong trng thi thng xuyn kim tra thng tin t mt thit b , t thng tin ny thit b s c np phn mm iu khin thch hp Khi mt thit b mi c im danh (enumeration) s nhn c mt a ch bus v c h tr qua mt phn mm c th Vic im danh c thc hin hon ton c lp bi h iu hnh, khi mt thit b mi c u ni vo c th xy ra hin tng l h iu hnh yu cu cn mt a iu khin thch hp Nhng cng c nhiu phn mm iu khin c tch hp trong h thng Qu trnh im danh l qu trnh h iu hnh tin hnh kim tra cc phn cng mi c u ni vo qua thng tin n thu c t thit b c u ni . Thng tin ny thng gi l bn tm lc Khi c mt thit b mi c u ni vo bus sau y din ra cc bc sau : Hub nhn bit c v n thng bo vi my ch l c mt thit b mi c u ni vo My ch hi li hub xem thit b c ni vo cng no My ch khi ny bit thit b c ni vo cng no , n s a ra mt lnh ni n cng v thc hin mt thao tc reset li bus Hub to ra mt tn hiu reset vi di 10 ms v cp mt dng in vi cng 100mA cho thit b . By gi thit b sn sng hot ng v tr li bng mt a ch mc nh 0 Trc khi nhn c mt a ch ring th thit b vn c trao i vi host thng qua a ch mc nh . my ch c byte u tin ca bn tm lc, xem ln bn tm lc l bao nhiu My ch gn cho thit b mt a ch bus ring Qua a ch mi my ch c tt c cc thng tin cu hnh c t thit b Qua my ch s gn cho thit b mt phn iu khin ph hp nu c th. By gi thit b s c php ly ra dng in tiu th nh trong bn tm lc nu. Nh vy l thit b v my ch u sn sng trao i
Mi thit b c cc thng s nh : m giao thc , nh sn xut , loi thit b , ln FIFO, dng tiu th Tt c cc thng tin ny c lu trong ROM ca thit b khi thit b c u ni vo vi iu khin ca hub s c cc thng tin ny v truyn cho my ch . my ch c nhng iu khin ph hp 6.4.5 Cc kiu truyn USB Truyn d liu USB l giai on nm gia phn mm my ch v im cui ca thit b ngoi vi . Thng tin c th i theo mt chiu hoc 2 chiu . My ch x l
vic trao i d liu vi tng thit b ngoi vi mt cch c lp . USB qun l 4 kiu truyn d liu Truyn iu khin ( control transfer ): l truyn theo kiu 2 chiu, kiu truyn ny c s dng ci t thit b ngoi vi giao thc truyn iu khin c bt u bng mt gi khung , tip theo l gi d liu v kt thc l gi bt tay . Mi thit b ngoi vi USB u phi x l c kiu truyn ny Truyn ngt : L truyn mt chiu . Cc thit b cung cp mt lng d liu nh tun hon nh : chut , bn phm, joystick . V my tnh khng th ngt nn cc ngt t thit b ngoi vi c x l trong vng i , tc theo chu k h thng s hi ( 10ms chng hn ) xem c d liu mi c gi n khng. Giao thc ny khi ng bng mt khung IN (IN token) . Thit b ngoi vi tr li bng mt gi NAK nu khng c ngt nu c ngt ngoi vi tr li bng mt gi d liu , khi vic nhn d liu hon thnh my ch tr li bng mt ACK , nu c li khng tr li . Nu b nghn im cui ca thit b ngoi vi n s gi n my ch gi STALL v i h thng x l Truyn ng thi: l phng php truyn mt chiu .V th cuc truyn cn hai im cui thit b ngoi vi hoc hai pipe phn mm my ch . Khi c mt lng ln d liu vi tc d liu c qui nh nh card m thanh , loa , in thoi s dng kiu truyn ny . theo kiu truyn ny vic khc phc li khng c thc hin bi nhng li truyn l t cng khng nh hng ng k n cht lng cuc truyn Truyn theo khi : Truyn 2 chiu , khi c lng ln d liu cn truyn v cn kim sot li , nhng khng c yu cu thc p v thi gian truyn th s dng kiu truyn ny. V d : my in , my qut
i vi cc ng dng trong o lng iu khin kiu truyn iu khin thng c s dng v va c an ton d liu va c tc ln 6.4.6 Giao thc USB Phn ny ta s m t v cc lp giao thc ca USB My ch USB s gi bus hot ng lin tc bng cch truyn i mt gi khi u khung SOF ( start of Frame) trong chu k 1ms . Ni chung mi ln truyn tin My ch USB cn 3 gi Gi m thng bo (Token packet) Gi d liu (Data packet) Gi bt tay (Handshake packet)
Trc khi i vo chi tit cc gi ta nh ngha mt s trng. Tu thuc vo tng gi m c to thnh bi cc trng khc nhau Cc trng
Trng Sync: Tt c cc gi u bt u bng trng ny , trng ny gm 8 bit . N c s dng ng b xung clock ca vic thu vi vic pht, 2 bit sau cng c s dng ch u trng PID bt u v im kt thc ca trng Sync Trng nh danh gi : Trng nh danh gi (PID) c cho theo sau trng Sync ca cc gi USB
Bn bit u ca trng ny cho ta bit kiu gi ,khun dng ca gi v kiu pht hin li c p dng cho gi Bn bit sau l bn bit b ca 4 bit trc n l cc bit kim tra n c s dng m bo qu trnh gii m l tin cy. Nu c mt li PID xy ra th 4 bit ny khng phi l 4 bit b ca 4 bit trc. Host v cc thit b chc nng phi gii m c tt c cc trng PID nhn c .Nu mt PID no c li xut hin li ny c th l do: khng gii m c gi tr , hoc mang n mt gi tr khng c nh ngha .Th thng tin ny b cho l sai lch v pha nhn s b qua. Sau y l bng cc kiu v gi tr PID vi cc gi khc nhau
Kiu PID Token
Tn PID OUT IN
Gi tr PID 0001 1001
M t Cho bit a ch v im cui trong giao tc t Host ti chc nng Cho bit a ch v im cui trong giao tc t chc nng ti Host Gi khi u khung v s khung Cho bit a ch v im cui trong giao tc SETUP t host ti chc nng Gi d liu chn Gi d liu l Bn nhn tip nhn c gi d liu khng c li Thit b nhn khng tip nhn d liu hoc thit b pht khng th gi gi liu i c im cui b dng hoc ng iu khin khng c h tr Khng p ng vic nhn Host ra tn hiu cho php cng downstream thc hin truyn tc thp
SOF SETUP Data Handshake DATA0 DATA1 ACK NAK
0101 1101 0011 1011 0010 1010
STALL NYET Special PRE
1110 0110 1100
106
ERR SPLIT PING Tr ng a ch
1100 1000 0100
Trng ny c 7 bit a ch do n tr ti c 127 a ch , a ch 0 l khng hp l. N ch c ngha khi thit b va u ni vo v y l a ch mc nh .
Trng ny ch ra ngun hoc ni n ca gi d liu Tr ng i m cu i Trng im cui (ENDP) c kch thc 4 bit tr c 16 im cui. Trng ny cho php xc nh cc im cui mt cch linh hot trong cc thit b c nhiu hn mt im cui
Tr ng d li u Trng d liu ca giao thc USB cho php c kch thc t 0 n 1024 byte v phi l mt s nguyn ca byte
Tr ng s khung C ln 11 bit do host tng thm trn mi khung c s , trng s khung ln ti con s cc i l 7FFH v ch c gi trong cc m thng bo SOF ti thi im khi u ca mi khung Tr ng ki m tra d phng tu n hon (CRC) c s dng bo v tt c cc trng NON-PID trong gi m thng bo (token) v gi d liu (data). Trng ny c pht sinh thng qua cc trng tng ng ca n b phn pht trc khi thc hin vc nhi bit. Tng t vy CRC c gii m b phn nhn sau khi loi b vic nhi cc bit. Nu mt CRC b li th cc trng tng ng s b b qua bn nhn Tr ng k t thc gi : Trng kt thc gi EOP n nh du s kt thc ca mt gi
6.4.7 Khun dng cc gi tin Trong phn ny ta s ta s m t v cc loi gi tin: gi tin bt u khung SOF, gi m thng bo (token),gi d liu (data packet),gi bt tay (handshake) y l 3 gi c s dng trong truyn tin USB. Host s gi bus hot ng lin tc bng cch truyn lin tc gi SOF trong chu k 1.00ms0.0005ms. Cuc truyn bt u khi b iu khin ch gi mt gi m thng bo gm a ch thit b , s hiu im cui ENDP, hng ca cuc truyn v dng ng. Thit b c a ch tng ng s t chn bng cch gii m a ch ca n t gi m thng bo . Trng ghi hng ca cuc truyn trong gi m thng bo s yu cu thit b ngoi vi pht d liu. Thit b ngoi vi s tr li bng gi d liu. Nu khng my ch s tip tc bng vic truyn d liu Tm li sau khi nhn c d liu , ni nhn ( host or ngoi vi) s gi li mt gi bt tay. Gi ny c th l : ACK ( chp nhn d liu), NAK (khng chp nhn d liu), STALL ( tc nghn) Khun dng gi bt u khung
Gi bt u khung SOF c a ra bi host vi tc 1.00ms0.0005ms cho full-speed v 125us 0.0625us cho high-speed Sync PID Frame Number CRC5 EOP
Mi gi SOF gm mt trng PID kch thc 8bit dng bo loi gi ( tc bo rng n chnh l gi SOF) , tip theo l 11 bit trng s khung v 5 bit CRC ( ta khng cp n Sync v EOP v hai trng ny l bt buc vi mi gi) Khun d ng gi m thng bo Sync PID ADDR ENDP CRC5 EOP
Gi ny gm trng PID 8 bit dng ch r kiu gi l gi IN ,OUT hay SETUP tip theo l 7 bit trng a ch ,4bit trng im cui v 5 bit trng CRC i vi giao tc OUT v SETUP cc trng a ch v im cui s xc nh ra im cui nhn gi d liu tip o. Hai giao tc ny dng cho cc giao tc t host n thit b chc nng
i vi giao tc IN cc trng ny ch ra im cui no cn phi truyn d liu i. Giao tc ny dng cho cc giao tc t thit b chc nng n host Khun d ng gi d li u Khun dng gi d liu gm 3 trng :
108
Trng PID (8 bit) dng xc nh loi gi Trng d liu ( t 0 n 1024 byte) Trng d phng CRC ( 16bit)
Sync
PID
DATA
CRC5
EOP
C hai kiu gi d liu l DATA0 v DATA1 Khun d ng gi b t tay Sync PID EOP
Cc gi bt tay ch c mt trng PID . Cc gi bt tay c s dng thng bo s giao tc l thnh cng hay khng thnh cng Cc tn hiu bt tay lun c tr v trong cc pha bt tay ca mt giao tc hoc c tr v trong pha d liu . Khi ny n khng gi gi liu m dng gi tn hiu bt tay C ba loi gi bt tay - ACK : Tn hiu ny bo rng gi d liu nhn c m khng c qu trnh nhi bit hoc c cc li CRC trng d liu v PID ca gi d liu nhn c l chnh xc . Tn hiu ACK c dng thch hp nht l trong cc giao tc khi m d liu c truyn i v ch tn hiu bt tay tr v . ACK c th c host tr v trong giao tc IN v c th c thit b chc nng tr v trong giao tc OUT v SETUP - NAK : Tn hiu ny s dng bo rng mt thit b chc nng khng th chp nhn d liu t Host gi n ( thng qua giao tc OUT hoc mt thit b chc khng c d liu truyn n Host ( thng qua giao tc IN ) . Tn hiu bt tay NAK c th c cc thit b chc nng tr v trong pha d liu ca giao tc IN hoc pha bt tay ca giao tc OUT . Host c th khng bao gi a ra tn hiu bt tay NAK. Ngoi ra tn hiu bt tay NAK cn c s dng cho nhng mc ch iu khin lung bo rng mt thit b chc nng tm thi khng th truyn hoc nhn d liu , nhng chc nng s dn dn c kh nng truyn hoc nhn d liu m khng cn s can thip ca host - STALL: Tn hiu ny dng bo rng mt chc nng khng th truyn hoc nhn d liu , hoc yu cu ng d liu m khng c h tr . Tn hiu bt tay ny c thit b chc nng tr v trong p ng ti m thng bo IN hoc sau khi pha d liu ca mt giao tc OUT. Tn hiu bt tay STALL c to ra bi thit b chc nng do mt trong hai nguyn nhn sau: Nguyn nhn th nht :c hiu nh l tc do chc nng (Functional stall) n lin quan n vic thit lp im cui ca cuc truyn khi m
host dt khot thit lp c tnh dng trn im cui Mt im cui ca chc nng m b dng th n lin tc tr v tn hiu bt tay STALL cho n khi tnh trng chm dt nh s can thip ca host Nguyn nhn th 2: c hiu nh l tc giao thc (protocol stall) iu ny ch lin quan n cc ng iu khin stall do nguyn nhn ny sinh ra c tr v trong giai on d liu hoc giai on trng thi ca qu trnh truyn iu khin
110
Chng 7. Giao tip vi cc thit b ngoi vi c bn
CHNG 7. GIAO TIP VI CC THIT B NGOI VI C BN

Mc tiu: Trnh by cu trc, nguyn l hot ng v lp trnh iu khin cho cc thit b ngoi vi c bn ca my tnh PC nh bn phm, chut, mn hnh,
Tm tt chng: Giao tip vi bn phm v chut Giao tip PC Game Monitor v card giao din ho
7.1. Giao tip vi bn phm v chut

7.1.1 Bn phm Cu trc v chc nng:
Hnh 7.8 - S nguyn l v cc ghp ni ca bn phm Chip x l bn phm lin tc kim tra trng thi ca ma trn qut (scan matrix) xc nh cng tc ti cc ta X,Y ang c ng hay m v ghi mt m tng ng vo b m bn trong bn phm. Sau m ny s c truyn ni tip ti mch ghp ni bn phm trong PC. Cu trc ca SDU cho vic truyn s liu ny v cc chn cm ca u ni bn phm. SDU 10 0 STRT DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 PAR STOP STRT: DB0 - DB7: PAR: STOP: bit start (lun bng 0) bit s liu t 0 n 7. bit parity (lun l) bit stop (lun bng 1).
Tn hiu xung nhp dng cho vic trao i d liu thng tin ni tip ng b vi mch ghp ni bn phm (keyboard interface) trn main board c truyn qua chn s 1. Mt b iu khin bn phm c lp t trn c s cc chp 8042, hoc 8742,8741. N c th c chng trnh ha (th d kha bn phm) hn na s liu c th truyn theo 2 hng t bn phm v mch ghp ni, do vy vi m ca chp bn phm c th gip cho vic nhn lnh iu khin t PC, th d nh t tc lp li ca nhn bn phm,.
112
Hnh 7.9 u cm bn phm AT
Hnh 7.10 u cm bn phm PS/2 M qut bn phm: Mi phm nhn s c gn cho 1 m qut (scan code) gm 1 byte. Nu 1 phm c nhn th bn phm pht ra 1 m make code tng ng vi m qut truyn ti mch ghp ni bn phm ca PC. Ngt cng INT 09h c pht ra qua IRQ1. Chng trnh x l ngt s x l m ny tu theo phm SHIFT c c nhn hay khng. V d: nhn phm SHIFT trc, khng ri tay v sau nhn C: make code c truyn - 42 (SHIFT) - 46 (C). Nu ri tay nhn phm SHIFT th bn phm s pht ra break code v m ny c truyn nh make code. M ny ging nh m qut nhng bit 7 c t ln 1, do vy n tng ng vi make code cng vi 128. Tu theo break code, chng trnh con x l ngt s xc nh trng thi nhn hay ri ca cc phm. Th d, phm SHIFT v C c ri theo th t ngc li vi th d trn: break code c truyn 174 ( bng 46 cng 128 tng ng vi C) v 170 (bng 42 cng 128 tng ng vi SHIFT). Phn cng v phn mm x l bn phm cn gii quyt cc vn vt l sau: Nhn v nh phm nhng khng c pht hin. Kh nhiu rung c kh v phn bit 1 phm c nhn nhiu ln hay c nhn ch 1 ln nhng c gi trong mt khong thi gian di. Truy xut bn phm qua BIOS BIOS ghi cc k t do vic nhn cc phm vo b m tm thi c gi l b m bn phm (keyboard buffer), c a ch 40:1E, gm 32 byte v do vy kt thc a ch 40:3D. Mi k t c lu tr bng 2 bytes, byte cao l m qut, v byte thp l m ASCII. Nh vy, b m c th lu tr tm thi 16 k t. Chng trnh x l ngt s xc nh m ASCII t m qut bng bng bin i v ghi c 2 m vo b m bn phm. B m bn phm c t chc nh b m vng (ring buffer) v c qun l bi 2 con tr. Cc gi tr con tr c lu tr trong vng s liu ca BIOS a ch 40:1A v 40:1C.
Ngt INT 16h trong BIOS cung cp 8 hm cho bn phm. Thng cc hm BIOS tr v mt gi tr 0 ca ASCII nu phm iu khin hoc chc nng c nhn.. Cc th d: Gi s phm a c nhn. MOV AH,00h ; chy hm 00h, c k t INT 16h ; pht mt interrupt Kt qu: AH = 30 (m qut cho phm a); AL = 97 (ASSCII cho a) Gi s phm .HOME c nhn. MOV AH,00h ; chy hm 00h, c k t INT 16h ; pht mt interrupt Kt qu: AH = 71 ( m qut cho phm HOME) AL = 00 (cc phm chc nng v iu khin khng c m ASCII) Gi s phm HOME c nhn. MOV AH,10h ; chy hm 10h, c k t INT 16h ; pht mt interrupt Kt qu: AH = 71 (m qut cho phm HOME) AL = E0h Chng trnh vi bn phm qua cc cng: Bn phm cng l mt thit b ngoi vi nn v nguyn tc c th truy xut n qua cc cng vo ra. Cc thanh ghi v cc port: S dng 2 a ch port 60h v 64h c th truy xut b m vo, b m ra v thanh ghi iu khin ca bn phm. Port 60h 60h 64h 64h Thanh ghi m ng ra m ng vo Thanh ghi iu khin Thanh ghi trng thi R/W R W W R
Thanh ghi trng thi xc nh trng thi hin ti ca b iu khin bn phm. Thanh ghi ny ch c (read only). C th c n bng lnh IN ti port 64h. 7 PARE PARE TIM
114
TIM
AUXB
KEYL
C/D
SYSF
INPB
0 OUTB
Li chn l ca byte cui cng c vo t bn phm; 1 = c li chn l, 0 = khng c. Li qu thi gian (time-out); 1 = c li, 0 = khng c.
AUXB KEYL C/D INPB OUTB
m ra cho thit b ph (ch c my PS/2); 1 = gi s liu cho thit b, 0 = gi s liu cho bn phm. Trng thi kha bn phm; 1 = khng kha, 0 = kha. Lnh/s liu; 1 = Ghi qua port 64h, 0 = Ghi qua port 60h. Trng thi m vo; 1 = s liu CPU trong b m vo, 0 = m vo rng. Trng thi m ra; 1 = s liu b iu khin bn phm trong b m ra, 0 = m ra rng.
Hnh 7.11 B iu khin bn phm Thanh ghi iu khin (64h) 7 PARE TIM AUXB
KEYL
C/D
SYSF
INPB
0 OUTB
Cc lnh cho b iu khin bn phm: M A7h A8h A9h Lnh Cm thit bph Cho php thit bph Kim tra ghp ni ti thit bph
AAh ABh ADh AEh C0h C1h C2h D0h D1h D2h D3h D4h E0h F0h FFh Kha bn phm: Start:
Tkim tra Kim tra ghp ni bn phm Cm bn phm Cho php bn phm c cng vo c cng vo ra (byte thp) c cng vo ra (byte cao) c cng ra Ghi cng ra Ghi m ra bn phm Ghi m ra thit bph Ghi thit bph Kim tra c cng vo Gi 1 xung ti li ra Cng
IN AL, 64h ; c byte trng thi TEST AL, 02h ; kim tra b m c y hay khng JNZ start ; mt vi byte vn cn trong b m vo OUT 64h, 0ADh ; kha bn phm Cc lnh cho bn phm: Tm tt cc lnh bn phm: M Lnh EDh Bt ON/OFF LED EEh Echo F0h t/nhn din F2h F3h F4h F5h F6h FEh Nhn din bn phm t tc lp li/tr Enable Chun/khng cho php Chun/cho php Resend M t Bt/tt cc n led ca bn phm Tr v byte eeh t 1 trong 3 m qut v nhn din cc m qut tp m qut hin ti. Nhn din ACK = AT, ACK+abh+41h=MF II. t tc lp li v thi gian tr ca bn phm Cho php bn phm hot ng t gi tr chun v cm bn phm. t gi tr chun v cho php bn phm. Bn phm truyn k tcui cng mt ln na ti b iu khin bn phm Chy reset bn trong bn phm
FFh Reset
Th d: lnh bt n led cho phm NUMCLOCK, tt tt c cc n khc. OUT 60H, EDH ; ra lnh cho bt tt cc n led WAIT: IN AL, 64H ; c thanh ghi trng thi
JNZ WAIT ; b m vo y OUT 60H, 02H ; bt n cho numclock Cu trc ca byte ch th nh sau: 0 0 0 0 0 CPL NUM SCR
CPL: NUM: SCR: 7.1.2 Chut
1 = bt n Caps Lock; 0 = tt 1 = bt n Num Lock; 0 = tt 1 = bt n Scr Lock; 0 = tt
Cu to Cu to ca chut rt n gin, phn trung tm l 1 vin bi thp c ph keo hoc nha c quay khi dch chuyn chut. Chuyn ng ny c truyn ti 2 thanh nh c t vung gc vi nhau. Cc thanh ny s bin chuyn ng ca chut theo 2 hng X,Y thnh s quay tong ng ca 2 a gn vi chng. Trn 2 a c nhng l nh lin tc ng v ngt 2 chm sng ti cc sensor nhy sng to ra cc xung in. S cc xung in t l vi lng chuyn ng ca chut theo cc hng X,Y v s xung trn 1 sec biu hin tc ca chuyn ng chut. Km theo c 2 hay 3 phm bm.
Hnh 7.12 S cu to ca chut Mch ghp ni v chng trnh iu khin chut Hu ht chut c ni vi PC qua cng ni tip, qua chut cng c cp ngun nui t PC. Khi dch chuyn hoc nhn, nh cc phm chut, n s pht ra mt gi cc s liu ti mch giao tip v mch s pht ra 1 ngt. Phn mm iu khin chut lm cc nhim v: chuyn ngt ti mch giao tip ni tip xc nh, c gi s liu v cp nht cc gi tr bn trong lin quan ti trng thi ca bn phm cng nh v tr ca chut.
Hn na, n cn cung cp 1 giao tip mm qua ngt ca chut l 33h nh cc gi tr bn trong ny cng nh lm dch chuyn con tr chut trn mn hnh tng ng vi v tr ca chut. C th chn kiu con tr chut cng hoc mm trong ch vn bn hay con tr chut ho trong ch ha. Cc hm 09h v 0Ah trong ngt 33h cho php nh ngha loi v dng con tr chut. Chng trnh vi con tr Ngt 33h cho php xc nh v tr, s ln bm nhy (click) phm con tr v hnh dng con tr. hin con tr trn mn hnh phi dng hm 01h. Hm 09h nh ngha con tr chut trong ch ha . Hnh bn di l th d ca mt n con tr hnh mi tn trong trong kiu hin VGA phn di cao 256 mu. y mt im nh (pixel) c biu din bng 1 byte. on chng trnh sau cho php hin con tr mm vi mu s 3 v sng nhp nhy: f............... ff.............. fxf............ fxxf........... fxxxf.......... fxxxxf........ fxxxxxf....... fxxxxxxf..... fxxxxffff.... .f . f f x f . . . . . . . . . ffxfxf......... f..fxxf....... f...fxf........ .....fxxf...... ......fxf....... .......f........ Hnh 7.13 Mt n con tr chut MOV AX, 0AH ; chn hm MOV BX, 00H ; con tr chut mm MOV CX, 00H ; xo k t trn mn hnh MOV DX, 8B02H ;BLNK=1b,BAK = 000b, INT = 1b, CHRx = 00000010b INT 33H ; gi ngt.
7.2. Giao tip PC Game

Cu trc v chc nng ca board ghp ni tr chi (PC game) nh hnh bn di. Bng lnh IN v OUT c th truy xut qua a ch 201h.
118
Hnh 7.6 - Cu trc v chc nng ca board ghp ni tr chi
Hnh 7.7 - Cu to ca u ni 15 chn v 2 joystick A v B
Chn ca u ni 15 chn 2 3 6 7 10 11 13 14 1, 8, 9, 15 4, 5, 12
Sdng cho Phm 1 ca Joystick A (BA1) Bin tr X ca Joystick A Bin tr Y ca Joystick A Phm 2 ca Joystick A (BA2) Phm 1 ca Joystick A (BB1) Bin tr X ca Joystick B Bin tr Y ca Joystick B Phm 2 ca Joystick A (BB2) Vcc (+5V) GND (0V)
Board mch c ni vi bus h thng ca PC ch qua 8 bits thp ca bus d liu, 10 bits thp ca bus a ch v cc ng iu khin IOR v IOW. Mt u ni 15 chn c ni vi board mch cho php ni cc i hai thit b cho PC game gi l joystick.
Mi joystick c 2 bin tr c gi tr bin i t 0 n 100k c t vung gc vi nhau i din cho v tr x v y ca joystick. Thm na chng c 2 phm bm, thng l cc cng tc thng h ph hp vi cc mc logic cao ca cc dy trn mch. C th xc nh c trng thi nhn hoc nh phm mt cch d dng bng lnh IN ti a ch 201h. Nibble cao ch th trng thi ca phm. V board khng dng ng IRQ do khng c kh nng pht ra 1 ngt, do vy board ch hot ng trong ch hi vng (polling). Byte trng thi ca board game nh sau: D7 BB2 D6 BB1 D5 BA2 D4 BA1 D3 BY D2 BX D1 AY D0 AX
BB2, BB1, BA2, BA1: Trng thi ca cc phm B2, B1, A2, A1; 1 = nh; 0 = nhn BY, BX, AY, AX: Trng thi ca mch a hi tu thuc vo bin tr tng ng.
7.3. Monitor v card giao din ho

7.3.1 Nguyn l hin nh trn monitor Phng php hin nh trn mn hnh ca monitor my tnh cng ging nh trong my thu hnh thng thng. Hnh bn di minh ha vic hin nh trn mn hnh kiu ng phng tia m cc CRT (cathode ray tube).
Hnh 7.14 Cu to ng hnh CRT Cc in t pht x t cathode trong ng c hi t thnh 1 chm tia, sau c tng tc v c lm lch hng chuyn ng bi cc b phn li tia. Tia ny s p vo mn hnh c ph cht hunh quang to thnh 1 im sng gi l 1 im nh. Do hin tng lu nh trong vng mc ca mt ngi nn khi tia in t c qut rt nhanh theo chiu ngang t tri sang phi s to nn 1 vt sng ngang c gi l dng qut. n cui 1 dng, n c qut ngc tr v bn tri qut tip dng
th 2 bn di ..v..v.. Qu trnh qut cc dng c dch dn t trn xung di cho sut chiu dc ca mn hnh c gi l qut dc. chi (sng ti) c quyt nh bi cng chm tia p vo mn hnh hunh quang v 1 im mu t nhin c hin nh s trn ln ca 3 mu: , xanh dng, xanh l cy theo 1 t l no . Ba mu ny c hin nh 3 tia in t cng bn vo 3 im trn mn hnh k cn nhau, mi im c ph cht hunh quang pht ra cc mu tng ng. 3 chm tia in t c pht ra bi 3 sng in t l 3 cathode c xp t bn trong CRT mt cch cn thn. C 2 kiu qut tia in t: Qut xen k (interlaced): cc dng l c qut trc cho n ht mn hnh theo chiu dc, gi l mnh l; sau cc dng chn to nn mnh chn c qut sau. Phng php ny c u im l thu hp c di tn s lm vic ca thit b nhng c nhc im l hnh nh b nhp nhy. Qut khng xen k (non-interlaced): cc dng qut c thc hin tun t. u im l hnh nh c iu chnh chnh xc v n nh nhng thit k mch in s kh hn v phi gii quyt vn tng di tn lm vic. Hin nay cn c cc monitor dng mn hnh tinh th lng LCD hoc ng cha kh c hot ng theo nguyn l tng t nh trn nhng khng c tia in t qut nn thay v cc im nh ring bit l cc phn t pht sng c nh a ch mt cch tun t. Do vy, trn cc monitor ny hnh nh cng c pht ra tng dng mt. Qu trnh qut ngc cng khng cn na v y n gin ch vic thay i a ch v phn t u dng tip o. 7.3.2 Card giao tip ha hin cc hnh nh, k t, hay hnh v trn mn hnh, PC phi thng qua mch ghp ni mn hnh (graphics adapter). Board mch ny thng c cm trn khe cm m rng ca PC. S khi nh hnh sau:
Hnh 7.15 S khi ca bn mch ghp ni mn hnh Bus Interface: Video Ram: Signal generator: Character code: Attribute information: Character rom: ghp ni bus; Ram Video my pht tn hiu; m k t thng tin thuc tnh; rom k t
Attribute decoder: b gii m thuc tnh; Shift register: thanh ghi dch Character generator: my pht k t; Synchronization information: thng tin ng b. Phn trung tm l chip iu khin ng hnh CRTC (cathode ray tube controller). CPU thm nhp RAM Video qua mch ghp ni bus ghi thng tin xc nh k t hay hnh v cn hin th. CRTC lin tc pht ra cc a ch Ram video c cc k t trong v truyn chng ti my pht k t (character generator). Trong ch vn bn (text mode), cc k t c xc nh bi m ASCII, trong c c cc thng tin v thuc tnh ca k t, th d k t c hin theo cch nhp nhy hay o mu en trng .ROM k t (character rom) lu tr cc hnh mu im nh ca cc k t tng ng my pht k t bin i cc m k t thnh 1 chui cc bit im nh (pixel bit) v chuyn chng ti thanh ghi dch (shift register). My pht tn hiu s s dng cc bt im nh ny cng vi cc thng tin thuc tnh t Ram video v cc tn hiu ng b t CRTC pht ra cc tn hiu cn thit cho monitor. Trong ch ha (graphics mode), thng tin trong RAM video c s dng trc tip cho vic pht ra cc k t. Lc ny cc thng tin v thuc tnh cng khng cn na. Ch t cc gi tr bit trong thanh ghi dch, my pht tn hiu s pht cc tn hiu v sng v mu cho monitor. My pht k t trong cc ch vn bn v ha: Mi k t c biu din bi 1 t 2 byte trong RAM video. Byte thp cha m k t, byte cao cha thuc tnh. Cu trc ca mt t nh video nh sau: 15 BLNK 14 BAK2 13 BAK1 12 BAK0 11 INT 10 FOR2 9 FOR1 8 FOR0
7 CHR7
6 CHR6
5 CHR5
4 CHR4
3 CHR3
2 CHR2
1 CHR1
0 CHR0
BLNK: Nhp nhy; 1 = bt, 0 = tt BAK2 BAK0: Mu nn; (t bng mu hin ti) INT: Cng sng ; 1 = cao, 0 = bnh thng FOR2 FOR0: Mu nn trc (t bng mu hin ti) CHR7CHR0: M k t. Trong ch vn bn, 6845 lin tc xut cc a ch cho RAM video qua MA0MA13. K t gc tn cng pha trn bn tri mn hnh c a ch thp nht m 6845 s cung cp ngay sau khi qut dc ngc. Logic ghp ni nh a ch cho RAM video bng vic ly ra m k t cng vi thuc tnh. M k t dng cho my pht k t nh l ch s th nht trong ROM k t. Lc ny, 6845 nh a ch hng qut u tin ca ma trn k t, a ch hng bng 0. Cc bit ca ma trn im nh by gi s c truyn ng b vi tn s video t thanh ghi dch ti my pht tn hiu. Nu
my pht tn hiu nhn c gi tr 1 t thanh ghi dch, n s pht tn hiu video tng ng vi mu ca k t. Nu nhn c 0 n s cp tn hiu tng ng vi mu nn. Vy dng qut th nht c hin ph hp vi cc ma trn im nh ca cc k t trong hng k t th nht. Khi tia in t t ti cui dng qut, 6845 kch hot li ra HS to ra qu trnh qut ngc v ng b ngang. Tia in t quay tr v bt u qut dng tip. Sau mi dng qut, 6845 tng gi tr RA0-RA4 ln 1. a ch dng ny hnh thnh mt gi tr offset bn trong ma trn im nh cho k t c hin. Da trn mi dng qut nh vy, mt dng cc im nh ca k t trong hng k t c hin ra. iu ny c ngha l vi ma trn 9x14 im nh cho 1 k t, hng k t th nht c hin sau 14 dng qut. Khi a ch RA0-RA4 tr v gi tr 0, 6845 s cp 1 a ch MA0-MA13 mi v hng k t th hai s c hin ra cng nh vy. cui dng qut cui cng, 6845 s reset a ch MA0-MA13 v RA0- RA4 v cho php li ra VS pht ra tn hiu qut ngc cng tn hiu ng b dc. Mi k t c chiu cao cc i ng vi 32 dng v c 5 ng a ch RA0-RA4, cn b nh video trong trng hp ny c ti 16K t v c a ch MA0-MA13 l 14 bit. Trong ch ha, chng kt hp vi nhau to thnh a ch 19 bit, lc 6845 c th nh a ch cho b nh video ln ti 512k t. Trong trng hp ny, cc byte trong RAM video khng c dch thnh m k t v thuc tnh na m trc tip xc nh cng sng v mu ca im nh. a s cc RAM video c chia thnh vi bng c nh a ch bi RA0-RA4. Cc ng MA0-MA13 s nh a ch offset bn trong mi bng. S liu trong RAM video lc ny c trc tip truyn ti thanh ghi dch v my pht tn hiu. ROM k t v my pht k t khng lm vic. T chc ca RAM video RAM video c t chc khc nhau tu theo ch hot ng v bn mch ghp ni. Th d, vi RAM video 128 KB, c th a ch ha ton b b nh mn hnh qua CPU nh b nh chnh. Nhng nu kch thc RAM video ln hn th lm nh vy s ln vng ROM m rng i ch C0000h. Do , card EGA v VGA vi trn 128 KB nh c tng cng thm 1 chuyn mch mm (soft-switch) cho php thm nhp cc ca s 128 KB khc nhau vo RAM video ln hn nhiu. Cc chuyn mch ny c quy nh bi ring cc nh sn xut board mch. T chc trong ch vn bn RAM video c coi nh mt dy t tuyn tnh, t u tin c gn cho k t gc trn tn cng bn tri mn hnh gi l hng 1 ct 1. T th 2 l hng 1, ct 2, . S t tu thuc vo phn gii ca kiu hin k t. Th d: phn gii chun 25 hng, 80 k t i hi 2000 t nh 2 byte. Nh vy, tng cng cn 4 KB b nh RAM video. Trong khi vi card c phn gii cao SVGA 60 hng, 132 k t cn n 15840 byte. Do RAM video thng c chia thnh vi trang. Kch thc ca mi trang tu thuc vo ch hin ca mn hnh v s trang cc i, ph thuc c vo kch thc ca RAM video. 6845 c th c chng trnh ha sao cho a ch khi pht ca MA0-MA13 sau qut ngc dc l khc 00h. Nu a ch khi pht l bt u ca 1 trang th c th qun l RAM video theo vi trang tch bit nhau, nu CPU thay i ni dung ca 1 trang m trang hin
ang khng hin th mn hnh cng khng thay i. Do , cn phn bit trang nh ang c kch hot (ang hin) v trang ang c x l. on chng trnh ghi k t 'A' c cng sng cao vo gc trn bn tri vi mu s 7 v mu nn s 0. Trang th nht v l duy nht bt u a ch B0000h. MOV AX, 0B000h; np thanh ghi ax vi a ch on ca Ram video MOV ES, AX; truyn a ch on vo ES MOV AH, 0F8h; np byte thuc tnh 1111 1000 vo AH MOV AL, 41h; np m k t ca A vo AL MOV ES:[00H],AX; ghi byte thuc tnh v m k t vo RAM video. T chc trong ch ha: T chc trong ch ny phc tp hn. V d: vi bn mch Hercules, RAM video c chia thnh 4 bng trn 1 trang . Bng th nht: m bo cc im nh cho cc dng 0, 4, 8, , 344; bng th hai cho cc dng 1, 5, 9, , 345; bng th 3 cho cc dng 2, 6, 10, ., 346; v bng th 4 cho cc dng 3, 7, 11, , 347. 64 KB c chia thnh 2 trang 32 KB. phn gii trong ch ha l 720 x 348 im nh, mi im nh c biu din bi 1 bit. Do vy, mt dng cn 90 byte (720 im nh / 8 im nh trn 1 byte). a ch ca byte cha im nh thuc ng i v ct j trong trang k l: B0000h+8000h*k+2000h* (i mod 4)+ 90*int (i/4)+int (j/8) B0000h l on video, 8000h l kch thc ca trang, 2000h* (i mod 4) l offset ca bng cha byte , 90*int (i/4) l offset ca dng i trong bng v int (j/8) l offset ca ct j trong bng. Trong bn mch CGA b nh video c chia thnh 2 bng cn vi EGA v VGA th phc tp hn. Truy xut mn hnh qua DOS v BIOS Truy xut qua DOS Cc hm ca int 21h c th hin cc k t trn mn hnh nhng khng can thip c vo mu: - Hm 02h: ra mn hnh. - Hm 06h: ra mt k t. - Hm 09h: ra mt chui. - Hm 40h: ghi file/ thit b T DOS 4.0 tr i c th dng lnh mode iu chnh s ct vn bn t 40 n 80 hay s dng t 25 n 50. Cc lnh copy, type v print trong command.com cho php hin text trn mn hnh. DOS gp chung bn phm v monitor thnh 1 thit b mang tn CON (console). Ghi CON l truyn s liu ti monitor, cn c CON l nhn k t t bn phm. V d: hin ni dung ca file output.txt ln mn hnh ca monitor s c cc cch sau: - copy output.txt con - type output.txt > con - print output.txt /D:con Truy xut qua BIOS
Bios thm nhp monitor bng int 10h vi nhiu chc nng hn DOS, nh t ch hin hnh, qun l t ng cc trang, phn bit cc im trn mn hnh nh cc ta , Nhng thng trnh ha: BIOS trn main board c sn nhng hm dng cho thm nhp MDA v CGA. BIOS ca ring EGA v VGA c nhng hm m rng tng ng trong khi vn gi nguyn nh dng gi. Mt trong nhng hm quan trng nht ca int 10h l hm 00h dng t ch hin hnh. thay i ch hin hnh cn phi lm rt nhiu bc chng trnh phc tp np cc thanh ghi ca chip 6845. Trong khi , hm 00h lm cho ta tt c cc cng vic ny. Th d: to kiu 6 vi phn gii 640*200 trn CGA. Mov ah, 00h ; hm 00h Mov al, 06h ; ch 6 Int 10h ; gi ngt Cc board EGA/VGA c ring BIOS ca chng. Trong qu trnh khi ng PC, n s chn int 10h li v chy chng trnh BIOS ca ring board mch. Thng trnh c (ca BIOS trn board mach chnh ) c thay a ch ti int 42h. Tt c cc lnh gi int 10h s c BIOS ca EGA/VGA thay a ch ti int 42h nu board mch EGA/VGA ang chy cc kiu hin tng thch vi MDA hay CGA. C cc kiu hot ng t 0 n 7. BIOS ca EGA/VGA dng vng 40:84h ti 40:88h lu s liu BIOS v cc thng s ca EGA/VGA. N c cc hm mi vi cc hm ph sau: Hm 10h: truy xut cc thanh ghi mu v bng mu Hm 11h: ci t cc bng nh ngha k t mi Hm 12h: t cu hnh h con video Hm 1Bh: thng tin v trng thi v chc nng ca BIOS video (ch c VGA) Hm 1Ch: trng thi save/restore ca video (ch c VGA) Sau y l chc nng ca cc hm v th d s dng chng: Hm 10h, hm ph 03h xo/t thuc tnh V d: Xo thuc tnh nhp nhy: Mov ah, 10h ; dng hm 10h Mov al, 03h ; dng hm ph 03h Mov bl, 00h ; xo thuc tnh nhp nhy Int 10h ; gi ngt - Hm 11h ghp ni vi my pht k t V d: Np bng nh ngha k t 8*14 khng cn chng trnh CRTC: Mov ah, 11h ; dng hm 11h Mov al, 01h ; np bng k t t Rom Bios vo Ram my pht k t. Mov bl, 03h ; gn s 3 cho bng
Int 10h ; gi ngt - Hm 12h, hm ph 20h chn thng trnh in mn hnh. Dng hm ph ny c th thay th thng trnh chun cho INT 05h bng thng trnh c th dng cho cc phn gii mi ca EGA/VGA. V d: Cho php thng trnh mi in mn hnh: Mov ah, 12h ; dng hm 12h Mov bl, 20h ; dng hm ph 20h n PRINT hoc SHIFT+PRINT gi thng trnh in c lp t. Truy xut trc tip b nh video: v 1 im trn mn hnh, BIOS phi lm nhiu th tc nhng nu mun v ton b 1 ca s hnh hay l tr th phi truy xut trc tip RAM video. Vi board n sc MDA trong kiu hin vn bn s 7, 4 KB RAM uc t chc nh 1 dy (array) gm 2000 t nh k nhau ( mi t l m thuc tnh: k t) to nn 25 dng, 80 ct. RAM video bt u an B0000h, trong k t gc trn cng bn tri l t th nht trong RAM video. Nh vy mi dng c 160 byte (A0h). a ch ca t nh ng vi k t dng i, ct j (i = 0-24, j = 0-79) c tnh theo cng thc sau: Address (i,j) = B0000h +A0h*i +02h*j. Vi board EGA, kiu hin vn bn t 0 n 3 m k t c lu tr trong lp nh 0 cng vi thuc tnh trong lp 1 ca RAM video. Mch logic chuyn a ch trn board thc hin s kt hp nht nh no sao cho t chc v cu trc ca RAM video cng nh cch tnh a ch vn tng ng vi cch ca CPU. Trong ch ha t 13 n 16, RAM video bt u t a ch on A000h. Cc im nh c xp k cn nhau trong b nh v mi im nh i hi 4 bit, cc bit ny c phn ra 4 lp nh. Nh vy a ch ca 1 trong 4 bit ny trn 1 im nh khng ch gm on video v offset m cn thm vo s lp nh na.
Hnh 7.16 Cc lp nh ca RAM Video
126
hin 1 im nh vi 1 trong 16 mu, khng phi ch tnh a ch bit m cn phi thm nhp 4 lp nh. Mun vy, phi dng thanh ghi mt n bn (map mask register). Thanh ghi ny c nh a ch qua cng ch s 3C4h vi a ch 02h v c th c ghi qua cng s liu 3C5h. Cu trc ca thanh ghi mt n bn nh sau: 7 Res 6 Res 5 Res 4 Res 3 2 LY3 LY2 1 LY1 0 LY0
LY3-LY0: Thm nhp ghi ti cc lp t 0 3; 1 = cho php; 0 = khng cho php Res : D tr V d: t bit 0 ca byte a ch A000:0000h cho l 0, 1, 3. Mov AX, 0A000h ; np an video vo AX Mov ES, AX ; truyn an video vo ES Mov BX, 0000h ; np offset 0000h vo BX Out 3C4h, 02h ; ch s 2 thanh ghi mt n bn Out 3C5h, 0Bh ; ghi 0000 1011b vo thanh ghi mt n bn (cho php lp 0, 1, 3) Mov 3C5h, 0Bh ; t bit 0 trong cc lp 0, 1 v 3 lu tr ni dung mn hnh cn phi c cc gi tr bit ca 4 lp khi dng thanh ghi chn bn c (read map select register). N c nh a ch vi ch s 04h qua cng ch s 3CEh, v c th c ghi qua cng s liu 3CFh. Cu trc ca thanh ghi ny: res res res res res res LY1 LY0
LY1-LY0: cho php thm nhp c vi: 00 = lp 0 01 = lp 1 10 = lp 2 11 = lp 3 res : d tr V d: c byte a ch A000:0000h cho lp 2: Mov AX, A000h ; np an video vo AX Mov ES, AX ; truyn an video vo ES Mov BX, 0000h ; np offset vo BX Out 3Ceh, 04h ; ch s 4 thanh ghi chn bn c Out 3CFh, 02h ; ghi 0000 0010b vo thanh ghi chn bn c (cho php lp 2) Mov AL, [ES:BX] ; np byte trong lp 2 vo AL. Ch rng 4 bit ti 4 lp i din cho 1 im nh nn trong kiu hin 16 EGA c phn gii cao nht mi dng cn 80byte (640 im nh / 8 im nh trn 1 byte); mi trang mn hnh gm 32 KB. a ch byte ca im nh dng i, ct j trang k (i=0349, j=0-639, k=0-1) l: Address (i,j,k) = A0000h + 8000h*k + 50h*j + int (i/8).
Vi board VGA, cc ch hin vn bn t 0 n 3 v 7 cng nh cc ch ha t 4 n 6 v 13 n 16 ca CGA. EGA v MDA u chy c trn n. Trong ch vn bn, m k t c lu tr trong lp nh 0 cng vi thuc tnh trong lp 1 ca RAM video VGA. Qu trnh chuyn ha a ch cng ging nh EGA nhng khc ch n vn m bo ch vn bn 7 vi phn gii 720x400, ma trn im nh 9x16. Trong ch ha 4 6 v 13 19 , mi t chc, cu trc cng nh cch tnh a ch tng t nh CGA v EGA. VGA c tng cng 3 kiu hin hnh mi t 17 n 19. Kiu 17 tng thch vi board ha ca my PS/2 kiu 30 l MCGA (multi colour graphics array). Cc im nh ch gm 1 bit (2 mu) c nh v ch trn lp 0. Th d, trong VGA kiu 17 vi 80 byte trn 1 dng (640 im nh / 8 im nh trn 1 byte). Mi trang mn hnh gm 40 KB. a ch ca byte dng i, ct j ( i= 0479), j=0- 639) nh sau: Address (i,j) = A0000h+50h*j+int (i/8) Kiu 18, 4 bit ca im nh c phn trong 4 lp nh nh EGA. Trong kiu VGA phn gii cao vi 16 mu khc nhau, 80 byte trn 1 dng (640 im nh / 8 im nh trn 1 byte), mi trang mn hnh gm 40 KB (A0000h byte); a ch ca mi byte dng i, ct j (i=0-479; j = 0-639) bng: Address (i,j) = A0000h + 50h*j + int (i/8). Kiu 19 vi 256 mu cho 1 im nh th RAM video li c t chc rt n gin nh 1 dy tuyn tnh, trong 1 byte tng ng vi 1 im nh. Gi tr ca byte phn nh mu ca im nh. Kiu ny i hi 320 byte (140h) trn 1 dng (320 im nh / 1 im nh trn 1 byte). Mt trang mn hnh gm 64 KB (10000h) nhng ch c 64000 byte c s dng. a ch ca im nh trong dng i, ct j (i = 0-199, j=0319) l: Address (i,j) = A0000h + 140h*j + i Bus cc b v chip x l ha tng tc hin ha c 2 gii php: Dng bus cc b 32 bit trnh hin tng nghn c chai (bottleneck) do bus ISA ch c 16 bit v tc hn ch (8.33Mhz); iu ny cho php 1 lng thng tin nhiu hn c trao i gia CPU v board mch trong 1 n v thi gian. Dng chip x l ha vi BIOS ring trn board mch iu khin monitor. Chip ny s lm hu ht cc cng vic tr mt t lnh v thng s m t ni dung phn mn hnh cn hin l c cp t CPU. Th d cn v 1 hnh ch nht vi mu no , board ch cnvi thng s ban u t CPU nh ta ca 2 gc v gi tri mu l . Cch gii quyt nh vy rt c li khi PC chy trong ch a nhim.
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Nguyn Tun Linh BM KTMT Khoa in t i hc k thut cng nghip Thi Nguyn

K thut ghp ni my tnh

Nguyn Tun Linh BM KTMT Khoa in T

Bi ging mn hc: K thut ghp ni my tnh

Vai tr v nhim v ca khi ghp ni (KGN) ..................................................... 9

Cu trc chung ca mt h ghp ni my tnh .................................................... 11

Chng trnh phc v trao i tin cho khi ghp ni ......................................... 12

CHNG 2. GIAO TIP VI TN HIU TNG T .................................. 15

Chuyn i tn hiu tng t - s ADC: ............................................................. 20

M t chc nng ca cc chn: ........................................................................... 27

CHNG 3. TH TC TRAO I D LIU CA MY TNH ................. 30

Cc ch trao i d liu ca my vi tnh ........................................................ 31 Trao i tin ngt vi x l..................................................................................... 32

Trao i tin trc tip khi nh ............................................................................ 39

CHNG 4. GHP NI QUA RNH CM M RNG ................................ 45

Nguyn Tun Linh BM KTMT Khoa in T

4.3. 4.4. 4.5.

CHNG 5. GHP NI TRAO I TIN SONG SONG ................................ 53

Vi mch PPI 8255A ............................................................................................ 56

Ghp ni song song qua cng my in ................................................................. 65

CHNG 6. GHP NI TRAO I TIN NI TIP ...................................... 75

t vn ........................................................................................................... 75 Yu cu v th tc trao i tin ni tip: .............................................................. 76

Truyn thng ni tip s dng giao din RS-232: .............................................. 78

Giao tip USB ca my PC: ............................................................................... 96

CHNG 7. GIAO TIP VI CC THIT B NGOI VI C BN ......... 111

Giao tip vi bn phm v chut ....................................................................... 112

Nguyn Tun Linh BM KTMT Khoa in T

Ti liu tham kho [1]. [2]. [3]. [4]. [5].

Nguyn Tun Linh BM KTMT Khoa in T

Chng 1: i cng v k thut ghp ni my tnh

CHNG 1. I CNG V K THUT GHP NI MY TNH

Nguyn Tun Linh BM KTMT Khoa in T

Chng 1: i cng v k thut ghp ni my tnh

1.1. Cu trc chung ca h thng

Chng 1: i cng v k thut ghp ni my tnh

1.2. Yu cu trao i tin ca my vi tnh i vi mi trng bn ngoi

Nguyn Tun Linh BM KTMT Khoa in T

Chng 1: i cng v k thut ghp ni my tnh

1.4. Vai tr v nhim v ca khi ghp ni

V tr v vai tr ca khi ghp ni

Chng 1: i cng v k thut ghp ni my tnh

Nguyn Tun Linh BM KTMT Khoa in T

Chng 1: i cng v k thut ghp ni my tnh

1.5. Cu trc chung ca mt h ghp ni my tnh

Phi hp ng dy thit b ngoi

Nguyn Tun Linh BM KTMT Khoa in T

ng dy my tnh (System bus)

Yu cu (INTR) Xc nhn (INTA) Lnh c

Thanh ghi trng thi Lnh vit

Thanh ghi m vit

Cu trc chung khi ghp ni

Chng 1: i cng v k thut ghp ni my tnh

1.6. Chng trnh phc v trao i tin cho khi ghp ni

Nguyn Tun Linh BM KTMT Khoa in T

Chng 1: i cng v k thut ghp ni my tnh

thanh ghi] := <Gi tr >;

thanh ghi>,<Gi tr >)

Chng 1: i cng v k thut ghp ni my tnh

Nguyn Tun Linh BM KTMT Khoa in T

Chng 2: Giao tip tn hiu tng t

CHNG 2. GIAO TIP VI TN HIU TNG T

Nguyn Tun Linh BM KTMT Khoa in T

Chng 2: Giao tip tn hiu tng t

2.1. Chuyn i tn hiu s sang tng t DACs