Chapter1.

An Overview of VLSI
1.1 Introduction
1.2 What is VLSI?
1.3 Complexity
1.4 Design
1.5 Basic concepts

An Overview of VLSI

This chapter deals with the basic concepts of VLSI and VLSI DESIGN. A few questions
such as what is VLSI/VLSI DESIGN? Why is VLSI? so on and so forth. The chapter
looks at the VLSI DESIGN flow and the various options of design that are available for a
designer.
1.1 Introduction
The expansion of VLSI is ‘Very-Large-Scale-Integration’. Here, the term ‘Integration’
refers to the complexity of the Integrated circuitry (IC). An IC is a well-packaged
electronic circuit on a small piece of single crystal silicon measuring few mms by few
mms, comprising active devices, passive devices and their interconnections. The
technology of making ICs is known as ‘MICROELECTRONICS’. This is because the
size of the devices will be in the range of micro, sub micrometers. The examples include
basic gates to microprocessors, op-amps to consumer electronic ICs. There is so much
evolution taken place in the field of Microelectronics, that the IC industry has the
expertise of fabricating an IC successfully with more than 100 million MOS transistors as
of today. ICs are classified keeping many parameters in mind. Based on the transistors
count on the IC, ICs are classified as SSI, MSI, LSI and VLSI. The minimum number of
transistors on a VLSI IC is in excess of 40,000.
The concept of IC was conceived and demonstrated by JACK KILBY of TEXAS
INSTRUMENTS at Dallas of USA in the year 1958.The silicon IC industry has not
looked back since then. A lot of evolution has taken place in the industry and VLSI is the
result of this. This technology has become the backbone of all the other industries. We
will see every other field of science and technology getting benefit out of this. In fact the
advancements that we see in other fields like IT, AUTOMOBILE or MEDICAL, are
because of VLSI. This being such important discipline of engineering, there is so much
interest to know more about this. This is the motivation for this course namely ‘VLSI
CIRCUITS’.
1.2 What is VLSI?
VLSI is ‘Very Large Scale Integration’. It is the process of designing, verifying,
fabricating and testing of a VLSI IC or CHIP.A VLSI chip is an IC, which has transistors
in excess of 40,000. MOS and MOS technology alone is used. The active devices used
are CMOSFETs. The small piece of single crystal silicon that is used to build this IC is
called a ‘DIE’. The size of this die could be 1.5cmsx1.5cms. This die is a part of a bigger
circular silicon disc of diameter 30cms.This is called a ‘WAFR’. Using batch process,
where in 40 wafers are processed simultaneously, one can fabricate as many as 12,000
ICs in one fabrication cycle. Even if a low yield rate of 40% is considered you are liable
to get as many as 5000 good ICs. These could be complex and versatile ICs. These could
be a PENTIUM Microprocessor IC of INTEL, or a DSP processor of TI costing around
Rs10,000. Thus you are likely to make Rs50 million (Rs5crore) out of one process flow.
So there is lot of money in VLSI industry. The initial investment to set up a silicon
fabrication unit (called ‘FAB’ in short and also called sometimes as silicon foundry) runs
into a few $Billion. In INDIA, we have only one silicon foundry-SCL at Punjab
(Semiconductor Complex Ltd., in Chandigarh). Very stringent and critical requirements
of power supply, cleanliness of the environment and purity of water are the reasons as to
why there are not many FABS in India.

1.3 Producing a VLSI chip is an extremely complex task. It has number of design and
verification steps. Then the fabrication step follows. The complexity could be best
explained by what is known as ‘VLSI design funnel’ as shown in the Figure1.1.

Figure1.1 The VLSI design tunnel

CHAPTER 3.0

PHYSICAL STRUCTURE OF CMOS ICs

3.1 IC Layers
3.2 MOSFETs
3.3 CMOS Layers
3.4 Designing FET array
3.5 Summary
References

PHYSICAL STRUCTURE OF CMOS ICs

3
VLSI chip design flow as discussed in the chapter 1, has two parts namely, the front-end
design and the back end design. The front-end design is all about logic and circuit design
of the chip. The back end design translates the circuit elements – active, passive
components and their interconnections to respective layouts. These are the layouts, which
ultimately sit on the silicon die at different layer levels to get the finished IC. The actual
dimensions of these innumerable polygons have to be designed. The optimal placing
(helps in saving silicon real estate) and routing (helps in achieving required speed of
operation) of these polygons is also part of the back end design. This is called the ‘
physical design’. This chapter discusses the various layers that one sees on an IC in
general and looks at the details of a CMOS process. A number of example circuits have
been dealt to show how the layouts are done optimally. This chapter will examine the
physical structure of a CMOS IC as seen at the microscopic silicon level in the design
hierarchy.
3.1 IC Layers
Any IC in general will have some conducting, semi conducting and the insulating
layers stacked vertically. These are starting semiconductor wafer, silicon dioxide
(insulator), diffusion (or implant), polycrystalline silicon (gate material in- short-
polysilicon) and the top metal layer. Using these layers, geometrical patterns are done and
appropriate connectivity is established among all the physical patterns. The layout details
of a basic IC is shown in Fig.3.1

Gate
S D SiO2 G
G SiO2
A
P-Substrate T
(a) (b) E
 Figure.3.1. IC layout (a) cross-sectional view (b) Top view

Once the layout details are known it is to evaluate the resistance and capacitance values
of the physical entities sitting on the silicon. This is required to evaluate the delay
encountered by the signal in flowing from one component to an other. The sheet
resistance (Rs) of each of the layers will be known in advance. Knowing the Rs value of a
layer, one can calculate the resistance of the pattern made out of a particular layer.
3.1.1 Sheet resistance
The resistance of layer with resistivity ρ and with the dimensions as shown in
Fig.3.2 is given by
Rs = ρ L = ρ L/ W. t
A 3.1
Where A = cross-sectional area of the layer, ρ = Resistivity of the layer material
in ohm-cm, L = the length of the layer, W = the width of the layer, t = thickness of the
layer.
In equation 3.1 if W = L, Rs = ρ / t = Sheet resistance (ohms per square). Thus
the sheet resistance of layer is defined as the resistance offered to the flow of current by
the layer of thickness ‘t’ and a perfect square. If the given layer is not a perfect square,
you can calculate equivalent number of squares ‘N’ (= L/W). Then the resistance R =
N.Rs = Z.Rs. ‘Z’ (L/W) is a number and it is the reciprocal of the aspect ratio.

ρ t

I W

Figure.3.1. The geometry of a layer

3.1.2 Layer capacitance

Knowing the area of the layer and the dielectric constant, area capacitance can be
calculated using the equation:

C= εA/t 3.2
Where ε = ε0 εins, and t = thickness of the layer
ε0 = 8.854 x10 –14 F/cm, εSio2 = 4.0, A = Area of the layer
3.1.3 Delay timer constant
The product of the resistance and the capacitance gives the delay time constant ‘τ’. The
output of a gate passes to an input of a gate through a connecting wire, which has a
resistance of Rline. There will be a capacitance (gate capacitance) at the input of the gate
as shown in the Fig 3.2. The signal will take ‘τ’ seconds to reach the input of the gate 2
from the output of the gate 1.

Gate1 Line Gate2 Rline

Cin Cline

τ = Rline. Cin
Figure.3.2 Delay through the interconnect wire between the 2 gates.
3.2 MOSFETs
Whenever a polysilicon cuts across the diffusion, at the intersection a MOSFET is
formed. In between these layers silicon dioxide is sand witched and you get the field
effect. While writing the layout diagrams oxide layer will not be shown. Other layers
like diffusion, polysilicon and the metal layer are shown. The NMOSFET symbol and
its layout are shown in the Fig.3.3.
Gate Gate

Drain Source D S
(a) (b)

Figure.3.3 NMOSFET a) symbol, b) layout

3.2.1 Current Flow in a FET

The current in a NMOSFET is due to flow of electrons from source to drain under the
influence of applied drain voltage VDD. The device goes to on state with VGS ≥ VT.
Here, VGS is the gate voltage with respect to the source, and VT is the threshold voltage
of the enhancement NMOSFET under consideration. Threshold voltage is the gate
voltage with respect to source at which the substrate underneath the gate between the
source and the drain gets inverted and the N-channel is formed. Now with VDD on, the
electrons move from source towards the drain. And the conventional drain current flows
from drain to source. The magnitude of the current is proportional to the total charge
created in the channel and inversely proportional to the transit time of the electrons. The
schematic of the NMOSFET showing the current flow is depicted in the Fig.3.4.
S G D
Key:
VDD Metal
Poly silicon
Diffusion
Field oxide
Gate oxide
 sNn
n+ n+
Channel
P-Substrate

Figure.3.4 Schematic of NMOSFET with different layers

The expression for IDS can be deduced as:

I DS = Charge in the channel / Transit time of electrons

= Q / τSD
Where τSD = Channel length / Electron drift velocity
= L / µn EDS

= L / µn VDS / L

= L 2 / µn VDS 3.3

The channel charge is given by:

Q = - C G (VGS – VT) 3.4

Where CG = Gate oxide Capacitance, as given by Equation 3.2

Combining Equations 3.3 and 3.4 we get,

IDS = ε0 εox µn W/ (L t ox) . (VGS –VT) .VDS 3.5

= βn. (VGS – VT).VDS

Where βn = gain factor (A/ V2)

3.3 CMOS Layers
CMOS FETS are fabricated using three processes, namely i) N-Well process ii) P- Well
process and iii) Twin –Tub Process. If the process is started with a P-substrate,
NMOSFETs can be fabricated. On the same wafer, to put PMOSFET, one should have a
N- semiconductor. This active N- area is obtained by ion implantation. This is called the
N-Well. You should have a P-Well to accommodate NMOSFETs, if the starting material
is a N-substrate. In the case of twin –tub process, an epitaxial layer of single crystal
silicon is grown by chemical vapor deposition process (CVD). On this layer, both N-
well and P-Well implants are done to accommodate PMOS and NMOS FETs. The top
view of the patterning of the FETs in a N-Well process is shown in the Fig.3.5.For the
 implementation of a particular logic; the NMOSFETs and PMOSFETs may have to be
connected in series or parallel.

P+ p+ P+ p+
n+ n+
n+ n+

N-Well

Figure.3.5 Top view of patterning of the FETs

3.4 Designing FET arrays
When a logic gate is implemented, NMOSFETs are arranged in the pull-down structure.
These transistors will depend upon the input pins of the gate. Depending on the Boolean
expression, these transistors are connected in series, parallel or series-parallel
combination. In any case these transistors could be arranged in an array. In order to
optimize the silicon space, layout design of these arrays is a must. Same thing hold good
for the PMOSFET arrays, which come as pull-up devices between VDD and the output
line. We shall discuss the design of the FETs connected in series and parallel.
3.4.1 NMOSFETs in series/ parallel
Silicon patterning for two NMOSFETs connected in series is
shown in Fig.3.5.

D1 S1 D2 S2 D1 S1 D2 S2
(a) (b)
Figure.3.5 Silicon patterning of 2 NMOS FETs in series
Silicon patterning of the 2 NMOSFETs connected in parallel is shown in Fig.3.6.

A B

y (a) (b)

Figure.3.6 Patterning of the 2 NMOSFETs connected in parallel (a) Schematic (b) Layout
 3.4.2 Layout of a NOT gate
The circuit schematic and the corresponding layout is shown in the Fig.3.7.In the NOT
gate NMOSFET is connected in series with the PMOSFET. The drains of the 2 transistors
are connected to the metal wire, which goes out as an output line. Similarly the two gates
of polysilicon have been connected together and the intersection points goes to the output
line.

VDD VDD

x x x y

VSS VSS
(a) (b)
Figure.3.7 Circuit to layout translation of NOT gate

The basic procedure to adopt while drawing layout diagrams for any logic circuit is to
make the circuit of the logic circuit. Then identify the drain and source of the NMOS and
the PMOS transistors. The source of PMOS will be connected to VDD and the source of
the NMOS will be connected to VSS. The drain(s) of bottom most transistor(s) is (are)
connected to the drain (s) of the top most transistor(s). This junction is the output line.
The polysilicon layer cuts across the P-diffusion and the N- diffusion to form the two
transistors and the junction is the input line.
Following the above given procedure layout of any logic gate can be easily drawn.
3.5 Summary
The various layers, which make an integrated circuit, are identified in this chapter. The
layers that are stacked together for simple CMOS process are explained. The logic
circuits can be easily translated to the layouts by following standard procedure. The
different layers are drawn in different colours. But a state of art of VLSI chip will have
many more layers. There could be 6-10 metal layers. When all these layers are stacked on
top of an other, you get a fat IC. The layout details of a transistor and the circuit will give
you a correct picture of the process flow. The order in which the layers are integrated on
the substrate will be clear.

REFERENCES(for all the 3 chapters)

1.Introduction to VLSI circuits and systems: John P. Uyemura,

Edition 2005, John Wiley & Sons, Inc.
2.Basic VLSI design: D.A. Pucknell, K.Eshraghian, III Edition,
Prentice-Hall OF India Pvt.Ltd.
3.CMOS Digital Integrated Circuits –Analysis and Design:
Sung- Mo Kang, Yusuf Leblebici, III Edition.,Tata
McGraw-Hill Publishing Company LTD.,
4. Application –specific Integrated Circuits: Smith, Addison
Wesley 1997.
5. CMOS Circuit design, Layout and Simulation: R.Jacob
Baker, IEEE Press.,2000
6. Principle of CMOS VLSI Design: Neil Weste and K.
Eshraghian Addison Wesley.,1998.