Professional Documents
Culture Documents
38EMB – P6 1
Principle of quantizing and sampling
u u
7
6
5
4 Quantization
3 step (LSB)
TP t
2 Min. error of conversion = ½ of TS TP < TS
the quantization step
1
TP – conversion time (some converters
0
t require change of input during
conversion less than ½ LSB)
TS – sampling period; fS = 1/TS
Sampling (Shannon-Kotelnikov) theorem: í
If a band-limited signal with maximum frequency fM (e.g. frequency of the highest harmonic
component of periodical signal which cannot be disregarded) is sampled with sampling
frequency fS, then if there is fS ≥ 2 fM, then the original signal can be completely reconstructed.
38EMB – P6 2
Sample-hold (S/H) circuit
(some ADCs require that input voltage changes by less than ½ LSB during the conversion)
R1 S
OZ τ1 = R1C - as low as possible
u1 + u2
τ2 = Rin C – as high as possible
uR RZ
C In practice - special IOs
u ∆UU
u2(t) Basic parameters of the S/H circuit:
HOLD
Sample (track)
38EMB – P6 3
Digital-to-analog converters (DACs)
Examples of 4-bit DAC
MSB LSB R
+
1 0
UO
1 0 1 0 1 0
z3 z2 z1 z0
n −1
U O = − R ∑ 2i I zi ; zi = 0, 1
8I 4I 2I I i =0
Ur
+ UO
MSB LSB
38EMB – P6 4
Analog-to-digital converters (ADCs)
Integrating ADC a) dual-slope integration
Series mode dist., (for
UX ui1 T1 = k TDIST no influence)
ui1 Integrator
UX'
ui2 T2'
P1 R VK UX
+
Ur 0 T1 T2 t
C
Ur
P2 0
t
CL
f UO
CO G DC
UO' Nulling of
1 1 ui2
u i 2(1) =
RC ∫ U X d t =
RC
U Xt ; counter
1 1
RC ∫
u i 2( 2) = U O − U r d t = U O − U rt t
RC N1 Ur
1 1 T2 N2
UO = U X T1 ; 0 = U O − U X T2 ; → U X = U r = Ur
RC RC T1 N1
Conversion time: tens of ms; Using: DMMs (modifications according to resolution)
38EMB – P6 5
Integrating ADC b)using U/f conversion
Ur t0 t0 + T
R1 t
C 0
VK
+ T
U2i
U1 R2
+ f2
I
Ur
tP
Ug u2i
PG
0
1 1
R1C T∫ R2 C t∫P
UP tP − U 1 d t − − U P dt = 0
Measurement of voltage:
Decoder U 1T U P t P 1 R2 U 1
f2 H Cont = → T = f 2 =
+ display. R1 R2 R1 U P t P
TN
38EMB – P6 7
c) U1> 0
TS
fS
t
LSB
ui
DS t
Digital filter evaluates occurences of log 0 a log 1 („mean value“) during N clock pulses
38EMB – P6 8
Compensation ADC
Balancing algorithm: Successive approximation
UX UČAP
VK AR CO
MSB
3Ur/4
LSB UX
UDAC Ur Ur/2
DAC VR
Ur/4
Input voltage cannot change during
conversion more than ADC resolution (i.e. 1 0 0 1 1 0
voltage corresponding to the ½ LSB) MSB LSB t
Number of bits n: 12 - 14 U n −1
(resolution Ur/2n) UX = r
2
∑ zi ;
2 i
i =0
zi = 0, 1
38EMB – P6 9
Comparison ADC – parallel comparison (FLASH)
Ur UX
R/2 Typical bits number n: 8 (255 comparators)
VK1
R Decoder Conversion time: 0,4 to 50 ns
VK2 m from k Binary (higher sampling rate achieved by cyclic
ULSB output
R to binary sampling of more converters)
VK3
k = 2n - 1 Using: Digital storage oscilloscope
R
VKk
R/2
Conversion time: 10 ns až 1 µs
38EMB – P6 10