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A Design Technique for Controllable / Observable

Continuous-time Analog Active Filters

Mani Soma
Design, Test & Reliability Laboratory
Department of Electrical Engineering, FT-10
University of Washington
Seattle, WA 98195
206-685-3810.
FAX: 206-543-3842
e-mail: soma@ee.washington.edu

ABSTRACT

A design-for-test (DFT) methodology which seeks to improve the controllability and observability of internal
signals in active analog filters is presented. Assuming that a filter is designed using the standard operational
amplifier approaches, we propose to add simple metal-oxide-semiconductor (MOS) switches to modify the
original filter design. The modified design works as a filter in normal operation, but is converted to an "analog
scan" structure in the test mode. This structure allows the observation and control of the input / output (I/O)
signals of every filter stage. The modification technique and the DFT methodology are described and applied to
a case study. The simulated and measured results confirm the validity of the methodology and demonstrate its
applicability. Design tradeoffs and possible extensions are discussed.

I. Introduction and Problem Statement

The design of analog integrated circuits (IC) has always been a challenge due to the sensitivity of circuit
parameters with respect to component variations and process technologies. To ensure the testability of a design
is an even more formidable task since testability is not well defined within the context of analog ICs. While the
number of I/O pins of an analog IC is reasonably small compared to that of a digital VLSI circuit, the
complexity due to continuous signal values in the time domain, and the inherent interaction between various
circuit parameters impede efficient functional verification and diagnosis. Analog testing frequently relies on
acceptable operational margins for critical parameters, and analog diagnosis is still more of theoretical interest
rather than experimental applications.

In view of this complexity, the general problem of design-for-test (DFT) for analog circuits is almost certainly
intractable. However, for specific classes of circuits, numerous attempts [11,12,14] have been made to improve
some measure of testability. This paper presents a DFT methodology applicable to the class of active analog
filters designed based on the standard operational amplifier approaches. Testability is defined as controllability
and observability of significant waveforms within the filter structure. Within the context of this paper, the
significant waveforms are the input / output (I/O) signals of every stage in the filter, and while we do not
propose a numerical measure of testability, the methodology permits full control and observation of these I/O
signals from the input to the first stage and the output of the last stage of the filter. We assume of course that
the first-stage input is controllable and the last-stage output is observable.

The problem to be solved can be simply stated as follows. Given a multi-stage analog active filter, how can
internal nodes be controlled and observed to facilitate test applications to individual stages? How can a path be
sensitized to enable fault excitation and fault propagation? We note in particular that path sensitization is, to
some extent, independent of the specific types of faults since a path is established only through non-faulty
devices to propagate signals or fault effects. The following section reviews fault models for the sake of
completeness and to set the stage for a discussion of previous works on DFT techniques applicable to these

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faults. The fundamental theory underlying the proposed controllable / observable filter designs is presented
followed by an algorithmic description and the results of a selected case study (among many). These results are
considered from the perspectives of the overhead incurred and the extension of this technique to other analog
structures.

II. A brief review of fault models

Numerous works [2-4,9-13] have been devoted to testing for catastrophic failures in analog circuits, i.e. failures
that manifest themselves in a totally malfunctioned circuit. These failures, frequently called catastrophic
failures, are easy to detect but difficult to locate and correct. A more general type of faults results in
performance outside specifications. The problem with out-of-specification faults is inherently more difficult
since the circuit still works but is unacceptable, e.g. a low-pass filter with wider bandwidth than as designed.
Various faults within the circuit could give rise to the observed effects at the output (or, to use the prevalent
terminology in digital testing, these faults are equivalent), thus fault isolation is an important aspect of testing
for these non-catastrophic faults.

The detection of out-of-specification faults or catastrophic faults is fairly easy to accomplish for simple circuits
based on a comparison between simulated outputs and measured data. For more complex circuits, unless a
specific fault model is created and test generation techniques have been devised to detect these faults, extensive
tests must be performed to guarantee the functional correctness of the circuit under test. Several questions
immediately arise: what test waveforms should be applied? do they need to be applied in some sequence? what
faults do they detect? The first two questions involve test generation techniques, and the third involves fault
identification for a given circuit. Both test generation and fault identification require path sensitization, and the
work proposed in this paper, by the virtue of improving controllability and observability of internal nodes, is
applicable to test generation and fault detection algorithms as will be demonstrated below.

III. Previous work in analog design-for-test and diagnosis

Most previous works in the area of analog fault modelling and diagnosis focus on the theoretical aspects of the
problem. Rapisarda and DeCarlo [1] uses a tableau approach in conjunction with a Component Connection
Model to generate a set of fault diagnosis equations to be solved by regular matrix inversion techniques. The
technique is quite computing intensive since it always results in, to use the authors' words, "a formidable set of
nonlinear equations." Lin and Elcherif [2] studies the analog fault dictionary approach with a focus on DC hard
failures (open or short), which could be used in conjunction with the technique in [1]. The more theoretical
works include Hakimi's extension of the t -fault diagnosable concepts to analog systems [3], Togawa's study of
linear algorithms for branch fault diagnosis [4], Huang and Liu's method for diagnosis with tolerance [5],
Visvanathan and Sangiovanni-Vincentelli's theory of diagnosability [6,7], Trick and Li's analysis of sensitivity
as a diagnostic tool [8], and Salama's decomposition algorithm for fault isolation [9]. These theoretical works
rely extensively on the characteristic matrix of the circuit under test to define conditions for testability and
diagnosability, and while they have a very general scope, their applications to specific circuits have not been
quite successful. Either the circuits under study were small (a 4-transistor amplifier in [1]) or numerous test
points are assumed. The accessibility of test points is a matter of course for board-based designs but cannot be
assumed for analog VLSI due to the premium in input-output pins in integrated circuits.

Analog test generation and design-for-test techniques have also been studied [10,11]. More recently, several
new works were presented at the International Test Conference (1988), which include a testability evaluation
tool [12], a test generation algorithm for DC testing [13], and a DFT scheme based on signal multiplexing [14].
These recent works approach the problem of analog testing from a more experimental perspective and discuss
some fundamental principles regarding controllability and observability of internal signals. While the traditional
techniques based on matrix solution and sensitivity analysis are still prevalent, the multiplexing technique [14]
approaches a real DFT methodology where tradeoffs seem reasonable. Several new approaches in analog test
and design-for-test were discussed at the 1991 Pacific Northwest Test Workshop: current monitoring [17],
sensitivity computation as a diagnostic tool [18], and a design framework to enhance testability [19].

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The work presented in this paper is influenced by the principles enunciated in [14] but seeks a different method
to improve controllability and observability while avoiding the obvious problems associated with multiplexing.
We also recognize that the general analog test problem is untractable and thus focus on the test methodologies
for analog macrocircuits frequently used in VLSI and signal processor designs. These macros include filters,
converters (DAC and ADC), comparators, operational amplifiers, phase-locked loops, etc. The limited focus
turns out to be quite valuable in pointing the way to more testable designs using the established DFT techniques
in digital VLSI. In particular, the scan design principle will be used in this paper in a modified form as the
fundamental method to modify analog filter structures to improve testability. This fundamental theory and its
application to filter DFT are presented in the next section.

IV. Fundamental path sensitization theory for analog filters

The success of scan techniques in digital testing relies heavily on the register structure in sequential logic
designs. A straightforward application of these techniques to analog circuits requires similarity in structures,
and one circuit class exhibiting this configuration is a multi-stage active analog filter (figure 1). A signal travels
sequentially across the stages, each of which has a well-defined function, and whose gain and bandwidth are
determined by the appropriate input and feedback impedances. Frequency effects internal to the operational
amplifiers or due to external compensation can be absorbed into the overall pole-zero configurations of the
stage or the entire filter.

The most significant functional difference between the analog filter stage and the register flipflop is that each
stage does not store analog information in the same way that a flipflop stores digital information. Instead, the
signal is modified by the stage gain and bandwidth before passing on to the next stage. Waveform scanning to
control and observe signals within the filter is possible only if somehow the bandwidth limitation can be relaxed
to accommodate the test signals for individual stages. With respect to figure 1 used as an example, stage 2
could be tested by itself if stages 1 and 3 are put in a test mode by widening their bandwidths. An input signal
can be applied at the filter input (stage 1) and "scanned" to the input of stage 2, thus improving the
controllability of the circuit internal signals. The output of stage 2 can be "scanned" across stage 3 to appear at
the filter output, thus improving the observability of these internal signals. The word "scanned" is used here
only in the figurative sense to demonstrate the philosophical similarity with the digital scan path technique,
since literally the signals are continuously transmitted in analog circuits and there is no need for any clock to
enable and disable this transmission.

The absence of a clock simplifies the incorporation of the scan technique to the analog filter structure. Further
simplifications result from the observation that the filter can be built using only three major circuit blocks:
inverting amplifier, non-inverting amplifier, and summing amplifier. The active elements are ideal operational
amplifiers, and the passive impedances can be synthesized with only two element types: resistor and capacitor.
We exclude for the time being the class of switch-capacitor filters, which will be revisited at the end of the
paper.

With respect to the conventional analog active filter structures, we have arrived at several conclusions:

1) the cascade of the stages resembles a scan path,

2) the major difference with digital scan is that the signal is continuously transmitted and
bandwidth-limited by each stage,

3) there are only 3 basic stage configurations, and

4) the filter bandwidth is realized by the passive impedances.

Waveform scanning to improve the controllability and observability of signals can be accomplished if the
bandwidth of each stage can be dynamically broadened in the test mode. The attendant change in gains is
unavoidable but is not a real issue since any gain change, as demonstrated below, involves a fixed scale factor

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and can be taken into account by programming the test equipment to compensate for this factor. Thus the
critical problem here is dynamic bandwidth expansion.

This bandwidth expansion to enable the scanning of waveforms in and out of a filter stage under test is
performed by reducing the capacitive effects in the impedances of the stages not under test. Given an active
analog filter, all the impedances are realizable based on a combination of four fundamental connections of
resistors and capacitors: single-resistor branch, single-capacitor branch, series RC branch, and parallel RC
branch. We now describe four canonical transformations which in effect, disconnect the capacitors from the
circuits using simple MOS switches. These canonical transformations form the basis for all impedance
modifications involved in making the filter testable.

1. Single-resistor transformation

An ideal resistor has an unlimited frequency bandwidth, thus the transformation in this case is the identity
transformation, i.e. the resistor does not need to be modified.

2. Single-capacitor transformation

The single-capacitor branch cannot simply be disconnected by a single MOS switch since such a disconnect
could create noise and instability problems, e.g. when the capacitor is the only feedback element in an
integrator subcircuit. Thus the transformation involves two MOS switches as shown in figure 2(a). Using the
frequency parameter s =jw , the impedance equations are:

original configuration :

modified configuration in normal mode (Ms on, Mp off):

modified configuration in test mode (Ms off, Mp on):

The impedance ZN is approximately the same as the original impedance Z only if Rs is small enough so that
the zero created does not affect the frequency response of the stage or of the overall circuit. The range of
acceptable values of Rs depends on the pole-zero pattern of the original filter, but it should be noted that a small
value of Rs requires a switch with large W/L . For the case of circuit boards, the size of Ms is irrelevant since
packaged MOS devices are available with very low on-resistance. The size of Mp does not matter since its
on-resistance only affects the gain in the test mode, which can be taken into account by the test equipment as
mentioned above.

3. Series RC transformations

The capacitive effect can be reduced by two possible transformations: a switch in series with the capacitor to
disconnect the branch in the test mode or a switch in parallel with the capacitor to make the branch resistive in
the test mode.

The series-switch transformation shown in figure 2(b) results in the following impedance equations:

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original configuration:

modified configuration in normal mode (Ms on):

modified configuration in test mode (Ms off):

To avoid significant perturbations of the original pole-zero locations, Rs must be much less than R .

The parallel-switch transformation shown in figure 2(b) results in the following impedance equations:

original configuration:

modified configuration in normal mode (Mp off):

modified configuration in test mode (Mp on):

There are two cases in which the impedance ZT appears almost purely resistive. The first is the obvious
requirement Rp << 1/w C, which merely means that the switch shorts out the capacitor during the test scan. The
second involves a pole-zero cancellation, which takes place if Rp << R . In this case, the zero at -1/(R||Rp)C
nearly cancels the pole at -1/RpC , and the branch impedance is just the series R + Rp . The design value of Rp
should be chosen as the larger of the two possible values to minimize the layout size of the switch Mp.

4. Parallel RC transformations

The parallel RC branch may be treated as a combination of a single-resistor branch (no transformation
required) and a single-capacitor branch. The single-capacitor transformation, as described above, involves two
switches; however, in the parallel RC case, only one switch is sufficient. The added switch can be either in
series with the capacitor to disconnect it or in parallel with the capacitor to short it out in the test mode. The
two transformations are analogous to that presented above for the series RC branch.

The series-switch transformation shown in figure 2(c) results in the following impedance equations:

original configuration:

modified configuration in normal mode (Ms on):

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modified configuration in test mode (Ms off):

To avoid significant perturbations of the original pole-zero locations, Rs must be much less than R .

The parallel-switch transformation shown in figure 2(c) results in the following impedance equations:

original configuration:

modified configuration in normal mode (Mp off):

modified configuration in test mode (Mp on):

There are two cases in which the impedance ZT appears almost purely resistive. The first is the obvious
requirement Rp << 1/w C, which merely means that the switch shorts out the capacitor during the test scan. The
resulting impedance is the expected R || Rp . The second involves a pole movement which takes place if Rp <<
R . In this case, the original pole at -1/RC has moved to the pole at -1/RpC , thus the bandwidth of the stage is
significantly widened. The design value of Rp should be chosen to broaden the bandwidth sufficiently for
waveform scanning and, at the same time, to reduce the layout size of the switch Mp if possible.

V. Design-for-test procedure

The design-for-test (DFT) procedure to improve controllability and observability follows directly from the
above discussion of the modification techniques to increase the bandwidths of individual filter stages. Given the
design of a conventional active filter with N stages, each stage i has bandwidth Bi and gain Gi . Let B = max
{Bi , i=1..N} . The DFT algorithm is:

1. Consider the first stage (i =1 ). Insert MOS switches according to the above transformations to widen
the stage bandwidth to at least B . Define the control waveforms necessary for normal mode and test
modes.

2. Repeat step 1 for stages i = 2 ..N.

3. Inter-stage (global) feedback circuits. The circuits in the inter-stage feedback loops can be modified in
a manner similar to step 1. Note that controllability and observability can be improved if the feedback
loops are disconnected or if the feedback impedances are modified by the additional MOS switches. Any
impedance modification of course should not affect the circuit stability.

4. Overhead reduction of control lines: from the control signals defined in steps 1-3, establish sets of
common control lines (i.e. lines that always have identical logic values during test and normal modes).

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Replace each set of common lines with one single line.

5. Overhead reduction of MOS sizes: from the overall pole-zero diagram of the modified filter, consider
additional movements of the poles / zeroes introduced by the test switches to see if these devices can be
made smaller without impeding signal scanning during test mode. For circuits on board where packaged
MOS devices are used as switches for testing, the sizes are irrelevant and this step is skipped. The
appropriate packages are chosen based on the specification of switch on-resistance.

The redesigned filter now provides better controllability and observability, and test generation and fault
isolation for any specific fault can proceed. We note that the ability to sensitize paths based on the proposed
technique does not dictate nor constraint any strategy for test generation and fault isolation, thus the designer
has more flexibility in applying his algorithms for specific faults germane to the design under consideration. We
will show some examples of test generation and fault isolation based on this technique in the case studies
below.

VI. Case studies and results

The above DFT technique has been applied to numerous case studies including low-pass, band-pass, high-pass,
and notch filters. The filter types include Chebyshev, Butterworth, inverse Chebyshev, and elliptic. This section
selects one of these circuits and presents a detailed application of the methodology.

The circuit used for this case study is a combined band-pass and low-pass biquad filter in figure 3(a). The data
are obtained from a board design using the Motorola MC14573 as the operational amplifier, and the
measurements are averaged to reduce noise due to the test equipment and digitized samples. Comparable data
for IC designs, with external capacitors due to their large values, have also been collected using basic CMOS
operational amplifiers in 2-mm technology.

The major purpose of this section is to show the usefulness of improved controllability and observability in test
application, thus complicated fault models are de-emphasized. The faults to be studied below are faults in the
passive elements (resistors and capacitors), even though faults in the operational amplifiers could have been
included. Their inclusion, due to the complexity of fault effects, would have obscured the focus of our proposed
path sensitization technique, which is independent of fault models as observed in sections I and II above.

The output of the first stage has band-pass characteristic, and the outputs of the second and last stages have
low-pass characteristics. The transfer function, assuming the last stage output is the circuit overall output, is:

The frequency response and the timing waveforms for a 1V-amplitude square wave input are shown in figure 4.
The filter has 2 zeroes at infinity and 2 poles at -501j1000 radians, corresponding to a pole frequency of 159
Hz.

The modification to improve controllability and observability involves adding 3 MOS switches (figure 3b): Ms1
in series with C1 (per parallel RC branch transformation), Ms2 in series and Mp2 in parallel with C2 (per
single-capacitor transformation). Note that we have not inserted a MOS device to modify the impedance of the
global feedback resistor R3 in the test mode. This omission is intentional and its effects will be evident in a
fault isolation example below.

The transfer function in normal operation (the 2 series switches are on, the parallel switch is off) is:

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The values of the switch resistances are chosen to meet two criteria:

1) the pole frequency movement must be negligible to preserve the original filter bandwidth, and

2) the two new zeroes introduced by the MOS switches must be as far outside the original filter bandwidth as
possible to avoid disturbing the magnitude and phase response of the original filter in the passband.

The second criterion requires that the zeroes must be at least 10 times larger than the original pole frequency
(1000 radians) to reduce phase perturbation within the passband. Since the new zeroes are at -1/Rs1C2 and
-1/Rs2C1, the switch on-resistance must be less than 1KW. Using NMOS as a switch and assuming the
following device parameters:

the switch resistance is approximately 400W (5V power supply and gate signal). These values are reasonable in
an analog design even though the W/L seems large compared to devices used in digital VLSI. Note that for the
case of filter design on a printed circuit board, MOS switch packages are available with on-resistance less than
100W and four to six switches are contained in one package. The overhead is thus even lower. The control line
overhead is two, which is acceptable for board designs. For IC designs of mixed analog-digital systems, these
control lines might be obtained from a digital scan path or merged with on-chip digital test control signals. In
general, since strictly analog circuits are not I/O-limited, the use of two extra pins for testability is reasonable.

Assuming that all 3 MOS have identical on-resistance of 400W, the poles and zeroes of the modified circuit
are: 2 poles at -901j1000 radians (or pole frequency at 159 Hz), 2 real zeroes at -2.5E4 radians (much larger
than pole frequency in radians). To be more exact in the pole frequency calculations, the pole movement is
from 159 Hz (original circuit) to 158.5 Hz (modified circuit). The frequency response is plotted in figure 4 and
is remarkably similar to the original response. The gain peaking at 159 Hz is preserved, the roll-off outside the
passband is identical up to 2 KHz (far outside the passband). The phase characteristics show more perturbation
due to the zeroes when the frequency exceeds 1 KHz. Since this frequency is an order of magnitude larger than
the filter bandwidth, the circuit response should not be affected significantly. This observation is more evident
in the filter response to an input square wave of amplitude 1V and frequency 100 Hz shown in figure 4. The
two voltage outputs are almost identical, showing that not only the phase perturbation is negligible but also the
total harmonic distortion (THD) introduced by the non-linear MOS resistors is insignificant. A Fourier analysis
of the measured spectra shows no increase in the THD of the modified circuit.

We have thus shown that the modified circuit performs almost identically to the original filter. It should also be
mentioned that the added MOS devices always operate in the linear region. The maximum VDS across an
on-switch is less than 2V in all modes, thus assuring that the switch is indeed a linear resistor. It would have
been disastrous had the devices entered the saturation mode as current sources. In all case studies conducted so
far, we have not encountered this problem with current sources.

The study of fault effects and the use of path sensitization to observe these effects will be presented next. Three
different faults will be studied to show how a fault can be excited and propagated using these built-in MOS
devices:

1. A catastrophic fault in the second stage: C2 has a broken connection to the opamp input. This is the type of
catastrophic faults usually assumed in previous works , which includes open circuit, short circuit, and bridging
faults. This fault is chosen to illustrate the possible application of path sensitization to fault detection and
isolation without resorting to a full fault dictionary.

2. A catastrophic fault in the global feedback resistor: R3 has a broken connection. As mentioned above, we
intentionally did not use a MOS device to control this feedback branch. This fault is chosen to illustrate that a

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partial application of the proposed technique, in order to reduce overhead, is still beneficial in improving
testability.

3. A non-catastrophic out-of-specification fault: R5 has the incorrect value of 100KW instead of the correct
value 10KW. This fault is chosen to illustrate the application of the proposed DFT methodology to study faults
due to parameter variations.

1. Intra-stage fault (C2 disconnected)

The output waveforms are shown in figure 5. It is obvious that the circuit malfunctions with a square-wave
output instead of the expected sine wave. The test procedure, using path sensitization, proceeds with 3
measurements: the filter in all-test mode (all switches set to disconnect capacitors from the circuit), stage 1 in
test mode, and stage 2 in test mode. Note that stage 3, being a simple gain stage, is not modified and does not
have a corresponding test mode.

The output waveform from the all-test mode (figure 5b) shows the correct response of a square wave opposite
in phase to the input. Thus the overall structure of the filter, especially in the sensitized signal path via R4, R2,
R5, and R6 is likely to be fault-free. A gain calculation also shows that R3 is fault-free. Thus the fault is most
likely to reside in either stage 1 or stage 2.

The output from testing stage 1 (figure 5b) shows an RC response to a pulse waveform as expected. The output
from testing stage 2 (figure 5a) shows an oscillatory response, thus confirming that a fault in stage 2 has been
excited from the first-stage input and propagated to the third-stage output. To carry the inference a step further,
since R2 has already been tested in the all-test mode, the fault is now isolated to the capacitor C2, which is the
actual fault.

This case study shows that the measured and simulated data can be used to make qualitative and quantitative
observations facilitated by path sensitization. Other experimental data easily collected during testing is the
Fourier spectra of the waveforms, gain and phase information, etc. The application of each test to a specific
stage is straightforward.

2. Inter-stage fault (global feedback R3 disconnected)

This fault is studied to show the extension of this technique in testing inter-stage faults even though no MOS
switch is used to control the feedback branch. R3 is assumed to be disconnected, and the output waveforms for
this case are shown in figure 6. The fact that the circuit malfunctions is obvious. The output waveform for the
all-test mode (figure 6b) shows the correct square wave having opposite phase to the input, and the gain
calculation shows that the output gain is about 20% larger than expected. This experiment seems to verify that
the overall signal path contains a resistor with incorrect value. The output from testing stage 1 (figure 6b)
shows the expected RC response to a pulse signal, but again incorrect amplitude values. The output from testing
stage 2 (figure 6a) shows a triangular wave whose negative swing is clipped due to the power supply limit. This
clipping would not have occurred if a smaller input signal (e.g. amplitude 0.1V instead of 1V) was applied;
however, we have used exactly the same input throughout to simplify the discussion and for consistency. Had a
smaller input signal been applied, the output would have been a perfect triangular wave. This output is correct
for stage 2 by itself, but within the context of the filter circuit with the overall feedback R3, it is actually
incorrect: the expected response is a 1-pole 1-zero response, not an integrator waveform (1 pole at f = 0). Thus
the testing of stage 2 shows that the stage itself functions but somehow the feedback signal from the filter
output back to stage 1 is incorrect.

The possible faults are thus limited to R5, R6, and R3. It becomes much more difficult at this point to locate the
fault since we have no control over stage 3 and the feedback from stage 3 to stage 1. It is possible to proceed
further even without this controllability. The phase information (figure 7) is now used to assist fault
identification if so desired. If the fault is due to R5 or R6, the gain would be affected but not the overall output
phase. Yet the output phase shows a clear degradation at low frequencies equivalent to a pole at f = 0 Hz. The

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existence of this pole strengthens the hypothesis, derived from output waveform observations above, that the
faulty component is likely to be R3. Further simulations and more output data collections (gains in various test
modes and Fourier spectra) confirm this hypothesis and further identify that R3 must be faulty to justify the
observed data.

This case study shows the difficulty of testing when we have no control over a stage (due to resistive
impedances) or global feedback components. It is possible to modify the circuit by adding two more MOS
switches (one in parallel with R6 and one in parallel with R3) to provide more controllability, but the overhead
incurred is higher. Even without this control, we have shown that the proposed DFT technique is valuable in
sensitizing paths to assist fault detection and location.

3. Out-of-specification fault (R5 incorrect)

This case study shows the application of the proposed DFT technique to detect non-catastrophic faults, which
are quite common yet very difficult to deal with. The fault is the incorrect value of R5 at 100KW instead of the
correct value of 10KW. The output waveform (figure 8a) has the correct sine wave but has an obvious shift in
phase and much lower gain than expected.

The outputs from the all-test mode and from testing stage 1 (figure 8b) show very low gain, thus the
preliminary indication is an incorrect resistor value along the sensitized signal path. The calculations of gain
and pole-zero locations from the circuit topology and the data in figure 9 for these two test modes verify that
R1, C1, R6 and R3 have correct values. The calculations of gain and pole-zero locations for the testing of stage
2 verify that R4 has correct value. The fault is thus likely to be with R2 or R5. Unfortunately, it becomes
impossible at this point to isolate the fault further since both resistors always appear together in all expressions
for the output waveforms, gains, and phases. The process stops at the identification of the possible faulty
resistors (R2 or R5).

This case study shows that the proposed technique offers considerable improvements over existing techniques
in identifying and isolating out-of-specification faults. The fault in this case could not be narrowed down to a
single resistor due to the lack of controllability of stage 3. In fact, if we had some controllability of stage 3, the
fault could have been located precisely. We note the interesting fact that the concept of "equivalent faults" is
applicable in this case since the incorrect values of R2 and R5 manifest in the same circuit characteristics for all
experiments.

VII. Design-for-test features and discussions

The proposed design-for-test technique has several unique features:

1. The overhead due to the extra MOS switches and control waveforms is small. For the above circuit, 3 MOS
devices, 2 control signals, and an inverter circuit are added, resulting in a layout overhead of less than 5%,
almost no additional power loss, and no additional total harmonic distortion in the output waveforms. For a
general case, the overhead is comparable to the simple scheme of multiplexing [14] the internal outputs for
observation, but we gain an advantage here of controllability and modifiability of circuit parameters during test
mode.

2. The proposed test methodology does not introduce more noise into the circuit either during the test mode or
the normal mode. In either mode, the control signals are stable (either always HIGH or always LOW) and no
switching noise is coupled into the operational amplifiers. The simulation of several circuits shows that the
change in noise figure and total harmonic distortion is negligible (less than 1% change) during normal
operation. The leakage currents at the source and drain of the MOS switches potentially can affect the input
offset currents and the output offset voltages, thus the layout of these switches requires careful placement. For
example, the switch Ms2 should be laid out between the capacitor C2 and the output of the stage 2 so that the
leakage currents of Ms2 do not affect the input circuit of stage 2.

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3. The DFT methodology is well-defined, thus is suitable for silicon compiler implementation. The use of
silicon compilers also relieves the designer of the placement task mentioned above, and the simulation models
can also be automatically generated for further use in testing and diagnosis. At the time of this writing, two
implementations have been completed at the University of Washington and at MCC [16].

4. The bandwidth loss due to the additional MOS devices is negligible compared to the original bandwidth of
the filter. The MOS parasitic capacitances are small compared to the capacitors used in the circuits. Phase
perturbation outside the passband is more of a concern, and simulation should be used to ensure that the filter is
unconditionally stable in any mode.

5. The added MOS devices are very simple and unlikely to fail compared to the rest of the circuit (which is
much more complex), so there is no additional fault introduced by these devices. The usual drawback that the
test devices themselves fail or add more faults is thus non-existent with this DFT technique.

6. Path sensitization is a fundamental tool for test generation and fault diagnosis, and our sensitization technique
has wide applications in these two disciplines. The above examples illustrate possible diagnostic procedures,
and their generalizations, including the use of analog fault dictionary during diagnosis, are straightforward. The
overall effort is still greatly reduced by the controllability and observability provided by this technique.

7. The test generation step in the proposed DFT algorithm can be automated since each stage has a well-defined
function. The generated test waveforms and frequency responses can also be automatically compared with the
measured data, and the entire procedure is amenable to a computer-aided design and test methodology
comparable to the methodologies for digital VLSI.

8. The proposed methodology is extensible for other analog circuits (as discussed below) and especially for
integrated analog-digital system design and test since only basic MOS switches are used to provide
controllability and observability.

VIII. Possible extensions of the proposed methodology

While the proposed DFT methodology was originally developed to address the problem of analog
continuous-time active filters, the extensions to other circuits and other parametric test procedures are possible:

1. Switch-capacitor filter (SCF) structures. The MOS devices are already an integral part of the SCF structures,
thus the application of our methodology will have lower overhead. The critical question here is not the extra
devices as much as the timing methodology used during the test mode. A timing discipline based on the same
idea of improving controllability and observability in SCF filters has been studied and is presented in [15].

2. The verification that a filter has acceptable noise figure is probably the most difficult test to perform, and our
technique provides a well-defined procedure to identify the possible noise sources in a filter circuit. The
fundamental idea is quite simple: since bandwidth, gain, and noise are strongly correlated, noise performance
can be inferred from bandwidth and gain data. The proposed DFT technique permits gain and bandwidth
controllability for each circuit stage, thus can be used to study the noise within a stage and identify the possible
locations generating excessive noise. Once the identification of a stage is accomplished, the stage can be
redesigned to reduce the noise to within specifications.

3. Most DFT techniques for analog circuits rely almost exclusively on DC testing to detect faults. The proposed
technique allows dynamic testing as well and provides an immense amount of information to assist fault
identification and location.

4. The global feedback components, especially if they are resistors, are very difficult to test. A MOS device in
series with a feedback resistor permits impedance modification during the test mode and reduces the test
difficulty. A second technique, more "brute force", is to isolate each stage and test it by itself with relatively no
interference from any other stages in the circuit. The implementation of this brute force technique, shown in

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figure 10, requires two extra MOS devices per stage. The overhead is higher, especially in the added control
lines, and care must be taken in the exercise of this technique. As shown in the above case study and from our
experience in numerous filter structures, the brute force implementation is rarely needed and should be resorted
to only when absolutely necessary. The testing procedure is straightforward: a test signal is connected to the
SUT via the MOS devices in the preceding stages, and the output is connected to the observable filter output via
the MOS devices in the succeeding stages. All other stages are inactive since the MOS switch at the output of
each stage is turned off to effectively disconnect the stage output. This technique is conceptually identical to the
multiplexing scheme even though the implementation is quite different.

IX. Conclusion

A design-for-test methodology for continuous-time analog active filters has been described. The methodology,
which exploits the filter structure and a modified form of signal scanning for analog circuits, provides
controllability and observability of internal signals of each filter stage. The DFT algorithm is discussed and
shown to be suitable for silicon compiler and CAD implementations. Possible extensions to switch-capacitor
filters and other structures are mentioned, and the proposed technique shows promise of wider applications in
analog design-for-test methodologies.

Acknowledgements

Dr. Thomas Morrin (IBM, San Jose), Thomas Alexander, and Pamela Aratani (both at University of
Washington) contributed several ideas regarding waveform scanning and the "brute-force" stage isolation
technique. Professor Jacob A. Abraham (University of Texas, Austin) suggested the method for noise testing
based on gain / bandwidth control. Partial financial support provided by the Washington Technology Center.

References

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[4]. Y. Togawa, T. Matsumoto, and H. Arai, "The TF - equivalence class approach to analog fault diagnosis
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[8]. T.N. Trick and Y. Li, "A sensitivity based algorithm for fault isolation in analog circuits," Proc. IEEE Intl.
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[9]. A.E. Salama, J.A. Starzyk, and J.W. Bandler, "A unified decomposition approach for fault location in large
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[10]. C.L. Wey and R. Saeks, "On the implementation of an analog ATPG: The linear case," IEEE Trans.
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[11]. Z.F. Huang, C.S. Lin, and R. Liu, "Node-fault diagnosis and a design of testability," IEEE Trans. Circuits
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[12]. G.J. Hemink, B.W. Meijer, and H.G. Kerkhoff, "TASTE: A tool for analog system testability evaluation,"
Proc. IEEE Intl. Test Conf., pp. 829-839, September 12-14, 1988, Washington DC.

[13]. M.J. Marlett and J.A. Abraham, "DC_IATP: An iterative analog circuit test generation program for
generating DC single pattern tests," Proc. IEEE Intl. Test Conf., pp. 839-845, September 12-14, 1988,
Washington DC.

[14]. K.D. Wagner and T.W. Williams, "Design for testability of mixed signal integrated circuits," Proc. IEEE
Intl. Test Conf., pp. 823-829, September 12-14, 1988, Washington DC.

[15]. M. Soma, "Path Sensitization Techniques for Switched-Capacitor Filters," submitted to IEEE Int.
Solid-State Circuits Conf. 1992.

[16]. M. S. Abadir, RA Testability Insertion Guidance Expert System for Mixed Analog / Digital Systems,S
IEEE Pacific NW Test Workshop, May 29-31, 1991, Seattle, WA.

[17]. I.M. Bell et al., RTesting Mixed Analogue and Digital Integrated Circuits,S IEEE Pacific NW Test
Workshop, May 29-31, 1991, Seattle, WA.

[18]. M. Slamani and B. Kaminska, RFault Diagnosis of Analog Circuits based on Sensitivity Computation and
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Footnotes

Manuscript received _____________________________.

This work is partially supported by the Washington Technology Center.

The author is with the Department of Electrical Engineering, University of Washington, Seattle, WA 98195.

List of figure captions

Figure 1.

Multistage analog filter block diagram.

Figure 2.

(a) Single-capacitor transformation

(b) Series RC branch transformations

(c) Parallel RC branch transformations

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Figure 3.

(a) Normal filter circuit diagram

(b) Modified filter circuit diagram

Figure 4.

(a) Output waveform comparison

(c) Output phase comparison

Figure 5.

(a) Output voltages with C2 fault

(b) Output voltages in scan modes (C2 fault)

Figure 6.

(a) Output voltages with R3 fault

(b) Output voltages in scan modes (R3 fault)

Figure 7.

Output phase with R3 fault

Figure 8.

(a) Output voltages with R5 fault

(b) Output voltages in scan modes (R5 fault)

Figure 9.

(a) Output gain with R5 fault

(b) Output gain in scan modes (R5 fault)

Figure 10.

A brute-force stage isolation technique

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