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EE/APR 2009/ECE590/KJE609/KJE416

UNIVERSITI TEKNOLOGI MARA FINAL EXAMINATION

COURSE

ELECTRONICS AND MICROPROCESSORS / ELECTRONIC AND MICROPROCESSORS / ELECTRONICS ECE590/KJE609/KJE416 APRIL 2009 3 HOURS

COURSE CODE EXAMINATION TIME

INSTRUCTIONS TO CANDIDATES 1. 2. 3. This question paper consists of five (5) questions. Answer ALL questions in the Answer Booklet. Start each answer on a new page. Do not bring any material into the examination room unless permission is given by the invigilator. Please check to make sure that this examination pack consists of: i) ii) iii) the Question Paper a four - page Appendix (MC68000 CPU instruction set) an Answer Booklet - provided by the Faculty

4.

DO NOT TURN THIS PAGE UNTIL YOU ARE TOLD TO DO SO

This examination paper consists of 7 printed pages
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EE/APR 2009/ECE590/KJE609/KJE416

QUESTION 1 a) Refer to the circuit in Figure Q1(a). The diode is made of silicon, calculate i) ii) iii) the current that flows in the 2.2 KQ resistor, the power dissipated in the 1.2 KQ resistor, the power delivered by the 20 V battery.

State any assumption(s) made.

20 V 1,2 K

j r Diode
2.2 K

Figure Q1 (a) (7 marks) b) Refer to the circuit in Figure Q1(b). The center-tapped transformer turns ratio is 10:1, and Vs is a 60 Hz sinusoidal voltage having RMS value of 240 V. Assume that the diodes are ideal. i) ii) iii) Sketch and label the voltage VL. Calculate the current in RL when Rl_ is 1 KQ. If voltage VL is filtered using a 47 uF capacitor, calculate the percentage ripple of the resulting voltage.
Diode

Transformer

Diode

Figure Q1(b) (8 marks)

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EE/APR 2009/ECE590/KJE609/KJE416

c)

Figure Q1(c) shows a load resistor RL, requires a voltage of 5 V with a current of 0.5 Amperes. The supply voltage VS is fluctuating from 11 to 17 volts. Calculate:i) ii) the value of resistor RS and its wattage. the maximum and minimum currents in the Zener diode.

vs

RL

Figure Q1(c) (5 marks)

QUESTION 2 a) Figure Q2(a) shows a single-stage common emitter amplifier using a Bipolar Junction transistor (BJT) having the DC gain p of 100. Given that VCC = 20 V, RB = 400 KQ, RC = 2 KQ, RE = 1 KQ. 1
RB Vcc

Figure Q2(a) For the BJT, use VBE = 0.7 V, determine :i) ii) the Emitter current lE, Base current lB, and Collector current l c . the Collector voltage Vc and draw the DC load line for the transistor. (8 marks)

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EE/APR 2009/ECE590/KJE609/KJE416

If the circuit shown in Figure Q2(a) above is made into an amplifier with a bypass capacitor being connected across resistor RE, calculate :i) ii) iii) the transresistance value, re. the input impedance ZlN, and output impedance ZOUT. the voltage gain, AV. (12 marks)

State and explain any assumption/s made during the analysis.

QUESTION 3 a) For the operational amplifier circuit in Figure 0.3(a) below :i) ii) Derive the output voltage Vo, in terms of input voltage VS and the resistors R1 and R2. Calculate the value of resistor R1, if the gain of the operational amplifier circuit is 5 and R2 = 250 KQ.

R2

A/W
Ri

VS

OP-AMP

VO

Figure Q3(a) (5 marks)

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EE/APR2009/ECE590/KJE609/KJE416

b)

Prove that the for operational amplifier circuit in Figure Q3(b) the gain is :Vo Vs

R,
Rl + R2J

R1

A/W
Vs
R2

OP-AMP

VO

Figure Q3(b) (6 marks) c) Convert the following numbers into the number system stated. Show all the calculations involved. i) ii) iii) iv) v) AF4516 convert into decimal number 724810 convert into binary number 3BE75416 convert into binary number 652468 convert into hexadecimal number 110100112 convert into decimal number (9 marks)

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EE/APR 2009/ECE590/KJE609/KJE416

QUESTION 4 a) Figure Q4(a) shows a logic circuit which has three inputs A, B, C and two outputs X andY. i) ii) Obtain the simplified sum-of-products (SOP) logic expression for the output X andY. Implement the full logic circuit using only active high outputs 3-to-8 decoder and OR gates.

Figure Q4(a) (8 marks) b) Design a synchronous counter that produces the following repeating counting sequence :- 4,5,3,6,7,0,... using JK flip-flop(s) and necessary logic gate(s). (12 marks)

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EE/APR 2009/ECE590/KJE609/KJE416

QUESTION 5 a) Explain the function(s) of the components of a Central Processing Unit (CPU) below. i) ii) b) General Registers Arithmetic and Logical Unit (ALU) (4 marks) Analyze the following programs. Determine the results of each of these instructions. i) MOVE.B ADD.B MOVEA.L MOVE.W ROL.W MOVE.W MOVE.B MOVE.B OR.B MOVE.B #$97, D2 #$3A, D2 #$4000, A0 #$AB12, DO #5, DO DO, (A0) #$35, D3 #$04, D4 D4, D3 D3, $5000 (8 marks) c) Figure Q5(c) shows the MC68230 Pl/T connection to a 7-segment display unit. Draw the flowchart and write a MC68000 CPU assembly language program that will display the number "8", when BOTH switches SW1 and SW2 are pressed. All other states of SW1 and SW2 cause the display to show number "0".

ii)

PA0-PA3 MC68230 P!/T

BCD to L \
7-sagmant I Decoder

1
*

rV

+5V %SW1 SW2

Grid Figure Q5(c) (8 marks)

END OF QUESTION PAPER

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APPENDIX 1 (1)

EE/APR2009/ECE590/KJE609/KJE416

Motorola MC68000 CPU Instruction Set

Assembler Syntax Dx,Dy - (Ax) , - (Ay) Dn,<ea> <ea>,Dn <ea>,An #x,<ea> #<l-8>,<ea> Dy,Dx - (Ay) ,-(Ax) <ea>,Dn Dn,<ea> #<data>,<ea> #<l-8>,Dy Dx,Dy <ea> .. . CCS <label> Bcc.W <label> Dn,<ea> #<data>,<ea> Data Size Condition codes X N Z V C

Instruction Description ABCD

Add BCD with extend ADD binary ADD ADD ADD ADD
binary to An Immediate 3-bit immediate extended

B-BWL -WL BWL BWL BWL BWL BWL BWL

* U * U * * * * * *

ADD
ADDA ADD I ADDQ ADDX AND ANDI ASL

* * * * * * * * * * * * * * * - * * 0 0 - * * 0 0 * * * * *

Bit-wise AND Bit-wise AND with Immediate Arithmetic Shift Left

ASR Bcc BCHG BCLR BSET BSR BTST CHK CLR CMP CMPA CMPI CMPM DBcc DIVS DIVU EOR EORI EXG EXT ILLEGAL JMP JSR LEA LINK LSL LSR MOVE MOVE MOVE

Arithmetic Shift Right Conditional Branch Test a Bit and CHanGe Test a Bit and CLeaR Test a Bit and SET Branch to SubRoutine Bit TeST CHecK Dn Against Bounds

BWL BWB-L

* * * * *

CLeaR CoMPare CoMPare Address CoMPare Immediate CoMPare Memory Looping Instruction Divide Signed Divide Unsigned Exclusive OR Exclusive OR Immediate Dn Exchange any two registers on ILLEGAL Sign EXTend <ea> ILLEGAL-Instruction Excepti <ea> JuMP to Affective Address <ea>,An --L Jump to SubRoutine An,#<displacement> Load Effective Address Dx,Dy BWL Allocate Stack Frame #<l-8>,Dy Logical Shift Left <ea> Logical Shift Right Between Effective Addresses i To CCR To SR .. . <ea>,<ea> <ea>,CCR <ea>,SR

BSR.S <label> BSR.W <label> Dn,<ea> #<data>,<ea> <ea>,Dn <ea> <ea>,Dn <ea>,An #<data>,<ea> (Ay)+,(Ax)+ DBcc Dn,<label> <ea>,Dn <ea>,Dn Dn,<ea> #<data>,<ea> Rx,Ry

B-L B-L BWB-L -WBWL BWL -WL BWL BWL -W-W-WBWL BWL --L -WL _ -

_ * _ _ * _

* 0 * * * * * * * *

uuu
1 * * * * * * * * 0 * * * * * * 0 0 0 * * * * 0 0 0 0

* * 0 0

BWL BWL -W-W-

* * * o *
* * 0 0

I I I I I I I I I I

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APPENDIX 1(2)

EE/APR2009/ECE590/KJE609/KJE416

MOVE MOVE MOVEA MOVEM MOVEP MOVEQ MULS MULU NBCD NEG NEGX NOP NOT OR ORI PEA RESET ROL

ROR ROXL ROXR RTE RTR RTS SBCD Sec STOP SUB SUBA SUB I SUBQ SUBX SWAP TAS TRAP TRAPV TST UNLK Symbol * 0 1 U I

SR,<ea> USP,An An,USP MOVE Address <ea>,An MOVE Multiple <regis ter list>,<ea> <ea>,< register list> MOVE Peripheral Dn,x(An) x(An),Dn MOVE 8-bit immediate #< -128.+127>,Dn MULtiply Signed <ea>,Dn MULtiply Unsigned <ea>,Dn Negate BCD <ea> NEGate <ea> NEGate with extend <ea> No operation NOP Form one's complement <ea> Bit-wise OR <ea>,Dn Dn,<ea> Bit-wise OR with Immediate #<data>,<ea> Push Effective Address <ea> RESET all external devices RESET Rotate Left #<l-8>,Dy Dx,Dy <ea> Rotate Right ROtate Left with extend Rotate Right with extend ReTurn from Exception RTE ReTurn and Restore RTR ReTurn from Subroutine RTS Subtract BCD with extend Dx,Dy -(Ax),-(Ay) Set to -1 if True, 0 if False <ea> Enable & wait for interrupts #<data> SUBtract binary Dn,<ea> <ea>,Dn SUBtract binary from An <ea>,An SUBtract Immediate #x,<ea> SUBtract 3-bit immediate #<data>,<ea> SUBtract extended Dy,Dx - (Ay) , - (Ax) Dn SWAP words of Dn <ea> Test & Set MSB & Set N/Z-bits #<vector> Execute TRAP Exception TRAPV TRAPV Exception if V-bit Set <ea> TeST for negative or zero An Deallocate Stack Frame From SR USP to/from Address Register Meaning Set according to result of operation Not affected Cleared Set Outcome (state after operation) undefined Set by immediate data

-W--L -WL -WL -WL --L -W0 0 * * 0 0 * * 0 0 U * u *

-wB-BWL BWL BWL BWL BWL --L BWL

* * 0 0 - * * 0 0 - * * 0 0 - * * 0 * _ * * I I * * * I I

BWL BWL BWL

* * * I I

0 * 0 * 0 * II II

B-B-BWL
-WT,

* U

* u*

I I III * * * * *

BWL BWL BWL -W-

* * * * * * * * * * * * * * * - * * 0 0 - * * 0 0

BWL

0 0

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APPENDIX 1 (3)

EE/APR2009/ECE590/KJE609/KJE416

<ea> <data> <label> <vector> <rg.lst> <displ.>

Effective Address Operand Immediate data Assembler label TRAP instruction Exception vector (0-15) MOVEM instruction register specification list LINK instruction negative displacement Same as previous instruction

Addressing Modes Data Register Direct Address Register Direct Address Register Indirect Address Register Indirect with Post-Increment Address Register Indirect with Pre-Decrement Address Register Indirect with Displacement Address Register Indirect with Index Absolute Short Absolute Long Program Counter with Displacement Program Counter with Index Immediate Status Register Condition Code Register Legend Dn An b w 1 x Rx

Syntax Dn An (An) (An) + -(An) w(An) b(An,Rx) w 1 w(PC) b(PC,Rx) #x SR CCR

Data Register (n is 0-7) Address Register (n is 0-7) 08-bit constant 16-bit constant 32-bit constant 8-, 16-, 32-bit constant Index Register Specification, one of: Dn.W Low 16 bits of Data Register Dn.L All 32 bits of Data Register An.W Low 16 bits of Address Register An.L All 32 bits of Address Register Condition Codes for Bcc, DBcc and Sec Instructions. Condition Codes set after CMP D0,D1 Instruction.

Relationship Dl < DO Dl <= DO Dl = DO Dl 1 - DO Clear! ) Dl > DO Dl >= DO

Unsigned CS LS EQ NE Carry Bit Set Lower or Same Equal (Z-bit Set) Not Equal (Z-bit Clear)

Signed LT LE EQ NE Less Than Less than or Equal Equal (Z-bit Set) Not Equal (Z-bit

HI - Higher than CC - Carry Bit Clear PL - PLus (N-bit Clear) VC - V-bit Clear (No Overflow) RA - BRanch Always

GT - Greater Than GE - Greater than or Equal Ml - Minus (N-bit Set) VS - V-bit Set (Overflow)

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APPENDIX 1 (4)

EE/APR2009/ECE590/KJE609/KJE416

DBcc Only

F - Never Terminate (DBRA is an alternate to DBF) T - Always Terminate SF ST Never Set Always Set

Sec Only

Partial MC68000 Pl/T registers Register Port General Control Register Port A Data Direction Register Port B Data Direction Register Port C Data Direction Register Port A Control Register Port B Control Register Port A Data Register Port B Data Register Port C Data Register Abbreviation PGCR PADDR PBDDR PCDDR PACR PBCR PADR PBDR PCDR

The PGCR Control format

be MODE b5
H34

b4
H12

b3
H4

b2
H3

b1
H2

bO
H1

OO: M o d e O Unidirectional 8 bits 0 1 : M o d e 1 i= Unidirectional 1 6 bits 1 0 : M o d e 2 c= Bidirectional 8 bits 1 1 : M o d e 3 = Bidirectional 16 bits

(Ports a n d bits individually programmable) (Ports A a n d B a r e together input or output) ( E a c h port input for r e a d a n d output for write) (Ports A a n d B are together input for r e a d a n d output for write)

O: Low active 1: High active Disable H 3 4 / H 1 2 Enable H 3 4 / H 1 2

The PACR Control format

b7"

b 6

t>S

b**

b1

f=ACR

S U B M O D E

H2

C O N T R O L

H2 INT

H1 S V C

H1 STAT

OO: S u b m o d e l O Double-buffered input 01: Submode 1 Double-buffered output I X : Bit I/O

OXX: H 2

input

100: H 2 output negated 101 : H 2 output asserted

1f

Specifies

O: H 1 i n t e r r u p t a n d DIvlA. r e q u e s t disabled 1 : Enable disable enable

110: H 2 handshake mode 11-1: H 2 p u l s e mode

O : 1H 2 i n t e r r u p t 1 : 1 2 interrupt H

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