Khoa CNTT

Bo mon Ky thuat May tnh

Pham Tng Hai oan Minh Vng Phan nh The Duy

Ti liu tham kho

Digital Logic Design Principles, N. Balabanian & B. Carlson John Wiley & Sons Inc., 2004 Digital Design, 3rd Edition, J.F. Wakerly, Prentice Hall, 2001 Digital Systems, 5th Edition, R.J. Tocci, Prentice Hall, 1991

Logic Design 1 - Chapter 4

Chng 4.

Logic Design 1 - Chapter 4

Dn nhp
Mch s c cc ng ra ch ph thuc vo gi tr/trng thi ca cc ng vo thi im hin hnh c gi l mch lun l t hp (combinational logic circuits) hay gi tt l mch t hp C th c nhiu mch t hp c thit k p ng cng 1 chc nng ra. Cc mch s ny c nh gi (nhm la chn mch no thch hp hn) da trn nhiu yu t khc nhau.
Tc hot ng phc tp Gi thnh phn cng Nng lng tiu tn S p ng v mt linh kin

Thit k ch trng tng yu t ny c th dn n s gim st yu t khc

Logic Design 1 - Chapter 4

Mch cng nh phn

Mch thc hin tc v cng i vi 2 gi tr nh phn Hiu sut ca mch nh gi theo tc thc hin php ton
C th da trn cc cng lun l ch to theo cng ngh thin v tc Tc c th tng ng k ty theo cch thit k mch m khng qu ph thuc vo cng ngh ch to cng lun l

Cn nhc la chn gia thit k u tin cho tc v thit k thin u tin cho chi ph phn cng S khi ca mch cng nh phn

Binary Adder

S
n+1

Logic Design 1 - Chapter 4

Mch cng (MC) ton phn

C th xy dng mch cng 2 s nh phn n-bit t cc mch cng nh phn 1-bit S khi ca mch cng ton phn (full adder) Bng s tht Ba Karnaugh
Ci yi 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 xi 0 1 0 1 0 1 0 1 Si 0 1 1 0 1 0 0 1 Ci+
1

xi

Si

yi

Full Adder
Ci

Ci+1

Si
Ci 0 1

yi xi 00 01 11 10 1 1 1 1

Dng hm ca cc ng ra
Si = xi yi Ci + xi yi Ci + xi yi Ci + xi yi Ci = xi yi Ci

0 0 0 1 0 1 1 1

Ci+1
Ci 0 1

yi xi 00 01 11 10 1 1 1 1

Ci+1 = xi yi + xi Ci + yi Ci = xi yi + Ci (xi + yi) = xi yi + Ci (xi yi + xi yi) = xi yi + Ci (xi yi)

Logic Design 1 - Chapter 4

MC bn phn v MC ripple-carry
Mch cng ton phn Si = xi yi Ci Ci+1 = xi yi + Ci (xi yi) Mch cng bn phn (half adder)
xi Si

Ci xi yi Si Ci+1

Mch cng ripple-carry

S3
Full Adder

B3 C3

B2 C2

B1 C1

Half Adder

Full Adder

Full Adder

yi

Half Adder

S2 A3 A2

S1 A1

S0 A0 B0

Ci+1

xi yi

Si Ci+1

C4

Gii hn do thi gian tr ca cc tn hiu carry !

7

Logic Design 1 - Chapter 4

Mch cng Carry-Lookahead

Tnh carry t cc bit ca ton hng A, B v Co nh ngha
Generated Carry Gi = Ai Bi Propagated Carry Pi = Ai Bi

C4 =

G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0 + P3 P3 P1 P0 C0

G3 G2 P3 G1 P2 P3 G0 P1 P2

Ta tnh c
Ci = = = = Ai-1 Bi-1 + Ci-1 (Ai-1 Bi-1) Gi-1 + Pi-1 Ci-1 Gi-1 + Pi-1 (Gi-2 + Pi-2 Ci-2) Gi-1 + Pi-1 Gi-2 + Pi-1 Pi-2 Ci-2

C4

Tnh ln lt
C1 = G0 + P0 C0 C2 = G1 + P1 G0 + P1 P0 C0 C3 = G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 C0
Logic Design 1 - Chapter 4

P3 C0 P0 P1 P2 P3

Mch cng Carry-Lookahead

Tng qut Ci+1 = Gi + Pi Gi-1 + Pi Pi-1 Gi-2 + Pi Pi-1 Pi-2 Gi-3 + + Pi Pi-1 Pi-2 P1 G0 + Pi Pi-1 Pi-2 P1 P0 C0 Mch cng Carry-Lookahead
C0 A0 B0 A1 B1 A2 B2 A3 B3 P0 G0 P1 G1 P2 G2 P3 G3 P1 P2 P3 S0

Carry-Lookahead

C1 C2 C3

S1 S2 S3 C4

Logic Design 1 - Chapter 4

Mch tr nh phn
Biu din s nguyn m nh phn di dng b 2 Mch cng 2 s di dng b 2 c khc g so vi mch cng nh phn xem xt ? Mch tr c thay th bng mch chuyn i b 2 v mch cng
B3 B2 B1 B0 M

A3 C4 C3

A2 C2

A1 C1

A0

S3

S2

S1

S0

Overflow

Logic Design 1 - Chapter 4

10

B dn knh
D liu sinh ra v tr A nhng c s dng v tr B
truyn d liu t A n B qua knh truyn thng

Lm sao c th truyn d liu t nhiu ngun khc nhau trn cng mt knh truyn duy nht ?
Demultiplexer

Multiplexer

communication channel

data in

data out

C ch cho php chn d liu no truyn trn knh truyn gi l k thut dn knh (multiplexing) Thit b thc hin dn knh gi l b dn knh (multiplexer) Pha thu, u bn kia ca knh truyn thng, cn b phn knh (demultiplexer) phn phi d liu trn knh truyn n cc ng ra
Logic Design 1 - Chapter 4 11

B dn knh
B dn knh s l mch c
2n ng d liu vo 1 ng d liu ra n ng vo select hay selector
D0 D1 D2 D3 D4 r

B dn knh vi n = 3

D0 D2 D3 D4 D5 D6 D7 s0 s1 s2

Multiplexer

D1

D5
r

D6 D7 s0 s1 s2

Logic Design 1 - Chapter 4

12

Xy dng mch t hp t b dn knh

Tn ti cc mch dn knh c thng mi ha di dng MSI Dng b dn knh hin thc 1 mch t hp bt k ? B dn knh c dng 2 lp AND-OR
Cng AND c n+1 ng nhp Dng s-o-p chnh tc ca 1 hm chuyn mch n+1 bin

Th d
f (x, y, z) = (1, 2, 4, 7) = z y x + z y x + z y x + z y x gn s0 = y v

s1 = z

f = s1 s0 x + s1 s0 x + s1 s0 x + s1 s0 x = s1 s0 D0 + s1 s0 D1 + s1 s0 D2 + s1 s0 D3 suy ra D0 = D3 = x v D1 = D2 = x V mch ?

B dn knh m-1 selector c th c s dng hin thc mch t hp ca hm m bin

Th d
f (w, x, y, z) = (0, 4, 9, 13, 14) Thit k ? V mch ?
13

Logic Design 1 - Chapter 4

B gii m B m ha
Mch t hp nhn n ng nhp (n 1) v nh tuyn d liu t cc ng nhp n mt trong s ti a 2n ng ra gi l b gii m (decoder) B m ha (encoder), mch ngc li vi b gii m, l mch nhn d liu t mt s rt ln cc ng nhp ri bin i thnh d liu xut ra trn mt s nh hn cc ng xut (khng nht thit ch 1 ng xut) C s gn ging gia
B m ha vi b dn knh B gii m vi b phn knh Hy ch ra s khc bit gia cc mch trn ?

Logic Design 1 - Chapter 4

14

B phn knh
B phn knh vi 8 ng xut
Mch lun l Bng s tht
Control inputs
Datainput x D0

D1

Data outputs

C2 0 0 0 0 1 1 1 1

C1 0 0 1 1 0 0 1 1

C0 0 1 0 1 0 1 0 1

D0 x 0 0 0 0 0 0 0

D1 0 x 0 0 0 0 0 0

D2 0 0 x 0 0 0 0 0

D3 0 0 0 x 0 0 0 0

D4 0 0 0 0 x 0 0 0

D5 0 0 0 0 0 x 0 0

D6 0 0 0 0 0 0 x 0

D7 0 0 0 0 0 0 0 x
C0 C1 C2

D2

D3

D4

D5

D6

D7

Logic Design 1 - Chapter 4

15

B gii m ng n ra 2n
B gii m ng n ra 2n (n-to-2n line decoder) c xy dng t b phn knh 2n ng xut bng cch:
B bt ng nhp d liu x Mi cng AND ch cn li n ng nhp

B gii m ng 3 ra 8
Control inputs
D0

Data outputs D0 1 0 0 0 0 0 0 0 D1 0 1 0 0 0 0 0 0 D2 0 0 1 0 0 0 0 0 D3 0 0 0 1 0 0 0 0 D4 0 0 0 0 1 0 0 0 D5 0 0 0 0 0 1 0 0 D6 0 0 0 0 0 0 1 0 D7 0 0 0 0 0 0 0 1
16

C2 0 0 0 0 1 1 1 1

C1 0 0 1 1 0 0 1 1

C0 0 1 0 1 0 1 0 1

Decoder 3x8

s0 s1 s2

D1 D2 D3 D4 D5 D6 D7

Logic Design 1 - Chapter 4

B gii m ng n ra 2n
MSI gii m ng thng dng
2 4 , 3 8 , 4 16

Gii m ma trn cng AND Gii m cy Xy dng mch t hp t cc b gii m ng

74LS139
A1a A0a Ea A1b A0b Eb Q3a Q2a Q1a Q0a Q3b Q2b Q1b Q0b

74LS154
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

74LS138
A2 A1 A0 E3 E2 E1 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0

E1 E0 A3 A2 A1 A0

Logic Design 1 - Chapter 4

17

Bi tp
Problem Problem Problem Problem Problem 4.4 4.7 4.10 4.11 4.12

Thy

Phan nh Th Duy
duypdt@cse.hcmut.edu.vn

Logic Design 1 - Chapter 4

18