Sequential Circuits

Introduction- Latches & Flip Flops

Combinational Circuit o/p levels at any instant of time depends only on the i/p levels at that instant

Absence of Memory

Intro of memory element Time has been introduced logic operations performed sequentially- info stored in memory location and released at particular pt of time

Sequentially operated circuits

Behavior defn at discrete intervals of time

Behavior changes at any instant of time

Synchronous

Asynchronous

Control Signal

Change when control applied speed depends upon control i/p ????

G1

Q
Stable

G2

Metastable

VG1(OUT) VG2(IN) VG1(IN)

Bistable Element

VG2(OUT)

SR- Latch

11010 S

G1

Q 001 S
1 1 Q 110 1

R
0 1 1 1

Q
0 0 1 1

Q
1 1 0 0

01110 R

G2

0 1

Undesirable State

Function Table
S
0 0

R
1 0 0 0

Q
0 0 1 1

Q
1 1 0 0

Q S

1 0

Undesirable State

S
1 1 0 0 0 0 1

R
0 0 0 0 1 1 1

QP
0 1 0 1 0 1 X

Qp
1 0 1 0 1 0 X

Q
1 1 0 1 0 0 U

Q
0 0 1 0 1 1 U

QP 0 0 1 1

Q 0 1 0 1

S 0 1 0 X

R X 0 1 0

Steering Table

S 1 G1

C 1 0 Q

R 1
R

G2

Controlled SR Latch

S 1

R 0

Q 0

Q 1

1
0 1 0

1
1 1 0

0
1 1 1

1
0 0 1 C 0 1 1 1 1 S X 0 0 1 1 R X 0 1 0 1 S X 1 1 0 0 R X 1 0 1 0 Q QP QP 0 1 U Q QP QP 1 0 U

S
C

D-Latch

D 01 S 1 C

10 G1 01 Q

R 10

01

G2 10

D 0 1

Q 0 1

Q 1 0

C 1 1
0

D 0 1
X

Q 0 1
Qp

Q 1 0
QP

Characteristic Table
C 1 1 0 D 0 1 X Q 0 1 Qp Q 1 0 QP D 0 1 Q(t+1) 0 1

Sequential Circuits
Latches & Flip Flops

Intro of memory element Time has been introduced logic operations performed sequentially- info stored in memory location and released at particular pt of time

Sequentially operated circuits

Behavior defn at discrete intervals of time

Behavior changes at any instant of time

Synchronous

Asynchronous

Control Signal

S
C

D-Flip Flop

i/p

o/p

Set-up Hold

Q1 Q2

D
G 1 C Q

D G 1 Q

G 2

G 2

J K -Flip Flop

J C K

Q J K 0 1 0 1 Q(t+1) Q(t) 0 1 Q(t)

Characteristic Table

0 0 1 1

J
0 0 0 0 1

K
0 0 1 1 0

Qt
0 1 0 1 0

Q(t+1)
0 1 0 0 1
JK Qt 00 01 11 1 10 1 1 1

1
1 1

0
1 1

1
0 1

1
1 0 D = JQ + KQ

J K

Q
J 0 0 K 0 1 0 1 Q(t+1) Q(t) 0 1 Q(t)

Characteristic Table

1 1

T-Flip Flop

Q T Q(t+1) Q(t) Q(t)

Characteristic Table

0 1

J C K

Characteristic Table
T Q(t+1)

0
1

Q(t)
Q(t)

T 0 0 1

Q 0 1 0

Q(t+1) 0 1 1

D = TQ + TQ D=TQ

0 D Q

Reset - Clear

Preset -Set

Asynch or Direct Inputs

Sequential Circuits
Registers

Clocked Sequential Circuits group of FFs and Combinational Gates

Storage

Goes a set of predetermined states

Registers

Counters

Counters a specail type of registers

1 bit data
1 nibble

1 D FF
- 4 D FFs

CLK I0

CLR D C R Q Q

I1

D C R

Q Q

Parallel Load

I2

D C R

Q Q

I3

D C R

Q Q

CLK LOAD

CLR D
C R

Q Q

I0
D I1

Q R Q

D C I2 D C I3 R R

Q Q

Q Q

Shift Registers
Cascade of FFs in a single IC package Data shift left- to right right to left

Q R Q

D C

Q R Q

D C

Q R Q

D C

Q R Q

CLK CLR

C D Q1 Q2 Q3 Q4

SIPO SISO PISO PIPO

Single Rail Double Rail

Types
Unidirectional Bidirectional Universal

Universal Shift Registers

SISO

SIPO
PISO

PIPO
Shift Left

Shift Right
Clear

Control

S1
0 0 1

S0
0 1 0 No Change Shift Right Shift Left

Parallel load

Sequential Circuits
Registers

Clocked Sequential Circuits group of FFs and Combinational Gates

Storage

Goes a set of predetermined states

Registers

Counters

Counters a specail type of registers

CLK LOAD

CLR D
C R

Q Q

I0
D I1

Q R Q

D C I2 D C I3 R R

Q Q

Q Q

Shift Registers
Cascade of FFs in a single IC package Data shift left- to right right to left

Q R Q

D C

Q R Q

D C

Q R Q

D C

Q R Q

CLK CLR

C D Q1 Q2 Q3 Q4

SIPO SISO PISO PIPO

Single Rail Double Rail

Types
Unidirectional Bidirectional Universal

Universal Shift Registers

SISO

SIPO
PISO

PIPO
Shift Left

Shift Right
Clear

Control

S1
0 0 1

S0
0 1 0 No Change Shift Right Shift Left

Parallel load

CLK CLR

D C

Q R Q

D C

Q R Q

D C

Q R Q

D C

Q R Q

s1 s0

4X1

4X1

4X1

4X1

I3

SR

I2

I1

I0 SL

SI

Reg A

SO

SI

Reg B

SO

CLK CONTROL

Serial Transfer

Timing
Initial T1

SA
1011 1101

SB
0010 1001

T2
T3 T4

1110
0111 1011

1100
0110 1011

SI CN CL

x3 1 0

x2 0 1

x1 1 0

x0 0 1
10

A B

S 01

FA
Ci+1

10

LOAD

Ci

SI

y3

y2

y1

y0

CN CL

1 0

0 1

0 1

0 1

CN CL

Counters - Ripple

Follow a particular sequence Sequence - Binary Binary Ripple counter 2- bit counter counts from 0 -3 N-bit counter counts from 0 2n-1

1 CLK

T C

T C A0

A1

CLK 0 1 0 1 0

2-binary up counter

1 CLK

T C

Q Q A0

T C

Q Q A1

CLK

T CLK C

T C

T C

T C

T C

Ripple counter Asynchronous counter as they do not have a common clock

Sequential Circuits
Counters

Clocked Sequential Circuits group of FFs and Combinational Gates

Storage

Goes a set of predetermined states

Registers

Counters

Counters a special type of registers

Counters - Ripple

Follow a particular sequence Sequence - Binary Binary Ripple counter 2- bit counter counts from 0 -3 N-bit counter counts from 0 2n-1

T CLK C

T C

T C

T C

T C

Ripple counter Asynchronous counter as they do not have a common clock

Counters -Synchronous

Follow a particular sequence Sequence - Binary Binary Synchronous counter 2- bit counter counts from 0 -3 N-bit counter counts from 0 2n-1 Clk common to all Flip Flops

Present State QC 0 0
0 0 1 1 1 1

Next State QC 0 0
0 1 1 1 1 0

Input QA 1 0
1 0 1 0 1 0

QB 0 0
1 1 0 0 1 1

QA 0 1
0 1 0 1 0 1

QB 0 1
1 0 0 1 1 0

TC 0 0
0 1 0 0 0 1

TB 0 1
0 1 0 1 0 1

TA 1 1
1 1 1 1 1 1

TB

TC

1
TB = QA TC = QBQA

00
01

1
1

00
01 1

11
10

1
1

11
10

T C

T C

T C

CLK QA QB QC

DIR

CLK T C Q Q

T
C

Q Q

T C

Q Q

Mod 8 counter 3-bit counter Mod N counter goes through n sequences Sequence need not be binary

Design
110

000

001

101 100

010

State Diagram

Present C 0 B 0 A 0

Next C 0 B 0 A 1

0 0
1 1 1

0 1
0 0 1

1 0
0 1 0

0 1
1 1 0

1 0
0 1 0

0 0
1 0 0

111

000

110

001

101 100

010 011

State Diagram

J
0 0 0 0 1

K
0 0 1 1 0

Qt
0 1 0 1 0

Q(t+1)
0 1 0 0 1 Qt 0 0 1 1 Q(t+1) 0 1 0 1 J 0 1 X X K X X 1 0

1
1 1

0
1 1

1
0 1

1
1 0

State Table
Present C B A Next C B A Input Inputs JC KC JB KB JA KA

0 0
0 1 1 1 0 1

0 0
1 0 0 1 1 1

0 1
0 0 1 0 1 1

0 0
1 1 1 0 1 0

0 1
0 0 1 0 0 0

1 0
0 1 0 0 0 0

0 0
1 X X X 1 X

X X
X 0 0 1 X 1

0 1
X 0 1 X X X

X X
1 X X 1 1 1

1 X
0 1 X 0 X X

X 1
X X 1 X 1 1

JA
00 01 11 10

0
1 0 0 1

1
X X X X

JB

00
01

0
X

1
X

JC
00 01 11 10

0
0 1 X 0

1
X 1 X X

11
10

X
0

X
1

JA = QB
KC 0 1 00 X 0 01 X 0 11 X 1

JB = QA
10 X 1

JC = QB

Input Equations/

Excitation Equations

KC = QB

J C K

J C

J C A

K 1

CLK

Design a Synchronous BCD counter

Present
Q8 Q4 Q2 Q1 Q8

Next
Q4 Q2 Q1 T8

Inputs
T4 T2 T1

0 0 0

0 0 0

0 0 1

0 1 0

0 0 0

0 0 0

0 1 1

1 0 1

0 0 0

0 0 0

0 1 0

1 1 1

0
0 0 0 0 1 1

0
1 1 1 1 0 0

1
0 0 1 1 0 0

1
0 1 0 1 0 1

0
0 0 0 1 1 0

1
1 1 1 0 0 0

0
0 1 1 0 0 0

0
1 0 1 0 1 0

0
0 0 0 1 0 1

1
0 0 0 1 0 0

1
0 1 0 1 0 0

1
1 1 1 1 1 1

T8 00 01 11 10

00

01

11

10

T4 00

00

01

11 1 1

10

1 X X 1 X X X X

01 11 10 X X

X X

X X 10

T2
T8 = Q8 Q1 + Q4 Q2 Q1 T4 = Q2 Q1 T2 = Q8 Q1 T1 = 1 00 01 11 10

00

01 1 1

11 1 1 X X

X X

T1 = 1 T2 = Q8 Q1 T4 = Q2 Q1 T8 = Q8 Q1 + Q4 Q2 Q1

Sequential Circuits
Counters

Clocked Sequential Circuits group of FFs and Combinational Gates

Storage

Goes a set of predetermined states

Registers

Counters

Counters a special type of registers

T CLK C

T C

T C

T C

T C

Ripple counter Asynchronous counter as they do not have a common clock

Counters -Synchronous

Follow a particular sequence Sequence - Binary Binary Synchronous counter 2- bit counter counts from 0 -3 N-bit counter counts from 0 2n-1 Clk common to all Flip Flops

DIR

CLK T C Q Q

T
C

Q Q

T C

Q Q

Mod 8 counter 3-bit counter Mod N counter goes through n sequences Sequence need not be binary

Design a Synchronous BCD counter

Present
Q8 Q4 Q2 Q1 Q8

Next
Q4 Q2 Q1 T8

Inputs
T4 T2 T1

0 0 0 0 0

0 0 0 0 1

0 0 1 1 0

0 1 0 1 0

0 0 0 0 0

0 0 0 1 1

0 1 1 0 0

1 0 1 0 1

0 0 0 0 0

0 0 0 1 0

0 1 0 1 0

1 1 1 1 1

0
0 0 1 1

1
1 1 0 0

0
1 1 0 0

1
0 1 0 1

0
0 1 1 0

1
1 0 0 0

1
1 0 0 0

0
1 0 1 0

0
0 1 0 1

0
0 1 0 0

1
0 1 0 0

1
1 1 1 1

T8 00 01 11 10

00

01

11

10

T4 00

00

01

11 1 1

10

1 X X 1 X X X X

01 11 10 X X

X X

X X 10

T2
T8 = Q8 Q1 + Q4 Q2 Q1 T4 = Q2 Q1 T2 = Q8 Q1 T1 = 1 00 01 11 10

00

01 1 1

11 1 1 X X

X X

T1 = 1 T2 = Q8 Q1 T4 = Q2 Q1 T8 = Q8 Q1 + Q4 Q2 Q1

Present Q8 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Q4 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Q2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Q1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Q8 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0

Next Q4 Q2 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 Q1 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 T8 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1

Inputs T4 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 1 T2 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 T1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1

T1 = Q8 + Q1 + Q4 Q2 T2 = Q8 Q1 + Q8 Q2 T4 = Q8 Q4 + Q8 Q2 Q1 T8 = Q8 Q4 + Q8 Q2 + Q8 Q1 + Q4 Q2 Q1

Design a BCD Ripple counter

Outputs
Q8 Q4 Q2 Q1

J1 = K1 = 1 J2 = Q8 K2 = 1 J3 = K3 = 1

0 0 0

0 0 0

0 0 1

0 1 0

0
0 0 0 0 1 1

0
1 1 1 1 0 0

1
0 0 1 1 0 0

1
0 1 0 1 0 1

J4 = Q4 Q2 K4 = 1

COUNT J CLK C K Q Q1 J C Q Q2 J A C K Q Q4 J C Q Q8

BCD COUNTER

COUNT

BCD COUNTER

COUNT

BCD COUNTER

COUNT

Three Decade Counter

Design a 4-bit ring counter

Design

1000

0001

0100

0010

DeBruijn

State Diagram

Present State QD Qc 1 0

Next State QB QA JD 0 0 X KD JC 1 1

Inputs KC JB X 0 KB JA X 0 KA X

QB QA QD Qc 0 0 0 1

0
0 0

1
0 0

0
1 0

0
0 1

0
0 1

0
0 0

1
0 0

0
1 0

0
0 1

X
X X

X
0 0

1
X X

1
X 0

X
1 X

0
1 X

X
X 1

JD 00 01 11 10

00 X 0 X X

01 1 X X X

11 X X X X

10 0 X X X

JC 00

00 X

01 0

11 X

10 0

01 11
10

X X
1

X X
X

X X
X

X X
X

JD = QA

JC = QD

JB 00 01 11 10

00 X 1 X 0

01 0 X X X

11 X X X X

10 X X X X

JA 00

00 X

01 X

11 X

10 1

01 11
10

0 X
0

X X
X

X X
X

X X
X

JB= QC

JA = QB

1 J C K Q QD J C Q QC

J
A C K

QB

J C

QA

CLK

Sequential Circuits
Counters

Clocked Sequential Circuits group of FFs and Combinational Gates

Storage

Goes a set of predetermined states

Registers

Counters

Counters a special type of registers

T CLK C

T C

T C

T C

T C

Ripple counter Asynchronous counter as they do not have a common clock

Counters -Synchronous

Follow a particular sequence Sequence - Binary Binary Synchronous counter 2- bit counter counts from 0 -3 N-bit counter counts from 0 2n-1 Clk common to all Flip Flops

DIR

CLK T C Q Q

T
C

Q Q

T C

Q Q

Mod 8 counter 3-bit counter Mod N counter goes through n sequences Sequence need not be binary

Design a 4-bit ring counter

Design

1000

0001

0100

0010

DeBruijn

State Diagram

Present State QD Qc 1 0

Next State QB QA JD 0 0 X KD JC 1 1

Inputs KC JB X 0 KB JA X 0 KA X

QB QA QD Qc 0 0 0 1

0
0 0

1
0 0

0
1 0

0
0 1

0
0 1

0
0 0

1
0 0

0
1 0

0
0 1

X
X X

X
0 0

1
X X

1
X 0

X
1 X

0
1 X

X
X 1

JD 00 01 11 10

00 X 0 X X

01 1 X X X

11 X X X X

10 0 X X X

JC 00

00 X

01 0

11 X

10 0

01 11
10

X X
1

X X
X

X X
X

X X
X

JD = QA

JC = QD

JB 00 01 11 10

00 X 1 X 0

01 0 X X X

11 X X X X

10 X X X X

JA 00

00 X

01 X

11 X

10 1

01 11
10

0 X
0

X X
X

X X
X

X X
X

JB= QC

JA = QB

1 J C K Q QD J C Q QC

J
A C K

QB

J C

QA

CLK

QD

QC

QB

QA

O0

O1 S1

O2

O3

MUX
S0

CLK

2-BIT COUNTER

QD

D C

QC

D A C

QB

D C

QA

Q CLK Present C 0 1 1 1 0 0 B 0 0 1 1 1 0 A 0 0 0 1 1 1 C 1 1 1 0 0 0

Q
Next B 0 1 1 1 0 0 A 0 0 1 1 1 0

Design a Counter with Load

Clear

CLK

Load

Count

Func

0
1 1

X
1 0

X
X 1

Clear all FFs

Load all FFs Count

No Change

Present State QB 0 0 1 1 QA 0 1 0 1

Next State QB 0 1 1 0 QA 1 0 1 0 JB 0 1 X X

Inputs KB X X 0 1 JA 1 X 1 X KA X 1 X 1

J C K R

J C

CLK CLEAR

Load 0 0 1 1

Count 0 1 0 1

J1 0 Q0 I1 I1

K1 0 Q0 I1 I1

J0 0 Q0 I0 I0

K0 0 Q0 I0 I0

J0 = Load.I0 + Load.Count K0 = Load.I0 + Load.Count J1 = Load.I1 + Load.Count.Q0 k1 = Load.I1 + Load.Count.Q0

State Reduction
Reduce no of states

Should not affect i/p o/p relationship

Can be done only when internal states not important

Two states are equivalent Same o/p Set of i/ps go to same or equivalent set

0/0 0/0 a 0/0

1/0 0/0 b

c 1/0 e 0/0

g 1/1
0/0

1/0 d 1/1 f 1/1

0/0 1/1

01010110100

Present

Next

Output

x=0
a b c a c a

x=1
b d d

x=0
0 0 0

x=1
0 0 0

d
e f g

e
a g e a

d f
d f f f

0
0 0 0

1
1 1 1

0/0 0/0 e 1/1 0/0 a 0/0

1/0 0/0 b 1/0 d 1/1

State
a b c d e

Assign1
000 001 010 011 100

Assign2
000 001 011 010 110

Assign3
00001 00010 00100 01000 10000

Sequential Circuits
Counters

Clocked Sequential Circuits group of FFs and Combinational Gates

Sequential Circuits
Design

Models Moore & Mealy

Moore o/p depends only on the present state

Mealy o/p depends on present state and i/p

Moore Model
00,01

0 0
01,11 10,11

1 1
00,10

Design a sequential circuit that will

detect a sequence of 3 or more 1s

0/0 0
S0

0/0 0

1/0 1

S1

1/0 1 0/0 0
S2

1/1 1

0 S0 0

S1 0

0
0

S3 1
1

S2 0

Present

Next
x=0 x =1 S1 S2 S3 S3

Outputs
x=0 0 0 0 1 x =1 0 0 0 1

S0 S1 S2 S3

S0 S0 S0 S0

State Assignment

S0
S1 S2 S3

00
01 10 11

Present x=0 00 01 10 11 00 00 00 00

Next x =1 01 10 11 11

Outputs x=0 0 0 0 1 x =1 0 0 0 1

Prese nt

Next x=0 x =1 01 10 11 11

Inputs DB DA x =0 00 00 00 00 x=1 01 10 11 11

Outputs x=0 0 0 0 1 x =1 0 0 0 1

00 01 10 11

00 00 00 00

BA

00 0 0 00 0 0

01 0 1 01 0 0

11 0 1 11 1 1

10 0 1 10 0 0

BA

00 0 1

01 0 0

11 0 1

10 0 1

0 1
BA

0 1

0
1

DB = xB + xA DB = x(B + A) DA = xB + xA

y = AB

DA = x(B+ A)

x
D Q

Design a sequential circuit that will

detect a sequence 101 overlapping

sequences are allowed

0/0 0
S0

1 1/0

1/0 1

S1

0/0 0 0/0 0
S2

1/1 1

Present

Next
x=0 x =1 S1 S1 S1

Outputs
x=0 0 0 0 x =1 0 0 1

S0 S1 S2

S0 S2 S0

State Assignment

S0
S1 S2 S3

00
01 11 10

Present x=0 00 01 11 10 00 11 00 00

Next x =1 01 01 01 00

Outputs x=0 0 0 0 0 x =1 0 0 1 0

Prese nt

Next x=0 x =1 01 01 01 00

Inputs DB DA x =0 00 11 00 00 x=1 01 01 01 00

Outputs x=0 0 0 0 0 x =1 0 0 1 0

00 01 11 10

00 11 00 00

DA = xAB

BA

00 0 1

01 1 1

11 0 1

10 0 0

0 1

DAB = BA+xA+xB

Design a sequential circuit that will

detect a sequence 101 10 overlapping

sequences are allowed

0/0 0
A

1/0 1

1/0 1

0/0 0
0/0 0

1/0 1

0/1 0

1/0 1

0/0 0

1/0 1

Sequential Circuits

Clocked Sequential Circuits group of FFs and Combinational Gates

Models Moore & Mealy

Moore o/p depends only on the present state

Mealy o/p depends on present state and i/p

Sequential Circuits
Analysis

Custom designed to generate any count sequence

To find out behavior of a circuit

Analysis

J C K

QC

J
A C

QB

J C

QA

CLK

JA = KA = QC JB = KB = QA JC = QBQA KC = QC

Present State QC 0 0 0 0 1 QB 0 0 1 1 0 QA 0 1 0 1 0

JC

Kc

JB

Kb

Ja

KA

Next State QC QB 0 1 1 0 0 QA 1 0 1 0 0

0 0 0 1 0

0 0 0 0 1

0 1 0 1 0

0 1 0 1 0

1 1 1 1 0

1 1 1 1 0

0 0 0 1 0

1
1 1

0
1 1

1
0 1

0
0 1

1
1 1

1
0 1

1
0 1

0
0 0

0
0 0

0
0 0

1
1 0

1
0 1

000

001 100 010

111

110

011
State Diagram

101

CLK T C QA Q y

T
C

QB

TA = xQB TB = x y = QAQB

Q(t+1) = TQ+TQ QA(t+1) = (QBx)QA + (QBx)QA QA(t+1) = QBQA + QAx + QAQBx QB(t+1) = x QB

Present State
QB 0 0 0 0 1 1 1 1 QA 0 0 1 1 0 0 1 1

I/P
x 0 1 0 1 0 1 0 1

Next State
QB 0 0 0 1 1 1 1 0 QA 0 1 1 0 0 1 1 0

O/P
y 0 0 0 0 0 0 1 1

00/0
1
1 0

11/1
1 1

01/0

10/0

State Diagram

x y

Q(t+1) = Q(t) x y

Present State 0 0 0 0 1 1 1 1

x 0 0 1 1 0 0 1 1

Y 0 1 0 1 0 1 0 1

Next State 0 1 1 0 1 0 0 1

10,01 00,11
00,11 0 10,01 1

State Diagram

ROM

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.. So Far

Now ..

 Array of identical cells have same function Arrays can be programmed Each cell AND-OR /may include FFs Combinational/Sequential

Random PLD VLSI

Memory ROM/PROM PLA PAL FPGA

Typical PLD may have hundreds of millions of gates

ROM RAM

FDD HDD

Random Access

Sequential Access

SRAM DRAM Read -Write

ROM PROM EPROM EEPROM (ICP)

Volatile

Non-volatile

Look at it as a combinational Logic

A0 A1 A2 D0 D1 D2

An-3 An-2 An-1

Dm-3 Dm-2 Dm-1

2n x m

O0 O1 A0 A1 A2 O2 O3 O4 O5 O6 O7

3 x8 decoder

D0

D1

D2

D3

Inputs
A2 0 A1 0 A0 0 D3 0

Outputs
D2 0 D1 0 D0 1

0
0 0 1 1 1 1

0
1 1 0 0 1 1

1
0 1 0 1 0 1

0
1 1 0 0 1 1

1
0 1 1 0 0 0

0
0 0 1 0 1 0

1
0 1 0 0 0 1

VCC

O0 O1 A0 A1 A2 O2 O3 O4 O5 O6 O7

3 x8 decoder

D0

D1

D2

D3

PROM

VCC

GND dataline 0 1 decoder o/p

EPROM/EEPROM - MOSFETs

ROM Organization
Reg 0 Reg 1 Reg 2 Address Decoder

Reg 2n - 1

o/p tristate buffer

CS OE

Q8 Q4 Q2 Q1

x a b c d e f g

f
e d

c x

BCD 7 segment

BCD 8 0 4 0 0 0 0 1 1 1 1 0 2 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 x 0 0 0 0 0 0 0 0 0 a 1 0 1 1 0 1 0 1 1

Segment outputs b 1 1 1 1 1 0 0 1 1 c 1 1 0 1 1 1 1 1 1 d 1 0 1 1 0 1 1 0 1 e 1 0 1 0 0 0 1 0 1 f 1 0 0 0 1 1 1 0 1 g 0 0 1 1 1 1 1 0 1

Programming Table

0 0 0 0 0 0 0 1

1 1
1 1 1 1 1

0 0
0 1 1 1 1

0 1
1 0 0 1 1

1 0
1 0 1 0 1

0 0
0 0 0 0 0

1 0
0 0 0 0 0

1 0
0 0 0 0 0

1 0
0 0 0 0 0

0 0
0 0 0 0 0

0 0
0 0 0 0 0

1 0
0 0 0 0 0

1 0
0 0 0 0 0

ROM

Random Logic ICs SSI MSI Gates, FFs, Counters Mux, Demux Encoder/ Decoders

LSI Memory Microprocessors Peripheral chips PLD

.. So Far

Now ..

 Array of identical cells have same function Arrays can be programmed Each cell AND-OR /may include FFs Combinational/Sequential

Memory ROM/PROM PLA PAL FPGA

Typical PLD may have hundreds of millions of gates

SRAM DRAM Read -Write

ROM PROM EPROM EEPROM (ICP)

Volatile

Non-volatile

Look at it as a combinational Logic

A0 A1 A2 D0 D1 D2

An-3 An-2 An-1

Dm-3 Dm-2 Dm-1

2n x m

A2 0 0 0

A1 0 0 1

A0 0 1 0

B5 0 0 0

B4 0 0 0

B3 0 0 0

B2 0 0 1

B1 0 0 0

B0 0 1 0

0 1
1 1 1

1 0
0 1 1

1 0
1 0 1

0
0 0 1 1

0
1 1 0 1

1
0 1 0 0

0
0 0 1 0

0
0 0 0 0

1
0 1 0 1

Programming Table

A2 0 0 0

A1 0 0 1

A0 0 1 0

B5 0 0 0

B4 -

B3 -

B2 1

B1 -

B0 1 -

0
1 1 1 1

1
0 0 1 1

1
0 1 0 1

0
0 0 1 1

1 1 1

1
1 -

1 -

1
0 1 0 1

Programming Table

B0 0 O0 B1

O1 A0
A1 A2 O2 O3 O4 O5 O6 O7 B2 B3 B4 B5

Mask

0,1/1 1/0 1/0 0,1/0

G 1/0

0/0
0,1/0 B 0,1/0 C 0,1/0 D F

0/0

0/0

Present
x=0 A B

Next
x =1 E 0

Output
x=0 x =1 0

B
C D

C
D A

C
D A

0
0 0

0
0 0

E
F G

F
D H

G
H H

0
0 0

0
0 0

State A B

Binary 000 001

C D E F G
H

010 011 100 101 110

111

Present
x=0 000 001

Next
x =1 100 0

Output
x=0 x =1 0

001
010 011

010
011 000

010
011 000

0
0 0

0
0 0

100
101 110

101
011 111

110
111 111

0
0 0

0
0 0

111

000

000

Present

Next
x=0 x =1 100

FF inputs
x=0 001 x =1 100

Output
x=0 0 x =1 0

000

001

001
010 011 100 101

010
011 000 101 011

010
011 000 110 111

010
011 000 101 011

010
011 000 110 111

0
0 0 0 0

0
0 0 0 0

110
111

111
000

111
000

111
000

111
000

0
1

0
1

QC 0 0 0 0 0 0 0 0 1 1 1 1

QB 0 0 0 0 1 1 1 1 0 0 0 0

QA 0 0 1 1 0 0 1 1 0 0 1 1

x 0 1 0 1 0 1 0 1 0 1 0 1

DC 0 1 0 0 0 0 0 0 1 1 0 1

DB 0 0 1 1 1 1 0 0 0 1 1 1

DA 1 0 0 0 1 1 0 0 1 0 1 1

y 0 0 0 0 0 0 0 0 0 0 0 0

Programming Table

1 1
1 1

1 1
1 1

0 0
1 1

0 1
0 1

1 1
0 0

1 1
0 0

1 1
0 0

0 0
1 1

DA O0 O1 QA QB QC A0 A1 A2 O2 O3 O4 O5

DA

DB

DB

QC

QC

Mask

3 x8 decoder x x'

O6
O7

PLA

Inputs

Inputs

Fixed AND

Programmable AND

Programmable OR

Programmable OR

Outputs

Outputs

ROM

PLA

F1

F2

F3

F1 x F2

y
z F3

Minterms

Outputs

AND

OR

Reduce no .of gates reduce expression

F1 (x, y, z) = (0,1,2,4) F2 (x, y, z) = (0,5,6,7) F3 (x, y, z) = (0,3,5,7)

00 0 1
1 0

00

01
1 0

11
0 0

10
1 0

0
1

1 1

01
0 1

11
0 1

10
0 1

00 0 1
1 0

01
0 1

11
1 1

10
0 0

F1 F1 F2 F2 F3 F3

= = = = = =

xy + yz + xz xy + xz + yz xy + xz + xyz xz + xz + xyz xz + yz + xyz yz + xz + xyz

Product x xy xz yz xyz 1 2 3 4 1 1 0

Inputs y 1 1 0 z 1 1 0

F1 C 1 1 1 -

F2 T 1 1 1

F3 T 1 1 1

F1 x F2

y
z F3

PAL

Random Logic ICs SSI MSI Gates, FFs, Counters Mux, Demux Encoder/ Decoders

LSI Memory Microprocessors Peripheral chips PLD

.. So Far

Now ..

Memory ROM/PROM PLA PAL FPGA

Typical PLD may have hundreds of millions of gates

Inputs

Inputs

Fixed AND

Programmable AND

Programmable OR

Programmable OR

Outputs

Outputs

ROM

PLA

F1

F2

F3

F1 x F2

y
z F3

Minterms

Outputs

AND

OR

Reduce no .of gates reduce expression

PAL

F1

y
z

F2

F1

F2

PAL
2 wide PAL

y
z

Inputs

Inputs

Programmable AND

Programmable AND

Programmable OR

Fixed OR

Common minterms Reduce Total no. of minterms

Outputs

Outputs

o/p fedback as i/p Reduce minterms/eqn

PLA

PAL

F1 (A, F2 (A, F3 (A, F4 (A,

B, B, B, B,

C, C, C, C,

D) D) D) D)

= = = =

(2,12,13) (7,8,9,10,11,12,13,14,15) (0,2,3,4,5,6,7,8,10,11,15) (1,2,8,12,13)

F1
00 01 11 10

00

01

11

10

F4
00 01

00

01

11

10

11 10

1 1

F1 = ABC + ABCD

F4 = ABC + ABCD+ABCD +ACD

F4 = F1+ABCD +ACD

F2
00 01 11 10

00

01

11

10

F3
00

00

01

11

10

1
1 1

1
1 1

1
1

1 1 1 1 1 1 1 1 1

01 11 10

F2 = A + BCD

F3 = AB + CD+BD

Product A 1 2 3 4 5 6 1 0 B 1 0

Inputs C 0 1 D 0 F1 -

Outputs F1 = ABC + ABCD

1 -

1 -

1 -

1 -

F2 = A + BCD

7
8 9 10 11 12

0
0 1

1
0 0 -

1 0 0

1 0 1 0

1 -

F3 = AB + CD+BD

F4 = F1+ABCD +ACD

F1

F2

F3

F4

Multiplicand
Multiplier
A1 B0 A1 B1 C A1 B1 + C A0 B1 A1 B0 + A0 B0

A1 A0
B1 B0 A0 B0

A0 B0

B1 0 0 0 0 0 0 0 0

B0 0 0 0 0 1 1 1 1

A1 0 0 1 1 0 0 1 1

A0 0 1 0 1 0 1 0 1

P3 0 0 0 0 0 0 0 0

P2 0 0 0 0 0 0 0 0

P1 0 0 0 0 0 0 1 1

P0 0 0 0 0 0 1 0 1

ROM 16 x 4

1 1
1 1 1 1 1 1

0 0
0 0 1 1 1 1

0 0
1 1 0 0 1 1

0 1
0 1 0 1 0 1

0 0
0 0 0 0 0 1

0 0
1 1 0 0 1 0

0 1
0 1 0 1 1 0

0 0
0 0 0 1 0 1

0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0

1
0 1 1 0

1
1 1 1

1
1 1

Methods & Algorithms

A 0 0 0
0 0 0 0 0

Q 0 1 1
1 0 1 0 0

M 1 1 0
0 0 1 0 0

0 0 0
1 0 0 0 0

0 1 0
0 1 0 0 0

0 1 1
0 1 0 1 1

0 0 1
1 0 1 0 0

0 0 0
0 1 0 1 1

1 1 1
1 0 0 1 1

0111 0111 0111

0111 0111 0111 0111 0111

1.

A 00000, Q Multiplier, M Multiplicand Count = 0

2. 3. 4.

If LSB of Q =1 then A = A+M Shift AQ right by 1 bit Logical Shift Count = Count +1

5.

If Count = n stop ; else go step 2

0 0 0 0 0 0 0 1 1

4-bit adder

Shift & Control

count

7 X -3 0
1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1

1
1 1 0 1 0

1
0 1 0

1
1 1

0
0

0
1

1
0

1
1

1
1 1 1

Multiplication
Methods & Algorithms

Shift & Add Method

1. 2. 3. 4. 5. A 00000, Q Multiplier, M Multiplicand Count = 0 If LSB of Q =1 then A = A+M Shift AQ right by 1 bit Logical Shift Count = Count +1 If Count = n stop ; else go step 2

Implementation of Shift & Add Algo

0 0 0 0 0 0 0 1 1

4-bit adder

Shift & Control

count

Signed Multiplication
1. Convert Multiplier Multiplicand to positive
numbers

2. Perform Multiplication
3. Takes twos complement of result if the sign of

two nos. are different

Start

A =0 M = Multiplier Q = Multiplicand Q-1 = 0 Count = n

10 A= A-M

Q0 Q-1 ?

01 A= A+M

ASR :AQQ-1 Count = Count -1

Count ?
0

Booths Algorithm

Stop

Booths Algorithm 7x-3

A
0 1 1 0 0 1 0 0 1 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1

Q
0 0 1 1 1 1 1 1 0 0 1 1

Q-1
0 0 1 1 0 0

M
0111 0111 0111 0111 0111 0111

1
1 1

1
1 1

0
1 1

1
0 0

0
1 1

1
0 0

1
1 1

1
1 1

1
1 1

0111
0111 0111

Booths Algorithm -7x-3

A
0 0 0 1 1 0 0 1 0 1 1 1 0 1 1 0 1 0 0 1 1 0 0 1 1 1 1 1 0 0 1 1 1 1 1 1

Q
0 0 1 1 1 1 1 1 0 0 1 1

Q-1
0 0 1 1 0 0

M
1001 1001 1001 1001 1001 1001

0
0 0

0
0 0

1
0 0

0
1 1

1
0 0

0
1 1

1
0 0

1
1 1

1
1 1

1001
1001 1001

Booths Algorithm 7x3

A
0 1 0 0 0 0 0 1

Q
0 0 0 0 1 1 1 1

Q-1
0 0

M
0111 0111

1
1 0 0 0 0

1
1 1 0 0 0

0
1 0 1 0 0

0
0 1 0 1 1

1
0 0 1 0 0

0
1 1 0 1 1

0
0 0 1 0 0

1
0 0 0 1 1

1
1 0 0 0 0

0111
0111 0111 0111 0111 0111

Why does it work ???

30 can be represented at 32 -2 M x 32 (24 + 23 +22 +21 ) M x (32-2) (25 21 ) 32 0001 1110 32 (0010 0000 0000 0010) 32 0010 0010 122 ????

Booths Algorithm

We can exploit this to create a faster multiplier How?

Sequence

of N 1s in the multiplier yields sequence of N

additions Replace with one addition and one subtraction

Booths Algorithm

7 x -3 7 -3 -3

0111 1101

(-0100 + 0001) (0-101)

Pencil-Paper Booths Method

0
0

1
1

1
0

1
1

0
0

0
0

0
0

0
0

0
0

1
0

1
0

1
0

1
0

1
0

0
0

0
0

Booth Algorithm - Implementation

0 0 0 0 1 0 1 0 0 1 0 1

4-bit adder/ 4-bit adder subtractor

Shift & Control

count

Booth - Performance
Worst case multiplier (101010) requires N/2 adds + N/2 subs
What is the worst case multiplier for straight multiplication? How is this better than normal multiplication?

Modified Booth Algorithm

Booth

Modified Booth

2 bits 1 Multiplier + 1 Helper Cycle count = n Signed Digit Encoding

3 bits 2 Multiplier bits + 1 helper Cycle count = n/2 Bit pair Encoding

Modified Booth
2 Q Bits 00 00 01 01 10 Helper 0 1 0 1 0 Multiplier ASR 2 +M ASR 2 +M ASR 2 +2M ASR 2 -2M ASR 2 Bit -Pair 1 -1 0 1 1 -

10 11
11

1 0
1

-M ASR 2 -M ASR 2
ASR 2

-1 -1
0

Modified Booth
A 0 0
0 0 1 1 1 1

Q 0 1
1 0 1 0 1 1

Q-1 0 0
1 1 1 1 1 1

M 0111 0111
0111 0111 0111 0111 0111 0111

0 1
0 0 0 1 1 1

0 1
1 1 0 1 0 0

1 1
1 1 1 0 1 1

1 1
1 1 1 1 0 0

1 1
0 1 1 1 1 1

0 0
1 0 0 1 1 1

Modified Booth 7x-3

0 0 1 0 1 0 1 0 0 0 0 1 -1 1 1 1 1 1 1 1