15-398 Introduction to Nanotechnology

Outline
Transistor theory Transistor reality Scaling

Transistors and Scaling

Seth Copen Goldstein seth@cs.cmu.edu CMU

Adapted from Intro to CMOS VLSI Design, Harris
lecture6 15-398 2004-5 Seth Copen Goldstein 1 lecture6 15-398 2004-5 Seth Copen Goldstein 2

nMOS Transistor
Four terminals: gate, source, drain, body Gate oxide body stack looks like a capacitor
Gate and body are conductors SiO2 (oxide) is a very good insulator Called metal oxide semiconductor (MOS) capacitor Even though gate is Source Gate Drain no longer made of metal Polysilicon
SiO2

MOS Capacitor
Gate and body form MOS capacitor Operating modes
Accumulation Depletion Inversion
Vg < 0 + polysilicon gate silicon dioxide insulator p-type body

(a)

0 < Vg < Vt + depletion region

(b)

n+ p

n+ bulk Si

V g > Vt + inversion region depletion region

(c)
lecture6 15-398 2004-5 Seth Copen Goldstein 3 lecture6 15-398 2004-5 Seth Copen Goldstein 4

Terminal Voltages
Mode of operation depends on Vg, Vd, Vs
Vgs = Vg Vs Vgd = Vg Vd Vds = Vd Vs = Vgs - Vgd
Vg + Vgs Vs + Vgd Vds + Vd

nMOS Cutoff
No channel Ids = 0
Vgs = 0

Source and drain are symmetric diffusion terminals nMOS body is grounded. First assume source is 0 too. Three regions of operation
Cutoff Linear Saturation By convention, source is terminal at lower voltage Hence Vds 0

+ s n+

+ d n+

Vgd

p-type body b

lecture6 15-398

2004-5 Seth Copen Goldstein

lecture6 15-398

2004-5 Seth Copen Goldstein

Channel forms Current flows from d to s (e- from s to d) Ids as Vds V >V V =V g Similar to + + s linear resistor d
gs t gd

nMOS Linear

nMOS Saturation
Channel pinches off Ids independent of Vds We say current saturates

gs

n+ p-type body b

n+

Vds = 0

Vgs > Vt

Vgs > Vt

+ + d n+ Vgs > Vgd > Vt Ids 0 < Vds < Vgs-Vt

+ -

Vgd < Vt

+ s n+

d Ids Vds > Vgs-Vt

n+ p-type body b

n+

p-type body b
lecture6 15-398 2004-5 Seth Copen Goldstein 7 lecture6 15-398 2004-5 Seth Copen Goldstein 8

I-V Characteristics
In Linear region, Ids depends on
How much charge is in the channel? How fast is the charge moving?

Channel Charge
MOS structure looks like parallel plate capacitor while operating in inversion
Gate oxide channel

Qchannel =

polysilicon gate W tox n+ L p-type body

lecture6 15-398 2004-5 Seth Copen Goldstein 9 lecture6 15-398 2004-5 Seth Copen Goldstein

n+

SiO2 gate oxide (good insulator, ox = 3.9)

gate Vg + + Cg Vgd drain Vgs source Vs Vd channel + n+ n+ Vds p-type body

10

Channel Charge
MOS structure looks like parallel plate capacitor while operating in inversion
Gate oxide channel

Channel Charge
MOS structure looks like parallel plate capacitor while operating in inversion
Gate oxide channel

Qchannel = CV C=

Qchannel = CV C = Cg = oxWL/tox = CoxWL V=

gate Vg + + Cg Vgd drain Vgs source Vs Vd channel + n+ n+ Vds p-type body
11

Cox = ox / tox

polysilicon gate W tox n+ L p-type body

lecture6 15-398 2004-5 Seth Copen Goldstein

polysilicon gate W tox n+ L p-type body

lecture6 15-398 2004-5 Seth Copen Goldstein

n+

SiO2 gate oxide (good insulator, ox = 3.9)

n+

SiO2 gate oxide (good insulator, ox = 3.9)

gate Vg + + Cg Vgd drain Vgs source Vs Vd channel + n+ n+ Vds p-type body

12

Channel Charge
MOS structure looks like parallel plate capacitor while operating in inversion
Gate oxide channel

Carrier velocity
Charge is carried by e Carrier velocity v proportional to lateral Efield between source and drain v=

Qchannel = CV C = Cg = oxWL/tox = CoxWL Cox = ox / tox V = Vgc Vt = (Vgs Vds/2) Vt

gate Vg + + Cg Vgd drain Vgs source Vs Vd channel + n+ n+ Vds p-type body
13

polysilicon gate W tox n+ L p-type body

lecture6 15-398 2004-5 Seth Copen Goldstein

n+

SiO2 gate oxide (good insulator, ox = 3.9)

lecture6 15-398

2004-5 Seth Copen Goldstein

14

Carrier velocity
Charge is carried by e Carrier velocity v proportional to lateral Efield between source and drain v = E called mobility E=

Carrier velocity
Charge is carried by e Carrier velocity v proportional to lateral Efield between source and drain v = E called mobility E = Vds/L Time for carrier to cross channel:
t=

lecture6 15-398

2004-5 Seth Copen Goldstein

15

lecture6 15-398

2004-5 Seth Copen Goldstein

16

Carrier velocity
Charge is carried by e Carrier velocity v proportional to lateral Efield between source and drain v = E called mobility E = Vds/L Time for carrier to cross channel:
t=L/v

nMOS Linear I-V

Now we know
How much charge Qchannel is in the channel How much time t each carrier takes to cross

I ds =

lecture6 15-398

2004-5 Seth Copen Goldstein

17

lecture6 15-398

2004-5 Seth Copen Goldstein

18

nMOS Linear I-V

Now we know
How much charge Qchannel is in the channel How much time t each carrier takes to cross

nMOS Linear I-V

Now we know
How much charge Qchannel is in the channel How much time t each carrier takes to cross

Q I ds = channel t =

I ds =

Qchannel t W = Cox L

V V Vds gs t 2 V = Vgs Vt ds Vds 2

V ds

: gain factor Depends on: Process geometry

= Cox

W L

lecture6 15-398

2004-5 Seth Copen Goldstein

19

lecture6 15-398

2004-5 Seth Copen Goldstein

20

nMOS Saturation I-V

If Vgd < Vt, channel pinches off near drain Now drain voltage no longer increases current
I ds =
When Vds > Vdsat = Vgs Vt

nMOS Saturation I-V

If Vgd < Vt, channel pinches off near drain Now drain voltage no longer increases current
When Vds > Vdsat = Vgs Vt

V I ds = Vgs Vt dsat 2

V dsat

lecture6 15-398

2004-5 Seth Copen Goldstein

21

lecture6 15-398

2004-5 Seth Copen Goldstein

22

nMOS Saturation I-V

If Vgd < Vt, channel pinches off near drain Now drain voltage no longer increases current V I ds = Vgs Vt dsat Vdsat 2
=
When Vds > Vdsat = Vgs Vt

nMOS I-V Summary

Shockley 1st order transistor models

(Vgs Vt )

0 V I ds = Vgs Vt ds 2 2 (Vgs Vt ) 2

Vgs < Vt V V < V ds ds dsat Vds > Vdsat

cutoff linear saturation

lecture6 15-398

2004-5 Seth Copen Goldstein

23

lecture6 15-398

2004-5 Seth Copen Goldstein

24

Example
Consider a 0.6 m process
From AMI Semiconductor tox = 100 2.5 2/V*s = 350 cm 2 Vt = 0.7 V
Ids (mA) Vgs = 5

pMOS I-V
All dopings and voltages are inverted for pMOS Mobility p is determined by holes
Typically 2-3x lower than that of electrons n 120 cm2/V*s in AMI 0.6 m process

Plot Ids vs. Vds

1.5 1

Vgs = 4

Vgs = 0, 1, 2, 3, 4, 5 Use W/L = 4/2

Thus pMOS must be wider to provide same current

Vgs = 3

0.5 0 0 1 2

Vgs = 2 Vgs = 1

3
Vds

3.9 8.85 1014 W W = Cox = ( 350 ) 8 L 100 10 L

W 2 = 120 A / V L

lecture6 15-398

2004-5 Seth Copen Goldstein

25

lecture6 15-398

2004-5 Seth Copen Goldstein

26

Ideal Transistor I-V

Shockley 1st order transistor models

Ideal nMOS I-V Plot

180 nm TSMC process Ideal Models
Ids (A) 400 300 Vgs = 1.8

0 Vgs < Vt V I ds = Vgs Vt ds Vds Vds < Vdsat 2 2 Vds > Vdsat (Vgs Vt ) 2
lecture6 15-398 2004-5 Seth Copen Goldstein

cutoff linear saturation

= 155(W/L) A/V2 Vt = 0.4 V VDD = 1.8 V

200

Vgs = 1.5 Vgs = 1.2 Vgs = 0.9 Vgs = 0.6 0 0.3 0.6 0.9 1.2 1.5 1.8

100

Vds

27

lecture6 15-398

2004-5 Seth Copen Goldstein

28

Simulated nMOS I-V Plot

180 nm TSMC process BSIM 3v3 SPICE models I (A) What differs? 250
ds

Simulated nMOS I-V Plot

180 nm TSMC process BSIM 3v3 SPICE models I (A) What differs? 250
ds

Vgs = 1.8 Vgs = 1.5 Vgs = 1.2 Vgs = 0.9

200 150 100 50

Less ON current No square law Current increases in saturation

Vgs = 1.8 Vgs = 1.5 Vgs = 1.2 Vgs = 0.9

200 150 100 50

Vgs = 0.6 0 0 0.3 0.6 0.9 Vds 1.2 1.5 0 0 0.3 0.6 0.9 Vds 1.2

Vgs = 0.6 1.5

lecture6 15-398

2004-5 Seth Copen Goldstein

29

lecture6 15-398

2004-5 Seth Copen Goldstein

30

Velocity Saturation
We assumed carrier velocity is proportional to E-field At high fields, this ceases to be true
Carriers scatter off atoms Velocity reaches vsat
Electrons: 6-10 x 106 cm/s Holes: 4-8 x 106 cm/s

sat

Vel Sat I-V Effects

Ideal transistor ON current increases with VDD2
2 W (Vgs Vt ) I ds = Cox = (Vgs Vt ) 2 2 L 2

v = Elat = Vds/L

Velocity-saturated ON current increases with VDD

I ds = CoxW (Vgs Vt ) vmax

Better model

sat / 2

Elat v= vsat = Esat E 1 + lat Esat

2004-5 Seth Copen Goldstein

Real transistors are partially velocity saturated

slope =

0 0

Esat

2Esat Elat

3Esat

Approximate with -power law model Ids VDD 1 < < 2 determined empirically
31 lecture6 15-398 2004-5 Seth Copen Goldstein 32

lecture6 15-398

-Power Model
0 V I ds = I dsat ds Vdsat I dsat Vgs < Vt Vds < Vdsat Vds > Vdsat cutoff linear saturation
Simulated -law Shockley

Channel Length Modulation

I dsat = Pc

(V 2

gs

Vt )

Vdsat = Pv (Vgs Vt )

/2

Reverse-biased p-n junctions form a depletion

region

Ids (A) 400 300

Vgs = 1.8 200 Vgs = 1.5 100 Vgs = 1.2 Vgs = 0.9 Vgs = 0.6 0 0.3 0.6 0.9 1.2 1.5 1.8 V ds
33 2004-5 Seth Copen Goldstein

Shorter Leff gives more current

Ids increases with Vds Even in saturation
GND Source

Region between n and p with no carriers Width of depletion Ld region grows with reverse bias Leff = L Ld
VDD Gate VDD Drain Depletion Region Width: Ld

n+

0
lecture6 15-398

L Leff p GND

n+ bulk Si
34

lecture6 15-398

2004-5 Seth Copen Goldstein

OFF Transistor Behavior

What about current in cutoff? Simulated results What differs?
Current doesnt go Ids 1 mA to 0 in cutoff
100 A 10 A 1 A 100 nA 10 nA 1 nA 100 pA 10 pA 0 Subthreshold Slope Vt 0.3 0.6 0.9 Vgs
lecture6 15-398 2004-5 Seth Copen Goldstein 35 lecture6 15-398

Leakage Sources
Subthreshold conduction
Transistors cant abruptly turn ON or OFF

Junction leakage
Vds = 1.8

Subthreshold Region

Saturation Region

Reverse-biased PN junction diode current

Gate leakage
Tunneling through ultrathin gate dielectric

Subthreshold leakage is the biggest source in modern transistors

1.2 1.5 1.8
2004-5 Seth Copen Goldstein 36

Subthreshold Leakage
Subthreshold leakage exponential with Vgs
Vgs Vt

DIBL
Drain-Induced Barrier Lowering
Drain voltage also affect Vt

I ds = I ds 0e

nvT

Vds v 1 e T

2 I ds 0 = vT e1.8

Vt = Vt Vds

n is process dependent, typically 1.41.5

High drain voltage causes subthreshold leakage to ________.

ttds

VVV

saraswat
lecture6 15-398 2004-5 Seth Copen Goldstein 37 lecture6 15-398 2004-5 Seth Copen Goldstein

Punch through
38

DIBL
Drain-Induced Barrier Lowering
Drain voltage also affect Vt

Junction Leakage
Reverse-biased p-n junctions have some leakage
VD I D = I S e vT 1

Vt = Vt Vds

High drain voltage causes subthreshold leakage to increase.

ttds

VVV

Is depends on doping levels

And area and perimeter of diffusion regions Typically < 1 fA/m2

p+ n+ n+ p substrate p+ n well p+ n+

saraswat
lecture6 15-398 2004-5 Seth Copen Goldstein 39 lecture6 15-398 2004-5 Seth Copen Goldstein 40

Gate Leakage
Carriers may tunnel thorough very thin gate oxides Predicted tunneling current (from [Song01])
109 106 VDD trend tox 0.6 nm 0.8 nm 1.0 nm 1.2 nm 1.5 nm 1.9 nm

Temperature Sensitivity
Increasing temperature
Reduces mobility Reduces Vt

J (A/cm ) G

103 100

ION ___________ with temperature IOFF ___________ with temperature

10-3 10-6 10-9 0 0.3 0.6 0.9 1.2 1.5

1.8

Negligible for older processes May soon be critically important

lecture6 15-398 2004-5 Seth Copen Goldstein

VDD

41

lecture6 15-398

2004-5 Seth Copen Goldstein

42

Temperature Sensitivity
Increasing temperature
Reduces mobility Reduces Vt

So What?
So what if transistors are not ideal?
They still behave like switches.

ION decreases with temperature IOFF increases with temperature

I ds
increasing temperature

But these effects matter for

Supply voltage choice Logical effort Quiescent power consumption Pass transistors Temperature of operation

Vgs
lecture6 15-398 2004-5 Seth Copen Goldstein 43 lecture6 15-398 2004-5 Seth Copen Goldstein 44

Scaling Methods
Dennard: scaling method that maintains constant electric field

polysilicon gate W tox n+ L p-type body n+

Xj

SiO (good in

saraswat
lecture6 15-398 2004-5 Seth Copen Goldstein 45