Giao tip AVR vi my tnh (I) I.

Gii thiu Bi vit ny s ni v cch giao tip gia AVR v my tnh c nhn (PC) theo mt cch n gin nhng kh ton din. N n gin v ti s dng mt giao din kh c in giao tip gia AVR v PC, giao din RS232 thng qua cc cng COM. Ton din v ti s hng dn cc bn t cch mc mch chuyn gia AVR v PC, cch vit chng trnh giao tip theo chun RS232 trn my tnh v trn AVR. C th bi ny bao gm: - S lt s v chc nng cc chn cng COM trn my tnh. - Mch chuyn kt ni AVR vi PC qua cng COM. - To cng COM o trn PC cho mc ch m phng. - S dng cc hm trong th vin xut nhp chun ca C nh printf, scanftrong WinAVR. - Vit chng trnh giao tip RS232 cho AVR. - S dng Hyper Terminal ca Windows trong giao tip RS232. - Vit chng trnh truy xut cng COM trn PC (Visual C++, Visual Basic) II. S lc v cng COM Cng COM hay cng ni tip (COM Port, Serial Port) l cng giao tip thuc vo dng lo lng trn PC, c my tnh bn v Laptop. Ngy nay vi s xut hin v bnh trng ca chun USB th cng COM (v c cng LPT hay cng song song) ang dn bin mt. Giao tip thng qua cng COM l giao tip theo chun ni tip RS232. Chun ny c tc kh chm nu em so snh vi USB. Tuy nhin, vi dn robotics hay control th COM-RS232 li rt c a chung v tnh n gin v cng vs chm chp ny. Cc cng COM trn cc my tnh hin ti (nu c) a s l dng cng c 9 chn (male 9 pins). Tuy nhin, u vn cn tn ti loi cng COM 25 chn, loi ny v hnh dng kh ging cng LPT nhng l loi male trong khi cng LPT l female. Hnh 1 th hin 2 dng ca cng COM v bng 1 tm tt chc nng cc chn ca cng ny.

Hnh 1. Cng COM 9 chn v 25 chn.

Bng 1: Cc chn trn cng COM

ng ch nht trong cc chn ca cng COM l 3 chn 0V SG (signal ground), chn pht d liu TxD v chn nhn d liu RxD. y l 3 chn c bn phc v truyn thng theo chun RS232 v tng thch vi UART trn AVR. Cc chn cn li cng c th c s dng nu ngi dng c 1 ch kin thc v t chc thanh ghi ca PC. Tuy nhin, trong a s trng hp giao tip qua cng COM th ch 3 chn trn c s dng. Nh trnh by trong bi AVR5-UART, chun RS232 v UART nhn chung l nh nhau v mt khung truyn, tc baudnhng khc nhau v mc in p v cc. Xem li v d so snh trong hnh 2.

Hnh 2. So snh UART v RS232. Trong chun UART (trn AVR), mc 1 tng ng in p cao (5V, TTL) trong khi i vi RS232 th mc 1 tng ng vi in p thp (in p m, c th -12V). Nh th r rng cn mt cu chuyn (converter) kt

ni gia 2 chun ny. May mn l chng ta khng cn phi t thit k cu chuyn ny v c cc IC chuyn dng. MAX232 l mt trong cc IC chuyn UART-RS232 c s dng nhiu nht. Tt nhin, bn hon ton c th t to mt mch chuyn n gin ch vi mt vi linh kin nh t in, in tr, diode v transisotor nhng tnh n nh th ti khng m bo. Hnh 3 m t cch dng IC Max232 kt ni gia UART trn AVR v cng COM ca PC.

Hnh 3. Kt ni AVR vi PC thng qua Max232. Mch in trn ch c tc dng thay i mc in p cho ph hp gia RS232 v UART, n hon ton khng lm thay i phng thc giao tip ca cc chun ny v v th vic lp trnh trn PC v AVR u khng c g thay i. Tht ra Max232 c n 2 cu chuyn, trong hnh 3 chng ta ch s dng cu chuyn 1. Chn pht TxD (chn 3) ca cng COM c ni vi chn R1IN (Receive 1 Input) ca Max232 th tng ng chn R1OUT (Receive 1 Output) phi ni vi chn nhn RX ca AVR. Tng t cho trng hp T1IN v T1OUT. Gi tr cc t in 10uF l tng i chun, tuy nhin khi bn thay bng t 1uF th mch vn hot ng nhng khong cch truyn (cab ni) s ngn hn (nu di qu s pht sinh li truyn thng). Cc in tr trong hnh 3 ch c tc dng lm bo v cng COM v cc IC, bn c th khng cn dng cc in tr ny vn khng nh hng hot ng ca mch. VCC v GND l ngun ca mch AVR. Ch : nu mun thc hin giao tip gia 2 my tnh vi nhau thng qua cng COM, bn cn dng1 cab cho (chn TxD ca PC1 ni vi RxD ca PC2 v ngc li) ni 2 cng COM li vi nhau. III. To cng COM o cho m phng Mun thc hin giao tip gia AVR v PC thng qua cng COM th hin nhin bn cn c ci cng COM, ngoi ra bn cn t lm mt mch AVR v cu chuyn Max232. Tht khng may l khng phi my tnh no cng c cng ny, nu bn ch mun hc cch giao tip AVR-PC hoc ch mun kim tra mt gii thut no th c l m phng l gii php c a thch hn. Cho mc ch m phng giao tip RS232, Proteus li mt ln na hu ch khi cho php m phng truyn nhn d liu vi cng COM. Nh th vn cn li l lm sao to cc cng COM o trn my tnh v kt ni chng vi nhau thc hin m phng giao tip. Do tnh cht ca cc cng COM l ch c m (open) 1 ln duy nht, ngha l 2 phn mm khng

th cng m 1 cng. tng ca chng ta l to ra 2 cng COM o c ni cho sn vi nhau (v d COM2 v COM3). Trong phn mm Proteus ng ra ca UART c ni vi COM2. Trong phn mm trn PC (v d Hyper Terminal) chng ta kt ni vi COM3. Bng cch ny chng ta c th thc hin giao tip gia AVR (m hnh Proteus) vi PC (phn mm Hyper Terminal). C mt vi phn mm tt c kh nng to cng COM o v kt ni o gia chng ng nh yu cu ca chng ta. Trong phn ny ti s gii thiu 2 phn mm nh th, trong c 1 phn mm min ph (Virtual Serial Port Emulator) v 1 phn mm thu ph (Eltima Virtual Serial Port Driver). Virtual Serial Port Emulator (VSPE): l mt phn mm to cng COM v kt ni o tt ca Eterlogic. iu c bit l phin bn dnh cho Windows 32 bits hon ton min ph, v vy y l phn mm u tin bn phi khi mun to dng cho mc ch hc tp. Trc tin bn hy download phn mm VSPE bn mi nht ti website chnh thc ca Eterlogic: http://www.eterlogic.com/Products.VSPE.html (nhn vo nt Download pha cui trang web). Gii nn file zip v chy file SetupVSPE.exe ci t. Sau khi ci t hy tm v chy chng trnh VSPE. Giao din ca VSPE nh trong hnh 4.

Hnh 4. Giao din phn mm VSPE. S dng VSPE kh n gin, bn ch vic nhn vo nt Create New Device c t trong hnh 4, hoc vo menu Device v chn Create, to 1 cng COM o. Trong hp thoi Specify device type bn chn nh bn di v nhn Next. Sau bn c th chn tn cho cng COM mnh mun to trong (v d COM2).

Hnh 5. To cng COM2 o bng VSPE. Bn c th tin hnh to bao nhiu cng COM o ty thch. V d bn to 2 cng COM2 v COM3, bc tip theo chng ta s u cho 2 cng ny vi nhau m phng vic truyn d liu qua RS232. T giao din chnh ca VSPE bn nhn tip vo nt Create new Device. Ln ny, trong hp thoi Specify device type bn khng chn Connector na m chn Serial Redirector nh trong hnh 6. Sau nhn next, chn 2 cng COM o to lc trc v nhn vo nt Finish.

Hnh 6. To kt ni gia 2 cng COM. Sau khi hon tt bn s thy cc cng COM o v kt ni gia chng c th hin trong giao din VSPE nh hnh 7. Bn c th minimize giao din VSPE n n vo taskbar. Ch l nu bn ng chng trnh VSPE li (tt) th cc cng COM o cng bin mt.

Hnh 7. Cc cng COM o v kt ni to bng VSPE. Virtual Serial Port Driver (VSPD): l mt phn mm to cng COM v kt ni o tt ca Eltima Software. y l phn mm c thu ph, bn c th download bn dng th 14 ngy ti website chnh thc ca Eltima Software: http://www.eltima.com/products/vspdxp/ So vi VSPE th VSPD d s dng v n nh hn (v l phn mm thng mi). Sau khi download bn trial v tin hnh ci t, bn hy tm v chy file Configure Virtual Serial Port Driver. Giao din ca VSPD nh trong hnh 8.

Hnh 8. Giao din phn mm VSPD. Trong tab Manager ports phn mm t ng ngh 1 cp cng COM o c th c to ra, bn c th chn li ty thch v nhn Add pair to 2 cng COM ny. Khc vi VSPE, cng COM o do VSPD to ra s xut hin trong Device list ca Windows v khng b mt i khi ngi dng tt phn mm VSPD. Hy chy trnh Device manager ca Windows, trong mc Ports (COM & LPT) bn s thy cc cng COM o c to thnh (xem v d trong hnh 9).

Hnh 9. Cc cng COM o v kt ni gia chng c to bi VSPD. IV. S dng th vin xut nhp chun stdio.h trong WinAVR Nhng ai tng hc ngn ng lp trnh C chc s khng qun chng trnh hello world u tin ca mnh:

Chng trnh ny ch lm 1 vic n gin l in dng ch hello, world ln mn hnh. Vic in dng ch c thc hin bi lnh printf trong dng 3. Lnh printf nm trong th vin stdio gi l th vin xut nhp chun (standard input/output). Lnh printf trong stdio khng ch c dng in ln mn hnh m c th in ln bt k thit b xut no (output device), ngay c in ra 1 file trn cng my tnhCho AVR, nu bn s dng trnh dch CodevisionAVR ca HPinfotech, khi bn gi lnh printf th chui d liu s c in ra (xut ra) module UART (tt nhin bn phi ci t cc thanh ghi ca UART kch hot UART trc). Nh th CodevisionAVR t hiu UART l thit b xut/nhp mc nh cho cc lnh trong th vin stdio (printf, scanf). Tuy nhin, vi WinAVR (avr-gcc) mi chuyn li khc, s dng cc lnh xut nhp chun chng ta cn khai bo mt thit b xut nhp v hm xut nhp c bn. Hm xut nhp c bn l hm do ngi dng nh ngha, nhim v ca n l xut (hoc nhp) mt k t ra mt thit b xut nhp no . V d trong bi AVR5 - giao tip UART chng ta nh ngha mt hm uart_char_tx xut k t ra UART nh sau:

Hoc trong bi TextLCD chng ta kho st hm putChar_LCD xut mt k t ra LCD nh bn di:

C 2 hm uart_char_tx v putChar_LCD nh v d trn u c th c dng lm hm xut nhp c bn cho cc hm nh printf...trong th vin xut nhp chun sdtio. Nu gi s hm uart_char_tx c dng th khi gi hm hm printf, chui d liu s c xut ra UART. Ngc li, trng hp hm putChar_LCD c s dng nh hm c bn th hm printf ca stdio s xut chui d liu ln LCD. Bng phng thc ny, trnh dch avr-gcc cho php chng ta tip cn th vin stdio mt cch mm do hn, bn c th dng cc hm ca stdio xut/nhp d liu vo bt k thit b no nh UART terminal, TextLCD, Graphic LCD hay thm ch SD, MMC cardmt khi bn nh ngha c hm xut nhp c bn. minh ha cho cch s dng cc hm trong th vin stdio, ti s trnh by mt v d xut d liu ra TextLCD v uart bng cc hm printfca stdio. Mch in m phng cho v d c ny th hin trong hnh 10 bn di.

Hnh 10. M phng v d xut d liu vi th vin stdio. Tt c cc d liu hin th trn LCD v uart terminal trong hnh 10 u c thc hin thng qua cc hm printf v fprintf. Ngoi ra trong v d ny, ngi dng c th nhp 1 k t t bn phm v m ASCII ca phm s c in ra trn Terminal. on code trnh by trong List1. List 1. Xut d liu ra LCD v UART bng th vin xut nhp chun stdio

 s dng cc hm trong th vin xut nhp chun, chng ta cn include file header ca th vin nh trong dng code 4 #include <stdio.h>. Ch khi s dng avr-gcc, cc hm lin quan n avr (avr-libc) nm trong th mc con /avr/ ca th mc include nn khi knh km phi ch r th mc con ny. V d header io.h hoc interrupt.h cha cc hm chuyn bit cho avr, khi nh km cc file ny chng ta ghi c th nh: #include <avr/io.h>Tuy nhin, cc file header ca ngn ng C chun (nh stdio.h, math.h, ) th nm trc tip th mc include, khi nh km cc file ny phi ghi trc tip nh trong dng code 4. Ngoi ra do v d ny c s dng LCD, bn cn copy v include th vin myLCD.h nh trong dng 5 (xem li bi TextLCD). Nh trnh by trn, s dng cc hm trong stdio chng ta cn c cc hm xut/nhp c bn. Cc dng code t 7 n 11 l hm xut d liu ra uart c tn uart_char_tx, hm ny s c dng lm hm c bn cho cc hm xut ca stdio sau ny. Thc cht hm uart_char_tx c trnh by trong bi hc v

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UART, y c mt thay i nh l dng code 8 if (chr==\n) uart_char_tx(\r), dng ny c ngha l khi gp ngi dng mun xut ra k t \n th hm uart_char_tx s xut ra thm k t \r . Nh th, nu sau ny bt gp mt du hiu xung dng \n (c m ASCII l 10, gi l Line Feed LF) cui cu th mt t hp m '\r'+'\n' (m '\r' = 13 gi l Carriage Return CR) s c gi thc hin xung dng. nm r hn vn ny bn tm hiu thm v CRLF (Carriage Return Line Feed) trong Windows. Hai dng code 13 v 14 rt quan trng khi mun s dng th vin stdio. ngha ca 2 dng ny l to 2 FILE o (hay cn gi l stream) dnh cho vic xut d liu. Chng ta kho st dng 14: to stream cho UART. static FILE uartstd= FDEV_SETUP_STREAM(uart_char_tx, NULL,_FDEV_SETUP_WRITE); Chng ta to 1 bin tn uartstd (ngi dng t t tn ty ) c kiu l FILE (mt dng thit b o), sau dng macro FDEV_SETUP_STREAM khi to v ci t cc thng s cho uartstd. Macro ny c chc nng m 1 thit b xut nhp (fdevopen) v gn cc cng c cho vic xut nhp ra thit b. #define FDEV_SETUP_STREAM(put, get, rwflag) Cc thng s km theo FDEV_SETUP_STREAM bao gm 1 hm c bn gi l put, mt hm c bn gi l get v mt c ch chc nng xut hoc nhp ca thit b c m. C th, trong dng code 13, bin uartstd l mt thit b o c dng cho vic xut d liu (do thng s _FDEV_SETUP_WRITE). Cng c xut ra uartstd l hm uart_char_tx m chng ta to pha trn. Khng c hm nhn d liu v t uartstd (thng s get = NULL). Bn c th hnh dung th ny: bin uartstd l mt t giy, hm uart_char_tx l mt con du (stamp) cho php in mt k t ln t giy uartstd. Chng ta gn uart_char_tx cho usrtstd th sau ny tt c vic in n ln t giy uartstd s do con du uart_char_tx thc hin. Hm uart_char_tx v th gi l hm xut c bn. Tng t nh th, trong dng code 13 chng ta to 1 t giy khc tn lcdstd v hm c bn cho n l hm putChar_LCD, hm ny c nh ngha sn trong th vin myLCD.h. Cc dng code trong chng trnh chnh t dng 17 n 25 dng khi ng UART v TextLCD, bn c th xem li cc bi lin quan hiu thm. Sau khi khi ng, UART v LCD sn sng cho vic xut d liu. By gi chng ta c th dng cc hm trong th vin stdio nh printf hay sprint xut d liu. Bn hay quan st hnh 10 v ti s dng n so snh i chiu vi cc dng code sau. Dng 27 printf("In lan 1"), mc ch l in chui In lan 1 ln LCD bng hm printf. Tuy nhin, xem trn hnh 10 bn khng nhn thy chui ny xut hin. Xem tip dng code 28 fprintf(&lcdstd," www.hocavr.com ") v xem li hnh 10, ln ny bn thy chui k t www.hocavr.com xut hin trn LCD, ngha l vic in thnh cng vi hm fprintf. Hm fprintf l hm xut d liu ra mt thit b o, trong tham s th nht ca hm tr n thit b v tham s th hai l chui d liu cn in. Trong trng hp ny chng ta dng fprintf xut chui www.hocavr.com ra thit b o lcdstd v thnh cng. Vy vi hm printf dng 27 th sao? Hy kho st tip cc dng t 30 n 32. Dng 30 chng ta li mt ln na dng hm printf printf("In lan 3") in dng In lan 3 ln LCD nhng vn khng thnh cng (xem LCD trong hnh 10). dng 31 chng ta gn stdout=&lcdstd trong stdout l mt bin (tht ra l 1 stream hay mt thit b o) c sn ca ngn ng C, bin ny qui nh thit b mc nh dng cho vic xut nhp d liu, khi gn stdout tr n lcdstd nh dng 31 ngha l chng ta khai bo LCD l thit b xut nhp mc nh. V vy, trong dng 32 chng ta gi hm printf printf("In lan 4: %i", x) chng ta thnh cng. Ln ny, quan st trn LCD bn s thy dng In lan 4: 8205 xut hin. y 8205 l gi tr ca bin x trong cu lnh dng 32. Tm li, hm fprintf cho php in trc tip ra mt thit b o c ch nh trong khi mun dng hm printf chng ta cn gn thit b xut nhp mc nh trc cho bin stdout. Hy quan st on code t dng 34 n 37 v ba dng u trong Terminal hnh 10, chc chn bn t l gii c cc dng code ny. Cui cng l trnh phc v ngt nhn d liu ca UART trong cc dng code t 41 n 44. Trong trnh ny, chng ta ch thc hin vic n gin l in dng Ma ASCII: km theo l gi tr nhn v t UART cha trong thanh ghi UDR: fprintf(&uartstd,"Ma ASCII: %i\n", UDR). tm hiu y v th vin stdio trong WinAVR bn cn c ti liu avr-libc Manual, phn Standard IO facilities. Trong bi 2 chng ta s tm hiu v Terminal trn my tnh v cch vit chng trnh giao tip trn my tinh bng Visual Basic v Visual C++ 6.

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Ni dung Bi 1

Cc bi cn tham kho trc

C cho AVR. UART TextLCD M phng vi Proteus.

1. RS232 Terminal 2. Lp trnh giao tip vi cng COM bng VB v Visual

C++ Download v d

IV. RS232 Terminal RS232 Terminal l thut ng dng ch cc phn mm my tnh c kh nng nhn v pht d liu ra cng COM (nh mt thit b u cui). Cc RS232 Terminal rt ha dng kim tra cc chng trnh truyn nhn d liu qua cng COM. H iu hnh Windows c sn mt RS232 Terminal gi l Hyper Terminal. Cng c ny kh tt cho mc ch giao tip thng thng. s dng Hyper Terminal bn hy vo All Programs/ Accessories/Communications/Hyper Terminal hoc n gin l vo Run v g lnh hypertrm. Mt hp thoi c tn Connection Description xut hin, hy in mt tn bt k cho cuc gi v nhn OK. Trong hp thoi tip theo, Connect to, hy chn cng COM m bn mun giao tip, v nhn OK. Cui cng l hp thoi COM Properties cho php bn thit lp cc thng s giao tip nh Baudrate, Parity bit, Stop bit nh trong hnh 11, ch hy chn Flow control l "none"v nhn OK.

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Hnh 11. Thit lp cuc gi. Gi s bn chy chng trnh v d trong phn demo ca stdio, bn thu c giao din HyperTerminal nh trong hnh 12.

Hnh 12. Giao din Hyper Terminal. Trong bi hc ny, ti gii thiu mt chng trnh Terminal c tn Hercules ca HW group (http://www.hw-group.com/products/hercules/index_en.html). y l mt Terminal min ph rt tt, d s dng v n nh. Ngoi chc nng RS232 Terminal, Hercules cn c dng cho cc giao din khc nh TCP, UDPBn ch cn download chng trnh v v chy file Hercules.exe. Bn thu c giao din Hercules nh sau:

Hnh 13. Giao din phn mm Hercules. Hy chn tab Serial giao tip vi cng COM, thit lp cc thng s nh tn cng, Baudrate, Data frameri nhn nt Open, bn sn sng s dng Hercules. Gi s bn c 3 cng COM o tn l COM2, COM3 ni vi nhau. Hy s dng v d trong phn stdio,

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trong mch in m phng Proteus ca v d hy xa thit b o Terminal. Hy thm vo mt thit b tn l COMPIM bng cch search vi keyword l COMPIM (hoc chy file AVR_STD_Terminal.DSN trong th mc AVR_STD ca v d trn). Kt ni nh trong hnh 14. Sau right click vo COMPIM vo hp thoi Edit component, i thng s Physical port thnh CM, i Virtual Baud Rate thnh 38400. Chy li m phng bn s thy kt qu hin th trn Hercules nh trong hnh 14. Type 1 phm bt k thy m ASCII. y l v d cho php bn giao tip gia chng trnh AVR m phng trong Proteus v ng dng chy trn Windows thng qua cc cng COM o. N thc cht l mt dng giao tip my tnh bng cng COM, dnh cho trng hp bn cha c mch AVR tht. Mu cht nm thit b COMPIM trong Proteus. COMPIM thc cht l m hnh cng COM tn ti trn my tnh ca bn. Trong trng hp ny chng ta dng Eltima VSPE (hoc VSPD) to 2 cng COM o trn my tnh l COM2 v COM3, chng c u cho vi nhau. Chng ta set COMPIM trong Proteus l COM2 trong khi cng trn Hercules l COM3. Khi chy m phng, AVR s gi d liu ra COMPIM (tc COM2), COM2 truyn n COM3 v hin th trn Hercules. Chng ta c th t vit cc chng trnh trn Windows nhn v gi gi tr qua COM thay cho Hercules. Trong phn tip theo ti s hng dn bn to chng trnh nh th.

Hnh 14. Kt hp m phng v Hercules. V. Lp trnh giao tip vi cng COM bng Visual Basic v Visual C++ Cc chng trnh Terminal cp trn l mt dng ng dng giao tip gia my tnh v vi iu khin mc n gin. Trong nhiu trng hp, yu cu giao tip i hi mc phc tp cao hn, v d lu tr d liu hay v th bin thin, th ngi dng cn phi t vit cc chng trnh trn my tnh ca ring mnh. Phn ny ti hng dn bn cc vit chng trnh trn my tnh truyn v nhn d liu t cng

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COM bng 2 ngn ng lp trnh Visual Basic v Visual C++ (6.0) trn nn Windows. Ch , mc ch bi vit ny l v AVR nn phn vit ng dng trn Windows ti ch trnh by mt cch n gin ct cho bn nm c nguyn l. pht trin cc ng dng phc tp hn ngi c cn t trang b cho mnh kin thc v lp trnh trn Windows. Trong tt c cc hng dn bn di ti gi s l ngi c t nht bit c cch to Project trong Visual Basic hoc/v Visual C++. 1. Vit chng trnh giao tip cng COM bng Visual Basic 6.0 K t cc phin bn Windows 2000 v sau, vic giao tip vi cc cng my tnh truyn thng, nh cng LPT, trong Windows tng i kh khn. Tuy nhin, vi cng COM th c iu may mn l Microsoft c cung cp mt cng c (tht ra l mt control iu khin) c tn gi l Microsoft Communication Control hay vit tt l MSComm. MSComm xut hin trong cc phn mm lp trnh ni ting ca MS nh Visual Basic hay Visual C++ di dng mt iu khin. V l mt iu khin c thit k sn cho cng COM nn MSComm cha tt c cc cng c cn thit giao tip vi cng ny, cng vic ca ngi vit chng trnh ch n gin l khai bo v s dng. minh ha cch s dng MSComm trong Visual Basic, hy lm theo hng dn bn di. Chy Visual Basic 6, vo menu File/New Project v to mt Standard EXE. Bn s thy mt Project c tn l Project1 km mt hp thoi nn (form chnh) c tn Form1 xut hin. Bn c th t tn bt k cho Project v form chnh. Hy quan st v d trong hnh 15. T thanh cng c Toolbox hy click vo control textbox v v ln form chnh 2 textbox tn l txtOuput v txtInput (xem hnh 15) (i tn cc textbox trong ca s Properties nm gc thp, bn phi). vi txtOutput, hy set thng s Multiple thnh True v ScrollBars thnh 3 Both

Hnh 15. Giao din Visual Basic 6. Tip theo hy a control MSComm vo form chnh. Theo mc nh, control MSComm khng c sn trong Toolbox ca Visual Basic, chng ta cn thm vo Toolbox trc khi s dng. thm MSComm vo Toolbox, chn Menu Project/Components bn s thy mt hp thoi tn Components xut hin nh trong

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hnh 16. Tm v click chn vo Microsoft Comm Control 6.0 nh trong hnh v nhn OK. Lc ny, quan trong Toolbox ca VB bn s thy icon ca MSComm xut hin. Click vo icon ny v v 1 i tng MSComm ln form chnh (xem li hnh 15). Gi tn mc nh ca i tng ny l MSComm1.

Hnh 16. Thm cng c MSComm vo Project.

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Vit code: Mc ch ca v d ny nh sau: d liu nhn v t cng COM s hin th trn textbox txtOutput, v khi ngi dng type 1 k t vo txtInput k t s c truyn i qua cng COM. Trc ht, hy doubleclick vo form chnh, vit on code sau vo s kin Form_Load():

Mc ch ca on code ny l ci t cc thng s cho MSComm1. - Thng s CommPort = 3 ngha l chng ta mun kt ni vi cng COM3. Thng s ny do ngi dng thay i ty theo cng COM chng ta mun giao tip. - Thng s Setting = 38400, N, 8,1 ngha l tc Baud=38400, khng s dng bit Parity, di khung truyn bng 8 v c 1 bit Stop. - RThreshold = 1 ngha l khi c 1 k t n cng COM, ngt nhn d liu s xy ra. - InputLen = 1 ngha l khi c d liu t b m nhn, chng ta s c ln lt 1 k t (1 byte). - PortOpen = True tc cho php m cng COM sn sng giao tip. Tip theo, doubleclick vo biu tng ca MSComm1 trn form chnh vit code vo s kin MSComm1_onComm():

S kin onComm() thc cht l trnh phc v ngt nhn d liu ca MSComm. Khi c 1 byte d liu gi n b m ca cng COM (s lng byte do RThreshold quy nh) th s kin onComm s xy ra (ngt xy ra), trong s kin ny chng ta s vit code nhn v x l d liu. Dng 2 chng ta khai bo 1 bin tm thi tn l InputText vi kiu d liu string. Ch l s kin onComm c th xy ra do nhiu nguyn nhn, y chng ta ch quan tm n trng hp d liu truyn n, dng 3 l mt dng lc s kin, chng ta ch thc hin cc dng code bn trong khi m s kin comEvReceive xy ra (d liu c nhn v): If Me.MSComm1.CommEvent = comEvReceive Then. Vic quan trng duy nht c d liu c gi n COM l c b m Input ca MSComm nh trong dng code 4: InputText = MSComm1.Input. Sau dng lnh ny d liu s c cha trong bin tm InputText. Tip theo chng ta ch cn cng dn cc k t nhn v vo ni dung ca Textbox txtOutput hin th ln mn hnh (dng 5) : txtOutput.Text = txtOutput.Text + InputText. Dng code 6 lm nhim v a con tr n cui ni dung ca txtOutput tin cho vic quan st d liu. Cui cng, doubleclick vo Textbox txtInput v tm s kin KeyPress vit cc dng code sau:

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S kin txtInput_KeyPress xy ra khi ngi dng nhn 1 phm no vo txtInput. Dng code Me.MSComm1.Output = Chr(KeyAscii) thc hin vic gi gi tr ca KeyAscii ra cng COM, trong KeyAscii l m Ascii ca phm c nhn. Bn hon tt vit chng trnh truyn nhn d liu qua cng COM bng Visual Basic. kim tra chng trnh ca bn, hy thc hin m phng theo cc bc sau: - Dng 1 trong 2 phn mm VSPD hoc VSPE to 2 cng COM o l COM2 v COM3, u cho chng vi nhau (xem li phn cng COM o). - Tm trong th mc cha v d AVR_STD v chy file m phng bng phn mm Proteus AVR_STD_Terminal.DSN. - Quay li Visual Basic, nhn nt Run hoc F5 chy Project va mi vit. - Nhn Run trong Proteus m phng mch in AVR_STD_Terminal.DSN. Bn s thy kt mt s text xut hin trng txtOutput nh trong hnh 17. Click vo txtInput v type bt k mt phm no xem kt qu. So snh vi m phng trong hnh 14 bn thy nt tng ng. Nh th bn thnh cng khi t vit cho mnh 1 ng dng giap tip vi cng COM bng Visual Basic. 2. Vit chng trnh giao tip cng COM bng Visual C++ 6.0 Phn ny chng ta s thc hin mt v d truyn nhn qua cng COM tng t nh v d phn trn nhng s dng Visual C++ (VC++) ca Microsoft. Mc ch chnh l hng dn cch s dng MSComm trong VC++, v th ti s trnh by rt s si nhng phn nh to Project trong VC++. Bn c cn t trang b thm kin thc v lp trnh VC++. Mt trong nhng ti liu rt hay cho ngi mi hc lp trnh VC l Teach Yourself Visual C++ 6 in 21 Days ca Sams Teach Yourself, bn c th tm c nu thy cn thit. T VC++ hy vo menu File/New to 1 Project mi. Chn loi Project l MFC AppWizard (exe), trong Project Name t tn cho Project l AVR_PC, nhn OK. Trong hp thoi th 2 hy chn Dialog based cho loi Project, v nhn Finish to Project (cc bc khc mc nh).

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Hnh 17. To Project MFC trong VC++6. Khi Project mi c to s c 1 hp thoi chnh (Dialog) xut hin vi 2 button OK v Cancel trn . Dng cng c Edit thm vo 2 Edit box v sp xp li giao din nh hnh 19. Right click vo cc Edit box v chn Proterties t cc Popup_menu, ln lt i ID ca 2 Edit box thnh IDC_OUTPUT v IDC_INPUT. Cng ging nh trong VB, Control MSComm khng xut hin mc nh trong Toolbox ca VC++, chng ta cn thm vo khi mun s dng control ny. Hy vo menu Project/Add to Project/ Components and Controls. Khi hp thoi Components and Control Gallery xut hin bn chn vo th mc Registered ActiveX Controls v tm n file Microsoft Communications Control, Version 6.0 ri nhn nt insert, nhn OK khi c hi bt k cu hi g, sau nhn nt Close ng hp thoi li. Lc ny icon ca MSComm s xut hin trong Toolbox ca VC++ nh trong hnh 19. Click chn icon ca MSComm v v 1 control vo Dialog chnh ca Project. Theo mc nh Control ny c tn IDC_MSCOMM1.

Hnh 18. Thm Control MSComm vo Toolbox trong VC++.

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Hnh 19. Giao din chng trnh trong Visual C++. Vic lp trnh trong VC++ tng i kh hn VB (cho ngi mi tm hiu). Cc thuc tnh ca cc Control nh Edit box khng c truy cp trc tip nh Textbox trong VB. V d gn v hin th mt chui hay s ln Edit box chng ta phi thc hin gn v cp nht d liu qua cc bin trung gian. bc ny chng ta i to 2 bin cho 2 Edit box. Nhn vo menu View/ClassWizard hoc t hp phm Ctrl+W , trong hp thoi MFC ClasWizard hy chn tab Member Variables. Click vo dng IDC_OUTPUT (chnh l edit pha trn), nhn vo nt Add vatiable v in tn bin l m_txtOutput vi kiu bin l CString nh trong hnh 20. Lp li cc bc trn to 1 bin tn m_txtInput cho IDC_INPUT. Cui cng l to 1 bin c tn m_comm cho IDC MSCOMM1. Nhn OK ng hp thoi MFC ClassWizard. T by gi, chng ta ch cn nh 3 bin m_txtOutput, m_txtInput, m_comm khi mun truy cp cc Edit boxes v MSComm trong lc vit code.

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Hnh 20. To bin txtOutput cho Edit box IDC_OUTPUT. Vit Code: Nhn Ctrl+W m li ClassWizard, ln ny chn tab Message Maps", trong Class name m bo rng CAVR_PCDlg c chn. Trong Object IDS hy chn "CAVR_PCDlg, Messages tm v chn "WM_INITDIALOGS sau nhn vo nt Edit Code (xem hnh 21).

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Hnh 21. Bt u vit code. By gi bn c th vit code cho s kin OnInitDilaog(), y l s kin xy ra khi bn chy chng trnh v Dialog chnh c khi ng. V th chng ta s ci t cc thng s cho m_comm vo y (m_comm l tn bin i din cho control IDC_MSCOMM1 m chng ta to cc bc trn). Hy thm cc dng sau vo sau dng // TODO: Add extra initialization here:

Nm dng code trn tng ng vi 5 dng trong phn Form_Load() khi vit Project bng VB m chng ta kho st trn, v th ti khng cn gii thch thm cho cc dng code ny. Tip theo chng ta s vit code cho s kin onComm (ngt nhn) ca control MSComm, trc khi vit code hy nhn Ctrl+W hin hp thoi ClassWizard v thc hin 6 bc nh trong hnh 22 thm s kin onComm vo Project.

Hnh 22. Thm s kin onComm nhn d liu t cng COM.

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Vit on code sa vo s kin onComm:

Nh trnh by trn, m_comm l bin i din cho MSComm vic thao tc vi cng COM by gi thc hin thng qua bin m_comm. Trong dng 4 chng ta khai bo 1 bin ph strInput c kiu CString dng cha gi tr nhn v sau ny. Cng ging nh trong VB, s kin onComm c th xy ra do nhiu nguyn nhn, chng ta ch quan tm n trng hp c d liu n b m, dng 5 cho php lc ra s kin cn thit: if (m_comm.GetCommEvent()==2 ). Dng 6 chng ta khai bo 1 bin ph tn in_dat vi kiu COleVariant. COleVariant l lp (class) ca MFC, tn gi ca n l s kt hp ca C + OLE +VARIANT trong OLE l Object Linking Embedded l mt kiu i tng khng c sn m c nhng vo, MSComm l mt loi OLE. VARIANT l mt kiu bin cha xc nh. Khi bn c mt bin x, i khi bn mun gn gi tr s cho x nhng cng c khi bn li mun gn chui k t cho x. Khi hy khai bao x l VARIANT. Trong trng hp MSComm, d liu vo v ra ca i tng ny thuc dng cha xc nh hay VARIANT. Trong dng 7 chng ta ch n gin nhn gi tr t m_comm v bin in_dat: in_dat = m_comm.GetInput(). Dng tip theo chng ta trch thnh phn chui k t t bin in_dat v gn cho bin strInput: strInput=in_dat.bstrVal (mt cch tng i c th hiu i in_dat thnh CString v gn cho strInput). Chng ta phi trch CString v cc Edit box ch hin th c CString. hin th d liu nhn v ln Edit box (IDC_OUTPUT) chng ta cng dn bin m_txtOutput (bin i din ca Edit box IDC_OUTPUT) bng dng lnh 9: m_txtOutput+=strInput. Cui cng, cho gi tr ca bin m_txtOutput cp nht ln Edit box chng ta phi gi hm UpdateData vi tham s FALSE nh dng 10: UpdateData(FALSE) (y l cch lm vic ca Visual C++). Cc dng code t 12 n 14 c dng vi mc ch a con tr v cui dng ca Edi box sau khi kt thc qu trnh nhn d liu. Bn c th b qua nu thy khng cn thit. Vic cui cng l vit code cho Edit box bn di (IDC_INPUT) khi chng ta g (type) vo y, k t s c gi n cng COM. Nhn Ctrl+W v thc hin cc bc bn di thm vo s kin onChange.

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Hnh 23. Thm s kin onChange cho IDC_INPUT. Hy vit on code sau vo s kin onChange ca Edit box Input:

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Khi ngi dng type 1 k t no vo Edit box, s kin onChange xy ra, khi chng ta s trch k t cui cng trong ni dung ca Edit box bn di m i din l bin m_txtInput bng dng lnh 11: tmpStr=m_txtInput.Right(1). Trong tmpStr l mt bin tm khai bo dng 9. Ch rt quan trong khi mun c ni dung ca Edit box chng ta cn gi hm UpdateData vi tham s TRUE trc nh trong dng 10. Sau cng, gi phng phng thc SetOutput ca i tng MSComm gi gi tr ra cng COM: m_comm.SetOutput(COleVariant(tmpStr)). gi mt k t (hay chui k t) ra cng COM trc ht chng ta cn p kiu k t v COleVariant v nh trnh by, MSComm ch lm vic vi COleVaraint. on COleVariant(tmpStr) thc hin vic p kiu ny. Sau khi vit xong on code cho s kin onChange bn c th nhn t hp phm Ctrl+F5 chy chng trnh. Dng mch in AVR_STD_Terminal.DSN v chy m phng nh trong phn lp trnh vi VB. Kt qu thu c s nh trong hnh 24.

Hnh 24. Giao tip gia AVR v Visual C++.

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iu khin ng c DC servo (PID) Ni dung Cc bi cn tham kho trc Gii thiu Incremental Optical Encoder Chip driver L298D Mch logic cho L298D Gii thut iu khin PID iu khin DC Motor bng AVR

1. 2. 3. 4. 5. 6.

Cu trc AVR. WinAVR. C cho AVR. M phng vi Proteus.

Download v d

I. Gii thiu iu khin ng c DC (DC Motor) l mt ng dng thuc dng c bn nht ca iu khin t ng v DC Motor l c cu chp hnh (actuator) c dng nhiu nht trong cc h thng t ng (v d robot). iu khin c DC Motor l bn c th t xy dng c cho mnh rt nhiu h thng t ng. Khi nim Servo m ti dng trong bi hc ny ch mt h thng hi tip. DC servo motor l ng c DC c b iu khin hi tip. Bi ny l mt bi tng hp nhiu vn ng dng AVR bao gm nhn d liu t ngi dng, iu khin motor, c encoder, hin th LCD, c gii thut iu khin PID v mch cng sut cho MotorDo , t nht bn phi nm c cc vn c bn nh Timer-Counter, TexLCD, mch cu H. Phn cn li ti s gii thch trong lc hc bi ny. C 2 phng php iu khin ng c DC l analog v digital. Mc ch chnh ca chng ta l dng AVR iu khin ng c DC nn phng php s m c th l phng php iu rng xung (PWM) s c gii thiu. Ngoi ra, khi ni n iu khin ng c DC c 2 i lng iu khin chnh l v tr (s vng quay) v vn tc. Trong phn gii thch v b iu khin PID ti s iu khin v tr lm v d, tuy nhin trong phn v d lp trnh cho AVR chng ta s thc hin iu khin vn tc cho DC Motor. Bng cch ny, bn c th t tin m rng v d iu khin cho c 2 i lng. V l iu khin mt cch t ng nn chng ta cn c v i lng iu khin (c th l v tr hoc vn tc motor) v hi tip (feedback) v hiu chnh PWM cp cho ng c. Chng ta s dng incremental optical encoder c s vng quay v hi tip v cho AVR. B iu khin PID s c dng v vn hnh bi AVR. Tng qut, bi hc ny bao gm: - AVR pht PWM iu chnh vn tc ng c: phn ny bn xem li bi 4 v Timer-Counter. iu c bn cn nm l bng cch thay i rng ca xung PWM chng ta s thay i c vn tc Motor. - Xung PWM khng trc tip lm quay ng c m thng qua mt mch cng sut gi l dirver. Driver cho DC Motor chnh l mch cu H m chng ta tm hiu trong bi Mch cu H. Trong bi hc ny, ti gii thiu mt chip c tch hp sn mch cu H, chip L298D. - vic iu khin chip driver L298D d dng, chng ta s to mt mch logic dng cc cng NOT v AND.

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- ng c DC m chng ta s dng c tch hp sn mt encoder 3 ng ra, chng ta s dng AVR c s xung (hay s vng quay) v tnh ra vn tc ca Motor. Vic c encoder s c thc hin bng ngt ngoi. - Mt gii thut PID c xy dng trong AVR hiu chnh vn tc ng c. - Ngi dng s nhp vn tc cn iu khin vo AVR thng qua cc switches. Vn tc mong mun v vn tc thc ca ng c c hin th trn Text LCD. Mch in v d c trnh by trong hnh 1.

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Hnh 1. H thng iu khin ng c DC servo. Trong mch in hnh 1, ti chia h thng thnh 3 nhm: nhm CONTROL bao gm AVR vn hnh gii thut iu khin PID v vic nhp, xut. Nhm LOGIC thc hin vic bin i cc tn hiu iu khin to

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ra cc tn hiu ph hp cho chip driver. Nhm POWER bao gm chip driver L298D v DC Motor. Ngoi ra cn c mt Encoder c tch hp sn trn DC Motor. Phn tip theo chng ta s tm hiu ring tng nhm, cui cng l vit chng trnh cho AVR iu khin h thng DC Servo Motor II. Incremental Optical Encoder iu khin s vng quay hay vn tc ng c th chng ta nht thit phi c c gc quay ca motor. Mt s phng php c th c dng xc nh gc quay ca motor bao gm tachometer (tht ra tachometer o vn tc quay), dng bin tr xoay, hoc dng encoder. Trong 2 phng php u tin l phng php analog v dng optiacal encoder (encoder quang) thuc nhm phng php digital. H thng optical encoder bao gm mt ngun pht quang (thng l hng ngoi infrared), mt cm bin quang v mt a c chia rnh. Optical encoder li c chia thnh 2 loi: encoder tuyt i (absolute optical encoder) v encoder tng i (incremental optical encoder). Trong a s cc DC Motor, incremental optical encoder c dng v m hnh ng c servo trong bi ny cng khng ngoi l. T by gi khi ti ni encoder tc l incremental encoder. Hnh 2 l m hnh ca encoder loi ny.

Hnh 2. Optical Encoder (trch t [1]). Encoder thng c 3 knh (3 ng ra) bao gm knh A, knh B v knh I (Index). Trong hnh 2 bn thy hy ch mt l nh bn pha trong ca a quay v mt cp phat-thu dnh ring cho l nh ny. l knh I ca encoder. C mi ln motor quay c mt vng, l nh xut hin ti v tr ca cp pht-thu, hng ngoi t ngun pht s xuyn qua l nh n cm bin quang, mt tn hiu xut hin trn cm bin. Nh th knh I xut hin mt xung mi vng quay ca motor. Bn ngoi a quay c chia thnh cc rnh nh v mt cp thu-pht khc dnh cho cc rnh ny. y l knh A ca encoder, hot ng ca knh A cng tng t knh I, im khc nhau l trong 1 vng quay ca motor, c N xung xut hin trn knh A. N l s rnh trn a v c gi l phn gii (resolution) ca encoder. Mi loi encoder c phn gii khc nhau, c khi trn mi a ch c vi rnh nhng cng c trng hp n hng nghn rnh c chia. iu khin ng c, bn phi bit phn gii ca encoder ang dng. phn gii nh hng n chnh xc iu khin v c phng php iu khin. Khng c v trong hnh 2, tuy nhin trn cc encoder cn c mt cp thu pht khc c t trn cng ng trn vi knh A nhng lch mt cht (lch M+0,5 rnh), y l knh B ca encoder. Tn hiu xung t knh B c cng tn s vi knh A nhng lch pha 90o. Bng cch phi hp knh A v B ngi c s bit chiu quay ca ng c. Hy quan st hnh 3.

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Hnh 3. Hai knh A v B lch pha trong encoder (trch t [1]) Hnh trn cng trong hnh 3 th hin s b tr ca 2 cm bin knh A v B lch pha nhau. Khi cm bin A bt u b che th cm bin B hon ton nhn c hng ngoi xuyn qua, v ngc li. Hnh thp l dng xung ng ra trn 2 knh. Xt trng hp motor quay cng chiu kim ng h, tn hiu i t tri sang phi. Bn hy quan st lc tn hiu A chuyn t mc cao xung thp (cnh xung) th knh B ang mc thp. Ngc li, nu ng c quay ngc chiu kim ng h, tn hiu i t phi qua tri. Lc ny, ti cnh xung ca knh A th knh B ang mc cao. Nh vy, bng cch phi hp 2 knh A v B chng ta khng nhng xc nh c gc quay (thng qua s xung) m cn bit c chiu quay ca ng c (thng qua mc ca knh B cnh xung ca knh A). Cu hi by gi l lm th no c encoder bng AVR? Ty theo i lng iu khin (v tr hay vn tc) v c im encoder ( phn gii) chng ta c cc gii php sau c encoder bng AVR - Dng input capture: mt s b timer-counter trn AVR c chc nng Input capture, hiu nm na nh sau. C mi ln c mt tn hiu (cnh ln hoc cnh xung) trn chn ICP (Input Capture Pin), gi tr thi gian ca timer c t ng gn cho thanh ghi ICR (Input capture Register). So snh gi tr thanh ghi ICR trong 2 ln lin tip s c c chu k ca tn hiu kch chn ICP. T suy ra tn s tn hiu. Nu mt knh ca encoder c ni vi chn ICP th chng ta c th o c tn s tn hiu ca knh ny. Ni cch khc, chng ta s tnh c vn tc ca ng c. Chng ta c th dng ngt Input capture v khi ngt xy ra, c th m s thm s xung bit c gc quay motor, cng c th xc nh c hng quay thng qua xc nh mc knh B trong trnh phc v ngt input capture. y l mt phng php hay, nhng c nhc im l kh phc tp khi s dng chc nng input capture ca AVR. Mc khc trn cc chip AVR t mega32 tr xung, Input capture ch c timer 1, trong khi Timer ny thng dng to PWM iu khin ng c. - Dng chc nng counter: t cc knh ca encoder vo cc chn m (T0, T1) ca cc b timer chng ta s m c s lng xung ca cc knh. y l phng php s dng t ti nguyn nht (t tn thi gian cho encoder). Nhc im ln nht ca phng php ny l khng xc nh c chiu quay, mc khc phng php ny khng n nh khi vn tc ng c c s thay i ln. - Cui cng l s dng ngt ngoi: y l phng php d nhng chnh xc c encoder v cng l phng php c dng trong bi hc ny. tng ca phng php rt n gin, chng ta ni knh A ca encoder vi 1 ngt ngoi (INT2 chng hn) v knh B vi mt chn no bt k (khng phi chn ngt). C mi ln ngt ngoi xy ra, tc c 1 xung xut hin trn knh A th trnh phc v ngt ngoi t ng

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c gi. Trong trnh phc v ngt ny chng ta kim tra mc ca knh B, ty theo mc ca knh B chng ta s tng bin m xung ln 1 hoc gim i 1. Tuy nhin, bn cn phi tnh ton rt cn thn khi s dng phng php ny. V d trng hp encoder c phn gii 2000 xung/vng, motor bn quay vi vn tc 100 vng/s th tn s xung trn knh A ca encode l 2000x100=200KHz, ngha l c mi 5 us ngt ngoi xy ra mt ln. Tn s ngt nh th l qu cao cho AVR, iu ny c ngha l AVR ch tp trung cho mi vic m xung, khng c thi gian thc thi cc vic khc. Trong bi ny, chng ta chn phn gii ca encoder l 112 (112 xung trn mi vng quay). Vn tc ti a ca ng c c chn vo khong 30 vng/s nn tn s xung ln nht t encoder l 112x30=3.36KHz. Gi tr ny hp l v tn s cho AVR trong bi ny c chn 8MHz. Knh A ca encoder c ni vi ngt INT2 ca chip atmega32, knh B c ni vi chn PB0, chng ta khng s dng knh I (xem hnh 1). Ch : cc ng ra trn a s (gn nh tt c) cc encoder c dng cc gp h (Open collector), mun s dng chng cn mc in tr ko ln VCC (5V). III. Chip driver L298D L298D l mt chip tch hp 2 mch cu H trong gi 15 chn. Tt c cc mch kch, mch cu u c tch hp sn. L298D c in p danh ngha cao (ln nht 50V) v dng in danh ngha ln hn 2A nn rt thch hp cho cc cc ng dng cng sut nh nh cc ng c DC loi nh v va. V l loi all in one nn l la chn hon ho cho nhng ngi cha c nhiu kinh nghim lm mch in t. Trong bi hc ny ti dng chip L298D lm driver cho motor. Hnh 4 th hin m hnh tht ca chip v cu trc bn trong chip.

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Hnh 4. Chip L298D Hnh pha trn l hnh dng bn ngoi v tn gi cc chn ca L298D. Hnh pha di l cu trc bn trong chip. C 2 mch cu H trn mi chip L298D nn c th iu khin 2 i tng ch vi 1 chip ny. Mi mch cu bao gm 1 ng ngun Vs (tht ra l ng chung cho 2 mch cu), mt ng current sensing (cm bin dng), phn cui ca mch cu H khng c ni vi GND m b trng cho ngi dng ni mt

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in tr nh gi l sensing resistor. Bng cch o in p ri trn in tr ny chng ta c th tnh c dng qua in tr, cng l dng qua ng c (xem hnh 4). Mc ch chnh ca vic o dng in qua ng c l xc nh cc trng hp nguy him xy ra trong mch, v d qu ti. Nu vic o dng ng c khng tht s cn thit bn c th ni ng current sensing ny vi GND (trong mch in ca bi ny, ti ni chn current sensing vi GND). ng c s c ni vi 2 ng OUT1, OUT2 (hoc OUT3, OUT4 nu dng mch cu bn phi). Mt chn En (EnA v EnB cho 2 mch cu) cho php mch cu hot ng, khi chn En c ko ln mc cao, mch cu sn sang hot ng. Cc ng kch mi bn ca mch cu c kt hp vi nhau v nhng mc in p ngc nhau do mt cng Logic NOT. Bng cch ny chng ta c th trnh c trng hp 2 transistor cng mt bn c kch cng lc (ngn mch). Nh vy, s c 2 ng kch cho mi cu H gi l In1 v In2 (hoc In3, In4). motor hot ng chng ta phi ko 1 trong 2 ng kch ny ln cao trong khi ng kia gi mc thp, v d In1=1, In2=0. Khi o mc kch ca 2 ng In, ng c s o chiu quay. Tuy nhin, do L298D khng ch c dng o chiu ng c m cn iu khin vn tc ng c bng PWM, cc ng In cn c t hp li bng cc cng Logic (xem phn tip theo). Ngoi ra, trn chip L298D cn c cc ng Vss cp in p cho phn logic (5V) v GND chung cho c logic v motor. Trong thc t, cng sut thc m L298D c th ti nh hn so vi gi tr danh ngha ca n (V=50V, I=2A). tng dng in ti ca chip ln gp i, chng ta c th ni 2 mch cu H song song vi nhau (cc chn c chc nng nh nhau ca 2 mch cu c ni chung). II. Mch logic cho L298D Thng thng, khi thit k mt mch driver cho motor ngi ta thng dnh 3 ng iu khin l PWM dng iu khin vn tc, DIR iu khin hng v En cho php mch hot ng. Chip L298D c sn ng En nhng 2 ng iu khin In1 v In2 khng tht s chc nng nh chng ta mong mun. V th, chng ta s thit k mt mch logic ph vi 2 ng vo l PWM v DIR trong khi 2 ng ra l 2 ng iu khin In1 v In2. Bng chn tr ca mch logic cn thit k c trnh by trong bng 1. Bng 1. bng chn tr ca mch logic cho driver L298D. PWM 0 0 1 1 DIR 0 1 0 1 In1 0 0 1 0 In2 0 0 0 1

T bng chn tr ny, chng ta c th vit hm bool cho 2 ng In1 v In2: In1=PWM.NOT(DIR) In2=PWM.DIR Mch logic v th s c dng nh trong hnh 5.

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Hnh 5. Mch logic cho L239 Ti s khng gii thch chi tit phn ny, tuy nhin iu bn cn nm l vi mch logic ny, ng DIR c chc nng o chiu ng c trong khi ng PWM iu khin vn tc ng c bng tn hiu PWM. V. Gii thut iu khin PID PID l cch vit tc ca cc t Propotional (t l), Integral (tch phn) v Derivative (o hm). Tuy xut hin rt lu nhng n nay PID vn l gii thut iu khin c dng nhiu nht trong cc ng dng iu khin t ng. gip bn c ci hiu r hn bn cht ca gii thut PID ti s dng mt v d iu khin v tr ca mt car (xe) trn ng thng. Gi s bn c mt xe ( chi...) c gn mt ng c DC. ng c sinh ra mt lc y xe chy ti hoc lui trn mt ng thng nh trong hnh 6.

Hnh 6. V d iu khin v tr xe trn ng thng Gi F l lc do ng c to ra iu khin xe. Ban u xe v tr A, nhim v t ra l iu khin lc F (mt cch t ng) y xe n ng v tr O vi cc yu cu: chnh xc (accurate), nhanh (fast response), n nh (small overshot). Mt iu rt t nhin, nu v tr hin ti ca xe rt xa v tr mong mun (im O), hay ni cch khc sai s(error) ln, chng ta cn tc ng lc F ln nhanh chng a xe v O. Mt cch n gin cng thc ha tng ny l dng quan h tuyn tnh: F=Kp*e (1)

34

Trong Kp l mt hng s dng no m chng ta gi l h s P (Propotional gain), e l sai s cn iu khin tc khong cch t im O n v tr hin ti ca xe. Mc tiu iu khin l a e tin v 0 cng nhanh cng tt. R rng nu Kp ln th F cng s ln v xe rt nhanh chng tin v v tr O. Tuy nhin, lc F qu ln s gia tc cho xe rt nhanh (nh lut II ca Newton: F=ma). Khi xe n v tr O (tc e=0), th tuy lc F=0 (v e=0) nhng do qun tnh xe vn tip tc tin v bn phi v lch im O v bn phi, sai s e li tr nn khc 0, gi tr sai s lc ny c gi l overshot (vt qu). Lc ny, sai s e l s m, lc F li xut hin nhng vi chiu ngc li ko xe v li im O. Nhng mt ln na, do Kp ln nn gi tr lc F cng ln v c th ko xe lch v bn tri im O. Qu trnh c tip din, xe c mi sao ng quanh im O. C trng hp xe dao ng cng ngy xng xa im O. B iu khin lc ny c ni l khng n nh. Mt xut nhm gim overshot ca xe l x dng mt thnh phn thng trong b iu khin. S rt l tng nu khi xe ang xa im O, b iu khin sinh ra lc F ln nhng khi xe tin gn n im O th thnh phn thng s gim tc xe li. Chng ta iu bit khi mt vt dao ng quanh 1 im th vt c vn tc cao nht tm dao ng (im O). Ni mt cch khc, gn im O sai s e ca xe thay i nhanh nht (cn phn bit: e thay i nhanh nht khng phi e ln nht). Mc khc, tc thay i ca e c th tnh bng o hm ca bin ny theo thi gian. Nh vy, khi xe t A tin v gn O, o hm ca sai s e tng gi tr nhng ngc chiu ca lc F (v e ang gim nhanh dn). Nu s dng o hm lm thnh phn thng th c th gim c overshot ca xe. Thnh phn thng ny chnh l thnh phn D (Derivative) trong b iu khin PID m chng ta ang kho st. Thm thnh phn D ny vo b iu khin P hin ti, chng ta thu c b iu khin PD nhu sau: F=Kp*e + Kd*(de/dt) (2) Trong (de/dt) l vn tc ca sai s e v Kd l mt hng s khng m gi l h s D (Derivative gain). S hin din ca thnh phn D lm gim overshot ca xe, khi xe tin gn v O, lc F gm 2 thnh phn Kp*e > =0 (P) v Kd*(de/dt) <=0 (D). Trong mt s trng hp thnh phn D c gi tr ln hn thnh phn P v lc F i chiu, thng xe li, vn tc ca xe v th gim mnh gn im O. Mt vn ny sinh l nu thnh phn D qu ln so vi thnh phn P hoc bn thn thnh phn P nh th khi xe tin gn im O (cha tht s n O), xe c th dng hn, thnh phn D bng 0 (v sai s e khng thay i na), lc F = Kp*e. Trong khi Kp v e lc ny u nh nn lc F cng nh v c th khng thng c lc ma st tnh. Bn hy tng tng tnh hung bn dng sc ca mnh y mt xe ti nng vi chc tn, tuy lc y tn ti nhng xe khng th di chuyn. Nh th, xe s ng yn mi d sai s e vn cha bng 0. Sai s e trong tnh hung ny gi l steady state error (tm dch l sai s trng thi tnh). trnh steady state error, ngi ta thm vo b iu khin mt thnh phn c chc nng cng dn sai s. Khi steady state error xy ra, 2 thnh phn P v D mt tc dng, thnh phn iu khin mi s cng dn sai s theo thi gian v lm tng lc F theo thi gian. n mt lc no , lc F ln thng ma st tnh v y xe tin tip v im O. Thnh phn cng dn ny chnh l thnh phn I (Integral - tch phn) trong b iu khin PID. V chng ta iu bit, tch phn mt i lng theo thi gian chnh l tng ca i lng theo thi gian. B iu khin n thi im ny y l PID: F=Kp*e + Kd*(de/dt)+Ki*edt (3) (du c ti dng thay cho du tch phn, edt l tch phn ca bin e theo t) Nh vy, chc nng ca tng thnh phn trong b iu khin PID gi r. Ty vo mc ch v i tng iu khin m b iu khin PID c th c lt bt tr thnh b iu khin P, PI hoc PD. Cng vic chnh ca ngi thit k b iu khin PID l chn cc h s Kp, Kd v Ki sao cho b iu khin hot ng tt v n nh (qu trnh ny gi l PID gain tuning). y khng phi l vic d dng v n ph thuc vo nhiu yu t. Ti tm tt mt kinh nghim c bn khi chn cc h s cho PID nh sau: - Chn Kp trc: th b iu khin P vi i tng tht (hoc m phng), iu chnh Kp sao cho thi gian p ng nhanh, chp nhn overshot nh. - Thm thnh phn D loi overshot, tng Kd t t, th nghim v chn gi tr thch hp. Steady state error c th s xut hin. - Thm thnh phn I gim steady state error. Nn tng Ki t b n ln gim steady state error ng thi khng cho overshot xut hin tr li.

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C mt phng php rt ph bin dng chn cc h s cho b iu khin PID gi l ZieglerNichols, bn quan tm c th t tm hiu thm. iu khin PID s Cng thc ca b iu khin PID trnh by trong (3) l dng hm lin tc ca bin e, trong c c thnh phn tuyn tnh, o hm v tch phn. Tuy nhin, h thng my tnh v vi iu khin li l h thng s. Mun xy dng b iu khin PID trn my tnh hay trn vi iu khin chng ta phi bit cch xp x phng trnh lin tc thnh dng ri rc. thc hin s ha b iu khin PID trc ht ti ni s qua th no l h thng s (digital) so vi h thng lin tc hay h thng tng t (analog). Hy quan st h thng iu chnh nhit n gin nh trong hnh 7.

Hnh 7. T ng iu chnh nhit Gi s chng ta cn iu chnh nhit trong phng mt mc no (ty theo gi tr tham chiu) bng qut. Cm bin o nhit v hi tip v b khuych i vi sai (so snh v khuych i). Nu c sai s gia gi tr tham chiu v gi tr o t cm bim, b khuych i vi sai s t ng khuych i sai s ny v lm tng hay gim vn tc ca qut iu chnh nhit . Qu trnh ny xy ra mt cch lin tc. B khuych i vi sai trong trng hp ny chnh l b iu khin tng t (analog controller). B khuych i ny l mt mch in t thng thng nh Opamp chng hn. Nu chng ta thay b khuych i ny bng mt vi iu khin AVR th qu trnh hiu chnh khng cn xy ra lin tc na m theo mt chu k no . V d c mi 10 ms chng ta c gi tr t cm bin mt ln tnh ton sai s v xut gi tr iu khin qut. B iu khin do AVR thc hin gi l b iu khin s (digital controller) v khong thi gian 10ms ny gi l thi gian ly mu (sampling time), l khong cch gia 2 ln iu khin lin tip. R rng thi gian ly mu cng nh (tn s cao) th vic hiu chnh cng tin gn n s lin tc v cht lng iu khin s tt hn. Trong cc b iu khin s, thi gian ly mu l mt yu t rt quan trng. Cn tnh ton thi gian ny khng qu ln nhng cng ng qu nh, v nh th s hao ph thi gian thc thi. V b iu khin PID xy dng trong AVR s l b iu khin s, chng ta cn xp x cng thc ca b iu khin ny theo cc khong thi gian ri rc. Trc ht, thnh phn P tng i n gin v l quan h tuyn tnh Kp*e, chng ta ch cn p dng trc tip cng thc ny m khng cn bt k xp x no. Tip n l xp x cho o hm ca bin e. V thi gian ly mu cho cc b iu khin thng rt b nn c th xp x o hm bng s thay i ca e trong 2 ln ly mu lin tip: de/dt =(e(k) e(k-1))/h. Trong e(k) l gi tr hin ti ca e, e(k-1) l gi tr ca e trong ln ly mu trc v h l khong thi gian ly mu (h l hng s).

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Hnh 8. Xp x o hm ca bin sai s e Thnh phn tch phn c xp x bng din tch vng gii hn bi hm ng biu din ca e v trc thi gian. Do vic tnh ton tch phn khng cn qu chnh xc, chng ta c th dng phng php xp x n gin nht l xp x hnh ch nht (sai s ca phng php ny cng ln nht). tng c trnh by trong hnh 9.

Hnh 9. Xp x tch phn ca bin sai s e

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Tch phn ca bin e c tnh bng tng din tch cc hnh ch nht ti mi thi im ang xt. Mi hnh ch nht c chiu rng bng thi gian ly mu h v chiu cao l gi tr sai s e ti thi im ang xt. Tng qut:

(4) Tng hp cc xp x, cng thc ca b iu khin PID s c trnh by trong (5)

(5) Trong u l i lng output t b iu khin. n gin ha vic tnh thnh phn tch phn, chng ta nn dng phng php cng dn (hay quy): (6) Vi I(k) l thnh phn tch phn hin ti v I(k-1) l thnh phn tch phn trc . Cc cng thc (5) v (6) rt d dng thc hin bng AVR. Do , n lc ny chng ta sn sng a tng vo lp trnh cho chip. VI. iu khin DC Motor bng AVR Phn ny chng ta s vn dng tt c phn l thuyt gii thiu trn vit chng trnh cho AVR. Mc ch l iu khin vn tc ca DC Motor bng gii thut PID. Mch in m phng c trnh by trong hnh 1. M hnh Motor dng trong v d l loi 12V c vn tc khng ti ti a l 720rpm (revolute per minute) tc 20 vng/s. Encoder dng cho motor c chn c phn gii 112 pulse/vng. Knh A ca encoder c ni vi ngt ngoi INT2 m xung, knh B ni vi chn PB0 (chn 1) ca chip Atmega32 xt hng quay. Bn switches c ni vi 4 bit cao ca PORTB ci t vn tc mong mun cn iu khin. Mt Text LCD dng hin th vn tc thc ca motor c t Encoder (Actual speed) v vn tc ci t (Desired speed). Do Text LCD c ni vi PORTC nn nu bn mun dng chng trnh ny cho ng dng tht th phi np li fuses v hiu ha JTAG. Gii thut PID s c vn hnh bi AVR trong thi gian ly mu l 25ms. Timer 2 c dng to khong thi gian 25ms. Timer 1 (16 bit) l b to PWM iu khin vn tc ng c. Ton b ni dung chng trnh c trnh by trong list 1. List 1. iu khin vn tc ng c DC

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Cc dng t 14 n 17 chng ta nh ngha cc chn iu khin DC Motor, chn DIR iu khin hng v EN kch hot hoc dng Motor (thc ra l dng L298D). Do mc ch ca chng ta l iu khin vn tc ng c, 2 chn ny ch c kch mt ln duy nht trong chng trnh chnh (khng cn i hng quay ca Motor). Dng 18 nh ngha thi gian ly mu, Sampling_time l 25 ms (.025s). Bin inv_Sampling_time dng 19 l nghch o ca Sampling_time, 1/0.025 = 40, v y cng l hng s, chng ta nh ngha trc sau ny khng cn thc hin php nghch o trong chng trnh chnh (tit kim thi gian thc thi). PWM dng iu khin ng c c chn c tn s 1KHz nn chu k la 1ms. Do chng ta dng ngun xung gi nhp 8MHz, to thi gian 1ms cn 8000 xung, gi tr ny c nh ngha trong dng 20 v s c gn cho thanh ghi ICR1 (TOP ca PWM, xem li bi Timer-Counter, Timer1, Fast PWM) trong chng trnh chnh (dng 81). Cc dng code t 22 n 27 khai bo mt s bin ton cc dng trong chng trnh chnh. Do cc bin ny s c dng c trong trnh phc v ngt v chng trnh chnh nn cn khai bo c tnh volatile, kiu bin l long int tc s nguyn 32 bit ( trnh b trn khi tnh ton sau ny). Bin Pulse v pre_Pulse l s xung hin ti v ln ly mu trc c t encoder. Cc bin trong dng 23 v 24 dng cho b iu khin PID, bin Ctrl_Speed l vn tc mong mun (set point) ton cc v bin Output cha gi tr tnh c t b iu khin PID. Trc khi i tm hiu chng trnh con cha gii thut PID, chng ta s kho st ni dung chng trnh main v cc trnh phc v ngt trc hiu tng quan cch thc thc hin. Chng trnh chnh bt u t dng 45 v kt thc dng 103. Phn u ca chng trnh chnh (ngoi vng lp while) khai bo v khi to cc module c s dng. 2 dng 49 v 50 ci t hng cho PORTB, do PORT ny dng c encoder v cc switches chng ta cn set n l input v c in tr ko ln. Hai dng 52 v 53 set hng cho ng c v s gi hng ny khng i trong sut qu trnh iu khin sau ny. Hai dng 55 v 56 khai bo ngt ngoi INT2 dng m xung knh A ca encoder. Ch l INT2 ch c 2 mode l cnh xung v cnh ln nn ch c 1 bit sense ISC2 chn mode. Bit ISC2 khng nm trong thanh ghi iu khin MCUCR nh cc ngt khc m nm trong thanh ghi iu khin-trng thi MCUCSR. Khi ISC2=0 th ch ngt cnh xung ca INT2 c chn (xem dng 55). Sau INT2 c cho php hot ng dng 56. Hy tm thi di chuyn n dng 109 xem trnh phc v ngt INT2. Chc nng ca INT2 trong bi ny l m xung encoder v th trnh phc v s lm vic ny. Khi c mt ngt INT2 xy ra tc c 1 xung t encoder vo th trnh phc v ngt ISR(INT2 vect) t ng c gi ra, dng 110 trong trnh phc v ngt kim tra trng thi chn PB0, tc kenh B ca encoder. Nu PB0=1 th tng bin xung m c Pulse ln 1, ngc li nu PB0=0 th gim Pulse i 1 trong dng 111. Quay v gii thch chng trnh chnh dng 59, y l cc khai bo cho timer 2. Chng ta s dng timer 2 to ra mt khong thi gian ly mu 25 ms, c sau 25 ms th s c ngt trn timer2 mt ln v trong trnh phc v ngt trn ca timer2 chng ta thc hin tnh ton PID. Dng 59 chng ta set cc bit CS chn b chia tn s, b chia Prescaler=1024 c chn v 25 ms kh ln so vi thi gian 1 chu k xung gi nhp (1/8 micro giy). Prescaler = 1024 ngha l sau 1024 nhp ca xung gi nhp, tc sau 128 micro giy (1024 *1/8=128 us) th thanh ghi gi tr TCNT2 mi tng 1 n v. Do chng ta mun to khong thi gian 25 ms tng ng 25000/128=195 n v m ca thanh ghi TCNT2, chng ta s gn gi tr khi to cho TCNT2 l 255-195=60 (timer 2 s trn mt ln khi TCNT2 m n 255, xem li bi TimerCounter). iu ny thc hin dng 60 TCNT2=60. Dng 61 cho php ngt trn timer2. Hai dng 64 v 65 khi ng Timer 1 dng nh mt b to xung Fast PWM, mode 14, trong thanh ghi ICR1 cha chu k PWM v 2 thanh ghi OCR1A, OCR1B cha duty cycle (khong ON) ca PWM. Cc dng t 68 n 70 ghi texts ln LCD. Cc dng t 80 n 83 khi ng PWM cho DC Motor v cho php ngt ton cc sei();. Trong vng lp while ch yu l cng vic kim tra v hin th, bin sample_count m s ln ngt trn timer2 xy ra, n c tng 1 n v khi c mt ngt trn (xem dng 106) tc sau 25ms. Dng 86, chng ta kim tra bin sample_count, vic hin th ch cthc hin mi 250 ms mt ln (sample_count=10) v vic ny tn kh nhiu thi gian. Trong dng 87 chng ta kim tra cc swiches xem ngi dng cho mun thay i vn tc tham chiu cho iu khin. Cc dng tip theo in bin rSpeed l s lng xung m c t encoder trong vng 25 ms (cho ti hin ti) dong 1 ca LCD v in bin Ctrl_Speed l s xung/25ms m ngi dng mong mun motor t c. Ni dung quan trng nht ca list 1, tuy nhin, khng nm trong chng trnh chnh m nm cc trnh phc v ngt v chng trnh con Motor_Speed_PID(long int des_Speed). Trc ht, trnh phc v ngt ISR(TIMER2_OVF_vect) c t ng gi sau mi 25ms, trong trnh ny

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chng ta cn set li gi tr khi ng cho thanh ghi gi tr TCNT2 (xem li bi Timer-counter) dng 105. Sau tng bin m sample_count ln 1 (cng cho vic m thi gian hin th, ni trn). Cui cng l gi chng trnh con tnh ton gii thut PID Motor_Speed_PID(long int des_Speed). y l on chng trnh tnh ton gii thut PID v xut gi tr iu khin Motor. Hy quay li dng 30 tm hiu chng trnh con ny. Do bin Pulse cha tng s xung c t encode (trong ISR(INT2_vect) ), chng ta ly gi tr ny tr i gi tr pre_Pulse, tc s lng xung thi im 25 ms trc , thu c tng s xung thu c trong 25 ms qua. y chnh l vn tc motor tnh trn 25 ms: rSpeed=Pulse-pre_Pulse. Sau khi tnh c vn tc rSpeed chng ta gn li gi tr Pulse cho pre_Pulse ln ly mu sau dng n (dng 32). Sai s vn tc c t tn l Err, bin ny c tnh bng bng cch ly vn tc mong mun tr vn tc hin ti: Err=des_Speed-abs(rSpeed) dng 33. Dng 34 tnh thnh phn P ca b iu khin pPart=Kp*Err. Dng 35 tnh thnh phn D ca b iu khin, nh chng ta tho lun trong cng thc (2) th thnh phn D c tnh l: dPart=Kd*(Err-pre_Err)/Sampling_time, trong pre_Err l gi tr sai s ln ly mu trc c lu li. Do 1/Sampling_time = inv_Sampling_time nn chng ta c th thay dng tnh dPart bng cng thc trong dng 35: dPart=Kd*(Err-pre_Err)*inv_Sampling_time. Dng 36 tnh thnh phn I (iPart), s dng phng php cng dn ( quy) chng ta thu c iPart bng iPart trc cng vi din tch hnh ch nht sai s hin ti: iPart+=Ki*Sampling_time*(Err+pre_Err)/1000. Chng ta phi chia iPart cho 1000 v Sampling_time c tnh theo ms trong khi n v tnh ton chun trong l s. Cng cc thnh phn ny li chng ta c gi tr Output tng hp trong dng 37. Tuy nhin, theo l thng th cng thc dng 37 phi l Output=pPart+dPart+iPart nhng y li l : Output+=pPart+dPart+iPart ( du + trc du =), ngha l Output c cng dn thay v l tng tc thi nh chng ta tho lun trong phn gii thut PID. Tht ra vic ny cng d hiu. Trong bi ton iu khin v tr, khi sai s bng 0 chng ta c th dng b iu khin (u=0) nhng trong bi ton iu khin vn tc, khi sai s bng 0 th gi tr u vn phi c gi l gi tr trc .V vy, trong bi ton iu khin vn tc gi tr Output c cng dn thay v gn trc tip, bn phi ghi nh iu ny trong cc ng dng iu khin ca mnh. Hai dng 40 v 41 xt trng hp bo ha (saturation) khi Output vt qu gii hn cho php ca PWM (xn 2 u). Cui cng l gn gi tr tnh ton c t PID cho thanh ghi OCR1A tng hoc gim duty cycle ca PWM trn chn OC1A (ni vi PWM ca Motor) v gn gi tr sai s Err cho bin pre_Err cho ln ly mu sau dng n. Chy m phng: ton b chng trnh v c mch in m phng c ti to sn. Ngi c ch cn c hiu v chy m phng mch in. Ch khi chy m phng hy thay i cc switches thay i vn tc cn iu khin. Gi tr vn tc thc cht l s xung encoder trong 25 ms, ngi c hy t tnh ra s vng /s. Do m hnh motor trong phn mm m phng khng hon ho lm nn p ng b iu khin hi chm, bn c th phi ch mt khong thi gian thy vn tc Motor t n vn tc yu cu. Hay thay gi tr Kd trong dng 23 thnh 1 hoc 0, bin dch li chng trnh v m phng quan st v so snh ovetshot (s vt qu) ca h thng.

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ng h thi gian thc DS1307

Ni dung

Cc bi cn tham kho trc

Cu trc AVR. WinAVR. C cho AVR. Text LCD Giao tip TWI-I2C

1. 2.

Chip DS1307. AVR v DS1307.

Download v d

I. Chip DS1307. DS1307 l chip ng h thi gian thc (RTC : Real-time clock), khi nim thi gian thc y c dng vi ngha thi gian tuyt i m con ngi ang s dng, tnh bng giy, pht, giDS1307 l mt sn phm ca Dallas Semiconductor (mt cng ty thuc Maxim Integrated Products). Chip ny c 7 thanh ghi 8-bit cha thi gian l: giy, pht, gi, th (trong tun), ngy, thng, nm. Ngoi ra DS1307 cn c 1 thanh ghi iu khin ng ra ph v 56 thanh ghi trng c th dng nh RAM. DS1307 c c v ghi thng qua giao din ni tip I2C (TWI ca AVR) nn cu to bn ngoi rt n gin. DS1307 xut hin 2 gi SOIC v DIP c 8 chn nh trong hnh 1.

Hnh 1. Hai gi cu to chip DS1307. Cc chn ca DS1307 c m t nh sau: - X1 v X2: l 2 ng kt ni vi 1 thch anh 32.768KHz lm ngun to dao ng cho chip. - VBAT: cc dng ca mt ngun pin 3V nui chip. - GND: chn mass chung cho c pin 3V v Vcc. - Vcc: ngun cho giao din I2C, thng l 5V v dng chung vi vi iu khin. Ch l nu Vcc khng c cp ngun nhng VBAT c cp th DS1307 vn ang hot ng (nhng khng ghi v c c). - SQW/OUT: mt ng ph to xung vung (Square Wave / Output Driver), tn s ca xung c to c th c lp trnh. Nh vy chn ny hu nh khng lin quan n chc nng ca DS1307 l ng h thi gian thc, chng ta s b trng chn ny khi ni mch. - SCL v SDA l 2 ng giao xung nhp v d liu ca giao din I2C m chng ta tm hiu trong bi TWI ca AVR. C th kt ni DS1307 bng mt mch in n gin nh trong hnh 2.

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Hnh 2. Mch ng dng n gin ca DS1307. Cu to bn trong DS1307 bao gm mt s thnh phn nh mch ngun, mch dao ng, mch iu khin logic, mch giao in I2C, con tr a ch v cc thanh ghi (hay RAM). Do a s cc thnh phn bn trong DS1307 l thnh phn cng nn chng ta khng c qu nhiu vic khi s dng DS1307. S dng DS1307 ch yu l ghi v c cc thanh ghi ca chip ny. V th cn hiu r 2 vn c bn l cu trc cc thanh ghi v cch truy xut cc thanh ghi ny thng qua giao din I2C. Phn ny chng ta tm hiu cu trc cc thanh ghi trc v cch truy xut chng s tm hiu trong phn 2, iu khin DS1307 bng AVR. Nh ti trnh by, b nh DS1307 c tt c 64 thanh ghi 8-bit c nh a ch t 0 n 63 (t 0x00 n 0x3F theo h hexadecimal). Tuy nhin, thc cht ch c 8 thanh ghi u l dng cho chc nng ng h (ti s gi l RTC) cn li 56 thanh ghi b trng c th c dng cha bin tm nh RAM nu mun. By thanh ghi u tin cha thng tin v thi gian ca ng h bao gm: giy (SECONDS), pht (MINUETS), gi (HOURS), th (DAY), ngy (DATE), thng (MONTH) v nm (YEAR). Vic ghi gi tr vo 7 thanh ghi ny tng ng vi vic ci t thi gian khi ng cho RTC. Vic c gi t 7 thanh ghi l c thi gian thc m chip to ra. V d, lc khi ng chng trnh, chng ta ghi vo thanh ghi giy gi tr 42, sau 12s chng ta c thanh ghi ny, chng ta thu c gi tr 54. Thanh ghi th 8 (CONTROL) l thanh ghi iu khin xung ng ra SQW/OUT (chn 6). Tuy nhin, do chng ta khng dng chn SQW/OUT nn c th b qua thanh ghi th 8. T chc b nh ca DS1307 c trnh by trong hnh 3.

Hnh 3. T chc b nh ca DS1307. V 7 thanh ghi u tin l quan trng nht trong hot ng ca DS1307, chng ta s kho st cc thanh ghi ny mt cch chi tit. Trc ht hy quan st t chc theo tng bit ca cc thanh ghi ny nh trong hnh 4.

43

Hnh 4. T chc cc thanh ghi thi gian. iu u tin cn ch l gi tr thi gian lu trong cc thanh ghi theo dng BCD. BCD l vit tt ca cm t Binary-Coded Decimal, tm dch l cc s thp phn theo m nh phn. V d bn mun ci t cho thanh ghi MINUTES gi tr 42. Nu quy i 42 sang m thp lc phn th chng ta thu c 42=0x2A. Theo cch hiu thng thng chng ta ch cn gn MINUTES=42 hoc MINUTES=0x2A, tuy nhin v cc thanh ghi ny cha gi tr BCD nn mi chuyn s khc, ti s din gii bng hnh 5.

Hnh 5. S BCD. Vi s 42, trc ht n c tch thnh 2 ch s (digit) 4 v 2. Mi ch s sau c i sang m nh phn 4-bit. Ch s 4 c i sang m nh phn 4-bit l 0100 trong khi 2 c i thnh 0010. Ghp m nh phn ca 2 ch s li chng ta thu c mt s 8 bit, l s BCD. Vi trng hp ny, s BCD thu c l 01000010 (nh phn) = 66. Nh vy, t s pht 42 cho DS1307 chng ta cn ghi vo thanh ghi MINUTES gi tr 66 (m BCD ca 42). Tt c cc phn mm lp trnh hay thanh ghi ca chip iu khin u s dng m nh phn thng thng, khng phi m BCD, do chng ta cn vit cc chng trnh con quy i t s thp nh phn (hoc thp phn thng) sang BCD, phn ny s c trnh by trong lc lp trnh giao tip vi DS1307. Thot nhn, mi ngi u cho rng s BCD ch lm vn n thm rc ri, tuy nhin s BCD rt c u im trong vic hin th nht l khi hin th tng ch s nh hin th bng LED 7 on chng hn. Quay li v d 42 pht, gi s chng ta dng 2 LED 7-on hin th 2 ch s ca s pht. Khi c thanh ghi MINUTES chng ta thu c gi tr 66 (m BCD ca 42), do 66=01000010 (nh phn),

44

hin th chng ta ch cn dng phng php tch bit thng thng tch s 01000010 thnh 2 nhm 0100 v 0010 (tch bng ton t shift >> ca C hoc instruction LSL, LSR trong asm) v xut trc tip 2 nhm ny ra LED v 0100 = 4 v 0010 =2, rt nhanh chng. Thm ch, nu chng ta ni 2 LED 7-on trong cng 1 PORT, vic tch ra tng digit l khng cn thit, hin th c s, ch cn xut trc tip ra PORT. Nh vy, vi s BCD, vic tch v hin th digit c thc hin rt d dng, khng cn thc hin php chia (rt tn thi gian thc thi) cho c s 10, 100, 1000nh trong trng hp s thp phn. Thanh ghi giy (SECONDS): thanh ghi ny l thanh ghi u tin trong b nh ca DS1307, a ch ca n l 0x00. Bn bit thp ca thanh ghi ny cha m BCD 4-bit ca ch s hng n v ca gi tr giy. Do gi tr cao nht ca ch s hng chc l 5 (khng c giy 60 !) nn ch cn 3 bit (cc bit SECONDS6:4) l c th m ha c (s 5 =101, 3 bit). Bit cao nht, bit 7, trong thanh ghi ny l 1 iu khin c tn CH (Clock halt treo ng h), nu bit ny c set bng 1 b dao ng trong chip b v hiu ha, ng h khng hot ng. V vy, nht thit phi reset bit ny xung 0 ngay t u. Thanh ghi pht (MINUTES): c a ch 0x01, cha gi tr pht ca ng h. Tng t thanh ghi SECONDS, ch c 7 bit ca thanh ghi ny c dng lu m BCD ca pht, bit 7 lun lun bng 0. Thanh ghi gi (HOURS): c th ni y l thanh ghi phc tp nht trong DS1307. Thanh ghi ny c a ch 0x02. Trc ht 4-bits thp ca thanh ghi ny c dng cho ch s hng n v ca gi. Do DS1307 h tr 2 loi h thng hin th gi (gi l mode) l 12h (1h n 12h) v 24h (1h n 24h) gi, bit6 (mu green trong hnh 4) xc lp h thng gi. Nu bit6=0 th h thng 24h c chn, khi 2 bit cao 5 v 4 dng m ha ch s hng chc ca gi tr gi. Do gi tr ln nht ca ch s hng chc trong trng hp ny l 2 (=10, nh phn) nn 2 bit 5 v 4 l m ha. Nu bit6=1 th h thng 12h c chn, vi trng hp ny ch c bit 4 dng m ha ch s hng chc ca gi, bit 5 (mu orange trong hnh 4) ch bui trong ngy, AM hoc PM. Bit5 =0 l AM v bit5=1 l PM. Bit 7 lun bng 0. (thit k ny hi d, nu di hn 2 bit mode v A-P sang 2 bit 7 v 6 th s n gin hn). Thanh ghi th (DAY ngy trong tun): nm a ch 0x03. Thanh ghi DAY ch mang gi tr t 1 n 7 tng ng t Ch nht n th 7 trong 1 tun. V th, ch c 3 bit thp trong thanh ghi ny c ngha. Cc thanh ghi cn li c cu trc tng t, DATE cha ngy trong thng (1 n 31), MONTH cha thng (1 n 12) v YEAR cha nm (00 n 99). Ch , DS1307 ch dng cho 100 nm, nn gi tr nm ch c 2 ch s, phn u ca nm do ngi dng t thm vo (v d 20xx). Ngoi cc thanh ghi trong b nh, DS1307 cn c mt thanh ghi khc nm ring gi l con tr a ch hay thanh ghi a ch (Address Register). Gi tr ca thanh ghi ny l a ch ca thanh ghi trong b nh m ngi dng mun truy cp. Gi tr ca thanh ghi a ch (tc a ch ca b nh) c set trong lnh Write m chng ta s kho st trong phn tip theo, AVR v DS1307. Thanh ghi a ch c ti t trong hnh 6, cu trc DS1307.

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Hnh 6. Cu trc DS1307. II. AVR v DS1307. Phn ny ti hng dn lp trnh iu khin v giao tip vi DS1307 bng AVR, dng WinAVR. Do DS1307 hot ng nh mt Slave I2C, bn nht thit phi c li Bi 8 - Giao tip TWI-I2C, nht l l 2 ch Master (Send v Reveive). Ti s khng cp li ton b giao din I2C nhng tm tt cch thc hin vi AVR nh sau: thc hin cuc gi ch Master, AVR s gi iu kin START, tip theo l 7 bit a ch Slave (SLA) +1 bit Write/Read, k n l qu trnh c hay ghi d liu gia Master v Slave bng cc byte d liu 8 bit (c th ch 1 byte hoc 1 dy bytes), c sau mi byte s c 1 bit ACK hoc NOT ACK. Cuc gi kt thc vi vic Master pht iu kin STOP. C mi mt qu trnh, s c 1 code c sinh ra trong thanh ghi trng thi TWSR, kim tra gi tr code ny bit qu trnh giao tip c thnh cng khng. Bn cn nh dy code thnh cng khi Master truyn d liu l: 0x08 -> 0x18 -> 0x28 ->->0x28. V dy code thnh cng khi Master truyn d liu l 0x08 - > 0x40 - > 0x50 ->->0x50 -> 0x58. Nm c cch ghi v c ca AVR Master l bn nm c 50% cch giao tip vi DS1307, 50% cn li chng ta phi hiu cch b tr dy d liu ca ring DS1307. Hy theo di phn tip theo.. V DS1307 l mt Slave I2C nn ch c 2 mode (ch ) hot ng giao tip vi chip ny. Hai mode ca DS1307 bao gm Data Write (t AVR n DS14307) v Data Read (t DS1307 vo AVR). Mode Data Write c dng khi xc lp gi tr ban u cho cc thanh ghi thi gian hoc dng canh chnh thi gian. Trong ch ny, AVR l 1 Master truyn d liu n DS1307 (Slave nhn d liu). Mode Data Read c s dng khi c thi gian t ng h DS1307 vo AVR hin th hoc so snh.Trong ch ny, AVR l Master nhn d liu v DS1307 l Slave truyn d liu. Hnh 7 m t cu trc d liu trong ch Data Write.

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Hnh 7. Ch Data Write. Trc ht hy ni v a ch Slave Address (SLA) ca DS1307 trong mng I2C. Nh chng ta u bit, trn mng I2C mi thit b s c mt a ch ring gi l SLA. SLA l con s 7 bit, nh th theo l thuyt s c ti a 128 thit b trong 1 mng I2C. Chip DS1307 l mt I2C Slave nn cng c mt a ch SLA, gi tr ny c set c nh l 1101000 nh phn, hay 0x68 thp lc phn. Do SLA ca DS1307 c nh nn trong 1 mng I2C s khng th tn ti cng lc 2 chip ny (iu ny thc s khng cn thit) nhng c th tn ti cc thit b I2C khc hoc tn ti nhiu Master AVR. Quan st hnh 7, sau khi iu kin START c gi bi Master (AVR) s l 7 bit a ch SLA ca DS1307 (1101000). Do ch ny l Data Write nn bit W (0) s c gi km sau SLA. Bit ACK (A) c DS1307 tr v cho Master sau mi qu trnh giao tip. Tip theo sau a ch SLA s l 1 byte cha a ch ca thanh ghi cn truy cp (tm gi l Addr_Reg). Cn phn bit a ch thanh ghi cn truy cp v a ch SLA. Nh ti cp trn, a ch ca thanh ghi cn tuy cp s c lu trong thanh ghi a ch (hay con tr a ch), v vy byte d liu u tin s c cha trong thanh ghi a ch ca DS1307. Sau byte a ch thanh ghi l mt dy cc byte d liu c ghi vo b nh ca DS1307. Byte d liu u tin s c ghi vo thanh ghi c a ch c ch nh bi Addr_Reg, sau khi ghi 1 byte, Addr_Reg c t ng tng nn cc byte tip theo s c ghi lin tip vo cc thanh ghi k sau. S lng bytes d liu cn ghi do Master quyt nh v khng c vt qu dung lng b nh ca DS1307. V d sau khi gi SLA+W, Master gi 8 bytes gm 1 byte u 0x00 v 7 bytes khc th con tr a ch s tr n thanh ghi u tin (0x00 thanh ghi SECONDS) v ghi lin tip 7 bytes vo 7 thanh ghi thi gian ca SD1307. y l cch m chng ta s thc hin trong phn lp trnh giao tip ( xem chng trnh con TWI_DS1307_wblock pha sau). Qu trnh ghi kt thc khi Master pht ra iu kin STOP. Ch , nu sau khi gi byte Addr_Reg, Master khng gi cc bytes d liu m gi lin iu kin STOP th khng c thanh ghi no c ghi. Trng hp ny c dng set a ch Addr_Reg phc v cho qu trnh c. Tip theo, chng ta kho st cch sp xp d liu trong ch Data Read, xem hnh 8.

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Hnh 8. Ch Data Read. Trong ch Data Read, bit R (1) c gi km sau 7 bit SLA. Sau l lin tip cc byte d liu c truyn t DS1307 n AVR. im khc bit trong cc b tr d liu ca ch ny so vi ch Data Write l khng c byte a ch thanh ghi d liu c gi n. Tt c cc bytes theo sau SLA+R u l d liu c t b nh ca DS1307. Vy th d liu c c bt u t thanh no? Cu tr li l thanh ghi c ch nh bi con tr a ch, gi tr ny c lu li trong cc ln thao tc trc o. Nh vy, mun c chnh xc d liu t mt a no , chng ta cn thc hin qu trnh ghi gi tr cho con tr a ch trc. ghi gi tr vo con tr a ch chng ta s gi chng trnh Data Write vi ch 1 byte c ghi sau SLA+W nh phn ch trn. Chng ta chun b y giao tip vi DS1307. Phn tip theo ti s trnh by chng trnh v m phng giao tip gia AVR v DS1307. Hy v mt mch in bng Proteus nh trong hnh 9. Trong v d ny, ban u chng ta s ci t thi gian cho DS1307, sau tin hnh c thi gian t chip ng h ny v hin th ln 1 Text LCD.

Hnh 9. V d giao tip AVR DS1307. Ti s chia chng trnh thnh 2 phn, phn giao tip vi DS1307 thng qua I2C c vit trong file myDS1307RTC.h v phn v d ghi-c, hin th c vit trong file DS1307RTC_Test.c.

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List 1. myDS1307RTC.h.

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Cc phn nh ngha trc dng 35 c trch t bi TWI nn ti khng gii thch li. Chng ta bt u t dng 36. C 3 chng trnh con c vit giao tip gia AVR vi DS1307 l: ghi 1 dy d liu vo DS1307 tc chng trnh con TWI_DS1307_wblock(uint8_t Addr, uint8_t Data[], uint8_t len), chng trnh ny c vit theo cch sp xp d liu ca ch Data Write trnh by trn. Chng trnh con c d liu t DS1307 l TWI_DS1307_rblock(uint8_t Data[], uint8_t len ) v mt chng trnh con dng set a ch thanh ghi cn truy cp c tn TWI_DS1307_wadr(uint8_t Addr). Chng trnh con TWI_DS1307_wblock(uint8_t Addr, uint8_t Data[], uint8_t len) nm t dng 54 n dng 77. Trong chng trnh con ny, tham s Addr l a ch thanh ghi cn truy cp, Data[] l mng d liu s ghi vo DS1307 v len l s byte d liu s ghi (khng tnh byte Addr). Dng 55, AVR pht ra iu kin START bt 1 cuc gi I2C, sau chng ta ch cho bit TWINT c set ln 1 dng 56 (TWINT = 1, cng vic c thc hin). Dng 57 kim tra nu iu kin START gi thnh cng hay khng bng cch so snh thanh ghi trng thi TWSR vi code tng ng (xem li hnh 2 trong bi giao tip TWI). Sau khi START c gi, dng 59 chng ta gn a ch SLA+W cho thanh ghi d liu TWDR pht ra trn I2C, TWDR=(DS1307_SLA<<1)+TWI_W. Trong dng ny, bin DS1307_SLA l SLA ca DS1307 c nh ngha trc dng 15 trong khi TWI_W l bit W (=0) c nh ngha dng 20. Qu trnh pht I2C ch bt u khi bit TWINT c xa, dng 60 thc hin vic ny, sau phi ch bit TWINT c set ln 1 chng t qu trnh pht SLA kt thc (dng 61). Cui cng l kim tra code trong thanh ghi TWSR xem qu trnh pht SLA c thanh cng, xem dng 62 v hnh 2 trong bi giao tip TWI. Chng ta s lun theo c ch ny khi lm vic vi TWI ca AVR, do trong cc phn tip theo ti ch gii thch ni dung truyn-nhn, khng gii thch li c ch. Sau khi pht SLA+W, cc dng 64 n 65 pht a ch thanh ghi cn truy cp (bin Addr) v sau pht mng d liu lin tip trong cc dng 69 n 74. Cui cng l pht in kin STOP kt thc cuc gi. Trong chng trnh con ghi DS1307 trnh by trn, nu tham s len=0 th cc dng 69 n 74 khng c thc hin, ngha l ch c a ch Addr c pht m khng c d liu no km theo. Chng ta c th dng c im ny set thanh ghi cho qu trnh c. Ti tch ra v vit thnh 1 chng trnh con tn TWI_DS1307_wadr(uint8_t Addr) trong cc dng t 36 n 52 dng thc hin vic set a ch ny. Chng trnh con c DS1307 TWI_DS1307_rblock(uint8_t Data[], uint8_t len ) c trnh by trong cc dng t 79 n 99. Trong , tham s Data[] l mng cha d liu c v, len l s bytes c v, c bit khng c tham s a ch thanh ghi v a ch ny s c set ring trc khi gi chng trnh con c DS1307. Dng 84 mt lnh pht SLA+TWI_R c thc hin, vi bit TWI_R=1 (xem nh ngha dng 21), AVR ang bo cho DS1307 rng n mun c d liu t DS1307. Qu trnh c c chia thnh 2 phn, trong phn 1 chng ta c len-1 bytes u tin (xem cc dng code t 88 n 92) v phn 2 c byte cui cng (dng 94 n 96). Chng ta cn tch vic c byte cui ra v nu nhn li ch c trnh by trong hnh 8, sau mi byte c c, Master phi gi 1 bit ACK n DS1307, ring byte cui cng Master phi gi bit NOT ACK bo DS1307 rng Master khng mun c thm (so snh 2 dng 89 v 94). Cui cng, Master gi iu kin STOP kt thc cuc gi. kim tra cc hm giao tip DS1307, hy to 1 Project bng WinAVR vi tn gi DS1307RTC_Test, to file DS1307RTC_Test v vit code nh trong list 2. List 2. DS1307RTC_Test.c.

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Chng trnh demo DS1307 dng cc hm trong file DS1307RTC.h trc , bn cn copy file ny vo cng th mc vi chng trnh demo ny. ng thi, chp c file myLCD.h v v d ny c hin th LCD. C ch ca chng trnh demo nh sau: trong phn thn chng trnh chnh, ban u chng ta ghi cc thng s thi gian khi to cho DS1307, ti chn thi im ghi vo l 11h:59p:55s ca ngy 31, thng 12 nm 09 (2009) cho mc ch kim tra. Vi thi im ny, sau khi chy chng trnh c 5s bn s thy cc thanh thi gian trong DS1307 t ng chuyn sang 0h:0p:0s ngy 1 thng 1 nm 10. Ch l ngun clock cho chip trong v d ny l 8MHz, Ti dng Timer0 to ra 1 khong thi gian delay khong 32.7ms, c 10 ln ngt Timer0 (tc khong 327ms) ti s c DS1307 v cp nht kt qu ln LCD. Cc bin ph Second, Minute, Hour, Day, Date, Month, Year c khai bo dng 8 v 9 cha thi gian (s thp phn bnh thng). Bin Mode chn h thng gi, Mode =0 l h thng 24h v Mode=1 l h thng 12h. Bin AP cha bui trong Mode 12h, AP=0 l bui sng (AM), AP=1 l bui chiu (PM). Mng tData[7] c 7 phn t trong dng 14 cha 7 bytes tm tng ng vi 7 thanh ghi thi gian ghi vo DS1307 hoc c ra t chip ny. Cc dng t 17 n 28 l 2 chng trnh con i t s BCD sang thp phn v ngc li. Chng ta bt u vi chng trnh con Display (void), hin th kt qu cha trong mng tData[7] ln LCD (dng 30 n 64). Cc dng t 31 n 37 dng c gi tr trong mng tData[7] ra cc bin hin th, v tData[7] cha gi tr c v t cc thanh ghi thi gian ca DS1307 nn n l cc s BCD, chng ta cn dng hm BCD2Dec i sang s thp phn trc khi gn cho cc bin nh Second, Minutehin th ln LCD. Ring vi thanh ghi HOURS (tng ng vi sData[2]) chng ta cn kim tra h thng gi, nu l h thng 12h th ch ly 5 bit u ca thanh ghi ny gn cho bin Hour (xem li phn t chc cc thanh ghi thi gian hnh 4), nu l h thng 24h th s ly 6 bit (xem 2 dng 33 v 34). Cc dng t 39 n 64 in cc bin thi gian ln LCD. Dng u tin ca LCD dng in gi-pht-giy, dng th 2 in nm-thng-ngy. Phn b tr v tr cc gi tr in ngi c t l gii. Chng trnh chnh main bt u t dng 66 v kt thc dng 106. Cc cng vic thc hin trong main bao gm khi ng Text LCD, khi ng Timer0 ch thng, Prescaler=1024 v cho php ngt trn (cc dng t 77 n 79). Vi f=8MHz, gi tr nh th mi ln trn Timer0 l : (1024(Prescaler)/8 (f))*256 (MAX)=32768 us =32.7ms. Cc dng t 83 n 90 gn gi tr cc bin thi gian vo mng tData chun b ghi vo DS1307. Trc khi gn cc bin ny cho tData, chng ta cn i gi tr thp phn ca chng thnh BCD vi hm Dec2BCD. Dng 91 khi ng I2C v dng 92 ghi 7 phn t ca mng tData vo DS1307 vi hm TWI_DS1307_wblock m chng ta nh ngha trong file DS1307RTC.h. Ch l a ch bt u ghi l 0x00, v th 7 bytes ca mng tData s c ghi chnh xc vo 7 thanh ghi thi gian ca DS1307. Sau khi ghi d liu, cn 1 khong thi gian nh DS1307 x l, _delay_ms(1) l . Cc dng t 97 n 100 tin hnh c thi gian t DS1307 v v hin th ln LCD. Dng 97 TWI_DS1307_wadr(0x00) dng set a ch thanh ghi cn truy cp trc khi c, chng ta mun c ht 7 thanh ghi thi gian nn s set a ch v 0 (thanh ghi SECONDS). Phi delay 1 khong nh trc khi tip tc c DS1307 (dng 98). Dng 99 chng ta c 7 thanh ghi thi gian vo mng tData v hin th ln LCD dng 100. Chng trnh chnh kt thc y, vic cn li cho trnh phc v ngt thc hin. Trong trnh phc v ngt trn ca Timer0 (t dng 107 n 125), chng ta tng 1 bin tm tn l Time_count, n khi no 10 ngt xy ra (khong 327ms) th mi tin hnh c DS1307 mt ln (cc dng t 111 n 113). Do c mi 327ms chng ta c DS1307 1 ln nn s c trng hp 2 ln c cng 1 gi tr, chng ta ch thc hin vic cp nht kt qu khi 1 giy qua. Dng 115 so snh kt qu c v vi bin Second, tc l so snh kt qu mi vi kt qu c, nu chng khc nhau s cp nht gi tr giy trn LCD (cc dng t 116 n 119). Chng ta iu bit vic ghi ln LCD s tn kh nhiu thi gian, v vy ch nn cp nht kt qu khi no c s thay i. Mt khc, khi s giy thay i th cc bin thi gian khc thay i rt chm, mt cch tt trnh vic xa v ghi LCD nhiu ln l c 60s hy thc hin hm Display (trong hm ny c c xa v ghi cc bin thi gian). Dng 120 gip thc hin tng ny, ch khi no bin Second v 0 ( qua 60s) mi gi hm Display(). n y, ton b vic truy cp DS1307 bng AVR hon tt. Cc tng m rng ng dng nh thm cc nt chnh thi gian, ci t bo gixin nhng li cho bn c t pht trin.

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Text LCD

Ni dung

Cc bi cn tham kho trc Bn s i n u. Text LCD. AVR v Text LCD. V d iu khin Text LCD bng th vin myLCD.

1. 2. 3. 4.

Cu trc AVR. WinAVR. C cho AVR. M phng vi Proteus.

Download v d I. Bn s i n u. Bi ny nm trong phn ng dng AVR thuc lot bi cng hc AVR. Trong bi ng dng ny chng ta khng kho st nhiu cu trc AVR m ch yu l tm hiu Text LCD cch iu khin bng AVR. Cng c chnh cng l 2 b phn mm quen thuc WinAVR v Proteus. Sau bi ny, ti hy vng bn c th hiu v thc hin c: - Cu trc Text LCD. - Nguyn l hot ng Text LCD - Pht trin 1 th vin iu khin Text LCD bng AVR c 2 ch 8 bit v 4 bit. - V d iu khin Text LCD bng AVR. II. Text LCD. Text LCD l cc loi mn hnh tinh th lng nh dng hin th cc dng ch hoc s trong bng m ASCII. Khng ging cc loi LCD ln, Text LCD c chia sn thnh tng v ng vi mi ch c th hin th mt k t ASCII. Cng v l do ch hin th c k t ASCII nn loi LCD ny c gi l Text LCD ( phn bit vi Graphic LCD c th hin th hnh nh). Mi ca Text LCD bao gm cc chm tinh th lng, vic kt hp n v hin cc chm ny s to thnh mt k t cn hin th. Trong cc Text LCD, cc mu k t c nh ngha sn. Kch thc ca Text LCD c nh ngha bng s k t c th hin th trn 1 dng v tng s dng m LCD c. V d LCD 16x2 l loi c 2 dng v mi dng c th hin th ti a 16 k t. Mt s kch thc Text LCD thng thng gm 16x1, 16x2, 16x4, 20x2, 20x4Hnh 1 l mt v d Text LCD 16x2.

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Hnh 1. Text LCD 16x2. Text LCD c 2 cch giao tip c bn l ni tip (nh I2C) v song song. Trong phm vi bi hc ny ti ch gii thiu loi giao tip song song, c th l LCD 16x2 iu khin bi chip HD44780U ca hng Hitachi. i vi cc LCD khc bn cn tham kho datasheet ring ca tng loi. Tuy nhin, HD44780U cng c coi l chun chung cho cc loi Text LCD, v th bn c th dng chng trnh v d trong bi ny test trn cc LCD khc vi rt t hoc khng cn chnh sa. HD44780U l b iu khin cho cc Text LCD dng ma trn im (dot-matrix), chip ny c th c dng cho cc LCD c 1 hoc 2 dng hin th. HD44780U c 2 mode giao tip l 4 bit v 8 bit. N cha sn 208 k t mu kch thc font 5x8 v 32 k t mu font 5x10 (tng cng l 240 k t mu khc nhau). 1. S chn. Cc Text LCD theo chun HD44780U thng c 16 chn trong 14 chn kt ni vi b iu khin v 2 chn ngun cho n LED nn. Th t cc chn thng c sp xp nh sau: Bng 1. S chn.

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Trong mt s LCD 2 chn LED nn c nh s 15 v 16 nhng trong mt s trng hp 2 chn ny c ghi l A (Anode) v K (Cathode). Hnh 2 m t cch kt ni LCD vi ngun v mch iu khin.

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Hnh 2. Kt ni Text LCD. Chn 1 v chn 2 l cc chn ngun, c ni vi GND v ngun 5V. Chn 3 l chn chnh tng phn (contrast), chn ny cn c ni vi 1 bin tr chia p nh trong hnh 2.Trong khi hot ng, chnh thay i gi tr bin tr t c tng phn cn thit, sau gi mc bin tr ny. Cc chn iu khin RS, R/W, EN v cc ng d liu c ni trc tip vi vi iu khin. Ty theo ch hot ng 4 bit hay 8 bit m cc chn t D0 n D3 c th b qua hoc ni vi vi iu khin, chng ta s kho st k cng hn trong cc phn sau. 2. Thanh ghi v t chc b nh. HD44780U c 2 thanh ghi 8 bits l INSTRUCTION REGISTER (IR) v DATA REGISTER (DR). Thanh ghi IR cha m lnh iu khin LCD v l thanh ghi ch ghi (ch c th ghi vo thanh ghi ny m khng c c n). Thanh ghi DR cha cc cc loi d liu nh k t cn hin th hoc d liu c ra t b nh LCDC 2 thanh ghi u c ni vi cc ng d liu D0:7 ca Text LCD v c la chn ty theo cc chn iu khin RS, RW. Thc t iu khin Text LCD chng ta khng cn quan tm n cch thc hot ng ca 2 thanh ghi ny, v th cng khng cn kho st chi tit chng. HD44780U c 3 loi b nh, l b nh RAM d liu cn hin th DDRAM (Didplay Data RAM), b nh cha ROM cha b font to ra k t CGROM (Character Generator ROM) v b nh RAM cha b font to ra cc symbol ty chn CGRAM (Character Generator RAM). iu khin hin th Text LCD chng ta cn hiu t chc v cch thc hot ng ca cc b nh ny: 2.1 DDRAM. DDRAM l b nh tm cha cc k t cn hin th ln LCD, b nh ny gm c 80 c chia thnh 2 hng, mi c rng 8 bit v c nh s t 0 n 39 cho dng 1; t 64 n 103 cho dng 2. Mi nh tng ng vi 1 trn mn hnh LCD. Nh chng ta bit LCD loi 16x2 c th hin th ti a 32 k t (c

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32 hin th), v th c mt s nh ca DDRAM khng c s dng lm cc hin th. hiu r hn chng ta tham kho hnh 3 bn di

Hnh 3. T chc ca DDRAM. Ch c 16 nh c a ch t 0 n 15 v 16 a ch t 64 n 79 l c hin th trn LCD. V th mun hin th mt k t no trn LCD chng ta cn vit k t vo DDRAM 1 trong 32 a ch trn. Cc k t nm ngoi 32 nh trn s khng c hin th, tuy nhin vn khng b mt i, chng c th c dng cho cc mc ch khc nu cn thit. 2.2 CGROM. CGROM l vng nh c nh cha nh ngha font cho cc k t. Chng ta khng trc tip truy xut vng nh ny m chip HD44780U s t thc hin khi c yu cu c font hin th. Mt iu ng lu l a ch font ca mi k t vng nh CGROM chnh l m ASCII ca k t . V d k t a c m ASCII l 97, tham kho t chc ca vng nh CGROM trong hnh 4 bn s nhn thy a ch font ca a c 4 bit thp l 0001 v 4 bit cao l 0110, a ch tng hp l 01100001 = 97. CGROM v DDRAM c t ng phi hp trong qu trnh hin th ca LCD. Gi s chng ta mun hin th k t a ti v tr u tin, dng th 2 ca LCD th cc bc thc hin s nh sau: trc ht chng ta bit rng v tr u tin ca dng 2 c a ch l 64 trong b nh DDRAM (xem hnh 3), v th chng ta s ghi vo nh c a ch 64 mt gi tr l 97 (m ASCII ca k t a). Tip theo, chip HD44780U c gi tr 97 ny v coi nh l a ch ca vng nh CGROM, n s tm n vng nh CGROM c a ch 97 v c bng font c nh ngha sn y, sau xut bn font ny ra cc chm trn mn hnh LCD ti v tr u tin ca dng 2 trn LCD. y chnh l cch m 2 b nh DDRAM v CGROM phi hp vi nhau hin th cc k t. Nh m t, cng vic ca ngi lp trnh iu khin LCD tng i n gin, l vit m ASCII vo b nh DDRAM ti ng v tr c yu cu, bc tip theo s do HD44780U m nhim.

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Hnh 4. Vng nh CGROM. 2.3 CGRAM.

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CGRAM l vng nh cha cc symbol do ngi dng t nh ngha, mi symbol c c kch thc 5x8 v c dnh cho 8 nh 8 bit. Cc symbol thng c nh ngha trc v c gi hin th khi cn thit. Vng ny c tt c 64 nh nn c ti a 8 symbol c th c nh ngha. Ti liu ny khng cp n s dng b nh CGRAM nn ti s khng i chi tit phn ny, bn c th tham kho datasheet ca HD44780U bit thm. 3. iu khin hin th Text LCD. 3.1 Cc chn iu khin LCD. Cc chn iu khin vic c v ghi LCD bao gm RS, R/W v EN. RS (chn s 3): Chn la chn thanh ghi (Select Register), chn ny cho php la chn 1 trong 2 thanh ghi IR hoc DR lm vic. V c 2 thanh ghi ny u c kt ni vi cc chn Data ca LCD nn cn 1 bit la chn gia chng. Nu RS=0, thanh ghi IR c chn v nu RS=1 thanh ghi DR c chn. Chng ta u bit thanh ghi IR l thanh ghi cha m lnh cho LCD, v th nu mun gi 1 m lnh n LCD th chn RS phi c reset v 0. Ngc li, khi mun ghi m ASCII ca k t cn hin th ln LCD th chng ta s set RS=1 chn thanh ghi DR. Hot ng ca chn RS c m t trong hnh 5.

Hnh 5. Hot ng ca chn RS. R/W (chn s 4): Chn la chn gia vic c v ghi. Nu R/W=0 th d liu s c ghi t b iu khin ngoi (vi iu khin AVR chng hn) vo LCD. Nu R/W=1 th d liu s c c t LCD ra ngoi. Tuy nhin, ch c duy nht 1 trng hp m d liu c th c t LCD ra, l c trng thi LCD bit LCD c ang bn hay khng (c Busy Flag - BF). Do LCD l mt thit b hot ng tng i chm (so vi vi iu khin), v th mt c BF c dng bo LCD ang bn, nu BF=1 th chng ta phi ch cho LCD x l xong nhim v hin ti, n khi no BF=0 mt thao tc mi s c gn cho LCD. V th, khi lm vic vi Text LCD chng ta nht thit phi c mt chng trnh con tm gi l wait_LCD ch cho n khi LCD rnh. C 2 cch vit chng trnh wait_LCD. Cch 1 l c bit BF v kim tra v ch BF=0, cch ny i hi lnh c t LCD v b iu khin ngoi, do chn R/W cn c ni vi b iu khin ngoi. Cch 2 l vit mt hm delay mt khong thi gian c nh no (tt nht l trn 1ms). u im ca cch 2 l s n gin v khng cn c LCD, do chn R/W khng cn s dng v lun c ni vi GND. Tuy nhin, nhc im ca cch 2 l khong thi gian delay c nh nu qu ln s lm chm qu trnh thao tc LCD, nu qu nh s gy ra li hin th. Trong bi ny ti hng dn bn cch tng qut l cch 1, s dng cch 2 bn ch cn mt thay i nh trong chng trnh wait_LCD (s trnh by chi tit sau) v kt ni chn R/W ca LCD xung GND. EN (chn s 5): Chn cho php LCD hot ng (Enable), chn ny cn c kt ni vi b iu khin cho php thao tc LCD. c v ghi data t LCD chng ta cn to mt xung cnh xung trn chn EN, ni theo cch khc, mun ghi d liu vo LCD trc ht cn m bo rng chn EN=0, tip n xut d liu n cc chn D0:7, sau set chn EN ln 1 v cui cng l xa EN v 0 to 1 xung cnh xung. 3.2 Tp lnh ca LCD.

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Bng 2 tm tt cc lnh c th ghi vo LCD

Danh sch lnh trn c ti t 2 mu khc nhau, cc lnh mu s c dng thng xuyn trong lc hin th LCD v cc lnh mu xanh thng ch c dng 1 ln trong lc khi ng LCD, ring lnh Read BF c th c dng hoc khng ty theo cch vit chng trnh wait_LCD. Phn tip theo ti gii thch ngh ca cc lnh v tham s km theo chng. Trc ht l nhm lnh : - Clear display xa LCD: lnh ny xa ton b ni dung DDRAM v v th xa ton b hin th trn LCD. V y l 1 lnh ghi Instruction nn chn RS phi c reset v 0 trc khi ghi lnh ny ln LCD. M lnh xa LCD l 0x01(ghi vo D0:D7). - Cursor home a con tr v v tr u, dng 1 ca LCD: lnh ny thc hin vic a con tr v v tr u tin ca b nh DDRAM, v th nu sau lnh ny mt bin c ghi vo DDRAM th bin ny s nm v tr u tin (1;1). RS cng phi bng 0 trc khi ghi lnh. M lnh l 0x02 hoc 0x03(chn 1 trong 2 m

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lnh, ty ). - Set DDRAM address nh v tr con tr cho DDRAM: di chuyn con tr n mt v tr ty trong DDRAM v v th c th c dng chn v tr cn hin th trn LCD. thc hin lnh ny cn reset RS=0. Bit MSB ca m lnh (D7) phi bng 1, 7 bit cn li ca m lnh chnh l a ch DDRAM mun di chuyn n. V d chng ta mun di chuyn con tr n v tr th 3 trn dng 2 ca LCD (a ch 42) chng ta cn ghi m lnh 0xAA v 0xAA=10101010 (binary) trong bit MSB bng 1, by bit cn li l 0101010=42, a ch ca nh mun n. - Write to CGRAM or DDRAM ghi d liu vo CGRAM hoc DDRAM: v y khng phi l lnh ghi instruction m l 1 lnh ghi d liu nn chn RS cn c set ln 1 trc khi ghi lnh vo LCD. Lnh ny cho php ghi m ASCII ca mt k t cn hin th vo thanh ghi DDRAM. Trng hp ghi vo CGRAM khng c kho st. K n l nhm lnh mu xanh: nhm lnh ny thng ch thc hin 1 ln (t nht l trong bi hc ny) v thng c vit chung trong 1 chng trnh con khi ng LCD ( chng ta gi l init_LCD trong bi hc ny). - Entry mode set xc lp cc hin th lin tip cho LCD: ni mt cch d hiu, lnh ny ch ra cch m bn mun hin th mt k t tip theo 1 k t trc . V d nu bn mun hin th 2 k t lin tip AB, trc ht bn vit A ti v tr 5, dng 1. Sau bn ghi B vo LCD, lc ny c 4 cch m LCD c th hin th B nh sau: hin th B bn phi A ti v tr s 6 (cch 1); B cng c th c hin th bn tri A, ti v tr s 4(cch 2); hoc LCD c th t dch chuyn A v bn tri n v tr 4 sau hin th B bn phi A, ti v tr 5(cch 3); v kh nng cui cng l LCD dch chuyn A v bn phi n v tr 6 sau hin th B bn tri A, ti v tr 5(cch 4). Chng ta c th chn 1 trong 4 cch hin th trn thng qua lnh Entry mode set. y l lnh ghi Instruction nn RS=0, 5 bit cao D7:3=00000, bit D2=1, hai bit cn li D1:0 cha m lnh la chn 1 trong 4 cch hin th. Xem li bng 2, bit D1 cha gi tr I/D v D0 cha S. Trong I/D ngha l tng hoc gim (Increment or Decrement). I/D= 1 l hin th tng tc k t sau s hin th bn phi k t trc, nu I/D=0 th hin th gim, tc k t sau hin th bn tri k t trc. S l gi tr Shift, nu S=1 th cc k t trc s c y i, k t sau chim ch k t trc, ngc li nu S=0 th v tr hin th ca cc k t trc khng thay i. C th tm tt 4 mode hin th ng vi 4 m lnh nh sau: + D7:0 = 0x04 (00000100) : hin th gim v khng shift (nh cch 2 trong v d). + D7:0 = 0x05 (00000101) : hin th gim v shift (nh cch 4 trong v d). + D7:0 = 0x06 (00000110) : hin th tng v khng shift (nh cch 1, khuyn khch). + D7:0 = 0x07 (00000111) : hin th tng v shift (nh cch 3 trong v d). - Display on/off control xc lp cch hin th cho LCD: lnh ny bao gm cc thng s cho php LCD hin th, cho php hin th cursor v m/tt blinking. y cng l mt lnh ghi Instrcution nn RS phi bng 0. M lnh cho lnh ny c dng 00001DCB trong D (Display) cho php hin th LCD nu mang gi tr 1, C (Cursor) bng 1 th cursor s c hin th v B l blinking cho cursor ti v tr hin th (blinking l dng 1 en nhp nhy ti v tr k t ang hin th). M lnh c dng ph bin cho lnh ny l 0x0E (00001110 - hin th cursor nhng khng hin th blinking). - Function set xc lp chc nng cho LCD: y l lnh thit lp phng thc giao tip vi LCD, kch thc font ch v s lng line ca LCD. RS cng phi bng 0 khi s dng lnh ny. M lnh function set c dng 001DLNFxx. Trong nu DL=1 (DL: Data Length) th mode giao tip 8 bit s c dng, lc ny tt c cc chn t D0 n D7 phi c kt ni vi b iu khin ngoi. Nu DL=0 th mode 4 bit c dng, trong trng hp ny ch c 4 chn D4:7 c dng truyn nhn d liu v kt ni vi b iu khin ngoi, cc chn D0:3 c trng. N quy nh s dng ca LCD, v chng ta ang kho st LCD loi hin th 2 dng nn N=1 (N=0 cho trng hp LCD 1 dng). F l kch thc font ch hin th, do LCD c 2 b font ch c sn trong CGROM nn chng ta cn la chn thng qua bit F, nu F=1 b font 5x10 c s dng v nu F=0 th font 5x8 c hin th. 2 bit thp trong m lnh ny c th c gn gi tr ty . M lnh c dng ph bin cho lnh function set l 0x38 (00111000 giao tip 8 bit, 2 dng vi font 5x8 ) hoc 0x28 (00101000 giao tip 4 bit, 2 dng vi font 5x8 ). V d trong bi ny s dng c 2 m lnh trn. 3.3 Giao tip 8 bit v 4 bit.

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Nh trnh by trong lnh function set, c 2 mode ghi v c d liu vo LCD l mode 8 bit v mode 4 bit: - Mode 8 bit: Nu bit DL trong lnh function set bng 1 th mode 8 bit c dng. s dng mode 8 bit, tt c cc lines d liu ca LCD t D0 n D7 (t chn 7 n chn 14) phi c ni vi 1 PORT ca chip iu khin bn ngoi (v d PORTC ca ATmega32 trong v d ca bi ny) nh trong hnh 3. u im ca phng php giao tip ny l d liu c ghi v c rt nhanh v n gin v chip iu khin ch cn xut hoc nhn d liu trn 1 PORT. Tuy nhin, phng php ny c nhc im l tng s chn dnh cho giao tip LCD qu nhiu, nu tnh lun c 3 chn iu khin th cn n 11 ng cho giao tip LCD. - Mode 4 bit: LCD cho php giao tip vi b iu khin ngoi theo ch 4 bit. Trong ch ny, cc chn D0, D1, D2 v D3 ca LCD khng c s dng ( trng), ch c 4 chn t D4 n D7 c kt ni vi chip b iu khin ngoi. Cc instruction v data 8 bit s c ghi v c bng cch chia thnh 2 phn, gi l cc Nibbles, mi nibble gm 4 bit v c giao tip thng qua 4 chn D7:4, nibble cao c x l trc v nibble thp sau. u im ln nht ca phng php ny ti thiu s lines dng cho giao tip LCD. Tuy nhin, vic c v ghi tng nibble tng i kh khn hn c v ghi d liu 8 bit. Trong bi hc ny, ti s trnh by 2 chng trnh con c vit ring ghi v c cc nibbles gi l Read2Nib v Write2Nib. III. AVR v Text LCD. 1. Trnh t giao tip Text LCD. Trnh t giao tip vi LCD c trnh by trong flowchart hnh 6.

Hnh 6. Trnh t giao tip vi Text LCD. s dng LCD chng ta cn khi ng LCD, sau khi c khi ng LCD sn sng hin th. Qu trnh khi ng ch cn thc hin 1 ln u chng trnh. Trong bi ny, qu trnh khi ng c vit trong 1 chng trnh con tn int_LCD, khi ng LCD thng bao gm xc lp cch giao tip, kch thc font, s dng LCD (funcstion set), cho php hin th LCD, sursor(Display control), ch hin th

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tng/gim, shift (Entry mode set). Cc th tc khc nh xa LCD, vit k t ln LCD, di chuyn con tr c s dng lin tc trong qu trnh hin th LCD v s c trnh by trong cc on chng trnh con ring. 2. AVR giao tip vi Text LCD trong WinAVR. Phn ny ti trnh by cch iu khin hin th Text LCD bng vi iu khin AVR trong mi trng C ca WinAVR. Hnh thc l mt th vin hm giao tip Text LCD trong 1 file header c tn l myLCD.h. Cc hm trong th vin bao gm (ch l phn code trong List 0 khng nm trong file myLCD.h). List 0. Cc hm c trong th vin myLCD. 1 2 3 4 5 6 7 8 9 10 char Read2Nib(); //c 2 nibbles t LCD void Write2Nib(uint8_t chr); //ghi 2 nibbles vo LCD void Write8Bit(uint8_t chr); //ghi tr tip 8 bit v LCD void wait_LCD(); //ch LCD rnh void init_LCD(); //khi ng LCD void clr_LCD(); //xa LCD void home_LCD(); //a cursor v home void move_LCD(uint8_t y, uint8_t x); //di chuyn cursor v tr mong mun (dng, ct) void putChar_LCD(uint8_t chr); //ghi 1 k t ln LCD void print_LCD(char* str, unsigned char len); //hin th chui k t

Tuy nhin, trc khi vit cc hm giao tip LCD chng ta cn nh ngha mt s macro v bin. Hy to 1 file Header c tn myLCD.h v vit cc on code bn di vo file ny (bt u t List 1). List 1. nh ngha cc bin thay th. 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 #include <util/delay.h> #define sbi(sfr,bit) sfr|=_BV(bit) #define cbi(sfr,bit) sfr&=~(_BV(bit)) #define EN 2 #define RW 1 #define RS 0 #define CTRL PORTB #define DDR_CTRL DDRB #define DATA_O #define DATA_I #define DDR_DATA /* #define LCD8BIT #define DATA_O #define DATA_I #define DDR_DATA */ PORTB PINB DDRB PORTD PIND DDRD

cbi v sbi l 2 macro c dng xa v set 1 bit trong 1 thanh ghi. V d cbi(PORTA, 5) l xa bit 5 trong thanh ghi PORT v 0. Do WinAVR khng h tr tuy xut trc tip cc bit nn cn nh ngha 2 macro ny h tr. Cc bin EN, RW v RS nh ngha s th t ca chn trn 1 PORT ca AVR c dng kt ni vi cc chn EN, R/W v RS ca LCD. CTRL l bin cho bit PORT no ca AVR c dng kt ni vi cc

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chn iu khin ca LCD. DDR_CTRL l thanh ghi iu khin hng ca PORT kt ni vi cc chn iu khin, DDR_CTRL lun ph thuc vo bin CTRL. Trong trng hp ca bi ny, bn thy ti nh ngha CTRL l PORTB ngha l PORTB c dng kt ni vi cc chn iu khin LCD, v CTRL l PORTB nn DDR_CTRL phi l DDRB (thanh ghi iu khin hng ca PORTB). EN nh ngha bng 2 ngha l chn EN ca LCD c ni vi chn 2 ca PORTB (PB2), tng t chn R/W ni vi chn 1 PORTB (PB1) v chn RS ni vi chn 0 PORTB (PB0). Vic chn cc PORT giao tip v th t chn ph thuc vo kt ni tht trong mch in giao tip, bn phi thay i cc nh ngha ny cho ph hp vi thit k mch in ca bn. L do cho vic nh ngha cc bin thay th kiu ny l nhm to ra tnh tng qut cho th vin hm. V d, mt ngi khng mun dng PORTB iu khin LCD m dng PORTA th ngi ny ch cn thay i nh ngha 2 dng 7 v 8, khng cn thay i ni dung cc hm v trong cc hm ny chng ta ch dng tn thay th l CTRL v DDR_CTRL. Tng t, ti nh ngha 3 bin thay th l DATA_O ngha l PORT xut d liu, DATA_I l PORT nhp d liu v DDR_DATA l thanh ghi iu khin hng. DATA_O v DATA_I l PORT ni vi cc chn D0:7 (mode 8 bit) hoc D4:7 (mode 4 bit) ca LCD, y l cc ng truyn v nhn d liu. Trong v d trn, ti dng chnh PORTB lm ng data v y l trng hp giao tip 4 bit, do 3 chn u ca PORTB kt ni vi cc chn iu khin nn PORTB ch cn tha li 5 chn, chng ta s ni 4 chn PB4, PB5, PB6 v PB7 tng ng vi D4, D5, D6 v D7 ca LCD. Hnh 7 m t cch kt ni AVR v LCD theo v d ny. Tt nhin bn c th s dng PORT khc lm ng data nht l khi bn mun s dng mode 8 bit, v trong mode ny cn ti 11 ng giao tip (3 iu khin + 8 data). Phn c che trong 2 du comment /* */ l trng hp bn mun dng mode 8 bit. s dng mode 8 bit, bn cn nh ngha 1 bin c tn LCD8BIT, bit ny s bo cho cc on chng trnh con thc hin ghi v c d liu theo cch 8 bit. ng thi, bn phi nh ngha li ng giao tip data (DATA_O, DATA_I, DDR_DATA).

Hnh 7. V d Kt ni LCD vi AVR trong mode 4 bit (chip mega8). Phn bn di l phn nh ngha cc hm trong th vin myLCD. Bn hm u tin (xem li List 0) l cc hm h tr, chng ch c dng bi cc hm khc trong th vin v khng c gi trong cc chng trnh ng dng bn ngoi. List 2. c 2 nibbles t LCD.

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01 char Read2Nib(){ 02 char HNib, LNib; 03 DATA_O |=0xF0; 04 sbi(CTRL,EN); //enable 05 DDR_DATA &=0x0F; //set 4 bits cao cua PORT DATA lam input 06 HNib=DATA_I & 0xF0; 07 cbi(CTRL,EN); //disable 08 09 sbi(CTRL,EN); //enable 10 LNib = DATA_I & 0xF0; 11 cbi(CTRL,EN); //disable 12 LNib>>=4; 13 return (HNib|LNib); 14 15 } Hm ny thc hin vic c d liu t LCD ra ngoi, c theo tng nibble 4 bit, kt qu tr v l 1 s 8 bit. Hm ny ch c dng duy nht khi c c Busy (BF) trong chng trnh ch LCD rnh (wait_LCD) mode 4 bit. Trc ht cn nh ngha 1 bin tm HNib (high nibble) v LNib (Low nibble) cha 2 nibbles c v (dng 2, List 2). Dng 5 set chn EN ln mc 1 chun b cho LCD lm vic. Chng ta cn i hng ca PORT d liu trn AVR sn sng nhn d liu v, do ch c 4 bit cao ca PORT data kt ni vi cc ng data ca LCD (v y l mode 4 bit) nn ch cn set hng cho 4 bit ny trn AVR, dng 6 thc hin vic set hng. Trong ch 4 bit, LCD s truyn v nhn nibble cao trc v th dng 7 c d liu t LCD thng qua cc chn DATA_I vo bin HNib, ch l chng ta ch cn ly 4 bit cao ca DATA_I nn cn phi dng gii thut mt n (mask) che cc bit thp li (and vi 0xF0). Dng 8 xa chn EN chun b cho bc tip theo. Tng t, cc dng 10, 11 v 12 c nibble thp vo bin LNib. Hai dng 13 v 14 kt hp 2 nibbles to thnh s 8 bit v tr kt qu v cho on chng trnh. List 3. Ghi 2 nibbles vo LCD. 01 void Write2Nib(uint8_t chr){ 02 uint8_t HNib, LNib, temp_data; 03 temp_data=DATA_O & 0x0F; //doc 4 bit thap cua DATA_O de mask, 04 HNib=chr & 0xF0; 05 LNib=(chr<<4) & 0xF0; 06 07 DATA_O =(HNib |temp_data); 08 sbi(CTRL,EN); //enable 09 cbi(CTRL,EN); //disable 10 11 DATA_O =(LNib|temp_data); 12 sbi(CTRL,EN); //enable 13 cbi(CTRL,EN); //disable 14 } 15 Hm Write2Nib thc hin ghi mt bin 8 bit c tn chr vo LCD theo tng nibble, hm ny c s dng rt nhiu ln trong mode 4 bit. Dng 2 nh ngha 3 bin tm l HNib, LNib v temp_data, khng ging nh khi c t LCD, vic ghi vo LCD c th lm nh hng n cc chn ca PORT dng lm ng d liu nht l khi cc ng iu khin v d liu dng chung 1 PORT (PORTB). Bin temp_data dng trong gii thut mt n khng lm nh hng n cc bit khc khi ghi LCD. Dng 3 c d liu t PORT

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DATA_O v che i cc bit cao, ch lu li cc bit thp vo bin temp_data v cc bit thp ny khng c dng xut nhp d liu (xem hnh 7, cc chn thp ca PORTB dng lm cc chn iu khin). ghi 1 gi tr 8 bit c tn l chr theo cch ghi tng nibbles chng ta cn tch bin chr thnh 2 nibbles. Dng 5 tch 4 bit cao ca chr v cha vo bin HNib. Dng 6 thc hin thm vic di chuyn 4 bit thp ca chr qua tri ri gn cho bin LNib. Nh vy sau 2 dng ny cc bin HNib v LNib c m t nh sau:

Do d liu c sp xp sn sng cc v tr cao (ng vi cc chn D4:7) nn cng vic tip theo ch n gin l xut 2 bin HNib v LNib ra ng DATA_O, cn phi to 1 xung cnh xung chn EN mi ln xut d liu (dng 9, 10). Ch l phi xut nibble cao trc v nibble thp theo sau. List 4. Ghi 8 bit trc tip vo LCD. 01 void Write8Bit(uint8_t chr){ 02 DATA_O=chr; //out 8 bits to DATA Line 03 sbi(CTRL,EN); //enable 04 cbi(CTRL,EN); //disable 05 } on ny rt n gin l xut d liu 8 bit ra DATA_O, dng trong mode 8 bit. Trong mode ny, 8 chn data ca LCD c ni vi 8 ng DATA_O ca AVR. List 5. Ch LCD rnh. 01 void wait_LCD(){ 02 #ifdef LCD8BIT 03 while(1){ 04 cbi(CTRL,EN); //xa EN 05 cbi(CTRL,RS); //y l Instruction 06 sbi(CTRL,RW); //chiu t LCD ra ngoi 07 08 DDR_DATA=0xFF; //hng data out 09 DATA_O=0xFF; // gi lnh c BF 10 sbi(CTRL,EN); //enable 11 12 DDR_DATA=0x00; // i hng data in 13 if(bit_is_clear(DATA_I,7)) break; 14 } 15 cbi(CTRL,EN); //disable for next step 16 cbi(CTRL,RW); //ready for next step 17 DDR_DATA=0xFF; //Ready to Out 18 #else 19 char temp_val; 20 while(1){ 21 cbi(CTRL,RS); //RS=0, the following data is COMMAND 22 sbi(CTRL,RW); //LCD -> AVR

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23 24 25 26 27 28 29 30 }

temp_val=Read2Nib(); if (bit_is_clear(temp_val,7)) break; } cbi(CTRL, RW); //ready for next step DDR_DATA=0xFF;//Ready to Out #endif //_delay_ms(1);

Hm wait_LCD ch lm mt vic n gin l ch cho n khi LCD rnh gn cc cng vic khc. on code trong list 5 trnh by cch 1: c c Busy Flag v ch n khi n bng 0 (LCD rnh). Vic c c BF ph thuc v mode ang s dng l 8 bit hay 4 bit, v th lnh #ifdef trong dng s 2 kim tra mode ph hp trc khi tin hnh c. #ifdef LCD8BIT ngha l nu bin LCD8BIT c nh ngha pha trn (mode 8 bit c dng) th s tin hnh c BF theo mode ny. Bng cch kim tra s c mt ca bin LCD8BIT chng trnh s bit cch ghi v c LCD ph hp, phng php dng #ifdef LCD8BIT c p dng cho tt c cc hm sau ny. Cc on code t dng 4 n 17 thc hin trong mode 8 bit. Trc khi c BF, chng ta cn gi 1 lnh c BF dng 9, sau dng 12 thc hin i hng cc chn data nhn gi tr v. Trong dng 10, kim tra bit th 7 ca DATA_I, DATA_I chnh l gi tr c v v bit th 7 trong gi tr nhn v chnh l c Busy Flag. Nu BF=0 (bit_is_clear(DATA_I,7)) th kt thc qu trnh lp ch vi lnh break;. Trong trng hp mode 4 bit c s dng (#else), qu trnh kim tra c BF cng tng t, im khc nhau duy nht l cch c d liu v c khc, chng ta dng hm Read2Nib c vit trc nhn gi tr v (xem dng 23). Nh trnh by, chng ta c th vit hm wait_LCD bng cch dng hm delay mt khong thi gian c nh, trong dng 29 bn thy mt hm _delay_ms(1) khng c s dng, nu mun bn c th xa ht cc dng lnh trc trong hm wait_LCD v dng hm delay ny thay th, LCD vn s hot ng tt. List 6. Khi ng LCD. 01 void init_LCD(){ 02 DDR_CTRL=0xFF; 03 DDR_DATA=0xFF; 04 //Function set-----------------------------------------------------------------------------05 cbi(CTRL,RS); // the following data is COMMAND 06 cbi(CTRL, RW); // AVR->LCD 07 cbi(CTRL, EN); 08 #ifdef LCD8BIT 09 Write8Bit(0x38); 10 wait_LCD(); 11 #else 12 sbi(CTRL,EN); //enable 13 sbi(DATA_O, 5); 14 cbi(CTRL,EN); //disable 15 wait_LCD(); 16 Write2Nib(0x28);//4 bit mode, 2 line, 5x8 font 17 wait_LCD(); 18 #endif 19 //Display control------------------------------------------------------------------------20 cbi(CTRL,RS); // the following data is COMMAND 21 #ifdef LCD8BIT 22 Write8Bit(0x0E); 23 wait_LCD();

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24 #else 25 Write2Nib(0x0E); 26 wait_LCD(); 27 #endif 28 //Entry mode set-----------------------------------------------------------------------29 cbi(CTRL,RS); // the following data is COMMAND 30 #ifdef LCD8BIT 31 Write8Bit(0x06); 32 wait_LCD(); 33 #else 34 Write2Nib(0x06); 35 wait_LCD(); 36 #endif 37 } Qu trnh khi ng gm 3 bc: function set, display control v entry mode set. Vi function set, ba dng 5,6 v 7 xc lp cc chn iu khin chun b gi cc lnh. Hai dng 9 v 10 vit lnh function set vo LCD theo mode 8 bit. Gi tr 0x38, tc 00111000 l mt lnh xc lp mode 8 bit, LCD 2 dng v font 5x8. Nu mode 4 bit c dng, chng ta cn vit hm function set khc i mt cht. Theo mc nh, khi va khi ng LCD th mode 8 bit s c chn, v th nu mt hm no c ghi vo LCD u tin, LCD s c gng c ht cc chn D0:7 ly d liu, do trong mode 4 bit cc chn D0:3 khng c kt ni vi AVR nn vic c ln u c th dn n sai s. V vy, vic u tin cn lm nu mun s dng mode 4 bit l gi mt lnh function set vi tham s DL=0 (0010xxxx) n LCD bo mode chng ta mun dng. Dng 13 lm vic ny, dng lnh ch n gin set bit D5 nhng chnh l gi lnh dng 0010xxxx n LCD, v th LCD s vo mode 4 bit sau lnh ny. Tip theo qu trnh thao tc vi LCD din ra bnh thng, dng 16 ghi vo LCD m ca function set, trong trng hp ny l m 0x28, tc 00101000: mode 4 bit, LCD 2 dng v font 5x8. Vi Display control, m lnh c dng l 0x0E, tc 00001110 trong 00001 l m ca lnh display control, 3 bit theo sau xc lp hin th LCD, hin th cursor v khng blinking. Vi Entry mode set, m lnh c dng l 0x06 tc hin th tng v khng shift. Xem li phn gii thch tp lnh LCD hiu thm ngha ca m lnh 0x06. List 7. Di chuyn cursor. 01 void home_LCD(){ 02 cbi(CTRL,RS); // the following data is COMMAND 03 #ifdef LCD8BIT 04 Write8Bit(0x02); 05 wait_LCD(); 06 #else 07 Write2Nib(0x02); 08 wait_LCD(); 09 #endif 10 } 11 void move_LCD(uint8_t y,uint8_t x){ 12 uint8_t Ad; 13 Ad=64*(y-1)+(x-1)+0x80; // tnh m lnh 14 cbi(CTRL,RS); // the following data is COMMAND 15 #ifdef LCD8BIT 16 Write8Bit(Ad); 17 wait_LCD();

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18 19 20 21 22 }

#else Write2Nib(Ad); wait_LCD(); #endif

List 7 trnh by 2 hm di chuyn cursor v home (home_LCD) v di chuyn n 1 v tr do ngi dng t. Hm home_LCD tng i n gin v ch cn ghi m lnh 0x02 vo LCD th cursor s t ng di chuyn v home (v tr u tin trn LCD). Hm move_LCD(uint8_t y,uint8_t x) cho php di chuyn cursor n v tr dng y, ct x. im cn ch trong hm ny l cch tnh m lnh cn ghi vo LCD. Thc cht y l lnh set DDRAM address. Xem li bng 2 ta thy m lnh cho lnh ny c dng 1xxxxxxx trong xxxxxxx l mt s 7 bit cha a ch ca DDRAM chng ta cn di chuyn n. V th trc khi thc hin ghi m lnh ny, chng ta cn tnh tham s xxxxxxx theo dng y, ct x. Xem li t chc ca DDRAM trong hnh 3, gi s mt nh dng y v ct x trn, do dng 2 bt u vi a ch 64, 2 nh cng 1 ct trn 2 dng s cch nhau 64 v tr (64*(y-1)). Mt khc do v tr nh c tnh t 0 trong khi chng ta mun gn ta x bt u t 1, v th chng ta cn thm (x-1) vo cng thc tnh. Cui cng chng ta cn phi thm m lnh set a ch DDRAM, m 0x80. Gi tr cui cng ca m lnh l : Ad=64*(y-1)+(x-1)+0x80 (dng 13). Cc dng lnh tip theo trong hm move_LCD thc hin ghi gi tr m lnh vo LCD. Cui cng l phn code hin th LCD c trnh by trong list 8. Phn hin th bao gm 1 chng trnh con: xa LCd, hin th 1 k t v hin th 1 chui cc k t. List 8. Hin th trn LCD.

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01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

void clr_LCD(){ //xa ton b LCD cbi(CTRL,RS); //RS=0 mean the following data is COMMAND (not normal DATA) #ifdef LCD8BIT Write8Bit(0x01); wait_LCD(); #else Write2Nib(0x01); wait_LCD(); #endif } void putChar_LCD(uint8_t chr){ //hin th 1 k t chr ln LCD sbi(CTRL,RS); //this is a normal DATA #ifdef LCD8BIT Write8Bit(chr); wait_LCD(); #else Write2Nib(chr); wait_LCD(); #endif } void print_LCD(char* str, unsigned char len){ //Hin th 1 chui k t unsigned char i; for (i=0; i<len; i++) if(str[i] > 0) putChar_LCD(str[i]); else putChar_LCD(' '); } }

xa ton b LCD chng ta cn gi 1 instruction c m 0x01 n LCD, hm clr_LCD() thc hin vic ny. Lu m lnh xa LCD l 1 instruction, v th cn xa chn RS xung 0 trc khi gi m ny xung LCD (dng 2 xa chn RS). Hm putChar_LCD(uint8_t chr) hin th 1 k t ln LCD, gi tr tham s ca hm ny l m ASCII ca k t cn hin th, chr. Ni dung ca hm hon ton ging hm xa LCD, ch khc y khng phi l 1 instruction nn cn set chn RS ln 1 trc khi gi m lnh n LCD (dng 12). M lnh cho hm ny chnh l m ASCII cn hin th. Cui cng hm print_LCD(char* str, unsigned char len) cho php hin th 1 chui k t lin tip ln LCD, thc cht y l qu trnh lp ca hm hin th 1 k t. Ch tham s len l chiu di cn hin th ca chui. IV. V d iu khin Text LCD bng th vin myLCD. Phn ny ti s minh ha cch s dng th vin myLCD.h hin th cc k t ln 1 Text LCD. S dng phn mm Proteus v mt mch in gm 1 LCD 2x16 (keyword: LM016L), 1 chip Atmega32 v 1 bin tr (POT-LIN) nh trong hnh 8. To 1 Project bng WinAVR c tn l TextLCD_Demo v to file source l main.c, to makefile vi khai bo s dng chip ATmega32 v clock 8MHz. Copy file myLCD.h vo th mc ca Project mi to. Vit code cho file main.c nh trong list 9. Ch cc nh ngha chn kt ni vi LCD trong phn u file myLCD.h phi ging vi kt ni tht trong hnh 8.

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Hnh 8. Mch in m phng LCD vi AVR. List 8. Chng trnh demo iu khin TextLCD, main.c. #include <avr/io.h> #include <util/delay.h> #include "myLCD.h" //include th vin myLCD int main(){ init_LCD(); //khi LCD clr_LCD(); // xa to b LCD putChar_LCD(' '); //ghi 1 khong trng putChar_LCD(' '); //ghi 1 khong trng putChar_LCD('D'); //Hin th kt 'D' print_LCD("emo of the",10); //hin th 1 chui k t move_LCD(2,1); //di chuyn cursor n dng 2, ct u tin print_LCD("2x16 LCD Display",16); //hin th chui th 2 while(1){ }; } s dng th vin myLCD, chng ta cn include file myLCD.h vo Project nh trong dng 3, #include "myLCD.h". Hai dng 6 v 7 thc hin khi ng v xa LCD. Sau , cc dng 9, 10 v 11 t 3 k t l cc khong trng v ch ci D bng hm putChat_LCD. Dng 12 in chui emo of the ngay tip theo ch ci D trc bng hm print_LCD. Dng 13 thc hin di chuyn cursor n v tr dng th 2, ct

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u tin ca LCD trc khi tin hnh in chui th 2 2x16 LCD Display dng code 14. Nu bn thc hin ng trnh t nh trn, kt qu thu c s nh trong hnh 8.

Ma trn LED

Ni dung

Cc bi cn tham kho trc

Cu trc AVR. WinAVR. C cho AVR. M phng vi Proteus.

1. 2.

Ma trn LED. AVR v ma trn LED.

Download v d

I. Ma trn LED. Ma trn LED tc Dot Matrix LED l tp hp nhiu n LED c b tr thnh dng ma trn hnh ch nht hoc vung vi s hng l a v s ct l b. Ma trn LED c dng rt nhiu trong cc ng dng hin th nh cc bin qung co, hin th thay th LCD hoc thm ch dng hin th video gim s lng cc

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ng iu khin, trong cc ma trn LED cc LED c ni chung vi nhau theo hng v ct. S lng LED trn ma trn LED l axb trong khi s lng ng ra bng tng s hng v ct: a + b. Vic iu khin 1 ma trn LED kch thc ln i hi thit k mt mch driver v iu khin rt phc tp. Vi mc ch gip bn c lm quen khi nim ma trn LED, trong phm vi bi ny ti ch trnh by thao tc vi 1 ma trn LED c kch thc 7x5 (7 hng, 5 ct). ma trn LED 7x5 thng c dng hin th cc k t trong bng m ASCII thay cho Text LCD. Tuy nhin, bn c th ghp cc ma trn LED ny li hin th cc loi hnh nh bt k c phn gii thp. Hnh 1 m t mt cu trc ca mt ma trn LCD 7x5 vi 12 ng ra c t tn t C0C4 v D0D6 (C i din cho Control line v D l Data line).

Hnh 1. Ma trn LED 7x5. Bn trong cc ca ma trn LED l cc LED pht sang. Trong m hnh trn, Cathod (cc m) ca cc LED trn mi hng c ni chung vi nhau v ng ra chung l cc ng D (Data). Cc Anod ca cc LED trn mi ct c ni chung to thnh cc ng C (Control). Thng thng, cc ng D v C c chn sao s s lng ng D nhiu hn ng C hoc sao cho s lng cc ng D gn nht vi s 8, 16, 32 (ly tha ca 2). L do ca vic chn ny nhm gim kch thc b font cha cc k t hoc hnh nh hin th ln ma trn LED, bn s hiu r hn khi tm hiu cc iu khin ma trn LED 7x5 bn di.

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a)

b)

Hnh 2 m t cch m ma trn LED 7x5 c dng hin th s 4. Trc ht chng ta s kho cch cho sang cc LED m khng cn quan tm n bng font. Quan st ct th nht (ct C0) trong hnh 2a, trong ct ny ch c 2 LED hng D2 v D3 l sang, cc LED cn li tt. iu ny c thc hin bng cch kch chn C0 (Anod) ln mc cao, ko cc chn D2, D3 xung mc 0 trong khi cc chn Data khc c gi mc cao. Cc ct khc c thc hin tng t. Tuy nhin, cu hi y l lm sao hin th cc ct vi cc n LED sng khc nhau trong khi cc ng Cathod ca chng u c ni chung (thnh cc chn D). V d mt ngi ko tt c 5 chn C0C4 ln mc cao vo xut tn hiu ra cc chn D, khi tt c cc LED trn dng mt hng s sng hoc tt nh nhau. B quyt y chnh l k thut qut, chng ta s hin th tun t cc ct vi cc gi tr tng ng ca chng ch khng hin th ng thi. Trong v d hin th s 4, trc ht hy kch chn C0 ln cao trong khi cc chn C1C4 mc thp, xut tn hiu ra cc chn D hin th ln ct C0. Tip theo ko chn C1 ln cao v cc chn Control khc mc thp, xut d liu ra cc chn D hin th ct C1C nh th cho n khi hin th ht cc ct th quay li ct C0. Qu trnh ny gi l qut LED. Do tc qut rt cao nn chng ta s khng c cm gic nhp nhy, cc ct ca ma trn nh c hin th ng thi. Ch l sng ca LED ph thuc vo s ct LED, nu bn qut qu nhiu ct LED, t l thi gian ON ca mi ct s rt nh so vi thi gian OFF v phi ch qut cc ct khc. V th nu ma trn LED c nhiu ct hoc khi ghp nhiu ma trn, cc mch driver cn c s dng m bo sng ca LED. Gi s mi LED i din cho 1 bit v cc LED sng i din cho gi tr nh phn 1 trong khi cc LED tt l s 0. Hnh 2b th hin m hnh s nh phn cho trng hp hin th s 4 trn ma trn LED 7x5. Nu xem mi ct ca ma trn l 1 con s 7 bit th 5 gi tr cn thit hin th s 4 l: 0x0C, 0x14, 0x24, 0x7F, 0x04. B 5 gi tr ny to thnh m font cho k t 4, chng s c nh ngha trc v lu trong b nh ca chip iu khin (AVR), mi ln mt k t c yu cu hin th, b font tng ng ca k t s c load ra v xut ln lt trn cc ng Data, y chnh l l do ti sao chng ta gi cc ng D l cc ng Data. Cch qut LED ti va trnh by l cch qut ngang, bn c th thc hin qut dc nu ng dng

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yu cu. Trong phng php qut dc, cc chn hng chung s c dng chn hng cn hin th, d liu s xut ra theo tng hng trn 5 ct v ln lt thay i hng (hng 0 trc, n 1v cui cng l 6). So snh 2 cch qut cho trng hp ma trn LED 7x5, r rng trong cch qut ngang chng ta ch cn quet 5 ct cho mi ln LED nn t l thi gian ON s cao hn (1/5 so vi 1/8 ca cch qut dc). Mt khc, nu thc hin qut dc chng ta cn 8 s s to thnh 1 b font cho mt k t v v th tn nhiu b nh hn cho vic lu tr bng font. Trong bi hc ny ti thc hin theo cch qut ngang v bng font cng c xy dng cho cch qut ny. II. AVR v Ma trn LED. Phn ny ti minh ha cch hin th ma trn LED 7x5 bng AVR. Chng ta s thc hin trn duy nht mt ma trn LED, cho cc ng dng cn nhiu LED bn c hy t pht trin t tng trong phn ny. Hy v mt mch in m phng bng phn mm Proteus nh trong hnh 3.

Hnh 3. Hin th ma trn LED bng AVR. Cc chn C ca ma trn c ni vi cc chn trn PORTC ca chip AVR ATmega32, v cc chn D c ni vi PORTD. Hy to 1 Project bng Programmer Notepad tn DotMatrix v to 2 file tn font.h cng dotmatrix.c trong Project ny. File font.h cha bng font ca cc k t v file dotmatrix.c l file chnh cho chng trnh demo. List 1 trnh l mt phn ni dung ca file font.h v List 2 l ni dung file dotmatrix.c. List 1. Bng font.

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List 2. Chng trnh demo.

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iu cn quan tm u tin l kch thc bng font, trong v d ny bng font c xy dng cho 223 symbol c m ASCII t 32 n 255 (do cc m ASCII trc 32 khng c symbol tng ng nn c th b qua tit kim b nh), mi symbol cn 5 s 8 bits, nh th chng ta cn tng cng 1115 byte cho bng font trong khi kch thc SRAM ca chip ATmega32 ch l 2KB (2048 byte). Nu dng SRAM cha bng font s rt ph phm v y l 1 bng tnh, gi tr trong bng hon ton khng thay i m ch c truy xut c. V th chng ta c th tn dng b nh chng trnh (Flash) lu bng font ny. Dng u tin trong List 1 chng ta include header pgmspace.h s dng cc thao tc trn b nh chng trnh. Tip theo chng ta khai bo 1 mng tnh c tn font7x5 vi kiu d liu l prog_char tc l kiu char nhng cha trong b nh chng trnh (Program memory). Gi tr cha trong mng font7x5 chnh l d liu ca bng font, thc cht mng font7x5 l mng 1 chiu lin tc, vic tch ra trn nhiu dng c mc ch gip ngi c d hnh dung khi truy cp cc gi tr ca mng xut ra sau ny. Bn hy hiu rng c mt t hp 5 s s to thnh mt symbol hin th cho ma trn LED. D liu trong bng font c sp xp theo trnh t ASCII v to iu kin thun li khi truy xut bng font theo m ASCII ca k t cn hin th. Tuy nhin cn ch l bng font c bt u cho symbol c m ASCII l 32 ch khng bt u t m ASCII 0, v th khi truy cn bng font t m ASCII chng ta cn ly m ASCII tr i 32 c v tr chnh xc trong bng. Tip theo chng ta s tm hiu chng trnh chnh, dng 3 trong list 2 include file font.h s dng bng font trong chng trnh chnh. Cc dng t 5 n 9 nh ngha cc PORT kt ni vi ma trn LED, PORTD l Data bus trong khi PORTC l control lines. Chng trnh con void DOTputChar75(uint8_t chr) trong dng 11 l th tc c d liu t bng font v hin th trn ma trn LED. Tham s chr ca chng trnh ny chnh l m ASCII ca k t cn hin th trn ma trn LED. Dng 12 khai bo 2 bin ph, trong bin line cha tn hiu iu khin cho cc ng Control. Dng 13 khai bo mt bin tm tchr dng cha a ch d liu cn ly ra t bng font xut ra cc ng Data, v m ASCII l mt s 8 bit trong khi s lng d liu trong bng font ln gp 5 ln s lng k t, v th cn khai bo bin tchr c kiu d liu 16 bit. Ni

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dung chnh ca on chng trnh ny nm trong vng lp for, bin i i din cho s th t ca cc chn Control c cho chy t 0 n 4, trong dng 15 CTRL_PORT=line; xut tn hiu iu khin ra CTRL_PORT tc ra cc chn C. Do bin line c khi to bng 1 nn ln lp u tin gi tr CTRL_PORT=0b00000001, tc chn C0 mc cao trong khi cc chn cn li mc thp, ct u tin c chn. Sau khi 1 ct c chn, dng 16 DATA_PORT=~pgm_read_byte(&font7x5[((tchr - 32) * 5) + i]); c v xut d liu t bng font ra cc chn Data. Trc ht l cch tnh a ch ca d liu trong bng font. Nh trnh by trong phn gii thch cho bng font, bng ny c chng ta bt u t k t c m 32 nn chng ta cn tr i 32 tham chiu n v tr chnh xc trong bng font: tchr-32. V d mun hin th k t c m chr = 48 (m ca k t 0), v tr ca t hp d liu to nn s 0 c cha trong bng font v tr 16, gi tr ny c tnh 48-32=16. Tip theo, do mi k t c to thnh t 5 s nn a ch thc cht ca s u tin trong t hp s l (tchr-32)*5. di chuyn trong phm vi 5 d liu ng vi 6 ct ca ma trn LED, bin i c cng dn vo a ch ny v chng ta c: tchr - 32) * 5) + i. c d d liu dng byte t b nh chng trnh, chng ta cn dng hm pgm_read_byte, hm ny c nh ngha trong header pgmspace.h c khai bo trong file font.h. Nh vy saiu khi thc hin pgm_read_byte(&font7x5[((tchr - 32) * 5) + i]) chng ta thu c d liu 1 byte tng ng vi ct th i ca k t chr t bng font, vic cui cng c th l xut gi tr ny ra DATA_PORT. Tuy nhin, trc khi xut byte c c ra DATA_PORT, chng ta cn o cc bit ca byte ny bng ton t ~, l do c gii thch l do cc LED trong ma trn trong v v ny c cc hng ni vi cc m Cathode, mt LED sng th gi tr cn cp cho bit D tng ng l 0 ngha l ngc li so vi cch chng ta to bng font (sng l 1). Ch bng mt thao tc n gin l ton t ~ chng c th d dng vt qua tr ngi ny. Trong trng hp ma trn LED c cc hng ni vi cc dng Anode th chng ta khng cn o gi tr c v. Dng 17 thc hin dch chuyn gi tr ca bin line sang tri 1 v tr, vic lm c tc dng chun b cho ln k tip chn C k tip s c kch. Hm delay trong dng 18 gip cc LED trong ct hin ti sng trong 1 khong thi gian trc khi chuyn qua ct khc. Chng trnh chnh trong v d ny tht s rt n gin, chng ta trc ht cn khi ng hng xut nhp cho cc PORT v sau gi hm DOTputChar75() trong vng lp v tn while(1). v d trn, k t 4 c xut ra v kt qu hin th nh trong hnh 3. Ch l hm DOTputChar75() ch qut qua cc ct 1 lt, v th mun hin th mt k t trong mt khong thi gian chng ta cn gi hm DOTputChar75() lp li trong khong thi gian .

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KeyPad

Ni dung

Cc bi cn tham kho trc

Cu trc AVR. WinAVR. C cho AVR. M phng vi Proteus. Text LCD

1. 2.

Keypad 4x4. ckeypad 4x4 bng AVR.

Download v d

I. Keypad 4x4. Keypad l mt "thit b nhp" cha cc nt nhn cho php ngi dng nhp cc ch s, ch ci hoc k hiu vo b iu khin. Keypad khng cha tt c bng m ASCII nh keyboard v v th keypad thng c tm thy trong cc thit b chuyn dng. Cc nt nhn trn cc my tnh in t cm tay l mt v d v keypad. S lng nt nhn ca mt keypad thay i ph thuc vo yu cu ng dng. Trong bi ny ti gii thiu cch iu khin ca mt loi keypad n gin, keypad 4x4. Gi l keypad 4x4 v keypad ny c 16 nt nhn c b tr dng ma trn 4 hng v 4 ct. Cch b tr ma trn hng v ct l cch chung m cc keypad s dng. Cng ging nh cc ma trn LED, cc nt nhn cng hng v cng ct c ni vi nhau, v th vi keypad 4x4 s c tng cng 8 ng ra (4 hng v 4 ct). M hnh Keypad 4x4 c th hin trong hnh 1.

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a) Hnh 1. Keypad 4x4.

b)

Hnh 1b l m hnh tht ca 1 keypad 4x4 v hnh 1a l cu hnh bn trong ca n. Bn hng ca keypad c nh du l A, B, C v D trong khi 4 ct c gi l 1, 2, 3 v 4. Hot ng ca keypad: Gi s nht '2' c nhn, khi ng C v 2 c ni vi nhau. Gi s ng 2 c ni vi GND (mass, 0V) th C cng s l GND. Tuy nhin, cu hi t ra l bng cch kim tra trng thi ng C chng ta s c kt lun nt '2' c nhn? Gi s tt c cc ng 1, 2, 3, 4 u ni vi GND, nu C= GND th r rng chng ta khng th kt lun nt '1',= hay nt '2' hay nt '3' hay nt '-' c nhn. K thut khc phc vn ny chnh l k thut "qut" keypad. K thut qut keypad bng AVR c trnh by nh sau: - Ni tt c 8 chn ca keypad vi 1 PORT ca AVR, v d PORTB theo th t bn di:

- Cc chn 1, 2, 3, 4 c set nh cc chn Output v gi mc cao, cc chn A, B, C, D l Input v c in tr ko ln. Ln lt ko chn 1, 2, 3, 4 xung thp (ln lt xut gi tr 0 ra tng chn), c trng thi

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cc chn A, B, C, D kt lun nt no c nhn. V d nh trong hnh 1, nt '2' c nhn th qu trnh qut s cho kt qu nh sau:

Bc 1: ko chn 1 xung 0 (cc chn 2,3,4 vn mc cao), kim tra 4 chn A, B, C, D thu c kt qu D=1, C=1, B=1, A=1. (gi tr c v ca PINB l 00001111 nh phn)

Bc 2: ko chn 2 xung 0, kim tra li A, B, C, D, kt qu thu c D=1, C=0, B=1, A=1 (gi tr c v ca PINB l 0b00001011 nh phn). Chn C=0 tc c 1 nt hng th 3 c nhn, chng ta li ang Bc th 2 tc nt nhn thuc ct th 2. Chng ta c th dng qu trnh qut ti y v kt qu thu v nt hng 3, ct 2 (tc nut '2' c) c nhn.

Qu trnh qut cho cc nt khc cng xy ra tng t. Ch , nu c 1 nt no c nhn th c 4 kh nng c th c v t 4 A,B,C,D l:

D=1, C=1, B=1, A=0: nt hng A c nhn, gi tr c v l 0x0E (cc ng A,B,C,D c ni vi 4 bit thp ca PORT trn AVR).

D=1, C=1, B=0, A=1: nt hng B c nhn, gi tr c v l 0x0D . D=1, C=0, B=1, A=1: nt hng C c nhn, gi tr c v l 0x0B . D=0, C=1, B=1, A=1: nt hng D c nhn, gi tr c v l 0x07 .

tin li khi so snh kt qu c v, khi lp trnh c keypad chng ta nn lp 1 mng 4 phn t cha 4 s c th c v t keypad. V d uint8_t scan_code[4]={0x0E,0x0D,0x0B,0x07}; Trong phn tip theo chng ta s kho st cch c keypad 4x4 bng 1 chip AVR Atmega32. II. c Keypad 4x4 bng AVR. Chng ta s m phng cch c v hin th gi tr t keypad 4x4 bng phn mm Proteus. Cc m c c t keypad s hin th ln 1 Text LCD 16x2. Th vin myLCD.h c dng hin th ln LCD (xem li bi Text LCD). Mch in m phng th hin trong hnh 2.

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Hnh 2. c v hin th t Keypad 4x4. Hy to 1 Project bng WinAVR vi tn gi KEYPAD, to file main.c v add vo Project, to Makefile, ng thi copy file myLCD.h t bi hc Text LCD vo th mc cha Project KEYPAD. M file myLCD.h v sa phn khai bo PORT nh List0. List 0. Khai bo PORT trong file myLCD.h 01 02 03 04 05 .... #define CTRL #define DDR_CTRL #define DATA_O #define DATA_I PORTC DDRC PORTC PINC

83

06 #define DDR_DATA 07 .... 08

DDRC

Vit on code trong List1 vo file main.c List 1. Ni dung file main.c

84

85

 dng 3 chng ta include file myLCD.h s dng cc hm thao tc Text LCD. Trong cc dng 5, 6 v 7 chng ta nh ngha PORT giao tip vi Keypad, theo PORTB c dng cho Keypad. Dng 9 khai bo mt mng 4 phn t cha m c v t Keypad nh tho lun trong phn trn. Cc dng code t 10 n 13 khai bo mt mng 2 chiu c 16 phn t cha m ASCII ca cc k t i din cho cc Button, ti sp xp cc k t dng ma trn d dng tng ng vi cc nt trn keypad. Dng 14 khai bo bin key loi 8 bit khng du, y l bin cha m ascii khi c keypad. Dng 15 khai bo hm qut Keypad c tn checkpad(). Tt c gii thut qut v c keypad u nm trong hm ny, gi tr tr v ca hm l m ascii ca nt c nhn. Trc khi kho st on code trong chng trnh main, chng ta s tm hiu chng trnh con checkpad(). dng 31 trong chng trnh con checkpad, chng ta khai bo 3 bin ph 8 bit khng du, i l bin i din cho ct ca keypad v j l hng, keyin l gi tr c v t cc chn A, B, C, D. Vng lp for 4 ln trong dng 32 ca bin i chnh l 4 bc qut m ti trnh by trong v d trn. bc 1, bin i=0, nu chng ta dch tri s 1 nh (1<<(4+i)) th gi tr thu c l (1<<(4+i))=0b00010000, kt hp vi dng code 33: KEYPAD_PORT=0xFF-(1<<(4+i)); chng ta thu c KEYPAD_PORT=0xEF. S 4 trong php dch xut hin v cc ct ca Keypad c ni vi 4 bit cao ca PORT trn AVR. Tm li, sau bc u tin ct th nht ca Keypad c ko xung mc 0, sn sng cho qu trnh kim tra cc hng A,B,C,D trong cc dng tip theo. Dng 35 c gi tr t Keypad v bin keyin, v chng ta kt ni cc chn A,B,C,D ca Keypad vi 4 bit thp ca PORT nn chng ta ch quan tm n gi tr ca 4 bit thp ny, vic AND (&) gi tr c v vi 0x0F cho php chng ta b qua 4 bit cao. Trong dng 36, chng ta kim tra xem nu gi tr c v khc 0x0F th thc hin cc dng tip theo. Nu keyin =0x0F ngha l khng c bt k nt no trn ct 1 c nhn, cc dng tip theo khng thc hin, vng lp for cho bin i c tip tc gi tr tip theo. Nu bin keyin khc 0x0F th chng ta bit rng c 1 nt no trn ct i c nhn, cc dng tip theo s xc nh chnh xc nt no c nhn. Dng 37 cho bin hng j chy t 0 n 4, dng 38 kim tra gi tr keyin, nu keyin bng phn t th j trong mng scan_code m chng ta nh ngha trc th nt trn hng j c nhn, tm li nt c nhn l nt hng j v ct i, chng ta tr v gi tr m ascii ca nt ny bng cch ly gi tr tng ng ca mng ascii_code c nh ngha trc : return ascii_code[j][i]. Nu qu trnh qut tht bi chng ta tr v gi tr 0. Ni dung ca chng trnh chnh l khi ng chip v thc hin demo qu trnh c Keypad, Dng 19 chng ta khai bo s dng 4 bit thp ca KEYPAD_PORT lm input (cc chn A,B,C,D l input) v 4 bit cao lm output. Dng 18 khi ng cc in tr ko ln cho 4 bit thp. Hai dng 21 v 22 khi ng v xa Text LCD. Trong vng lp v tn while(1), chng ta qut keypad dng 24 v hin th ln LCD dng 25 (ch hin th nu qu trnh qut thnh cng). Trong v d ny ti ch trnh by gii thut qut Keypad c bn, vn cn mt s vn khc nh kim tra s kin nhn (key down), th (key up)...bn c hy t gii tuyt theo cch ca ring mnh

86

Giao tip card MMC/SD

Ni dung

Cc bi cn tham kho trc Gii thiu S lt v MMC/SD card Phng php giao tip MMC/SD card Giao tip AVR vi MMC/SD card S dng th vin myMMC

1. 2. 3. 4. 5.

Cu trc AVR. WinAVR. C cho AVR. M phng vi Proteus. Giao tip AVR vi my tnh (I)

Download v d I. Gii thiu Bi vit ny gii thiu v cu trc v phng thc giao tip vi cc loi th nh (card) MMC v SD. Trong cc phng thc giao tip vi MMC/SD, SPI s c chn minh ha cch s dng AVR c v ghi card MMC/SD. C th bi ny bao gm: - S lt cc loi card MMC/SD - S mch in giao tip vi MMC/SD card - nh dng lnh v phng thc giao tip vi MMC/SD - Giao tip ghi/c MMC/SD bng AVR thng qua chun SPI Ch : khi ni v MMC/SD card ngi ta hay ni thm v cc nh dng a FAT, FAT32 cho MMC/SD card. Tuy nhin, y l mt vn ln khc m bi hc ny khng cp. Chng ta ch hc cc giao tip vi MMC/SD m khng cn quan tm n FAT hay FAT32. II. S lt v MMC/SD Card MMC l vit tt ca cm t ting anh Multi-Media Card v SD l Secure Digital Card. Nhn chung MMC v SD ging nhau v mt cu trc vt l v phng thc giao tip. im khc nhau ln nht ca 2 loi card ny l v tnh nng bo mt d liu v tc giao tip. SD card xut hin sau MMC card nn SD c nhiu tnh nng v tc cao hn MMC. Tuy nhin, i vi vic ghi-c MMC v SD tc thp bng cc vi iu khin (nh AVR) th s khc nhau ca 2 loi card ny l khng ng quan tm. V vy, t by gi chng ta s dng cm t chung MMC/SD ch chung cho cc loi card ny. V phng thc giao tip, MMC v SD card u c th c giao tip thng qua 2 ch (mode) c bn l SD/MMC mode v SPI mode. Giao tip vi bng mode SD/MMC c tc cao nhng i hi chip iu khin cng phi c tc cao. Mode ny khng ph hp vi vic giao tip bng vi iu khin. Ngc li, mode giao tip SPI tuy c tc thp hn nhng ph hp vi cc chip iu khin nh AVR. Phn gii thiu v MMC/SD card trong bi ny v th ch tp trung vo mode SPI. V hnh dng bn ngoi, MMC v SD c cng kch thc v cu trc chn gn nh nhau, nh trong hnh 1.

87

Hnh 1. B tr chn ca MMC v SD card Nh trnh by trong hnh 1, MMC card (hnh bn phi) c 7 chn trong khi SD card (hnh bn tri) c 9 chn. Cc chn thm 8, 9 trn SD card l cc chn d liu ca mode SD/MMC nn khng quan trng khi giao tip mode SPI. Ngoi ra 7 chn cn li trn SD card hon ton ging vi MMC. Phn bn di m t chc nng cc chn trong mode SPI. - Chn 1: CS (Chip Select) l chn chn chip dng trong mode SPI, chn ny ni vi chn chn chip ca chip iu khin (AVR). - Chn 2: DI (Data Input) hay l chn MOSI ca chun SPIm, chn ny cn c ni vi chn MOSI trn chip iu khin (AVR). - Chn 3, 6: l cc chn GND. - Chn 4: l chn ngun. - Chn 5: CLK l chn gi nhp trong mode SPI, chn ny s c ni vi SLK trn chip iu khin (AVR). - Chn 7: DO (Data Output) hay chn MISO ca chun SPI, chn ny c ni vi chn MISO trn chip iu khin (AVR). Ngun nui MMC/SD card: y l im cn lu khi s dng cc card MMC/SD, ngun cho cc card ny phi nm trong khong 2.7V n 3.6V. iu ny thng gy kh khn khi iu khin MMC/SD card bng cc vi iu khin v cc mch iu khin thng dng mc in p 5V. V th, khng ging nh cc chip in t s thng thng, bn khng c php ni MMC/SD card trc tip vi cc chip iu khin c ngun nui 5V. Theo ngh ca ti, chng ta c th dng ngun 3.3V cho MMC/SD card. Ngun 3.3V c th c to bng cc chip n p nh 1084K33, LM317 hoc bng cc cu chia p dng in tr. Kt ni gia mch iu khin (5V) v MMC c th thc hin gin tip thng qua cc chip buffer, qua transitor, optotransistor hay cu chia p in tr,Ti ngh mt mch in kt ni gia chip iu khin vi card MMC/SD nh trong hnh 2.

88

Hnh 2. S kt ni gia chip iu khin v card MMC/SD Trong s hnh 2 cc cu chia p 1.8K-3.3K c dng to mc in p khong 3.3V cho card MMC/SD. Do mch iu khin dng in p ngun 5V, tn hiu xut ra t cc ng SS, MOSI hay SCK c mc thp 0V v mc cao 5V, nu kt ni trc tip cc ng ny vi card MMC/SD c th lm hng card. Gi in p c chia khi ti MMC/SD card l V, bn c th d dng tnh c in p t mch iu khin nh sau. Khi ng ra 0V in p V=0V, khi in p ng ra 5V th V=5*3.3/(3.3+1.8)=3.2V, gi tr ny ph hp cho MMC/SD card. Trng hp chn MISO (7), y l chn d liu truyn t MMC/SD card v mch iu khin nn khng cn gim in p, tn hiu 3.3V t MMC/SD c th c chip iu khin chp nhn. Do , chn MISO c ni trc tip gia MMC/SD v chip iu khin. Ch l card v chip iu khin c ni GND chung. III. Phng thc Giao tip MMC/SD Card Nh ni t u, chng ta ch kho st giao tip vi MMC/SD ch SPI, v th cc thut ng giao tip c mc nh l SPI. Nu xem li bi hc v SPI bn s thy c 4 modes hot ng ca chun ny ty thuc vo cnh ca xung gi nhp SCK. MMC/SD card hot ng tt mode 0 ca SPI tc l CPHA=0, CPOL=0. Nu gi d liu giao tip gia chip iu khin ch (hy gi l host) v MMC/SD card l mt thng ip (Message) th thng ip ny c chia thnh 3 loi: Lnh (Command), Tr li (Response) v D liu (Data token). Giao tip gia host v card c bt u khi host ko chn chn chip CS (chn 1) xung mc 0. Lnh c host truyn n card thng qua ng MOSI (chn 2). Tr li c card gi ln host qua ng MISO v ng CLK l ng gi nhp ca host vi card. Giao tip gia host v card thng c phn thnh 2 giai on: giai on khi ng v giai on truy cp d liu. Trong giai on khi ng, host s gi mt s lnh khi ng, reset, ci t mt s thng s giao tip nh di 1 khi d liu (chng ta gi l sector)V trong giai on truy cp d liu, mt hay nhiu khi d liu s c host ghi vo card hoc

89

host c t card mt cch lin tip. Trong cc loi thng ip giao tip gia host v card, Lnh l thng ip quan trng v phc tp nht. c th thc hin giao tip gia host v card chng ta cn bit cu trc v chc nng ca Lnh. Phn ny chng ta kho st cu trc ca 1 lnh v sau tm hiu mt s lnh c bn nht giao tip vi MMC/SD card. Lnh t host gi n card phi c ng gi trong 1 nh dng gm 48 bit. ngha ca cc bit c gii thch nh sau:

Dng u tin trong bng trn m t tn cc bit (Description), dng th 2 ch v tr bit (Bit position), dng 3 ch rng ca tng nhm bit (Width) v dng 4 ch cc gi tr m cc bit c th mang. - Bit 47, gi l start bit, l bit bo hiu cho card rng sp c 1 lnh c host gi n. Gi tr ca start bit lun bng 0. - Bit 46, Tranmission bit, bit ny ni rng Lnh s c gi theo chiu t host n card. Bit ny lun c gi tr 1 trong tt c cc lnh. - Bit 45:40, cc bit t 40 n 45 gi l ch s lnh (Command index). Thc ra y l m lnh m host gi cho card. C 1 danh sch cc lnh c bn, mi lnh c 1 chc nng ring v ch s lnh l th t ca lnh trong danh sch ny. Chng ta s kho st chc nng ca tng lnh sau. - Bit 39:8, cc bit t 8 n 39 l cc tham s ca lnh (argument). V d host mun c 1 khi d liu t card, trc ht n phi gi m lnh (command index) sau phi gi km a ch ca khi d liu m n mun c. Gi tr a ch khi d liu trong v d ny gi l tham s ca lnh c d liu. - Bit 7:1, y l 7 bit mang gi tr kim tra. CRC l vit tt ca cm t Cyclic Redundancy Check, l mt chun kim tra tnh hp l ca d liu c gi. Nhn chung vic tnh CRC tng i phc tp, rt may trong cc lnh giao tip c bn vi card ch c lnh 0 (CMD0) l cn CRC, chng ta s kho st k hn v iu ny trong lc vit chng trnh giao tip vi card. - Bit 0, l Stop bit bo hiu lnh kt thc, bit ny c gi tr mc nh l 1. Nh th, gi 1 lnh c ngha n card, host cn phi sp xp cc bit thnh 1 nh dng 48 bit nh trn, sau chia 48 bit ny thnh tng byte gi n card thng qua SPI. Trong cc phn tip theo chng ta s kho st cc lnh c bn giao tip vi MMC/SD vi host l vi iu khin AVR. IV. Giao tip AVR vi MMC/SD Card minh ha giao tip vi MMC/SD card theo SPI, chng ta s dng chip AVR Atmega32 lm chip ch host. Chng ta s to 1 th vin mang tn myMMC trong WinAVR. Th vin myMMC bao gm 1 file header myMMC.h khai bo cc hm giao tip vi MMC/SD card v file myMMC.c cha ni dung cc hm. Do vic giao tip vi MMC/SD card c thc hin thng qua module SPI ca AVR, bn phi nm cch s dng module SPI ca AVR trc khi c cc phn tip theo ca bi ny. Cc hm giao tip vi MMC/SD card c rt nhiu, chng ta ch tm hiu v s dng cc hm c bn nht. bit thm thng tin v cc hm cho MMC/SD, bn c c th tham kho phn 4.8 - Commands trong ti liu SanDisk SD Card Product Manual. Vi cc hm c chn gii thiu, ti s gii thch c th

90

trong lc vit hm. to th vin myMMC, hy to 1 file myMMC.h c ni dung nh trong List 1.

91

92

File header myMMC.h gm 2 phn. Phn u cha cc nh ngha v chn, PORT ca module SPI trn AVR, phn ny c th c thay i ty theo cu hnh c th ca tng loi AVR. Dng 12 chng ta nh ngha 1 bin tn Block_len = 512, bin ny ch di ca 1 khi d liu. Khc vi cc chip nh (RAM, EEPROM,) cc MMC/SD card khng cho php truy cp (c ghi) trn tng byte ring l m phi truy cp 1 hoc nhiu khi d liu. Mt khi d liu c th bao gm 512 bytes, 1024 bytes,ty theo cch khai bo khi khi ng card. Tuy nhin, trong bi ny chng ta ch dng khi d liu c di 512 bytes. Cc dng t 23 n 27 nh ngha mt s ch s lnh (m lnh) c bn giao tip vi MMC/SD card. C th chng ta s s dng cc m lnh sau: Lnh CMD0 (0x00): Go to Idel state, reset card v a card vo trng thi ngh, ch i. Lnh CMD1 (0x01): Send operation condition, yu cu card tr li v trng thi hot ng hin ti ca card. Lnh CMD16 (0x10): Set blocklen, ci t gi tr di ca khi d liu. Lnh CMD17 (0x11): Read single block, c 1 khi d liu t card. Bin mmc_status l mt bin ton cc cha trng thi li khi giao tip vi MMC/SD card, nu vic giao tip din ra thun li gi tr ca mmc_status bng 0, ngc li gi tr ca mmc_status s bo cho chng ta bit li xy ra v tr no, c th: mmc_status = 0: ok mmc_status = 1: li khi reset, timeout xy ra trong qu trnh reset mmc_status = 2: li xy ra khi gi lnh CMD1 mmc_status = 3: li xy ra khi set di khi d liu mmc_status = 4: li khi gi lnh writeblock CMD24, timeout xy ra mmc_status = 5: timeout xy ra trong qu trnh ghi d liu mmc_status = 6: timeout xy ra do card ang bn mmc_status = 7: li khi gi lnh readblock CMD17 mmc_status = 8: li khi kim tra token (du hiu) ca lnh c d liu Cc dng t 44 n 46 khai bo cc hm khi ng, truyn v nhn thng qua SPI ca AVR. Cc dng t 50 n 54 l cc hm giao tip vi MMC/SD card. C th ni dung cc hm ny s c kho st trong file myMMC.c, xem List 2, List 3 v List 4.

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List 2 l phn u ca file myMMC.c cha ni dung cc hm khi ng v truyn/nhn thng qua SPI. Hm SPI_MasterInit(void) khi ng module SPI ca AVR nh 1 Master SPI, cho php ngt nhn d liu SPI v mode hot ng l mode 0 (CPHA=0, CPOL=0). Hm SPI_tByte(uint8_t data) truyn 1 byte d liu

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t AVR n card v hm SPI_rByte(void) c 1 byte d liu t card v AVR.

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96

List 3 cha cc hm c bn cho MMC/SD card bao gm hm nhn Response t card, hm gi Lnh n card v hm khi ng card. Hm mmc_rResponse(uint8_t Response): sau khi gi bt c th g n card, card u tr li li bng 1 gi tr gi l Response, ty vo trng hp c th m Response c gi tr khc nhau (thng l 0). Hm mmc_rResponse(uint8_t Response) cho php kim tra response c ng vi yu cu hay khng, nu ng th tr v 0, khng th tip tc yu cu card tr v response (bng cch gi dummy byte (byte v ngha) l 0xFF qua SPI). Vic yu cu response s c lp i lp li (dng vng lp while) cho n khi no card tr v ng response mong mun hoc s ln lp vt qu 1 con s no gi l Timeout. Timeout (ht gi) l khi nim ch mt s kin c ch i, yu cu rt nhiu ln nhng vn khng t c. Trc khi gii thch ngha ca hm mmc_tCommand, cn nhc li nh dng 1 thng ip Lnh (48 bit) cho MMC/SD card nh sau:

Hm mmc_tCommand(uint8_t Cmd, uint32_t arg): l hm gi 1 thng ip Lnh (48 bits) n MMC/SD card. Cc tham s km theo hm bao gm: Cmd l m lnh, arg tham s ca lnh (v d a ch khi d liu cn ghi/c). Dng 13 chng ta ko chn SS xung kch hot MMC/SD card nh l 1 Slave ca SPI. Tip theo gi 1 byte v ngha 0xFF n card (dng 14) bng hm SPI_tByte, ch l bt k lnh no u c start bit bng 0, do khi bt u chng ta gi byte 0xFF (c bit u bng 1) th card khng nhn ra byte nh 1 lnh v b qua byte ny. Xem li nh dng ca mt thng ip Lnh phn III chng ta thy rng 8 bit u tin trong 48 bit ca thng ip lnh bao gm Start bit + transmission bit + 6 bit m lnh. Dng 15 gi 8 bit u tin n card, SPI_tByte(Cmd | 0x40). Bn bit rng 0x40 = 01000000 (nh phn) nn Cmd | 0x40 chnh l ghp gi tr ca m lnh Cmd v u 01 (0: start bit, 1: transmission bit) to thnh byte u tin v sau gi n card. Cc dng t 16 n 19 ln lt gi 4 byte ca tham s arg (32 bit) n card. Dng 20 gi 7 bit CRC7 v stop bit. Bn thy rng chng ta gi gi tr 0x95 thay cho CRC va Stop bit, iu ny c gii thch nh sau. Tht ra, gi tr CRC7 phi c tnh ton ty thuc vo gi tr cc bit gi trc (m lnh, arg,), tuy nhin vic tnh ton ny l rt kh khn v tn nhiu thi gian. Trong khi i vi MMC/SD card ch c lnh CMD0 (reset v a card vo trng thi ngh) l cn tnh CRC7 chnh xc. Tham s ca m lnh CMD0 l 0, gi tr CRC7 cho m lnh ny c tnh sn l 74 tc 0x4A, hay 1001010 (nh phn). V vy CRC7+stop bit cho lnh CMD0 s l 10010101 (stop bit) = 0x95. Cn lu l hm mmc_tCommand dng gi bt k thng ip lnh no n card ch khng ring g lnh CMD0, nhng chng mc nh CRC7+stop bit=0x95 vn c th chp nhn c v i cc lnh khc, MMC/SD card khng yu cu tnh chnh xc CRC7. Dng SPI_tByte(0xFF) cui cng ch l dng v ngha v trc Stop bit c gi n MMC/SD card. Hm mmc_init(void): khi ng MMC/SD card. Vic khi ng card phi c tin hnh theo trnh t nh trong hnh 3.

97

Hnh 3. Trnh t khi ng MMC/SD card Trc khi khi ng card chng ta cn khi ng module SPI ca AVR nh 1 Master SPI (dng 25). Vic khi ng card c bt u bng cch to ra lin tip 80 xung (hoc hn) trn ng CLK ca SPI trong lc chn chon chip SS cn mc cao (Card cha c kch hot). Dng 26 ko chn SS ln cao v dng 27 cho SPI gi 10 byte lin tip, do s c t nht 80 xung c to ra trn CLK. Sau khi pht 80 xung trn CLK n lc kch hot card nh mt SPI Slave bng cch ko chn SS xung mc 0 nh trong dng 28. Cc dng t 29 n 34 thc hin gi m lnh CMD0 n card, trong lc gi nu c li hay timeout xy ra th hm khi ng s b dng li v gi tr li s c cha trong bin mmc_status. Cc dng t 36 n 45 thc hin gi v kim tra li i vi m lnh CMD1. Ch l cc tham s km theo 2 m lnh CMD0 v CMD1 l 0. Dng 46 gi lnh CMD16 quy nh di 1 khi d liu, tham s km theo l arg=Block_len trong Block_len l bin c nh ngha trc trong file myMMC.h, Block_len=512. Cui cng, nu qu trnh

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khi ng card xy ra thun li, gi tr 0 s c tr v.

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List 4 cha 2 hm ghi v c MMC/SD card. Hai hm ny ch cho php ghi v c1 khi d liu n thng qua 2 m lnh CMD24 v CMD17. Hm mmc_writeblock(uint32_t LBAddress, uint8_t *buff): ghi 1 khi d liu (512 bytes) vo MMC/SD card. Khi d liu cn ghi c cha trong mng buff v a ch card ni khi d liu c ghi vo chnh l tham s LBAddress. Vic ghi vo card phi c thc hin theo tun t: gi lnh write single block CMD24 (dng 6, 7) -> kim tra Response t card (dng 8 n 12) -> gi du hiu -d liu (data token, 0xFE) (dng 13)> ghi lin tip 1 khi d liu 512 bytes (dng 14) -> ghi 2 byte dummy 0xFF (dng 15, 16) -> c Response t card v so snh vi 0x05 (dng 19 n 25) -> ch cho mmc rnh (dng 27 n 33). Hm mmc_writeblock thc hin ng theo trnh t ny nn bn c c th t theo di. Ti ch gii thch mt s im quan trng v mi trong hm trn. Th nht l v du hiu d liu (data token). Bn quan st sau khi gi m lnh ghi d liu CMD24 dng 7 v ch Response t card, dng 13 chng ta khng gi ngay d liu m gi 1 byte c gi tr 0xFE ( SPI_tByte(0xFE) ). Gi tr 0xFE ny gi l data token, bo cho card rng mi th sn sng, d liu s c gi n card ngay sau y. Th hai, v cch tnh a ch LBAddress cho lnh CMD24. LBAddress l vit tt ca cm t Logical Block Address ngha l a ch logic (hay a ch danh ngha) ca khi d liu (512 bytes). Nh th khong cch gia 2 LBAddress lin tip l 512 bytes. Trong khi m lnh CMD24 yu cu tham s l a ch byte u tin ca 1 khi d liu (tnh theo a ch byte), chng ta khng th gn trc tip LBAddress cho CMD24 m phi qua 1 bc chuyn i. Hnh

Hnh 4. Quan h gia a ch khi LBAddress v a ch byte

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Trong hnh 4, gi tr bn trong cc nh l a ch tnh theo byte, gi tr bn ngoi l a ch logic ca khi d liu. Khi trn c a ch LBAddress = 0, khi di c LBAddress = 1,Gi s by gi bn mun in 512 bytes d liu vo khi di (LBAddress = 1) bng m lnh CMD24, bn khng c php gn tham s 1 cho lnh CMD24 m phi gn a ch u tin ca khi di, tc gi tr 512. T , chng ta d dng nhn thy a ch byte ca byte u tin trong khi th LBAddress l: a = 512 * LBAddress. V th trong dng 4 chng ta thc hin php gn tempA=512*LBAddress vi tempA l gi tr a ch tnh theo byte, tempA s c dng lm tham s a ch khi gi m lnh c d liu CMD24 dng 7. Hm mmc_readblock(uint32_t LBAddress, uint8_t *buff): c 1 khi d liu (512 bytes) t MMC/SD card vo mng buff. Khi d liu cn c c cha trong card ti a ch LBAddress. Ni dung hm ny cng tng t hm ghi vo card, ch khc l ti dng 45 m lnh CMD17 c s dng c d liu t card. Qu trnh c 1 khi d liu t MMC/SD card c thc hin theo trnh t sau: gi lnh read single block CMD17 (dng 44, 45) -> kim tra Response t card (dng 46 n 50) -> kim tra cho n khi no nhn c du hiu d liu (data token, 0xFE) (dng 52 n 56) -> c lin tip 1 khi d liu 512 bytes (dng 58) -> ghi 2 byte dummy 0xFF (dng 60, 61). V. S dng th vin myMMC Phn ny chng ta kho st v d minh ha cch s dng th vin myMMC lu tr v c card MMC/SD. Phn mm m phng mch in Proteus s c s dng cho mc ch minh ha v phn mm ny c th m phng i tng card mmc. Mch in m phng cho v d c trnh by trong hnh 5.

Hnh 5. M phng v d giao tip gia AVR v MMC/SD Trong mch in hnh 5 mt chip AVR Atmega32 c dng iu khin 1 card mmc, 2 Led 7 on hin th cc bc v li khi chy chng trnh (Led trn hin th cc bc, Led di hin th li ghi/c MMC/SD card). Gi tr c v t card s c xut ra uart v hin th trn Terminal. List 5 trnh by chng trnh v

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d, file myMMC_test.c

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Chng trnh v d ny c s dng cc hm xut nhp chun xut d liu t card ra uart, bn c c th tham kho thm bi Giao tip AVR vi my tnh (1) nm r hn. Ngoi ra chng trnh cng dng b nh flash (bin hocavr[] dng 32) lu tr d liu tm trc khi ghi vo card nn phn u chng trnh chng ta cn nh kem 1 headers sdtio.h v avr/prmspace.h. Cn phn lin quan n uart s khng c gii thch thm, ti ch gii thch phn ghi v c d liu t mmc card. Ti dng 31 chng ta khai bo 1 mng 512 phn t c tn l buff, mng ny s dng cha d liu trc khi ghi vo card hoc d liu c v t card. Phn chng trnh chnh c chia thnh 3 phn. Phn u bao gm cc khai bo v khi ng card nhu dng 45 gi hm khi ng mmc card mmc_init(). Trong phn th hai, 4 khi d liu ( y ti gi l sector) c ghi vo card mmc a ch t 1 n 4. V phn cui cng, ton b 4 khi d liu ny ln lt c c v xut ra uart, hin th trn Terminal. bt u 1 qu trnh ghi vo mmc ngi dng cn chun b trc d liu, cha d liu trong 1 mng. Dng 51 khai bo 1 con tr kiu char (1 byte) tr n 1 chui k t s c ghi vo sector 1 (khi d liu c a ch 1). Chui k t ny c ghi vo card bng hm mmc_writeblock(1, teststring) dng 53. Tng t, con tr teststring c gn cho 1 chui khc v ghi vo sector 2 dng 63, mmc_writeblock(2, teststring). Hm mmc_writeblock khng c kh nng truy cp trc tip d liu cha trong b nh chng trnh (flash). ghi khi d liu hocavr[] c cha trong flash trc chng ta cn c ni dung t flash ra v gn cho mng buff trc, bng hm pgm_read_byte. Cc dng t 66 n 74 thc hin iu ny. Sau khi c d liu t flash vo buff, chng ta s tin hnh ghi vo card nh dng 75. Do d liu ca bin hocavr[] kh ln, cn n 2 sector cha, cc dng t 79 den 86 tip tc ghi phn cn li ca khi hocavr[] vo sector 4. on code t dng 92 n 108 c v xut tng khi d trong card ra terminal. Ngoi hm c card mmc_readblock, cc dng code phn ny kh quen thuc, bn c hy t gii thch. Trc khi tin hnh m phng, bn hy vo th mc cha Project ca v d ny, to 1 th mc tn card, trong th mc card to 1 file trng tn mycard.mmc. M ca s Properties ca m hnh mmc card trong phn mm Proteus, ti phn Card Image File, dng nt cng c bn phi tm n file mycard.mmc to. Ni dung Card Image File by gi s l card\mycard.mmc. Tin hnh m phng, kt qu m phng hin th

Hnh 6. Kt qu ghi c d liu t mmc card.

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