JNTU Online Exam Memory Hierarchy Questions

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JNTU ONLINE EXAMINATIONS [Mid 2 - dld] 1. "Locality of Reference" is related to: [01D01] 1. Register 2. Cache 3. Primary Memory 4. Magnetic Tape 2. Expand CAM [01D02] 1. Cache Access Memory 2. Call Access Mode 3. Contents Addressable Memory 4. Cache Access Module 3. Associative Memory is like [01D03] 1. Primary Memory 2. Secondary Memory 3. Cache Memory 4. Auxiliary Memory 4. In the Memory Hierarchy, top to bottom (Registers to Tape) [01M01] 1. Capacity Decreases 2. Capacity Increases 3. Speed Increases 4. Cost per bit Increases 5. In the Memory Hierarchy, top to bottom (Registers to Tape) [01M02] 1. Cost per bit decreases 2. Cost per bit Increases 3. Speed Increases 4. Access Time Decreases 6. In the Memory Hierarchy, bottom to top (Tape to Registers) [01M03] 1. Speed Decreases 2. Access time Increases 3. Capacity Increases 4. Capacity Decreases 7. In the Memory Hierarchy, top to bottom (Registers to tape) [01M04] 1. Speed Increases 2. Speed decreases 3. Cost per bit Increases 4. Access time decreases 8. In the Memory Hierarchy, the following Memory has least capacity [01S01] 1. Register 2. Cache 3. Primary Memory 4. Magnetic Tape
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9. In the Memory Hierarchy, the following Memory has maximum Access time [01S02] 1. Register 2. Cache 3. Primary Memory 4. Magnetic Tape 10. In the Memory Hierarchy, the following Memory has least Access time [01S03] 1. Register 2. Cache 3. Primary Memory 4. Magnetic Tape 11. In the Memory Hierarchy, Speed is most for [01S04] 1. Register 2. Cache 3. Primary Memory 4. Magnetic Tape 12. In the Memory Hierarchy, Speed is least for [01S05] 1. Register 2. Cache 3. Primary Memory 4. Magnetic Tape 13. In the following which is Sequential Access [01S06] 1. Register 2. Cache 3. Primary Memory 4. Magnetic Tape 14. In the Memory Hierarchy, Cost per bit is least for [01S07] 1. Register 2. Cache 3. Primary Memory 4. Magnetic Tape 15. In the Memory Hierarchy, the Cost per bit is most for [01S08] 1. Register 2. Cache 3. Primary Memory 4. Magnetic Tape 16. 512 x 8 ROM indicates [02D01] 1. 512 data, 8 address lines 2. 512 address, 8 data lines 3. 520 address lines 4. 520 data lines 17. The Principal technology used for main Memory is based on [02M01] 1. Semi conductor 2. Conductor ICs
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3. Both Semi Conductor and Conductor ICs 18. 4. Using Insulator The Static RAM consists of [02M02] 1. Capacitors 2. Internal Flip Flops 3. Internal Caches 4. Filters The Dynamic RAM consists of [02M03] 1. Capacitors 2. Internal Flip Flops 3. Internal Caches 4. Filters Refreshing is required for [02M04] 1. All RAMs 2. Only DRAMs 3. Only SRAMs 4. Both SRAMs and DRAMs Boot Strap loader requires [02M05] 1. RAM 2. ROM 3. Any Memory 4. Only Processor The decoder used before 512 x 8 ROM consists of how many input lines? [02S01] 1. 512 2. 8 3. 9 4. 520 The Principal technology used for main Memory is based on [02S02] 1. Semi conductor 2. Conductor ICs 3. Both Semi Conductor and Conductor ICs 4. Using Insulator 24. Refreshing is required for [02S03] 1. All RAMs 2. Only DRAMs 3. Only SRAMs 4. Both SRAMs and DRAMs 25. Boot Strap loader requires [02S04] 1. RAM 2. ROM 3. Any Memory 4. Only Processor
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26. By making programs and data available at a rapid rate, it is possible to [03D01] 1. Decrease the performance 2. Increase the performance 3. Save Memory 4. Reduce cost 27. The part of the computer system that supervises the flow of information between Auxiliary Memory and Main Memory is called [03D02] 1. Processor Management System 2. Data Management System 3. Address Management System 4. Memory Management System 28. The part of the computer system that supervises the flow of information between Auxiliary Memory and Main Memory is called [03D03] 1. Processor Management System 2. Data Management System 3. Address Management System 4. Memory Management System 29. Existence of two or more programs in different parts of the Memory Hierarchy at the same time is defined as: [03M01] 1. Uni programming 2. Multi programming 3. Multi processing 4. Uni processing 30. If Cache Access time is 100ns, Memory access time is 1000ns, if the hit percentage is 100 %, what is the Average access time [03M02] 1. 100 2. 1000 3. 1100 4. 10 31. If both Cache Memory and Main Memory are updated for a write operation, the type of the Cache Memory is called [03M03] 1. Write-back 2. Write-through 3. Associative 4. TLV 32. If only Cache location is updated during a Write operation as long as there is no replacement, the type of the Cache Memory is called [03M04] 1. Write-back 2. Write-through 3. Associative 4. BLV 33. Replace the block that has been not used for the longest period of time [03M05] 1. FIFO
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2. LRU 3. MRU 4. LFU Replace the page that entered the Memory at first [03M06] 1. FIFO 2. LRU 3. MRU 4. LFU A faster and smaller Memory in between CPU and main Memory is [03S01] 1. Primary Memory 2. Secondary Memory 3. Cache Memory 4. Auxiliary Memory To compensate speed mismatch between main Memory and Processor, the Memory used is [03S02] 1. Primary Memory 2. Secondary Memory 3. Cache Memory 4. Auxiliary Memory If Hit ratio is 0.8, the miss ratio [03S03] 1. 9.2 2. 92 % 3. 0.2 4. 20 % In the following, which is not a Cache Mapping technique [03S04] 1. Associative Mapping 2. Direct Mapping 3. Test-Associative Mapping 4. Set-Associative Mapping In four-way Set-Associative mapping, the number of tags are [03S05] 1. One 2. Two 3. Four 4. Sixteen In the following, which is the fastest mapping technique [03S06] 1. Direct Mapping 2. Associative Mapping 3. Test-Associative Mapping 4. Set-Associative Mapping In Cache, the data stored is [03S07] 1. Most frequently used 2. Least frequently used 3. Never used
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4. Segment with large data The transfer of data between main Memory and Cache is [03S08] 1. WORD 2. BLOCK 3. LINE 4. CHARACTER The transfer of data between Processor and Cache is [03S09] 1. WORD 2. BLOCK 3. FRAME 4. CHARACTER "Beladys Anomaly" is for [04D01] 1. FIFO 2. LRU 3. MRU 4. Optimal replacement In "Paged Segmentation" [04D02] 1. More fragmentation 2. More Access time 3. Zero fragmentation 4. Zero Access time In Paging technique, the logical address space is [04M01] 1. Divided into equal parts 2. Divided into unequal parts 3. divided into two parts 4. Either equal or unequal parts The technique of Segmentation suffers which fragmentation [04M02] 1. Internal 2. External 3. both Internal and External 4. Neither Internal nor External "Paged Segmentation" has [04M03] 1. Internal fragmentation 2. External fragmentation 3. Zero fragmentation 4. Neither Internal nor External The time taken to access a particular track is [04S01] 1. Seek time 2. Latency time 3. Access time 4. Burst time The time taken to access a particular sector is [04S02] 1. Seek time
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2. Latency time 3. Access time 4. Burst time For a magnetic tape, the access is [04S03] 1. Random Access 2. Sequential Access 3. Both Random and Sequential 4. Rotational For a magnetic disc, the access is [04S04] 1. Random Access 2. Sequential Access 3. Both Random and Sequential 4. Rotational The technique of Paging suffers which fragmentation [04S05] 1. Internal 2. External 3. both Internal and External 4. Neither Internal nor External By using TLB in Paged segmentation [05D01] 1. Access time decreases 2. Access time increases 3. Speed decreases 4. Fragmentation decreases Contents addressable Memory (CAM) is related to [05D02] 1. Page table 2. Associative Page table 3. Inverted Page table 4. Normal Page table If there are sixteen bits in the Virtual Address format, the size of the Virtual Address is [05M01] 1. 16K 2. 16 3. 64 K 4. 16M If the size of the Page is 1K for a Virtual Address space of 16K, the size of the Frame in main Memory is [05M02] 1. 16K 2. 8K 3. 4K 4. 1 K Discs that are permanently attached to the unit assembly and cannot be removed by the occasional user are called [05S01] 1. Floppy discs
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2. Hard discs 3. External discs 4. Flash Memory A disk drive with a removable disk is called [05S02] 1. Hard disk 2. Floppy disk 3. Permanent disk 4. Cache In the following, which is not a Physical Memory [05S03] 1. Primary Memory 2. Cache Memory 3. Flash Memory 4. Virtual Memory Which Page Replacement technique is most efficient [05S04] 1. FIFO 2. LRU 3. MRU 4. LFU Page table contains [05S05] 1. Starting address of Page 2. Page no., Frame no. 3. Length of the page 4. page no., Segment no. Printing Characters in ACSII code are [06D01] 1. 128 2. 94 3. 34 4. 8 Non Printing Characters in ACSII code are [06D02] 1. 128 2. 94 3. 34 4. 8 ASCII code uses how many bits [06M01] 1. 5 2. 7 3. 8 4. 9 The Cathode Ray Tube contains an electronic gun which can be deflected [06M02] 1. Only horizontally 2. Only vertically 3. Both horizontally and vertically 4. Neither horizontally nor vertically
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67. Input/Output devices connected to the computer are also called as [06S01] 1. Modems 2. Routers 3. Peripherals 4. Processors 68. Which of the following is not a Printer? [06S02] 1. Daisy Wheel 2. Dot Matrix 3. Laser Printer 4. Scanner 69. In the following which is sequential access [06S03] 1. Magnetic Disc 2. Magnetic Tape 3. Flash Memory 4. Cache Memory 70. The command used to activate the peripheral and to inform it what to do is [07D01] 1. Control command 2. Status command 3. Data output command 4. Data input command 71. The command that causes the interface to respond by transferring data from the Bus into one of its registers is [07D02] 1. Control command 2. Status command 3. Data output command 4. Data input command 72. The command used that causes the interface to receive an item of data from the peripheral and places it in its Buffer register is [07D03] 1. Control command 2. Status command 3. Data output command 4. Data input command 73. In Asynchronous data transfer, both sender and receiver accompany a control signal that is: [07M01] 1. Strobe 2. Hand Shaking 3. Two wire control 4. single wire control 74. The circuit which provides the interface between computer and similar interactive terminal is [07M02] 1. USRP 2. UART 3. Flip Flop
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4. D-Flip Flop The command used to test various status conditions in the interface and the peripheral is [07S01] 1. Control command 2. Status command 3. Data output command 4. Data input command In the following which mapping does not distinguish Memory address and I/O address [07S02] 1. Memory mapped I/O 2. Isolated I/O 3. Independent I/O 4. Interrupt driven I/O In the following which mapping uses different address space for Memory and I/O [07S03] 1. Memory mapped I/O 2. Isolated I/O 3. Independent I/O 4. Interrupt driven I/O The rate at which Serial information is transmitted and is equivalent to the data transfer in bits per second [07S04] 1. Baud rate 2. Bit rate 3. Control rate 4. Strobe rate In Daisy chaining, the number of interrupt request lines are [08D01] 1. n 2. 2n 3. only one 4. changes In Daisy chaining, the number of interrupt acknowledge lines are [08D02] 1. n 2. 2n 3. only one 4. changes In the following, which is not priority interrupt method [08D03] 1. Polling 2. Daisy chaining 3. Parallel priority 4. Direct Memory Access In the following, which uses separate controller for data transfer [08M01] 1. Programmed I/O 2. Interrupt initiated I/O
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3. Direct Memory Access 4. Memory mapped I/O In Polling, the drawback is [08M02] 1. Cost is more 2. Complex hardware is required 3. Time consuming 4. Maintenance is more Daisy Chaining is [08M03] 1. S/w method 2. H/w method 3. Both s/w and h/w 4. Neither S/W nor H/w In the following, which is not a mode of transfer [08S01] 1. Programmed I/O 2. Interrupt initiated I/O 3. Direct Memory Access 4. Memory mapped I/O In Priority interrupt when two devices interrupt the computer at the same, the computer services the device [08S02] 1. With larger length at first 2. with shorter length at first 3. with highest priority at first 4. with lowest priority at first Polling is [08S03] 1. S/w method 2. H/w method 3. Both s/w and h/w 4. Neither S/W nor h/w In Daisy chaining, device with highest priority in [08S04] 1. First position 2. Middle position 3. Last position 4. Any position Continuously monitoring I/O devices is done in [08S05] 1. Programmed I/O 2. Interrupt initiated I/O 3. Direct Memory Access 4. Memory mapped I/O In the following, which is more time consuming [08S06] 1. Programmed I/O 2. Interrupt initiated I/O 3. Direct Memory Access 4. Memory mapped I/O
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91. A block sequence consisting of a number of Memory words is transferred continuously while a DMA controller master of Memory Bus. This is [09D01] 1. Polling 2. Daisy Chaining 3. Burst transfer 4. Cycle Stealing 92. DMA controller transfer one data word at a time and after that control of the Bus has been returned to CPU. This is [09M01] 1. Polling 2. Daisy Chaining 3. Burst transfer 4. Cycle Stealing 93. In the following, which is a method related to DMA. [09S01] 1. Polling 2. Daisy Chaining 3. Parallel Priority 4. Cycle Stealing 94. For fast transfer of information between Magnetic Disc and Memory [09S02] 1. Programmed I/O 2. Daisy Chaining 3. Polling 4. DMA 95. The DMA controller acts like [09S03] 1. Primary Memory 2. CPU 3. Cache Memory 4. Router 96. The number of basic I/O commands in IBM 370 computer IOP is [10D01] 1. 50 2. 6 3. 8 4. 40 97. The number of basic I/O commands in Intel 8089 computer IOP is [10D02] 1. 50 2. 6 3. 8 4. 40 98. The Intel 8089 I/O processor contains the IC package of [10M01] 1. 64 pins 2. 40 pins 3. 16 pins 4. 32 pins 99. A Processor with Direct Memory Access capability that communicates with I/O devices is
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[10S01] 1. Input Output Processor 2. Data communication processor 3. Data communication programmer 4. Input Output programmer A processor that communicates with remote terminals over telephone and other communication media in a serial fashion is called [10S02] 1. Input Output Processor 2. Data communication processor 3. Data communication programmer 4. Input Output programmer The I/O processor in IBM 370 computer is called [10S03] 1. Router 2. Channel 3. Device 4. Modem _ _ _ _ _ _ _ _ is a collection of processing segments through which binary information flows. [11D01] 1. vector 2. pipeline 3. array 4. instruction Let the time takes to process a sub-operation in each segment be 20ns. Assume That the pipeline has 4 segments and executes 100 tasks in sequence. What is the Speed up of pipeline system? [11D02] 1. 8000ns 2. 3060ns 3. 2060ns 4. 6000ns The _ _ _ _ _ _ _ _ _ _ architecture represents the organization of a computer Containing a single control unit, a processor unit and a memory unit. [11M01] 1. SIMD 2. MISD 3. SISD 4. MIMD Total operations performed going through all the segments in the pipeline is Called as _ _ _ _ _ _ _ _ _ [11M02] 1. function 2. process 3. sequence 4. task One type of parallel processing that does not fit Flynns classification is _ _ _ _ _ _ _ _ processing. [11M03]
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1. 100ns 2. 120ns 3. 110ns 4. 130ns 113. Each entry in the BTB consists of the address of a previously executed _ _ _ _ _ _ _ _ instruction and the _ _ _ _ _ _ _ _ instruction for that branch [12D02] 1. branch, target 2. branch, buffer 3. target, branch 4. buffer, branch
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1. array 2. vector 3. multi 4. pipeline The main purpose of parallel processing is _ _ _ _ _ _ _ _ _ _ [11S01] 1. increasing throughput 2. increasing computational speed 3. increasing data processing 4. increasing efficiency The sequence of instructions read from memory constitutes _ _ _ _ _ _ _ _ [11S02] 1. data stream 2. execution stream 3. instruction stream 4. process stream Most of the multi processors and multi computer systems can be classified in _ _ _ _ _ _ _ _ category. [11S03] 1. MISD 2. SIMD 3. SISD 4. MIMD The behavior of a pipeline can be illustrated with _ _ _ _ _ _ _ diagram [11S04] 1. frequency-time 2. timing 3. space-time 4. dataflow As the number of tasks increases, the speed up is equal to the number of _ _ _ _ _ _ In the pipeline [11S05] 1. tasks 2. segments 3. suboperations 4. instructions. and the interface registers have a Suppose the time delays of four segments are delay of tr=100ns. What is the clock cycle time? [12D01]
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114. _ _ _ _ _ _ _ _ _ conflicts arise when an instruction depends on the result of a previous instruction [12M01] 1. resource 2. branch 3. segment 4. data dependency 115. When an overflow occurs, the mantissa of the sum or difference is shifted _ _ _ _ _ _ And exponent incremented by _ _ _ _ _ _ [12M02] 1. right, one 2. left, one 3. right, two 4. left, two 116. A _ _ _ _ _ _ _ _ pipeline divides an arithmetic operation into suboperations for Execution in the pipeline segments. [12S01] 1. vector 2. arithmetic 3. instruction 4. multiple 117. _ _ _ _ _ _ _ _ _ pipeline operates on a stream of instructions by overlapping phases of instruction cycle. [12S02] 1. arithmetic 2. instruction 3. vector 4. multiple 118. The instruction fetch segment can be implemented by means of a _ _ _ _ _ _ buffer [12S03] 1. LIFO 2. FIFO 3. FILO 4. LILO 119. The instruction stream queuing mechanism provides an efficient way for reducing _ _ _ _ _ _ _ _ _ _ to memory for reading instructions [12S04] 1. access time 2. seek time 3. overlapping time 4. processing time 120. _ _ _ _ _ _ _ _ _ _ _ mode instruction does not need an effective address calculation [12S05] 1. direct 2. implied 3. register 4. immediate 121. _ _ _ _ _ _ _ _ _ is a circuit that detects instructions whose source operands are
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destinations of instructions further up in the pipeline [12S06] 1. operand forwarding 2. interlocks 3. delayed load 4. data decoder RISC machines use two separate buses with two memories, one for storing The _ _ _ _ _ _ _ _ _ _ and the other for storing the _ _ _ _ _ _ _ _ _ _ [13D01] 1. instruction, data 2. instruction, process 3. process, data 4. process, files The method used in most RISC processors is to rely on the compiler to redefine the branches so that they take effect at the proper time in the pipeline. This method is called _ _ _ _ _ _ _ _ _ _ [13D02] 1. delayed branch 2. delayed load 3. delayed store 4. delayed add The RISC consists of only _ _ _ _ _ _ _ _ length instruction format [13M01] 1. variable 2. fixed 3. small number 4. large number The data transfer instructions in RISC are limited to _ _ _ _ _ _ _ and _ _ _ _ _ _ _ _ Instructions [13M02] 1. add, sub 2. mul, div 3. load, store 4. in, out Since all operands are in registers, there is no need for _ _ _ _ _ _ _ _ of operands from memory [13S01] 1. fetch 2. decode 3. execute 4. store Advantage of RISC over CISC is that RISC can achieve pipeline segments, Requiring just _ _ _ _ _ _ _ _ _ clock cycles [13S02] 1. two 2. four 3. one 4. three The concept of delaying the use of the data loaded from memory is referred to as _ _ _ _ _ _ _ _ _ _ [13S03]
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1. delayed branch 2. delayed load 3. delayed store 4. delayed add The compiler for a processor that uses delayed branches is designed to analyze the Instructions _ _ _ _ _ _ _ _ _ _ _ the branch [13S04] 1. before 2. after 3. before & after 4. later The registers available in the RISC processor is called _ _ _ _ _ _ _ registers [13S05] 1. shift 2. cpu 3. logical 4. parallel A computer capable of vector processing eliminates the overhead associated with The time it takes to _ _ _ _ _ _ _ _ and _ _ _ _ _ _ _ _ _ _ the instructions in the program loop [14D01] 1. fetch, decode 2. fetch, execute 3. execute, decode 4. fetch, store A vector processor that uses an n-way interleaved memory can fetch _ _ _ _ _ _ _ _ _ _ _ operands from _ _ _ _ _ _ _ _ _ different modules [14D02] 1. n, n 2. n, m 3. 1, 1 4. 1, 2 Matrix _ _ _ _ _ _ _ is one of the most computational intensive operations performed In computers with vector processors [14M01] 1. addition 2. subtraction 3. transpose 4. multiplication A computer with vector instructions and pipelined floating-point arithmetic operations is referred to as _ _ _ _ _ _ _ _ computer [14M02] 1. mini 2. mainframe 3. super 4. micro A measure used to evaluate computers in their ability to performs a given number of floating-point operations per second is referred as _ _ _ _ _ _ _ _ _ _ [14M03] 1. MIPS
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2. KIPS 3. FLOPS 4. BAUDS _ _ _ _ _ _ _ _ _ _ processing deals with computations involving large matrices [14S01] 1. arithmetic 2. parallel 3. pipeline 4. vector Aerodynamics and space flight simulations uses _ _ _ _ _ _ _ _ _ _ processing [14S02] 1. vector 2. arithmetic 3. parallel 4. pipeline In _ _ _ _ _ _ _ memory, different sets of addresses are assigned to different memory modules [14S03] 1. associate 2. Random 3. interleaved 4. multiple A vector is an ordered set of _ _ _ _ _ _ _ _ _ dimensional array of data items [14S04] 1. two 2. three 3. one 4. four Instruction format for vector instruction is _ _ _ _ _ _ _ _ address instruction [14S05] 1. zero 2. one 3. two 4. three One of the following _ _ _ _ _ _ _ _ _ system is an example for array processor [15D01] 1. VAX 2. PDP-11 3. MPP 4. ILLIAC-IV Each processing element of SIMD will have _ _ _ _ _ _ _ _ _ memory [15D02] 1. global 2. shared 3. local 4. temporary An array processor consists of _ _ _ _ _ _ _ _ _ instructions and _ _ _ _ _ _ _ data organization [15M01] 1. single, multiple 2. multiple, single
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3. single, single 4. multiple, multiple The objective of the attached array processors is to provide _ _ _ _ _ _ _ _ capabilities to a conventional computer [15M02] 1. high speed 2. pipelined 3. parallel 4. vector manipulation The function of the master control unit in SIMD processor is to _ _ _ _ _ _ _ _ _ _ _ the instruction [15M03] 1. fetch 2. decode 3. execute 4. store _ _ _ _ _ _ _ _ _ _ array processor is an auxiliary processor attached to a general purpose computer [15S01] 1. attached 2. auxiliary 3. parallel 4. distributed The attached processor is a _ _ _ _ _ _ _ _ machine driven by the host computer [15S02] 1. front-end 2. back-end 3. master 4. slave Scalar and program controlled instructions directly executed with in the _ _ _ _ _ _ unit [15S03] 1. master control 2. memory 3. PE 4. local memory The system with the attached processor satisfies the needs for _ _ _ _ _ _ _ arithmetic applications [15S04] 1. complex 2. simple 3. scalar 4. vector _ _ _ _ _ _ _ _ _ _ schemes are used to control the status of each PE during the execution [15S05] 1. masking 2. blocking 3. delayed
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4. translation The inter process communication mechanism used in loosely coupled system is _ _ _ _ [16D01] 1. pipes 2. fifos 3. shared memory 4. message queues Tightly coupled systems can tolerate a _ _ _ _ _ _ _ degree of interaction between tasks [16D02] 1. no 2. higher 3. lower 4. minimal Multiprocessing can improve performance by decomposing a program into _ _ _ _ _ _ _ executable tasks [16M01] 1. serial 2. parallel 3. multiple 4. several A multiprocessor system with common shared memory is classified as _ _ _ _ _ _ _ _ _ _ [16M02] 1. shared memory 2. distributed memory 3. time shared 4. multistage _ _ _ _ _ _ _ _ technology has reduced the cost of computer components to such a low level [16M03] 1. SSI 2. MSI 3. VLSI 4. LSI A multi processor system is an interconnection of _ _ _ _ _ _ _ _ CPU's with memory and I/O [16S01] 1. one 2. two 3. three 4. two or more Multiprocessors are classified as multiple processor _ _ _ _ _ _ _ _ systems [16S02] 1. SISD 2. MIMD 3. SIMD 4. MISD _ _ _ _ _ _ _ _ _ architecture forms a computer network [16S03]
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1. multiprocessor 2. multi computer 3. single computer 4. distributed computer Each processor element in a _ _ _ _ _ _ _ _ _ system has its own private local memory [16S04] 1. tightly coupled 2. loosely coupled 3. time shared 4. multistage The inter process communication mechanism used in tightly coupled system is _ _ _ _ [16S05] 1. pipes 2. fifos 3. shared memory 4. message queues The _ _ _ _ _ _ _ _ _ _ interconnection is suitable for connecting small number of processors [17D01] 1. cross bar 2. multiport 3. multi stage 4. hypercube The basic component of a multi stage network is a 2-input 2-output interchange _ _ _ _ _ [17D02] 1. crossbar 2. connection point 3. switch 4. hub _ _ _ _ _ _ _ _ _ memory system employees separate buses between each memory module and each CPU [17M01] 1. common bus 2. multiport 3. crossbar 4. multistage switch A three cube structure consists of _ _ _ _ _ _ _ nodes [17M02] 1. 1 2. 2 3. 4 4. 8 _ _ _ _ _ _ _ _ _ consists of a number of points that are placed at intersections between processor buses and memory parts [17S01] 1. cross bar 2. multiport
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3. common bus 4. hypercube _ _ _ _ _ _ _ _ _ is to control the communication between a number of sources and destinations [17S02] 1. cross bar 2. multiport 3. commonbus 4. multistage switch The _ _ _ _ _ _ _ _ multiprocessor structure is a loosely coupled system with 2n processors [17S03] 1. crossbar 2. multi port 3. hypercube 4. multistage switch A single common bus system is restricted to transfer _ _ _ _ _ _ _ _ _ _ processor at a time [17S04] 1. one 2. two 3. many 4. IOP _ _ _ _ _ _ _ _ multiprocessor system consists of a number of processors connected through a common path to a memory unit [17S05] 1. common bus 2. multiport 3. crossbar 4. hypercube The crossbar switch consists of _ _ _ _ _ _ _ _ _ _ _ _ devices [17S06] 1. decoder 2. encoder 3. multiplexer 4. de-multiplexer The IEEE 796 standard bus as _ _ _ _ _ _ _ _ data _ _ _ _ _ _ _ address and _ _ _ _ _ _ _ _ control lines [18D01] 1. 36,24,36 2. 10,24,30 3. 16,24,26 4. 16,20,20 _ _ _ _ _ _ _ _ _ _ _ _ must then be performed to resolve the multiple contention for the shared resources [18D02] 1. arbitration 2. multiplexing 3. looping 4. controlling
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173. The processor in a shared memory multiprocessor system request access to common memory through _ _ _ _ _ _ _ _ [18M01] 1. system bus 2. internal bus 3. synchronized bus 4. asynchronus bus 174. The parallel bus arbitration technique uses _ _ _ _ _ _ _ _ priority encoders and decoders [18M02] 1. internal 2. maximum 3. external 4. low 175. The _ _ _ _ _ _ _ _ _ _ _ _ _ algorithm gives the highest priority to the requesting device that has not used the bus for the longest interval [18M03] 1. polling 2. LRU 3. FIFO 4. time slice 176. _ _ _ _ _ _ _ _ bus , each data item is transferred during a time slice known to source and destination in advance [18S01] 1. serial 2. parallel 3. synchronus 4. asynchronus 177. In serial arbitration procedure the device closest to the priority line is assigned _ _ _ _ _ _ _ priority [18S02] 1. low 2. high 3. normal 4. no 178. The _ _ _ _ _ _ _ _ algorithm allocates a fixed length time slice of bus time that is offered to each processor [18S03] 1. polling 2. LRU 3. FIFO 4. time slice 179. The _ _ _ _ _ _ _ _ _ _ scheme , request or served in the order received [18S04] 1. polling 2. LRU 3. FIFO 4. time slice 180. The _ _ _ _ _ _ _ _ _ _ sequence is normally programmable and as a result the selection priority can be altered under program control [18S05]
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1. polling 2. LRU 3. FIFO 4. time slice Out of the following which one is the hardware instruction to implement semaphore [19D01] 1. flag 2. turn 3. spin 4. test and set To protect data from being changed simultaneously by 2 or more processors is called _ _ _ _ _ _ _ _ _ _ [19M01] 1. protection 2. access matrix 3. hiding 4. mutual exclusion _ _ _ _ _ _ _ _ _ _ _ _ _ is often used to indicate whether or not a processor is executing a critical section [19M02] 1. monitor 2. spin lock 3. semaphore 4. rendezbous _ _ _ _ _ _ _ _ is the common communication mechanism used between processors [19S01] 1. FIFO 2. semaphore 3. shared memory 4. message queue _ _ _ _ _ _ _ _ _ _ multiprocessor system memory is distributed among the processors and there is no shared memory for passing information [19S02] 1. tightly coupled 2. shared memory 3. loosely coupled 4. specialized A _ _ _ _ _ _ _ _ _ _ _ is a program sequence that once begun must complete execution before another processor access the same shared resource [19S03] 1. critical section 2. entry section 3. mutual exclusion 4. exit section A scheme that allows writable data to exists in atleast one cache in a method that employees _ _ _ _ _ _ _ _ _ _ in its compiler [20D01] 1. distributed local table
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2. distributed global table 3. centralized local table 4. centralized global table A memory scheme is _ _ _ _ _ _ _ _ _ _ _ _ _ _ if the value returned on a load instruction is always the value given by the latest store instruction with the same address [20M01] 1. conflict 2. coherence 3. concurrent 4. coupling The bus controller that monitors the cache coherence problem is referred as _ _ _ _ _ _ _ [20M02] 1. snoopy cache controller 2. split cache controller 3. direct cache controller 4. side cache controller In _ _ _ _ _ _ _ _ mechanism both cache and main memory are updated with every write operation [20S01] 1. write back 2. write both 3. write through 4. write once In _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ mechanism only the cache is updated and the location is marked so that it can be copied later into main memory [20S02] 1. write back 2. write both 3. write through 4. write once

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