POLITEKNIK TUANKU SYED SIRAJUDDIN JABATAN KEJURUTERAAN ELEKTRIK

COURSE CODE : EC303 LAB : Lab Exercise

COURSE : Computer Organization DATE :

Architecture

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TITLE : COMBINATIONAL AND SEQUENCIAL LOGIC Objective : Upon completion of this experiment, students should be able to: Differentiate between combinational and sequential logic circuits. Know the characteristics of an SR bistable anda clocked SR bistable and simulate the timing diagram Know the JK and D bistable circuit and simulate the timing diagram Equipment/Software : QUARTUS II 8.1 WEB EDITION THEORY: Combinational logic circuits are circuits having inputs and outputs where the outputs states are fixed by the particular input states. For a particular input state, the outputs will always be the same logic values. Sequential logic circuits have inputs and outputs as for combinational circuits but the output states are not entirely dependent on the current input states but depend on the previous input states, i.e. there is an element of memory in the circuit that remembers previous states and this affects the output settings for a particular input state.

THE SR ( SET-RESET ) BISTABLE

The SR bistable is a circuit having two inputs labeled S and R and the two outputs labeled Q and Q. The two outputs should be of opposite logic states at any time, i.e. if one is at logic 1, the other is at logic 0. Table 1.1 is the corresponding truth table for an SR bistable with the inputs active in the high logic state.

POLITEKNIK TUANKU SYED SIRAJUDDIN JABATAN KEJURUTERAAN ELEKTRIK

INPUTS S 0 0 1 1 R 0 1 0 1

OUTPUTS Q 0 0 1 0 Q 1 1 0 0 Table 1.1

STATUS HOLD RESET SET INVALID

THE CLOCKED SR BISTABLE CIRCUIT Figure 1.1 shows the block diagram for a clocked SR bistable and waveforms for a circuit having inputs active high, the clock signal being level sensitive. With this circuit the output state does not change immediately the SR inputs are set but occurs at the receipt of an input to the clock input and this enables changes to be synchronized with changes at other gates. The circuit may operate with the clock input level sensitive or it may be edge sensitive to either a rising or falling edge.

POLITEKNIK TUANKU SYED SIRAJUDDIN JABATAN KEJURUTERAAN ELEKTRIK

Figure 1.1: SR BIstable Circuit

THE JK BISTABLE CIRCUIT The 74LS112 or 74LS76 device provided is clocked on the falling, negative going, edge of the clock pulse as indicated by the circle on the clock input connection of the diagram as shown in Figure 1.2 and active low preset and clear inputs are provided.

Figure 1.2

INPUTS J 0 0 1 1 K 0 1 0 1

OUTPUTS Q 0 0 1 0 Q 0 1 0 0 Table 1.2

OUTPUT STATE HOLD RESET SET TOGGLE

POLITEKNIK TUANKU SYED SIRAJUDDIN JABATAN KEJURUTERAAN ELEKTRIK

THE D-TYPE (DATA) BISTABLE Figure 1.3 shows the block diagram of the 0-type bistable 74LS74. This has one data input, two outputs, as for the SR bistable, a clock input and separate preset and clear input facilities to allow the output state to be preset initially in the desired state.

Figure 1.3 The preset and clear facilities are active in the low state, as indicated by the circle on their input connections and these inputs must be held at logic level 1 normally and pulled down to 0 momentarily to activate the particular facility required. With this circuit, data presented at the data input connection D is fed through to the output Q when an active clock input is received, the data can then be changed and the revised data will be fed through at the next active clock input. The 74LS74 device is edge triggered, the active clock input being rising, or positive, edge. D-type bistable can also be constructed using JK flip flop by connecting an inverter between the J and K input. If the input of D is high (logic 1), the input J is also high and input for K is low, the output will be high (SET). When the input of D is low (logic 0), the input to J is low and K is high, the output will be low (RESET). Refer to the

POLITEKNIK TUANKU SYED SIRAJUDDIN JABATAN KEJURUTERAAN ELEKTRIK

truth table in Truth table 1.3

INPUT 0 1

OUTPUT AFTER CLK 0 1 Table 1.3

PROCEDURE : Experiment 1: SR BISTABLE CIRCUIT

1. Construct the circuits as shown as Figure 1.1 and compile the circuit without

any error
2. Simulate the timing diagram and set the input sequence such as the Table 1.4.

OUTPUTS INPUTS S 0 0 1 1 0 0 1 1 R 0 1 0 1 0 1 0 1 CLK 1 1 1 1 1 1 1 1 Table 1.4 BEFORE CLOCK AFTER PULSE PULSE Q Q Q CLOCK Q

OUTPU T STATE

POLITEKNIK TUANKU SYED SIRAJUDDIN JABATAN KEJURUTERAAN ELEKTRIK

Experiment 2: JK BISTABLE CIRCUIT

1. Construct the circuits as shown as Figure 1.1 and compile the circuit without

any error
2. Simulate the timing diagram and set the input sequence such as the Table 1.4.

OUTPUTS INPUTS J 0 0 1 1 0 0 1 1 K 0 1 0 1 0 1 0 1 BEFORE PULSE QN 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 Table 1.5 Experiment 3: D TYPE BISTABLE CIRCUIT CLK AFTER PULSE QN QN+1

OUTPU CLK T STATE QN+1

1. Construct the circuit as shown at Figure 1.3. 2. Compile the circuit and simulate the timing diagram based the input from table 1.6.

POLITEKNIK TUANKU SYED SIRAJUDDIN JABATAN KEJURUTERAAN ELEKTRIK

INPUTS D 0 0 1 1 1 0 0 CLK 0 1 0 1 0 0 1

OUTPUTS Q Q

Table 1.6 Questions: