CHUYN ASIC

i tng: sinh vin nm 5, ngnh in t

ThS. NGUYN B HI Khoa in t Vin thng

Sch tham kho.............................................................................................................2 Cch thc tnh im......................................................................................................2 Dn nhp .......................................................................................................................3 CHNG 1: Gii thiu ASIC......................................................................................4
1.1
1.1.1. 1.1.2. 1.1.3. 1.1.4.

Cc loi ASIC ......................................................................................................... 5

Full-custom ASIC.............................................................................................................5 Standard-Cell-Based ASIC (CBIC) ..................................................................................6 Gate-array-based ASIC (GA) ...........................................................................................8 PLD & FPGA ...................................................................................................................8

1.1.4.1.
1.2 1.3 2.1
2.1.1. 2.1.2. 2.1.3.

PLA & PAL ...................................................................................9

Qui trnh thit k ASIC ......................................................................................... 9 Kt lun................................................................................................................. 10 CMOS transistor .................................................................................................. 12

Transistor knh dn loi p...............................................................................................15 Bo ha vn tc (velocity saturation) .............................................................................15 Mc logic........................................................................................................................15

CHNG 2: CMOS logic ..........................................................................................11

2.2 2.3 2.4

2.4.1. 2.4.2. 2.4.3.

Qui trnh ch to CMOS ..................................................................................... 16 Qui lut thit k.................................................................................................... 18 T bo logic t hp (Combinational Logic Cell) ............................................... 20
nh lut de Morgan.......................................................................................................20 Drive strength .................................................................................................................20 TG & MUX ....................................................................................................................22

2.5
2.5.1. 2.5.2. 2.5.3.

T bo logic tun t (Sequential Logic Cell) ..................................................... 23

B cht d liu latch or D-latch...................................................................................24 Flip-Flop .........................................................................................................................24 Cng o c xung clock - Clocked Inverter ...................................................................26

2.6 2.7 3.1 3.2 3.3

3.3.1. 3.3.2.

I/O cell ................................................................................................................... 26 Trnh dch cell - Cell Compiler ........................................................................... 26 M hnh tr ca transistor .................................................................................. 27 T k sinh ............................................................................................................. 27 Logical Effort........................................................................................................ 27
c tnh tr.....................................................................................................................29 Din tch logic & hiu qu logic.....................................................................................30

CHNG 3: Thit k th vin ASIC ........................................................................27

3.4

Bi tp ................................................................................................................... 31

CHNG 4: VHDL....................................................................................................33

Sch tham kho

1. 2. 3. 4. 5. 6. 7. 8. 9. Michael J.S. Smith, Application Spesific ICs, Addison Wesley, 1997 Charles H. Roth, Digital System Design using VHDL, PWS, 1998 Stephen Brown & Zvonko, Fundamentals of Digital Logic with VHDL Design, McGrawHill, 2000 Neil H.E. Weste & Kamran, Principles of CMOS VLSI Design a system prospective, Addison Wesley, 1993 David Johns & Ken Martin, Analog IC design, John Wiley & Sons, 1997 Kang & Leblebici, CMOS Digital ICs, Mc-GrawHill, 1999 Allen & Holberg, CMOS Analog Circuit Design, Oxford University Press, 2002 John P. Uyemura, Circuit Design for CMOS VLSI, Kluwer Publisher, 1992 Nguyen Quoc Tuan, Giao trinh ngon ngu VHDL de thiet ke vi mach, 2002

Cch thc tnh im

Bi tp: 20% Thi cui k (cho php dng ti liu): Thc hnh: 60% 20%

Dn nhp
Bng Karnaugh, 2-input NAND, NOR & v mch CMOS logic tng ng, k hiu. Tm quan trng ca NAND & NOR gates. Cng hn hp (compound gate), n-input gates, AND gate Bi tp 1 Tham kho file [M-chip Disk on chip, filename: NOR_vs_NAND.pdf]: So snh cng ngh NOR v NAND: kin trc ca NOR ch thch hp cho cc thit b lu tr t 1 4MB, NOR cho hiu sut c cao nhng thi gian xa v thi gian lp trnh ln, nn khng thch hp cho cc thit b lu tr yu cu dung lng v tc cao nh hin nay. NAND c c cc tnh nng va nu, dung lng t 8 512 MB cng vi gi c phi chng hn. B li, cc nh ch to phi ng u vi giao din khng chun (non-standard interface) v s qun l phc tp (complicated management) ca NAND

CHNG 1: Gii thiu ASIC

ASIC (Application Specific IC). IC and PGA package (Pin Grid Array) (hnh 1.1).
Hnh 1-1. An integrated circuit (IC). (a) A pingrid array (PGA) package. (b) The silicon die or chip is under the package lid.

Tnh ton kch c IC: theo s lng cng (logic-gate hay transistor) bn trong IC. n v tnh kch c IC l NAND hoc NOR gate. V d: 100k-gate = 100.000 twoinput NAND gates. 2-input NAND gate = 4 CMOS transistors. Tng t cho NOR gate. (xem chng dn nhp) Cc giai on pht trin ca cng ngh tch hp: SSI (thp nin 70), MSI, LSI, VLSI, ULSI. (SSI vi vi chc transistor tc c 1-10 gates, LSI c th ch to microprocessor, thut t VLSI (ph bin) = ULSI (Nht))
TTL (ECL emitter coupled logic) NMOS u thp nin 70

Thp nin 70

CMOS

Thp nin 80

Bipolar IC Tn nng lng Gi thnh cao Kch c ln MOS IC Metal gate nMOS, cha c pMOS t cc bc masking Mt cao hn (denser) Tiu tn t nng lng (consumed less power) Th trng MOS IC CMOS IC t ph: Polysilicon Gate cho php tch hp nMOS & pMOS trn cng IC Tiu tn t nng lng hn na Polysilicon cho php n gin qu trnh ch to dn n thu nh kch c IC

Bipolar & BiCMOS ICs vn c s dng trong cc ng dng in th cao (s/v CMOS) nh in t cng sut, xe hi, mch in thoi ... Feature size: c trng bi ; = smallest transistor size; VD: = 0,25m tng ng transistor nh nht c kch c 0.5 m (lin h cu to CMOS transistor v cn ngh ch to) Thng thng, xy dng h thng vi in t (microelectronic system) s dng cc thnh phn chun - standard parts hay IC chun - standard ICs. Sau s ra i ca VLSI nhng nm 80, ta c th xy dng mi th trn mt IC n cho cc ng dng chuyn dng khc nhau (customized to a particular system) custom ICs. Tt nhin l khng phi trng hp no cng thch hp. Nguyn tc l nh ngha yu cu

bi ton (xc nh design entry), sau xy dng mt s phn s dng standard IC, phn cn li s dng custom IC gi r, tng tin cy. Custom IC l hon ton khng cn thit i vi b nh chng hn. IEEE Custom IC Conference (CICC) custom IC c pht trin mnh m cho v s cc ng dng khc nhau thut ng ASIC, IEEE International ASIC Conference cho ring ASIC.
Not ASIC ASIC Lng tnh

ROM DRAM, SRAM Microprocessor TTL, TTL-equivalent IC cc mc tch hp SSI, MSI, LSI qui tc: c th tm thy trong data book

Gu chi ni c PC chip Satellite chip Modem chip Chip m nhn vic giao tip gia workstation CPU vi b nh Chip cha microprocessor cng vi thnh phn logic khc chuyn dng (Application Specific IC) sn xut rng ri (ASSPs)

Nhn dng ngi: Gng mt Cc c im vt l

Nhn dng ASIC: Cc c im vt l Gi thnh Phng php thit k ASIC cc loi ASIC

1.1

Cc loi ASIC

Nu cc khi nim Wafer, Mask layer, Interconnect. Full-custom ASICs logic cells & mask layers c thit k theo yu cu user gi thnh cao 8 tun ch to (khng k thi gian thit k) Semi-custom ASICs logic cells c thit k sn cell library mt vi hoc tt c mask layers c thit k theo yu cu user standard-cell-based ASICs gate-array-based ASICs Progammable ASICs logic cells & mask layers u c thit k sn PLDs FPGAs (what we can do in Danang!!!) 1.1.1. Full-custom ASIC c im: logic cells & mask layers c thit k theo yu cu user gi thnh cao thi gian ch to 8 tun (khng bao gm thi gian thit k)

1.1.2. Standard-Cell-Based ASIC (CBIC) Nu cc khi nim: Standard cell = logic cell = cell (AND, OR, MUX, Flip-Flop, Latch). Megacell = full-custom block = System Level Macro (SLM) = fixed block = core = Functional Standard Block (FSB). VD: SRAM, SCSI Controller, MPEG Decoder
Hnh 1-2 (CBIC) die with a single standard-cell area (a flexible block) together with 4 fixed blocks. The flexible block contains rows of standard cells. This is what you might see through a low-powered microscope looking down on the die of Hnh 1.1(b). The small squares around the edge of the die are pads that are connected to the pins of the ASIC package.

c im CBIC: mask layers c thit k theo yu cu user v vy cell & megacell c th t bt k u v trn cng 1 chip u:
Cell c thit k sn (predesigned) Cell c kim tra (pretested) Cell c c t r (precharacterized) mi cell c thit k ti u c lp gim ri ro gim gi thnh tit kim thi gian thit k

Nhc:
Thi gian thit k hay chi ph mua th vin cell Thi gian ch to cc mask layer Thi gian ch to: 8 tun (khng bao gm thi gian thit k)

Cell-based ASIC (CBIC)

Gate-based ASIC (GA)

im chung: Predesigned cells C th thay i kch c transistor trong cell Kch c transistor c nh (fixed cell) ti u ha tc v hiu sut S tha hip gia din tch (area) v hiu S tha hip gia din tch (area) v hiu sut (performance) tng th vin sut (performance) tng silicon

ASIC tin tin dng 2 n 3 lp kim loi (metal layer) hoc nhiu hn cho interconnect. Metal 1: power bus. Metal 2: input hay output cells. Xem hnh 1.3.

Hnh 1-3 layout of a standard cell, with = 0.25 microns. Standard cells are stacked like bricks in a wall; the abutment box (AB) defines the edges of the brick. The difference between the bounding box (BB) and the AB is the area of overlap between the bricks. Power supplies (VDD and GND) run horizontally inside a standard cell on a metal layer that lies above the transistor layers. Each different shaded and labeled pattern represents a different layer. This standard cell has center connectors (the three squares, labeled A1, B1, and Z) that allow the cell to connect to others. The layout was drawn using ROSE, a symbolic layout editor developed by Rockwell and Compass, and then imported into Tanner Researchs L-Edit.

Cc khi nim: Feedthrough: Spacer cell: Row-end-cell: Power-cell:

ng dn kim loi xuyn qua cell hiu chnh chiu dc cc hng cell kt ni ngun cho cc hng khc nhau dng khi cell-row qu di

Hnh 1-4 Routing the CBIC (cell-based IC) shown in hnh 1.2. The use of regularly shaped standard cells, such as the one in hnh 1.3, from a library allows ASICs like this to be designed automatically. This ASIC uses two separate layers of metal interconnect (metal1 and metal2) running at right angles to each other (like traces on a printed-circuit board). Interconnections between logic cells uses spaces (called channels) between the rows of cells. ASICs may have three (or more) layers of metal allowing the cell rows to touch with the interconnect running over the top of the cells.

Datapath: Khi nhiu tn hiu i qua mt bus d liu th cc logic cell khng cn hiu qu, khi , datapath c s dng. To ra datapath bng datapath compiler t cc nh SX. Datapath library bao gm cc datapath cell nh l: b cng - adder, b tr subtracter, b nhn - multiplier & khi logic s hc n gin simple ALU. u: kt ni cc datapath cell to nn datapath thng thng cho ra layout cht hn (tn t din tch) & hot ng nhanh hn (so vi standard-cell hay gate-array). 1.1.3. Gate-array-based ASIC (GA) SV t c sch. 1.1.4. PLD & FPGA Logic cell v mask layer c sn (khng theo yu cu user) Interconnect kh trnh Ma trn cc macrocell bao gm cc PAL + FF hoc Latch Thi gian thit k hon chnh kh nhanh (vi gi) Field-programmable: PROM, EPROM, EEPROM, UVPROM Mask-programmable: Mask- programmable ROM (Masked ROM) Field-programmable: cc kt ni dng chuyn mch lp trnh c (cu ch chng hn, CMOS transistor) & v vy chm hn cc kt ni cng nhng c u im l r khi SX vi s lng nh v thi gian lp trnh tc th. Mask-programmable: cc kt ni bn trong c thc hin bng phn cng khi SX c nhc im l lp trnh mt vi thng, song b li gi thnh gim nu SX vi s lng ln. PLD: gm khi cng AND ni vi khi cng OR. Mch logic thc hin trong PLD theo dng tng ca tch (sum-of-product). Cc loi PLD: PLD c bn: PAL (Khi AND kh trnh, khi OR c nh) PLD linh hot: PLA (Khi AND v OR u kh trnh). PLA c th l maskprogrammable hay field- programmable. C hai loi PLD trn cho php thc hin cc mch logic tc cao. Tuy nhin cu trc n gin ca n ch cho php hin thc cc mch logic nh. Cc PLD phc tp (complex PLD - CPLD) c bit n nh nhng FPGA.

V d:

Hnh 1-5 FPGA die. Cu trc FPGA c bn bao gm cc cell kh trnh bao quanh bi interconnect kh trnh. Cc loi FPGA khc nhau c s lng cell & kch c cell rt khc nhau.

1.1.4.1. PLA & PAL

Cu trc PLA: Mng logic kh trnh. Tm bng PLA hng ti thiu Cu trc PAL: Logic mng kh trnh, l tr.h ring ca PLA - mng OR c nh. Bi tp 2

1.2

Qui trnh thit k ASIC

Hnh 1-6 ASIC design flow

Better impress this flow on the memory by explaining in comparison with building construction. 1. M t bi ton: s dng ngn ng m t phn cng HDL (VHDL hay Verilog) (VHDL by Department of Defense in 1980s and standardized by IEEE in 1993 - Verilog is created by Cadence in 1989 and standardized by IEEE in 1995) 2. Tng hp logic: dng HDL v cng c tng hp logic xy dng netlist l s m t cc t bo (cell), cc khi (block) v kt ni (interconnect) gia chng 3. Phn chia h thng: chia h thng ln thnh cc phn thch hp 4. M phng tin layout: kim tra tnh ng n ca thit k (tin layout = s mch logic ch gn ng vi thc t) 5. Sp xp cc khi trn chip: sp xp cc khi ca netlist trn chip. Nn xem xt c kha cnh vt l v logic khi thit k bc ny 6. B tr cell: nh v cell bn trong khi 7. Thit k tuyn: kt ni gia cc cell v cc khi 8. Kim tra tnh hp l ca bc 7: tnh ton tr khng v dung khng lp interconnect

9. M phng hu layout: kim tra kh nng lm vic n nh ca ton b thit k trong trng hp c thm ti t lp interconnect (hu layout = s mch thc t) Cc bc thit k 1 - 5: logic. Cc bc thit k 5 9 : vt l.

1.3

Kt lun

ASIC: thay v phi xem xt nhiu kha cnh trong khi thit k ch to IC chun th cng ngh ASIC cho php ti u ha thit k theo mt mc ch c th (specific task) nn s cho hiu sut cao hn, c th l cho php lu gi lng mch logic (ch ch l mch logic) ln hn so vi cc chip chun cng kch thc. Bn cnh tnh tin cy cao th IC n l cn chim dng t khng gian hn trn bo mch in, ko theo gi thnh r hn so vi 1 h thng c cng mc ch s dng nhiu IC chun. Trnh t thit k ASIC theo cc bc : 1. Thit k logic (logic design) 2. Chn k thut thch hp thit k mch vt l (physical design) 3. Ch to chip (fabrication) bi cng ty chuyn nghip. ASIC kh trnh: CPLD hay FPGA: cha cc chuyn mch lp trnh c nhiu ln (cc chuyn mch s dng cho c cell kh trnh v interconnect kh trnh). Cc PLA thng c xem l thnh phn c bn ca FPGA. CPU Pentium 4 cha 55 triu cng ch to bng cng ngh 80-130nm. Vi cc vt liu mi, chip ngy cng c thu nh th khi lng in thot ra khi bng bn dn cng ln, do to ra sc nng ln hn v khin cc transistor d b hng (ta nh phin ta nhit cng nh th kh nng tn nhit cng thp). Theo ghi nhn ca cc nh khoa hc H Maryland (M) th silicon c hu du: l carbon nanotube. Cht ny c dn in mnh gp 70 ln silicon, ng thi cng cho cng dng in ln hn. Trong khi theo hng Toyota v Denso th cht mi l Silicon Carbua (SiC). Cui nm 2003, Intel thng bo s cho ra i chip 45 - 65nm trong thi gian ti, th vo thng 09 nm 2004, chip mi vi cng ngh 65nm (1 t transistor) ra i. Intel khng cho bit tn chnh xc loi vt liu mi.

10

CHNG 2: CMOS logic

Dn nhp: chng ta bit ti vic s dng NAND hoc NOR nh cc thnh phn c bn trong ch to IC. Vy ti sao li phi l NAND hoc NOR? Cu thnh NAND hay NOR theo cng ngh CMOS c bn tiu tn 4 transistor (2 nMOS v 2 pMOS) trong khi cc cng AND, OR cng c th ch to t 4 transistor!!! NAND gate: Z = (AB)
1 A B

AND gate: Z = AB
1 A

B
A NAND gate

AND gate

A
B

Diode v vng ngho: cc tip xc kim loi thng ni vi vng p+ v n+ (c mc kch tp cao hn so vi p v n) trnh cc diode schottky. Vng p+ c lng ln cc ion dng t do cn trong vng n+ c lng ln cc ion m t do. L trng trong p+ c khuynh hng khuch tn sang pha n trong khi electron trong n li khuch tn sang p+ (ging nh cc loi gas trn ln vo nhau). S khuch tn v vy lm gim s tp trung ca cc ion t do trong vng tip xc. Khuch tn ca electron t n s lm x/h vng in tch + bn pha n ti vng t/x, ngc li, khuch tn ca l trng t p+ s lm x/h vng in tch - bn pha p ti vng t/x. S khuch tn ca cc ion t do ny hnh thnh nn vng t/x ngho (depletion region).
SiO2 Anode Cathode in trng

p+ n p-n junction p+

n+

p+

+ + +

Bulk

Vng ngho M hnh n gin rng vng ngho ln hn cho pha kch tp thp n

Mt ct diode p-n

Hnh 2-1 Diode p-n

Diode schottky: khi c tip xc kim loi trc tip ti b mt cht bn dn kch tp nh (n, n- hay p, p-), iu ny khin cho c tnh diode c thay i so vi p-n junction diode thng thng, 1. VD nh hn bnh thng, ch 0.3-0.5V s/v 0.6-0.8V /v silicon p-n diode, l do s khc bit v tnh nng lm vic gia kim loi v n- l cao hn s/v gia kim loi v n+. 11

2. Dng trong diode schottky ch do ht dn a s to nn (electrons). Khi diode phn cc thun s khng cn s tch in ca ht dn thiu s trong vng n-, hay ni Cd = 0 (depletion cap) trong m hnh tng ng tn hiu nh. iu ny lm cho diode p ng nhanh hn, c bit l khi turn-off - v khng cn phi x in tch thiu s. GaAs c dng ch to diode schottky.
SiO2 Anode Cathode

Al

n+ Vng ngho diode schottky npBulk

Mt ct diode Schottky

Hnh 2-2 Diode Schottky

Vai tr n+ cho cc tip xc gia bn dn kch tp nh vi kim loi?

2.1

CMOS transistor
Hnh 2-3 nMOS transistor. The gate-oxide thickness, TOX , is approximately 100 angstroms (0.01u m). A typical transistor length, L=2 . bulk = substrate = well. The diodes represent pn-junctions that must be reverse-biased.

Khi khng c cc tc ng ca in th bn ngoi, min khng gian gia cc D v S khng dn in (khng c s di chuyn ca cc in tch - electron). kch dn transistor MOS loi knh n, chng ta cn a vo cc G in th VGS dng ln hn `in th ngng Vtn threshold voltage c 0.5V. in th ny lm hnh thnh 1 knh dn rt mng (50Ao , 1Ao = 1010 m ) bn di b mt cc ca G. (MOS tran to ra dng r vi micro ampe khi VGS b hn Vtn, tm thi khng xem xt ti TH ny). Transistor MOS c th dn m khng c dng chy qua. Dng ch c khi t in th VDS hp l vo 2 cc D v S. VDS l dng vi nMOS. Well (bulk , substrate or tub): kt ni vi ni c in th nh nht, k hiu GND hay VSS, nhm m bo phn cc ngc cho cc diode hnh thnh bi cc tip gip p-n ca bulk drain hay bulk source. Mi tn terminal 4 - bulk biu din chiu ca cc diode ny.

12

Dng qua transistor (A) = in tch (C) / thi gian (s)

Nu gi Q l tng in tch trong knh dn, tf l thi gian cc in t di chuyn t S sang D (ni c in th thp sang ni c in th cao), th dng IDSn c gi tr: Q (0.1) I DSn = tf Tm tf: Tht vy, theo Ohms Law: v = n E (0.2)

n di ng in t = 500-1000 cm 2V 1s 1 . E (Vm-1) trng in t gy bi VDS.

n gin, vi E ta ch xt thnh phn ngang Ex, b qua thnh phn dc Ey. E x = VDS / L tnh t D ti S. L: chiu di gate, = 2 . in t di chuyn qua on ng L vi vn tc v = n E tn khong thi gian: L L2 = (0.3) v x nVDS Tm Q: knh dn v gate to nn 2 b mt ca 1 t in m cht cch in l dioxide. Vi t tuyn tnh Q=CV. Vi TH chng ta, knh dn l b mt dn in phi tuyn tnh - in tch ch xut hin trn knh khi VGC ln hn Vtn . Vi t phi tuyn th ny, ta c: Q = C (VGC Vtn ) (0.4) WL ox = WLCox Trong C = Tox ox l hng s in mi gate-oxide. Cox l in dung n v. Ta c VGC = VGS ti S v VGC = VGS VDS . Nu gi s VGC l hm tuyn tnh theo x (0 L), th gi tr trung bnh ca in tch: 1 (0.5) Q = C (VGS Vtn ) VDS 2 biu din Q theo cc tham s transistor: 1 (0.6) Q = WLCox (VGS Vtn ) VDS 2 Cui cng ta c cng thc cho IDS: Q W 1 I DS = = nCox (VGS Vtn ) VDS VDS 2 tf L tf =
1 W ' (0.7) kn (VGS Vtn ) VDS VDS 2 L 1 = n (VGS Vtn ) VDS VDS 2 ' trong , tham s h dn (transconductance parameter) kn : =
' kn = nCox H s li: ' W n = kn L

(0.8) (0.9)

13

vi

W l h s hnh dng (shape factor). L

Vng tuyn tnh VGS > Vtn ,VDS VGS Vtn = VDS ( sat ) : linear region - triode region (0.7) biu din hot ng transistor trong vng tuyn tnh . Vng bo ha VGS > Vtn ,VDS > VGS Vtn = VDS ( sat ) : saturation region active region

khi VDS vt qu gi tr VDS ( sat ) th gi tr VGC khng cho vic duy tr knh dn,
VGC ( sat ) = VGS VDS ( sat ) VGC Vtn khiVDS VDS ( sat )

, hay ni knh dn b tht ti cc D.

Tnh xp x:

I DS sat =

W ' kn (VGS Vtn ) 2 = n (VGS Vtn ) 2 2L 2 VDS

(0.10)

Hnh v di y ch ra c tuyn IDS-VDS cho cng ngh CMOS 0.5um (gi l G5).

(a) knh dn ngn, W = 6 m & L = 0.6 m (m) knh dn di (W = 60 m, L = 6 m)

(b) c tuyn 6/0.6 dng b mt

(c) quan h I DS v V GS /v knh dn di theo lut hm m trong vng bo ha (VDS = 3 V). knh dn ngn cho kt qu tuyn tnh hn do hin tng bo ha vn tc. Thng thung, tt c transistor trong ASIC l loi knh dn ngn Hnh 2-4 c tuyn cho CMOS knh dn n cng ngh 0.5 m (G5)

V layout cng CMOS NAND2, ch ra th t thit k cc layer?

14

2.1.1. Transistor knh dn loi p C 2 cch biu din, hoc theo tr tuyt i, hoc theo du m nh sau W ' 1 I DS = k p (VGS Vtp ) VDS VDS VDS > VGS Vtp (0.11) 2 L
2 trong Vtp ,VDS ,VGS < 0 I DS =

(VGS Vtp ) 2 VDS < VGS Vtp

2.1.2. Bo ha vn tc (velocity saturation) Vi transistor knh dn ngn, gi tr thc ca IDS-sat thng gp 2 ln gi tr trong (0.10). V 3 l do: 1. Vtn const , 2. Leff < Lreal ,

3. BT v = n E khng cn ng vi in trng cao, vmax n = 105Vm 1 khi in trng vo c 106Vm 1 , tc electron bo ha vn tc (velocity saturated) Khi ny t f =
2.1.3.
Leff vmax n

1 v I DS = Wvmax nCox (VGS Vtn ) L; 2

VDS > VDSsat

(0.12)

Mc logic

interesting why 0, not GND

15

Hnh 2-5 Cc mc logic khe v yu (a) 0 khe (b) 1 yu (c) 0 yu (d) 1 khe

Ch vic v hnh, thot u ch nhn bitm cc G, cn cc D v S cha xc nh. Hnh a. logic 1 ti G, logic 0 ti S (nhn bit cc ny l S v in th thp nht), khin transistor dn dng (electron di chuyn t S ti D). Nu thot u D l logic 1 th nMOS x in tch ca t ni vo D (t hnh thnh bi cell khc). Khi t x hon ton, VGS = VGD = VDD . Transistor dn rt mnh nhng khng c dng chy qua (VDS = 0 v t f I DS ). Ng ra D lc ny chuyn sang logic 0 v y thc s l logic 0 ng ngha logic 0 khe. Gii thch tng t, hnh b cho logic 1 yu, hnh c cho logic 0 yu, hnh d cho logic 1 khe.
Kt lun: nMOS cung cp logic 0 khe, logic 1 yu. pMOS th ngc li. Ghi nh nguyn tc ny khi thit k mch.

Nu cc cell c ng dng nguyn tc trn, phn tch hot ng ca cell lm r u im m nguyn tc mang li?

2.2

Qui trnh ch to CMOS

Hnh 2-6 Ch to IC. Pht trin crystalline silicon (1); to wafer (23); oxidation - to lp silicon dioxide (oxide) trong l luyn (4); ng dng cht cn quang (5); ng dng lp photomask lm cng lp cn quang (6); wafer vi lp cn quang mm b loi b (7); khc axit lp oxide (8); cy ion (910); g b hon ton lp cn quang (11); g b lp oxide (12).

Cc bc c bn ch to IC cng ngh bn dn CMOS bao gm:

1. Silicon Wafer: Silicon c tinh ch t thch anh (nh hn 1 tp cht trn 1010 nguyn t silicon). t thi silicon tinh th n trong l nung c im nng chy 1500oC (im nng chy ca silicon ti p sut 1 atm l 1414oC). Cc cht kch tp loi p (cht nhn) hay n (cht cho) c th c thm vo pht trin loi silicon mong mun. Cng ngh CMOS di 1um hay dng silicon wafer loi p. Dng ca kim cng ct thi silicon thnh cc bnh wafer ng knh 6-12inches, dy 600um. Cc gc vc ch nh hng tinh th. 2. Ph oxide - Oxidation: tip tc vic ch to IC, thot u cho cc bnh wafer xp k nhau trong l nung ph ln b mt wafer lp silicon dioxide 16

(oxide). Oxide pht trin ln trn b mt song cng ng thi thm vo trong wafer. Thng thng, oxide thickness t 150-10000
Silicon dioxide
0.44 thickness
Silicon wafer (bulk - well)
o

Oxide thickness

Original silicon surface

Hnh 2-7 Pht trin silicon dioxide trn b mt silicon wafer

3. To lp cn quang photoresist Deposition (v hnh): to lp cn quang (c th l m hay dng - either negative or positive photoresist) trn b mt wafer. Chiu tia cc tm xuyn qua lp photomask nhm lm thay i cng lp cn. Lp cn quang c lm cng c nhim v bo v lp poly bn di trong qu trnh khc axit sau .
U V

Photoresist Oxide Well

Photoresist

Oxide

Well

4. Khc axit hoc plasma - Etching (v hnh): loi b lp cn quang v polysilicon ti nhng v tr thch hp bng axit hoc plasma.

We ll

5. Khuch tn Diffusion hoc Cy ion - Ion Implantation: nhng ion ca cht kch tp loi n hay p c gia tc vi vn tc ln vo tm silicon wafer (bulk) vi chiu su t 0.1 - 0.6um. Khuch tn hay cy ion u c cng mc ch, song cy ion c nhiu u im hn.

17

As+ Photoresist Oxide Well

6. Loi b lp cn quang.

2.3

Qui lut thit k

SV t c sch. Further in [Neil & Kamran, Principle of CMOS VLSI Design section 3.4]
Layout cho cng CMOS NAND2:
1

M3 A B

M4

Z M1 A M2 B NAND gate

VDD

p-well (1) n-well (2) p-diff (3) n-diff (3) contact (5) poly (4)

M3

p+M4 p+

metal (6) M1
n+

AB
M2
n+

VSS

Thit k layout cho clocked-inverter? V layout cho NOR2, NAND3?

18

1 M3

M4 Z

M1 A B

M2

NOR2 gate

VDD

p-well (1) n-well (2) p-diff (3)

M3

p+M4 p+

metal (6) M1
n+

A+ B
M2
n+

n-diff (3) contact (5) VSS poly (4)

B
1 M6 C

M4 A B

M5

M1 A M2

NAND3 gate B M3 C

19

p-well (1) VDD n-well (2) p-diff (3)

M4

p+M5 p+

M6

metal (6) M1
n+

ABC
M2
n+

M3

n-diff (3)

contact (5)

VSS poly (4) A B C

V layout AND3, ch gii y ?

2.4

T bo logic t hp (Combinational Logic Cell)

AOI & OAI cell cho nhng hiu qu cao trong CMOS. Di y l cc vd AOI221 & OAI321. Cc k hiu ny tuy khng chun ha nhng c s dng rng ri. Cc ch ci i din cc tng v th t ca chng - ch s ln hn 1 ch nh ng vo cho tng th nht, trong khi ch s bng 1 ch nh ng vo cho tng th 2. Cc ch s thng c vit theo th t gim dn. AOI211 biu din hm Z=(AB+C+D). OAI111 = NAND3.
Hnh 2-8 Tn cell t hp v cch nh ch s gim dn cho cc cell t hp phc tp (a) AND-OR-INVERT cell (b) OR-ANDINVERT cell.

Theo , hm logic trong (a) s l Z=(AB+CD+E). Ghi tc Z=OAI221(A,B,C,D,E). Hay, Z=AOI321(A,B,C,D,E,F) ngha rng F c ni trc tip n tng 2. Xy dng cc cell OA, AO bng cch thm cng o vo sau OAI, AOI.
2.4.1. nh lut de Morgan o hc chng dn nhp. o K hiu bubble. 2.4.2. Drive strength Drive Strength - bn iu khin: 2 transistor loi n v p trong cng o c cng tr khng. Ni cch khc chng c cng h s khuch i. Tng qut hn, 2 phn transistor nMOS va pMOS c cng tr khng. t c Drive Strength bng cch thay i h s hnh dng hoc tham s h dn

20

' Mc ch su xa ca bn iu khin: l v IDS ~ n = kn

W cho nn n / p = 1 cho L php t ti (capacitive load) np v x vi khong thi gian bng nhau, ngha l dng do INV cung cp v thu nhn l nh nhau.
Vout

n / p = 0.1

n / p = 1
n / p = 10
Vin

Bi ton trong hnh v cho KQ l 2/1 cho phn nMOS v 1/1 cho phn pMOS.

Hnh 2-9 AOI221

Gi s cc transistor c kch thc c nh v bng nhau. INV cu thnh bi 2 transistor c tham s h dn ln lt l 2kn v kp/2 (kp=4kn). Nu mun dng NOR2 to INV t c bn iu khin th cc transistor trong NOR2 phi c tham s h dn l bao nhiu? Gii thch, v hnh? Tr li:
kp

kp/2 A Z 2kn

kp A

kn

kn

21

INV vi cc gi thit cho l t c bn iu khin. bit: R t l nghch vi W W = k , trong c nh. Cho nn: L L 1 2 = R pINV = R pNOR 2 + R pNOR 2 k pNOR 2 = k pINV k pINV / 2 k p NOR 2 1 2knINV RnINV = RnNOR 2 // RnNOR 2 1 2kn NOR 2 knNOR 2 = knINV

Tnh ton con s 224 cells (for AOI family)

2.4.3. TG & MUX

Hnh 2-10 CMOS transmission gate (TG). (a) transistor knh p v n mc song song to thnh TG. (b) K hiu TG thng dng (c) hin tng chia s in tch

Biu thc TG:

Z = TG(A, S)

Ch ra u im s dng 2 transistor s/v pass transistor, v, gii thch. Nhc ca TG: hin tng chia s in tch (charge sharing) vi phn mch nh trn cho v d chng minh. VF = VSMALLCSMALL + VBIGCBIG . CBIG = 0.2pF (10 ln gi tr ti C +C
SMALL BIG

chun vi G5) CSMALL = 0.02pF. VBIG =0V, VSMALL=5V th tnh c VF = 0.45V. Cch ci tin: ng vo mnh hoc l dng buffer gia A v Z
Thit k MUX: 2 cch: 1. s dng TG 2. s dng t bo logic AOI, OAI Cch 1: Thit k MUX2:1 S)=A.S+B.S=MUX(A,B,S)

dng

TG:

TG(A,

S')

TG(B,

22

Hnh 2-11 CMOS MUX. (a) MUX2:1 dng TG khng c b m (b) K hiu MUX (c) K hiu MUX theo chun IEEE (d) K hiu MUX ph bin (theo IEEE) (e) MUX o c m ng ra (f) MUX2:1 c m vo ra.

Gii thch. Cc trng hp (e) v (f) l ci tin ca (a). Gii thch ngha G v cch thc tc ng. Nu l MUX4:1 ta c w0,1,2,3 vi s1,0.
Cch 2: Thit k MUX2:1 o dng OAI cell: ZN = A'S' + B'S= [(A'S')' (B'S)']' = [(A+S)(B+S')]' = OAI22[A,S,B,NOT(S)]
Hnh 2-12 MUX2:1 dng OAI22 cell (Sum-ofProduct circuit)

Thit k MUX2:1 s dng t bo logic AOI? Thit k MUX 4:1 dng AOI cell? Thit k MUX 4:1 dng MUX 2:1? Thit k MUX 16:1 dng MUX 4:1? Thit k tri-state buffer dng TG trnh hin tng chia s in tch?

XOR
XOR(A1,A2)=A1.A2+A1A2=MUX(A1,NOT(A1),A2) XOR(A1,A2)=NOT[MUX(NOT(A1),NOT(NOT(A1)),A2)] XOR(A1,A2)=A1.A2+A1A2=[A1.A2+A1.A2]=[(A1.A2)+(A1+A2)]=[(A1.A2)+NOR(A1,A2)] =AOI21[A1,A2,NOR(A1,A2)]

XNOR
XNOR(A1,A2)=A1.A2+A1.A2=NOT[NOT[MUX(A1,NOT(A1),A2)]]=OAI21[A1,A2,NAND(A1,A 2)]

Ch ra cc u im TG so vi pass transistor? Thit k XOR2 s dng TG sao cho tng s transistor l 8 hoc 6?

2.5

T bo logic tun t (Sequential Logic Cell)

So snh mch logic t hp (CL) v logic tun t (SL). Moore & Mealy. FSM.

23

Hai pp clocking chnh trong cng ngh VLSI: 1. Xung ng h a pha hoc n pha - multiphase or single clock 2. Thit k ng b - synchronous design Cch 2 c nhiu u im hn nh 1. Cho php thit k t ng 2. An ton 3. Cho php thc thi ASIC ging nh m phng - vendor signoff
2.5.1. B cht d liu latch or D-latch Hnh di y ch ra 1 logic cell tun t - latch hay D-Latch. Xung ng h bn trong (ni) CLKN (N for negative) & CLKP (P for positive), to t xung clock h thng CLK, bi 2 cng o (I4, I5). Hai cng o ny l bn trong latch. Tuy c th tit kim khng gian song s nguy him nu to cc tn hiu ny bn ngoi.
Hnh 2-13 CMOS latch. (a) Latch kch khi mc dng (dng TG khng c m ng ra), xung clock c m bn trong (b) Latch dn khi xung clock mc cao (c) Latch lu gi trng thi ti D khi xung clock xung mc thp.

nhn mnh s khc nhau gia latch vi FF ngi ta gi ng vo clock l tn hiu cho php (enable), nhn vo hnh (b), khi xung clock mc cao, Latch dn thng, ngha l mi thay i D dn n s thay i ng ra Q (rt khc so vi FF s xem xt sau). Cn khi clock xung mc thp, nh trong hnh (c), cng o I2 v I3 kt ni vi nhau to nn vng lu gi trng thi c ti D cho n khi c clock mc cao tr li. Vng ny thc hin cng vic lu gi chng no cn cung cp ngun, cho nn gi y l latch tnh. Logic tun t khc vi logic t hp l v c im lu tr hay nh ny (feature of storage or memory). Ng ra Q l khng m v kt ni trc tip n ng ra I2, chnh l nt lu tr. Th vin ASIC thng c thm 2 INV ng ra cho Q v QN nhm m bo cch ly cho nt lu tr. Khi ny Latch bao gm 7 INV v 2 TG bn trong (4.5 gates). Latch kch khi mc m: thm cng o cho cc xung clock bn trong hoc hon i chc nng CLKN vi CLKP.
2.5.2. Flip-Flop Dng 2 D-latch (master latch & slave latch) xy dng Flip-flop nh trong hnh. FF gm 9 inverters & 4 TGs, tc tng cng 6.5 gates. Nt lu tr S c m.

24

Tr clock-to-Q + tr inverter = tr clock-to-QN.

Hnh 2-14 CMOS flip-flop. (a) FF kch khi cnh m gm latch ch v t (b) Khi clock mc cao, latch ch dn thng (c) Khi clock mc thp, latch t chuyn ti gi tr ca latch ch. (d) Dng sng m t nh ngha setup time t SU , hold time t H , & clock to Q propagation delay t PD ca FF.

Khi clock mc cao: latch ch dn thng, nt M bin i theo ng vo D. Latch t b tch bit vi latch ch v lu tr trng thi M trc . Khi clock chuyn xung mc thp: latch t dn thng khin cho trng thi ng ra Q c cp nht theo trng thi nt M. Gi tr ca M ngay ti cnh m xung clock s c lu gi ti ng ra Q bt chp thay i ti ng vo D khi clock mc thp. Khi clock ln mc cao tr li, latch t gi li gi tr M c trn. Tin trnh c th tip tc.

Kt hp 2 latch nh trn c th ly mu ng vo D ti cnh m xung clock, tc ta c FF kch khi cnh m. R rng hnh vi FF rt khc vi latch. Hnh (d): gi cho d liu n nh (logic 1 hay 0) khong thi gian tSU trc cnh m xung clock v tH sau cnh m xung clock. im tham chiu l gia cnh m (50%VDD) trip point. D-FF trn c dng rt ph bin trong thit k ASIC. Mt s loi khc cng c dng trong ASIC cell lib l JK-FF, T-FF (toggle), & SR-FF nhm tng thch vi cc thit k TTL. i khi khi nim register ch 1 tp cc FFs hoc latch, song n cng

25

c ngha l ch 1 FF hay latch m thi. Tc gi ngm nh register c hn 1 FF hay latch. to DFF vi cc chn set, reset, ta th INV (c trong latch ch v t) bi NAND2 cell. Set tc ng mc thp: th I2 v I7. Reset tc ng mc thp: th I3 v I6. Ch th 1 INV c khng? Vi loi TTL FF c reset hoc set tri (dominant), nhng rt kh lm iu ny trong ASIC. Set i khi c gi l preset (IEEE k hiu l P). Reset i khi gi l clear (R).
2.5.3. Cng o c xung clock - Clocked Inverter Hnh v ch r thit k clocked inverter dng inverter v TG. Mi tn ch ra chiu dng in khi np (IR) v x (IF) ca t ti qua TG. D thy rng ta c th g b mi ni m khng lm thay i bn cht hot ng ca mch. K hiu trong hnh tuy thng dng song khng chun.
Hnh 2-15 Clocked inverter. (a) inverter + transmission gate (TG). (b) Dng np x t ti qua TG. Vic g b mi ni khng lm nh hng hot ng mch. (c) g b mi ni to thnh clocked inverter. (d) k hiu thng dng

Ta c th s dng clocked inverter thay th cho cp INV-TG trong latch hay FF. Latch: thay th I1 & I3 (cng vi TGs theo sau) bi clocked inverter. Trong TH ca latch hi kh nhn thy u im no vt tri, ngoi tr vic thit k layout d dng hn v c t hn 1 mi ni. FF: thay th I1, I3 & I7 (cng vi TGs theo sau) bi clocked inverters. Cn vic th I6 l khng c. Th TG sau M bi clocked inverter s lm thay i Q ng ra thnh QN. Khi ny: Tr clock-to-QN + tr inverter = tr clock-to-Q. Theo , mun tr clock-to-QN ngn th s dng clocked inverters, ngc li, cn tr clock-to-Q ngn th dng INV-TG. Thc t, ta khng dng c Q v QN cho nn vi th vin ch c Q hoc QN tit kim ti nguyn. Layout cho clocked inverter d xy dng hn INV-TG, v vy FF trong thng mi hay s dng c 2 cch thc thi.

2.6 2.7

I/O cell Trnh dch cell - Cell Compiler

(Xem sch)

(Xem sch)

26

CHNG 3: Thit k th vin ASIC

Drive strength: 1X, 2X. H s scale s. T l logic r.

3.1

M hnh tr ca transistor

Hnh 3-1 M hnh tr logic (a) CMOS INV vi ti Cout (b) falling propagation delay, t PDf (input trip point: 0.5, output trip point: 0.35 (falling) and 0.65 (rising)). M hnh cho ra t PDf R pd (C p + C out). (c) M hnh cho INV bao gm: t ng vo, C ; in tr ko ln R pu & in tr ko xung R pd); t ng ra k sinh C p

Bi ton: Vin thay i t 0 n VDD, ng ra Vout thay i t VDD n 0 (falling). Tnh thi gian truyn lan tPD vi cc trip point nh cho? Tht vy, ban u M1 tt, vin tng ko theo M1 dn trong min bo ha, sau dn trong min tuyn tnh. Ta m hnh M1 bi Rpd (ko xung), M2 bi Rpu (ko ln). Tr l do Rpd, Rpu, Cp, Cout to nn. Nu gi s Rpd = const th vout t ti gi tr 0,35VDD khi :
tPDf 0,35VDD = VDD exp R pd (Cout + C p ) 1 1 nn tPDf Chn 0,35 l v ln 0,35

R pd (Cout + C p )

3.2 3.3

T k sinh Logical Effort

(Xem sch)

Gi tq l tr do s khng l tng gy nn, ta c tq bao gm: o Tr ph thuc t k sinh bn trong o Tr ph thuc thi gian Vin t ti Vth (ngng) ca cell o Tr ph thuc slewrate ca ng vo

27

Th tPD

R (Cout + C p ) + tq

Vi C5 (Compass, 3,3V, 0,5um) (Compass Lib s dng m hnh PSPICE phc tp v chnh xc hn G5), th vi NAND2 cell 1X drive, ta c : tPD (0,07 + 1, 46Cout + 0,15)ns S hng th nht ng vi RCp, s hng th hai tc R~1,46K, s hng ba l tq. Tr cho bi ton rising cng xp x nh cho bi ton falling va t c. Nu cell c h s scale s (W ln gp s ln, L = const), th R R/s Cp sCp tq khng l tng cho nn kh tin on (ch gi s l thay i tuyn tnh) R (Cout + sC p ) + stq s V d, NAND2 cell 2X drive, s=2 th tPD (0,03 + 0,75Cout + 0,51)ns , theo , Rp v Cp l ng tin on, trong khi tq rt khc hon ton vi gi thit t ra trn. Vy, tPD cho cell c h s scale s l tPD Vit li tPD c tPD R (Cout + sC p ) + stq s dng Cin ca cell c h s scale s l Cin = sC, ta s C RC out + RC p + stq Cin

n v ha tPD bng cch chia cho = RinvCinv . Vi Rinv l in tr ko, Cinv t ng vo ca INV 1X (minimum). C RC out + RC p + stq t Cin = f + p+q d = PD =

c xem l c tnh c bn ca cng ngh CMOS.

C5, INV 1X drive tPD = (0,06 + 1,6Cout + 0,1)ns tc Rinv = R pd = R = 1,6 K C5, = RinvCinv = (1,6 K ).(0,036 pF ) 0,06ns (Cinv from data book)

d = f + p+q = effort delay + parasitic delay + nonideal delay =g*h+p+q = logical effort * electrical effort + parasitic delay + nonideal delay
Logical effort g: ch ph thuc loi cell m khng ph thuc kch c cell. RC const = v RR/s, CsC g=

Cch tm g: thay i cell sao cho c cng drive ( bn iu khin) nh INV 1X, th C g = in , vi Cin l ca cell va thay i. Cinv

28

Hnh 3-2 Logical effort (a) Cin ca INV 1X (min size) (b) thay i cell sao cho cng bn iu khin nhu INV 1X (h s logic bng 2), tnh Cin (c) tm g, g=4/3

Logical effort ph thuc h s logic r. Xem bng.

Electrical effort h: ph thuc Cout (t ti) & Cin (t ng vo) ca logic cell C h = out Cin RC p Parasitic delay p: p =

Cell

Cell effort (logic ratio = 2)

Cell effort (logic ratio = r)

Parasitic delay/

Nonideal delay/

inverter n -input NAND n -input NOR

1 (by definition) 1 (by definition) p inv (by definition) 1 q inv (by definition) 1 ( n + 2)/3 (2 n + 1)/3 ( n + r )/( r + 1) ( nr + 1)/( r + 1) n p inv n p inv n q inv n q inv

C5, pinv =1, qinv=1,7, Rinv=1,5K,Cinv=0,036pF

Table 3-1 Cell effort, parasitic delay, nonideal delay (in units of ) cho cell CMOS n tng

ngha chnh ca logical effort?

3.3.1. c tnh tr

Tnh delay cho NOR3 2X drive iu khin 4 ng ra (fanout of 4) v ti 0.3 pF (bao gm t input ca 4 cell v t interconnect). T bng trn, ta c p = 3 pinv v q = 3 qinv. Cin cho NOR3 1X l gC inv , do cho NOR3 2X cell, C in = 2 gC inv . Do vy C out g (0.3 pF) (0.3 pF)

gh = g = = . (3.27) C in 2 g C inv (2)(0.036 pF) (Nhn thy g khng nh hng n delay, ta s xem xt tip trong phn 3.3.3) Delay ca NOR logic cell tnh theo n v 0.3 10
12

(tau), l

29

d = gh + p + q = + (3)(1) + (3)(1.7) (2)(0.036 10 12 ) = 4.1666667 + 3 + 5.1 = 12.266667 . Tng ng delay tuyt i l (3.28)

t PD = 12.3 0.06 ns = 0.74 ns.

Delay cho 2X drive, NOR3 logic cell trong th vin C5 l

t PD = (0.03 + 0.72 C out + 0.60) ns . (3.29) Vi C out = 0.3 pF, t PD = 0.03 + (0.72)(0.3) + 0.60 = 0.846 ns . (3.30)
Kt lun: So vi gi tr c on ca chng ta l 0.74 ns. Sai lh y ch yu do sai lch trong c on nonideal delay. Logical effort cho ta pp kho st cc delay tng i song khng hon ton chnh xc. Song quan trng hn l logical effort cho chng ta hiu v sao logic gy ra delay. 3.3.2. Din tch logic & hiu qu logic Hnh di ch ra OAI cell n tng: c cc logical effort khc nhau ti cc input. Logical effort cho OAI221 l logical-effort vector g = (7/3, 7/3, 5/3). VD, thnh phn u tin ca vector 7/3 chnh l logical effort ca input A & B tring hnh.

Hnh 3-3 OAI221 g = (7/3, 7/3, 5/3). Logical effort cho input A v B l 7/3, logical effort cho input C v D l 7/3, cho input E l 5/3. Din tch logic l 33 logical square

Gi din tch transistor knh n 1X (min) l logical squares. Tnh din tch cc transistor trong logic cell (b qua routing area, drain area, & source area) theo logical square. Din tch logic ca OAI221 1X drive tnh nh sau: n -channel transistor sizes: 3/1 + 4 (3/1) p -channel transistor sizes: 2/1 + 4 (4/1) din tch logic tng cng = 2 + (4 4) + (5 3) = 33 logical squares AOI221 cell n tng trong hnh sau, vi g = (8/3, 8/3, 6/3). Tng t: n -channel transistor sizes: 1/1 + 4 (2/1) 30

p -channel transistor sizes: 6/1 + 4 (6/1) din tch logic tng cng = 1 + (4 2) + (5

6) = 39 logical squares

Figure 3-4 AOI221, vi logical-effort vector, g = (8/3, 8/3, 7/3). Din tch logic l 39 logical squares.

Nhn xt: OAI221 n tng vi din tch logic = 33 logical squares v logical effort (7/3, 7/3, 5/3) cho hiu qu logic cao hn AOI221 n tng vi 39 logical squares v logical effort cng ln hn (8/3, 8/3, 6/3).

3.4

Bi tp

Pull resistance. Ch ra rng vi VDS nh, n-transistor ging nh 1 in tr VGS = VDD 1 6 R= . Vi VDS = 0 trong min tuyn , tnh R cho transistor 0,6 n (VDD Vtn ) kn = 200 AV 2 tnh?
Tnh logical effort vector cho AOI221 cell vi logical ratio r thay i? (XOR cell & logical effort). Ch ra cch thc hin XOR2 s dng AOI22 & 2 INV. Da vo logical effort so snh cch xy dng ny vi trng hp s dng AOI21 & 1 NOR ? Bi 3.11 (*AOI & OAI cell efficiency) 1 th vin cell chun c cc d liu sau: AOI221: tR = 1.061.15ns; tF = 1.091.55ns; Cin = 0.210.28pF; WC = 28.8 m OAI221: tR = 0.771.05ns; tF = 0.810.96ns; Cin = 0.250.39pF; WC = 22.4 m ( WC : cell width; cell height 25.6 m.) (a) Tnh logical effort (b) Tnh din tch logic cho AOI221 v OAI221 cells. Thc thi OAI221 kiu n tng: OAI221 = OAI221(a1, a2, b1, b2, c), Thc thi AOI221 kiu a tng: AOI221 = NOT(NAND(NAND(a1, a2), AOI21(b1, b2, c))). (c) C cch thc thi no khc cho 2 cell ny khng? (d) Gii thch s thc thi

31

Bi 3.18 (Set & reset, 10 pht.) Ch ra cch thm synchronous set hoc synchronous reset vo FF trong hnh 2.18(a) s dng 2:1MUX.?

32

CHNG 4: VHDL (12 tit)

LED 7 on B m. B iu khin n giao thng. XILINX FPGA KIT.

33