a Micropower Single-Supply

Rail-to-Rail Input/Output Op Amps

OP191/OP291/OP491
FEATURES
Single-Supply Operation: 2.7 V to 12 V
Wide Input Voltage Range PIN CONFIGURATIONS
Rail-to-Rail Output Swing
Low Supply Current: 300 ␮A/Amp 8-Lead Narrow-Body SO 8-Lead Narrow-Body SO
Wide Bandwidth: 3 MHz
Slew Rate: 0.5 V/␮s 1 8 1 8
Low Offset Voltage: 700 ␮V 2 7 2 7
OP191 OP291
No Phase Reversal 3 6 3 6
4 5 4 5
APPLICATIONS
Industrial Process Control
Battery-Powered Instrumentation
Power Supply Control and Protection
Telecom
8-Lead Plastic DIP 14-Lead Plastic DIP
Remote Sensors
Low-Voltage Strain Gage Amplifiers
DAC Output Amplifier +V
OUTA 1 OP291 8 OUTA 1 14 OUTD

–INA 2 7 OUTB –INA 2 13 –IND

+INA 3 6 –INB +INA 3 12 +IND

GENERAL DESCRIPTION
The OP191, OP291, and OP491 are single, dual and quad –V 4 5 +INB +V 4 OP491 11 –V

micropower, single-supply, 3 MHz bandwidth amplifiers fea- +INB 5 10 +INC

turing rail-to-rail inputs and outputs. All are guaranteed to –INB 6 9 –INC
operate from a 3 V single supply as well as ± 5 V dual supplies. OUTB 7 8 OUTC

Fabricated on Analog Devices’ CBCMOS process, the OP191

family has a unique input stage that allows the input voltage to
safely extend 10 V beyond either supply without any phase inver-
sion or latch-up. The output voltage swings to within millivolts 14-Lead SO 14-Lead TSSOP
of the supplies and continues to sink or source current all the
way to the supplies.
1 14
OUTA 1 14 OUTD
Applications for these amplifiers include portable telecom –INA 2 13 –IND
2 13
3 12
equipment, power supply control and protection, and interface +INA 3 12 +IND 4 OP491 11
for transducers with wide output ranges. Sensors requiring a +V 4 OP491 11 –V 5 10
6 9
rail-to-rail input amplifier include Hall effect, piezo electric, and +INB 5 10 +INC
7 8
–INB 6 9 –INC
resistive transducers.
OUTB 7 8 OUTC
The ability to swing rail-to-rail at both the input and output
enables designers to build multistage filters in single-supply
systems and maintain high signal-to-noise ratios.
The OP191/OP291/OP491 are specified over the extended
industrial (–40°C to +125°C) temperature range. The OP191
single and OP291 dual amplifiers are available in 8-lead plastic
SO surface mount packages*. The OP491 quad is available in
14-lead DIPs and narrow 14-lead SO packages. Consult factory
for OP491 TSSOP availability.
*The OP291 dual is also available in 8-lead Plastic Dip.

REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com
under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2002
OP191/OP291/OP491–SPECIFICATIONS
ELECTRICAL SPECIFICATIONS (@ V = +3.0 V, V S CM = 0.1 V, VO = 1.4 V, TA = 25ⴗC unless otherwise noted.)
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage OP191G VOS 80 500 µV
–40°C ≤ TA ≤ +125°C 1 mV
OP291/OP491G VOS 80 700 µV
–40°C ≤ TA ≤ +125°C 1.25 mV
Input Bias Current IB 30 65 nA
–40°C ≤ TA ≤ +125°C 95 nA
Input Offset Current IOS 0.1 11 nA
–40°C ≤ TA ≤ +125°C 22 nA
Input Voltage Range 0 3 V
Common-Mode Rejection Ratio CMRR VCM = 0 V to 2.9 V 70 90 dB
–40°C ≤ TA ≤ +125°C 65 87 dB
Large Signal Voltage Gain AVO RL = 10 kΩ , VO = 0.3 V to 2.7 V 25 70 V/mV
–40°C ≤ TA ≤ +125°C 50 V/mV
Offset Voltage Drift ∆VOS/∆T 1.1 µV/°C
Bias Current Drift ∆IB/∆T 100 pA/°C
Offset Current Drift ∆IOS/∆T 20 pA/°C
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 100 kΩ to GND 2.95 2.99 V
–40°C to +125°C 2.90 2.98 V
RL = 2 kΩ to GND 2.8 2.9 V
–40°C to +125°C 2.70 2.8 V
Output Voltage Low VOL RL = 100 kΩ to V+ 4.5 10 mV
–40°C to +125°C 35 mV
RL = 2 kΩ to V+ 40 75 mV
–40°C to +125°C 130 mV
Short Circuit Limit ISC Sink/Source ± 8.75 ± 13.5 mA
–40°C to +125°C ± 6.0 ± 10.5 mA
Open-Loop Impedance ZOUT f = 1 MHz, AV = 1 200 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = 2.7 V to 12 V 80 110 dB
–40°C ≤ TA ≤ +125°C 75 110 dB
Supply Current/Amplifier ISY VO = 0 V 200 350 µA
–40°C ≤ TA ≤ +125°C 330 480 µA
DYNAMIC PERFORMANCE
Slew Rate +SR RL = 10 kΩ 0.4 V/µs
Slew Rate –SR RL = 10 kΩ 0.4 V/µs
Full-Power Bandwidth BWP 1% Distortion 1.2 kHz
Settling Time tS To 0.01% 22 µs
Gain Bandwidth Product GBP 3 MHz
Phase Margin θO 45 Degrees
Channel Separation CS f = 1 kHz, RL = 10 kΩ 145 dB
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 2 µV p-p
Voltage Noise Density en f = 1 kHz 35 nV/√Hz
Current Noise Density in 0.8 pA/√Hz
Specifications subject to change without notice.

–2– REV. A
 OP191/OP291/OP491
ELECTRICAL SPECIFICATIONS (@ V = +5.0 V, V S CM = 0.1 V, VO = 1.4 V, TA = 25ⴗC unless otherwise noted.)

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS
Offset Voltage OP191 VOS 80 500 µV
–40°C ≤ TA ≤ +125°C 1.0 mV
OP291/OP491 VOS 80 700 µV
–40°C ≤ TA ≤ +125°C 1.25 mV
Input Bias Current IB 30 65 nA
–40°C ≤ TA ≤ +125°C 95 nA
Input Offset Current IOS 0.1 11 nA
–40°C ≤ TA ≤ +125°C 22 nA
Input Voltage Range 0 5 V
Common-Mode Rejection Ratio CMRR VCM = 0 V to 4.9 V 70 93 dB
–40°C ≤ TA ≤ +125°C 65 90 dB
Large Signal Voltage Gain AVO RL = 10 kΩ , VO = 0.3 V to 4.7 V 25 70 V/mV
–40°C ≤ TA ≤ +125°C 50 V/mV
Offset Voltage Drift ∆VOS/∆T –40°C ≤ TA ≤ +125°C 1.1 µV/°C
Bias Current Drift ∆IB/∆T 100 pA/°C
Offset Current Drift ∆IOS/∆T 20 pA/°C
OUTPUT CHARACTERISTICS
Output Voltage High VOH RL = 100 kΩ to GND 4.95 4.99 V
–40°C to +125°C 4.90 4.98 V
RL = 2 kΩ to GND 4.8 4.85 V
–40°C to +125°C 4.65 4.75 V
Output Voltage Low VOL RL = 100 kΩ to V+ 4.5 10 mV
–40°C to +125°C 35 mV
RL = 2 kΩ to V+ 40 75 mV
–40°C to +125°C 155 mV
Short Circuit Limit ISC Sink/Source ± 8.75 ± 13.5 mA
–40°C to +125°C ± 6.0 ± 10.5 mA
Open-Loop Impedance ZOUT f = 1 MHz, AV = 1 200 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = 2.7 V to 12 V 80 110 dB
–40°C ≤ TA ≤ +125°C 75 110 dB
Supply Current/Amplifier ISY VO = 0 V 220 400 µA
–40°C ≤ TA ≤ +125°C 350 500 µA
DYNAMIC PERFORMANCE
Slew Rate +SR RL = 10 kΩ 0.4 V/µs
Slew Rate –SR RL = 10 kΩ 0.4 V/µs
Full-Power Bandwidth BWP 1% Distortion 1.2 kHz
Settling Time tS To 0.01% 22 µs
Gain Bandwidth Product GBP 3 MHz
Phase Margin θO 45 Degrees
Channel Separation CS f = 1 kHz, RL = 10 kΩ 145 dB
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 2 µV p-p
Voltage Noise Density en f = 1 kHz 35 nV/√Hz
Current Noise Density in 0.8 pA/√Hz
NOTE
+5 V specifications are guaranteed by +3 V and ± 5 V testing.
Specifications subject to change without notice.

REV. A –3–
OP191/OP291/OP491
ELECTRICAL SPECIFICATIONS (@ V = ⴞ5.0 V, –4.9 V ≤ V O CM ≤ +4.9 V, TA = 25ⴗC unless otherwise noted.)

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS
Offset Voltage OP191 VOS 80 500 µV
–40°C ≤ TA ≤ +125°C 1 mV
OP291/OP491 VOS 80 700 µV
–40°C ≤ TA ≤ +125°C 1.25 mV
Input Bias Current IB 30 65 nA
–40°C ≤ TA ≤ +125°C 95 nA
Input Offset Current IOS 0.1 11 nA
–40°C ≤ TA ≤ +125°C 22 nA
Input Voltage Range –5 +5 V
Common-Mode Rejection CMR VCM = ± 5 V 75 100 dB
–40°C ≤ TA ≤ +125°C 67 97 dB
Large Signal Voltage Gain AVO RL = 10 kΩ, VO = ± 4.7 V, 25 70
–40°C ≤ TA ≤ +125°C 50 V/mV
Offset Voltage Drift ∆VOS/∆T 1.1 µV/°C
Bias Current Drift ∆IB/∆T 100 pA/°C
Offset Current Drift ∆IOS/∆T 20 pA/°C
OUTPUT CHARACTERISTICS
Output Voltage Swing VO RL = 100 kΩ to GND ± 4.93 ± 4.99 V
–40°C to +125°C ± 4.90 ± 4.98 V
RL = 2 kΩ to GND ± 4.80 ± 4.95 V
–40°C ≤ TA ≤ +125°C ± 4.65 ± 4.75 V
Short Circuit Limit ISC Sink/Source ± 8.75 ± 16 mA
–40°C to +125°C ±6 ± 13 mA
Open-Loop Impedance ZOUT f = 1 MHz, AV = 1 200 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = ± 5 V 80 110 dB
–40°C ≤ TA ≤ +125°C 70 100 dB
Supply Current/Amplifier ISY VO = 0 V 260 420 µA
–40 ≤ TA ≤ +125°C 390 550 µA
DYNAMIC PERFORMANCE
Slew Rate ± SR RL =10 kΩ 0.5 V/µs
Full-Power Bandwidth BWP 1% Distortion 1.2 kHz
Settling Time tS To 0.01% 22 µs
Gain Bandwidth Product GBP 3 MHz
Phase Margin θO 45 Degrees
Channel Separation CS f = 1 kHz 145 dB
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 2 µV p-p
Voltage Noise Density en f = 1 kHz 35 nV/√Hz
Current Noise Density in 0.8 pA/√Hz
Specifications subject to change without notice.

5V VS = ⴞ5V
100 RL = 2k⍀
AV = +1
90
INPUT VIN = 20V p-p

OUTPUT

10
0%
5V 200␮s

Figure 1. Input and Output with Inputs Overdriven by 5 V

–4– REV. A
 OP191/OP291/OP491
ABSOLUTE MAXIMUM RATINGS 1 ORDERING GUIDE
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . GND to VS 10 V Temperature Package Package
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Model Range Description Option
Output Short-Circuit Duration to GND . . . . . . . . . . Indefinite OP191GS -40ⴗC to +125ⴗC 8-Lead SOIC SO-8
Storage Temperature Range OP291GP* -40ⴗC to +125ⴗC 8-Lead Plastic DIP N-8
P, S, RU Packages . . . . . . . . . . . . . . . . . . . –65°C to +150°C OP291GS -40ⴗC to +125ⴗC 8-Lead SOIC SO-8
Operating Temperature Range OP491GP -40ⴗC to +125ⴗC 14-Lead Plastic DIP N-14
OP191/OP291/OP491G . . . . . . . . . . . . . . . –40°C to +125°C OP491GS -40ⴗC to +125ⴗC 14-Lead SOIC SO-14
Junction Temperature Range OP491GRU -40ⴗC to +125ⴗC 14-Lead TSSOP RU-14
P, S, RU Packages . . . . . . . . . . . . . . . . . . . –65°C to +150°C
*Not for new design; obsolete April 2002.
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C

Package Type ␪JA2 ␪JC Units

8-Lead Plastic DIP (P) 103 43 °C/W
8-Lead SOIC (S) 158 43 °C/W
14-Lead Plastic DIP (P) 76 33 °C/W
14-Lead SOIC (S) 120 36 °C/W
14-Lead TSSOP (RU) 180 35 °C/W
NOTES
1
Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2
θJA is specified for the worst case conditions; i.e., θJA is specified for device in socket
for P-DIP packages; θJA is specified for device soldered in circuit board for TSSOP
and SOIC packages.

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. WARNING!
Although the OP191/OP291/OP491 feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper
ESD SENSITIVE DEVICE
ESD precautions are recommended to avoid performance degradation or loss of functionality.

REV. A –5–
OP191/OP291/OP491–Typical Performance Characteristics
180 120 0
VS = +3V VS = +3V VS = +3V
160 T = 25ⴗC
A –40ⴗC < TA < +125ⴗC –0.02 VCM = 0.1V

INPUT OFFSET VOLTAGE – mV

100
140 BASED ON BASED ON 600 OP AMPS
1200 OP AMPS
–0.04
120 80 VCM = 0V
100 –0.06

UNITS
UNITS

VCM = 3V
60
80 –0.08
60 40
–0.10
40 VCM = 2.9V
20 –0.12
20

0 0 –0.14
–0.18 –0.10 –0.02 0.06 0.14 0.22 0 1 2 3 4 5 6 7 –40 25 85 125
INPUT OFFSET VOLTAGE – mV INPUT OFFSET VOLTAGE – ␮V/ ⴗC TEMPERATURE – ⴗC

TPC 1. OP291 Input Offset Voltage TPC 2. OP291 Input Offset Volt- TPC 3. Input Offset Voltage vs.
Distribution, VS = +3 V age Drift Distribution, VS = +3 V Temperature, VS = +3 V

40 0 36
VCM = 3V
30 –0.2 30 VS = +3V
VS = +3V VCM = 0.1V 24
INPUT OFFSET CURRENT – nA
INPUT BIAS CURRENT – nA

20 –0.4

INPUT BIAS CURRENT – nA

VCM = 2.9V VCM = 2.9V 18
10
–0.6 12
0 VCM = 3V
6
VS = +3V –0.8
–10 0
VCM = 0.1V –1.0
–20 –6
VCM = 0V
–1.2 –12
–30
–18
–40 –1.4
–24
VCM = 0V –1.6
–50 –30
–60 –1.8 –36
–40 25 85 125 –40 25 85 125 0 0.30 0.60 0.90 1.2 1.5 1.8 2.1 2.4 2.7 3.0
TEMPERATURE – ⴗC TEMPERATURE – ⴗC INPUT COMMON-MODE VOLTAGE – V

TPC 4. Input Bias Current vs. TPC 5. Input Offset Current vs. Tem- TPC 6. Input Bias Current vs. Com-
Temperature, VS = +3 V perature, VS = +3 V mon-Mode Voltage, VS = +3 V

3.00 160 1200

+VO @ RL = 100k⍀ VS = +3V RL = 100k⍀,
140
TA = 25ⴗC VCM = 2.9V
1000
2.95 120
OPEN-LOOP GAIN –V/mV
OPEN-LOOP GAIN – dB
OUTPUT SWING – V

100 RL = 100k⍀,
800 VCM = 0.1V
PHASE SHIFT – ⴗC

2.90 80 0

+VO @ RL = 2k⍀ 60 45 600

2.85 40 90
400
20 135
2.80 0 180
200
VS = +3V –20 225
VS = 3V, VO = 0.3V/2.7V
2.75 –40 270 0
–40 25 85 125 100 1k 10k 100k 1M 10M –40 25 85 125
TEMPERATURE – ⴗC FREQUENCY – Hz TEMPERATURE – ⴗC

TPC 7. Output Voltage Swing vs. TPC 8. Open-Loop Gain and Phase TPC 9. Open-Loop Gain vs.
Temperature, VS = +3 V vs. Frequency, VS = +3 V Temperature, VS = +3 V

–6– REV. A
 OP191/OP291/OP491
50 160 90
40 VS = +3V CMRR VS = +3V
140
TA = 25ⴗC VS = +3V
30 89
120 TA = 25ⴗC
CLOSED-LOOP GAIN – dB

20 100
88

CMRR – dB
10

CMRR – dB
80
0 60 87
–10 40
–20 86
20
–30 0
85
–40 –20

–50 –40 84
10 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M –40 25 85 125
FREQUENCY – Hz FREQUENCY – Hz TEMPERATURE – ⴗC

TPC 10. Closed-Loop Gain vs. TPC 11. CMRR vs. Frequency, TPC 12. CMRR vs. Temperature,
Frequency, VS = +3 V VS = +3 V VS = +3 V

160 113 1.6

VS = +3V VS = +3V
140 ⴞPSRR
VS = +3V 1.4
112
120 TA = 25ⴗC ⴙSR
1.2

SLEW RATE – V/␮s

100
111
1.0
PSRR – dB

80
PSRR – dB

ⴙPSRR
60 110 0.8

40 –PSRR 0.6
109
20
0.4
0 –SR
108
0.2
–20
–40 107 0
100 1k 10k 100k 1M 10M –40 25 85 125 –40 25 85 125
FREQUENCY – Hz TEMPERATURE – ⴗC TEMPERATURE – ⴗC

TPC 13. PSRR vs. Frequency, TPC 14. PSRR vs. Temperature, TPC 15. Slew Rate vs. Tempera-
VS = +3 V VS = +3 V ture, VS = +3 V

MKR: 36.2 nV/冪Hz

0.35 2.8
VS = +3V VIN = +2.8V p-p
SUPPLY CURRENT/AMPLIFIER – mA

2.6
VS = +3V
MAXIMUM OUTPUT SWING – V

0.30 100
2.4 AV = +1 90
RL = 100k⍀
0.25 2.2

2.0
0.20
1.8

0.15 1.6 10
0%
1.4
0.10
1.2

0.05 1.0
MKR: 0 Hz BW: 2.5kHz
1000 Hz 15.0 Hz
–40 25 85 125 0.1 0.5 1.0 10 30 50 70 100 150 200 250 300
TEMPERATURE – ⴗC FREQUENCY – kHz

TPC 16. Supply Current vs. TPC 17. Maximum Output Swing vs. TPC 18. Voltage Noise Density,
Temperature, VS = +3 V, +5 V, ± 5 V Frequency, VS = +3 V VS = +3 V to ± 5 V, AVO = 1000

REV. A –7–
OP191/OP291/OP491
70 120 0.15
VS = +5V VS = +5V
VS = +5V
60 TA = 25ⴗC
100 –40°C < TA < +125ⴗC
BASED ON 600 0.10
OP AMPS BASED ON 600 OP AMPS
50
VCM = 0V
80
0.05

VOS – mV
40
UNITS

UNITS
60
30
0
40
20
VCM = +5V
–0.05
10 20

0 0 –0.1
–0.50 –0.30 –0.10 0.10 0.30 0.50 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 –40 25 85 125
INPUT OFFSET VOLTAGE – mV INPUT OFFSET VOLTAGE – ␮V/ⴗC TEMPERATURE – ⴗC

TPC 19. OP291 Input Offset Voltage TPC 20. OP291 Input Offset TPC 21. Input Offset Voltage vs.
Distribution, VS = +5 V Voltage Drift Distribution, VS = +5 V Temperature, VS = +5 V

40 1.6 36
VS = +5V +IB VS = +5V
1.4 30 VS = +5V
30
–IB
INPUT OFFSET CURRENT – nA

VCM = 5V 24

INPUT BIAS CURRENT – nA

1.2
20 18
1.0 12
10 VCM = 0V
6
IB – nA

0.8
0 0
0.6
–6
–10
0.4 –12
–20 –18
VCM = 0V 0.2
–IB –24
–30 0 VCM = 5V
+IB –30
–40 –0.2 –36
–40 25 85 125 –40 25 85 125 0 1 2 3 4 5
TEMPERATURE – ⴗC TEMPERATURE – ⴗC COMMON MODE INPUT VOLTAGE – Volts

TPC 22. Input Bias Current vs. TPC 23. Input Offset Current vs. TPC 24. Input Bias Current vs.
Temperature, VS = +5 V Temperature, VS = +5 V Common-Mode Voltage, VS = +5 V

5.00 160 140

RL = 100k⍀ VS = +5V VS = +5V
140
TA = 25ⴗC 120
4.95 120
OPEN-LOOP GAIN – V/mV

RL = 100k⍀, VCM = 5V
OPEN-LOOP GAIN – dB
OUTPUT SWING – V

100 100
4.90
80 0
PHASE SHIFT – ⴗC

80
4.85 60 45
40 90 60
RL = 2k⍀ RL = 100k⍀, VCM = 0V
4.80 20 135 40
0 RL = 2k⍀, VCM = 5V
180
4.75 20
VS = +5V –20 225
RL = 2k⍀, VCM = 0V
4.70 –40 270 0
–40 25 85 125 100 1k 10k 100k 1M 10M –40 25 85 125
TEMPERATURE – ⴗC FREQUENCY – Hz TEMPERATURE – ⴗC

TPC 25. Output Voltage Swing vs. TPC 26. Open-Loop Gain and Phase TPC 27. Open-Loop Gain vs.
Temperature, VS = +5 V vs. Frequency, VS = +5 V Temperature, VS = +5 V

–8– REV. A
 OP191/OP291/OP491
50 160 96
VS = +5V VS = +5V
40 CMRR
140 95
TA = 25ⴗC VS = +5V
30 120 TA = 25ⴗC 94
CLOSED-LOOP GAIN – dB

20 100 93

CMRR – dB
10 92

CMRR – dB
80
0 60 91
–10 40 90

–20 20 89

–30 0 88

–40 –20 87

–50 –40 86
10 100 1k 10k 100k 1M 10M 100 1k 10k 100k 1M 10M –40 25 85 125
FREQUENCY – Hz FREQUENCY – Hz TEMPERATURE – ⴗC

TPC 28. Closed-Loop Gain vs. TPC 29. CMRR vs. Frequency, TPC 30. CMRR vs. Temperature,
Frequency, VS = +5 V VS = +5 V VS = +5 V

160 0.6 0.50

VS = +5V
140 ⴞPSRR 0.45
VS = +5V
0.5
120 TA = 25ⴗC 0.40
+SR
100 0.35
0.4 –SR

SR – V/␮s
0.30
PSRR – dB

80 +SR –SR
SR – V/␮s

+PSRR
60 0.3 0.25
40 0.20
–PSRR 0.2
20 0.15

0 0.10
0.1
–20 VS = +5V 0.05
–40 0 0
100 1k 10k 100k 1M 10M –40 25 85 125 –40 25 85 125
FREQUENCY – Hz TEMPERATURE – ⴗC TEMPERATURE – ⴗC

TPC 31. PSRR vs. Frequency, TPC 32. OP291 Slew Rate vs. TPC 33. OP491 Slew Rate vs.
VS = +5 V Temperature, VS = +5 V Temperature, VS = +5 V

20 80 5.0
VS = ⴞ5V VIN = +4.8V p-p
18 +ISC, VS = ⴞ5V 70 4.5 VS = +5V
SHORT CIRCUIT CURRENT – mA

MAXIMUM OUTPUT SWING – V

4.0 AV = +1
16 60 RL = 100k⍀
–ISC, VS = ⴞ5V 3.5
4 PARTS
VOLTAGE – ␮V

14 50
3.0
+ISC, VS = +3V
12 40 2.5

10 30 2.0
–ISC, VS = +3V
10k⍀ 1.5
8 20 1k⍀
VO
A B 1.0
6 10 10k⍀
0.5
VIN = 10V p-p @ 1kHz
4 0 0
–40 25 85 125 0 500 1000 1500 2000 2500 0.1 0.5 1.0 10 30 50 70 100 150 200 250 300
TEMPERATURE – ⴗC FREQUENCY – Hz FREQUENCY – kHz

TPC 34. Short Circuit Current vs. TPC 35. Channel Separation, TPC 36. Maximum Output Swing
Temperature, VS = +3 V, +5 V, ± 5 V VS = ± 5 V vs. Frequency, VS = +5 V

REV. A –9–
OP191/OP291/OP491
10 0.15 50
VIN = +9.8V p-p VS = ⴞ5V VS = ⴞ5V
9 VS = ⴞ5V 40 +IB
MAXIMUM OUTPUT SWING – V

INPUT OFFSET VOLTAGE – mV

8 AV = +1 0.10 30 VCM = +5V
–IB
RL = 100k⍀
7 VCM = –5V 20
4 PARTS
6 0.05 10

IB – nA
5 0

4 0 –10

–20 VCM = –5V

3
VCM = +5V –IB
2 –0.05 –30
+IB
1 –40
0 –0.1 –50
0.1 0.5 1.0 10 30 50 70 100 150 200 250 300 –40 25 85 125 –40 25 85 125
FREQUENCY – kHz TEMPERATURE – ⴗC TEMPERATURE – ⴗC

TPC 37. Maximum Output Swing vs. TPC 38. Input Offset Voltage vs. TPC 39. Input Bias Current vs.
Frequency, VS = ± 5 V Temperature, VS = ± 5 V Temperature, VS = ± 5 V

1.6 36 5.00
VS = ⴞ5V RL = 100k⍀
1.4 VS = ⴞ5V 4.95

OUTPUT VOLTAGE SWING – V

INPUT OFFSET CURRENT – nA

24 4.90
INPUT BIAS CURRENT – nA

1.2
VCM = –5V 4.85
1.0 12 4.80 RL = 2k⍀
0.8 4.75 VS = ⴞ5V
0 0
0.6
–4.75
0.4 –12 –4.80

0.2 –4.85
RL = 2k⍀
–24 –4.90
0 VCM = +5V
–4.95 RL = 100k⍀
–0.2 –36 –5.00
–40 25 85 125 –5 –4 –3 –2 –1 0 1 2 3 4 5 –40 25 85 125
TEMPERATURE – ⴗC COMMON-MODE INPUT VOLTAGE – V TEMPERATURE – ⴗC

TPC 40. Input Offset Current vs. TPC 41. Input Bias Current vs. Com- TPC 42. Output Voltage Swing vs.
Temperature, VS = ± 5 V mon-Mode Voltage, VS = ± 5 V Temperature, VS = ± 5 V

70 200 50
VS = ⴞ5V VS = ⴞ5V
60 VS = ⴞ5V 180 40
TA = 25ⴗC
TA = 25ⴗC 30
50 160
CLOSED-LOOP GAIN – dB
OPEN-LOOP GAIN – V/mV
OPEN-LOOP GAIN – dB

40 0 140 RL = 100k⍀ 20

30 45 120 10

0
PHASE SHIFT – ⴗC

20 90 100
10 135 80 –10

0 180 65 –20

–10 225 40 –30

RL = 2k⍀
–20 270 25 –40

–30 0 –50
1k 10k 100k 1M 10M –40 25 85 125 10 100 1k 10k 100k 1M 10M
FREQUENCY – Hz TEMPERATURE – ⴗC FREQUENCY – Hz

TPC 43. Open-Loop Gain and Phase TPC 44. Open-Loop Gain vs. TPC 45. Closed-Loop Gain vs.
vs. Frequency, VS = ± 5 V Temperature, VS = ± 5 V Frequency, VS = ± 5 V

–10– REV. A
 OP191/OP291/OP491
160 102 160
CMRR VS = ⴞ5V
140 101 140 ⴞPSRR
VS = ⴞ5V VS = ⴞ5V
120 TA = 25ⴗC 100 120 TA = 25ⴗC
100 99 100

CMRR – dB
CMRR – dB

98 80

PSRR – dB
80
60 97 60 +PSRR
40 96 40
–PSRR
20 95 20
0 94 0
–20 93 –20
–40 92 –40
100 1k 10k 100k 1M 10M –40 25 85 125 100 1k 10k 100k 1M 10M
FREQUENCY – Hz TEMPERATURE – ⴗC FREQUENCY – Hz

TPC 46. CMRR vs. Frequency, TPC 47. CMRR vs. Temperature, TPC 48. PSRR vs. Frequency,
VS = ± 5 V VS = ± 5 V VS = ± 5 V

115 0.7 1k
VS = ⴞ5V VS = ⴞ5V 900 VS = +3V
OP491 0.6 TA = 25ⴗC
110 800
+SR
OP291 0.5 700
600
PSRR – dB

105 –SR

ZOUT – ⍀
SR – V/␮s

0.4
500

100 0.3 400

300
0.2
95 200 AVCL = 100
0.1
100 AVCL = 10
AVCL = +1
90 0 0
–40 25 85 125 –40 25 85 125 100 1k 10k 100k 1M 10M
TEMPERATURE – ⴗC TEMPERATURE – ⴗC FREQUENCY – Hz

TPC 49. OP291/OP491 PSRR vs. TPC 50. Slew Rate vs. Temperature, TPC 51. Output Impedance vs.
Temperature, VS = ± 5 V VS = ± 5 V Frequency

1.00V 2.00V
100 100

90 90

INPUT
INPUT

VS = +3V VS = ⴞ5V
OUTPUT RL = 200k⍀ RL = 200k⍀
10 10
AV = +1V/V
0% OUTPUT 0%
500mV 2.00␮s 100mV 1.00V 2.00␮s 100mV

TPC 52. Large Signal Transient TPC 53. Large Signal Transient
Response, VS = +3 V Response, VS = ± 5 V

REV. A –11–
OP191/OP291/OP491
FUNCTIONAL DESCRIPTION
The OP191/OP291/OP491 are single-supply, micropower
amplifiers featuring rail-to-rail inputs and outputs. In order to
achieve wide input and output ranges, these amplifiers employ
unique input and output stages. As the simplified schematic
shows (Figure 2), the input stage is actually comprised of two
differential pairs, a PNP pair and an NPN pair. These two stages
do not actually work in parallel. Instead, only one or the other
stage is on for any given input signal level. The PNP stage (tran-
sistors Q1 and Q2) is required to ensure that the amplifier remains
in the linear region when the input voltage approaches and
reaches the negative rail. On the other hand, the NPN stage
(transistors Q5 and Q6) is needed for input voltages up to and
including the positive rail.
For the majority of the input common-mode range, the PNP
stage is active, as is evidenced by examining the graph of Input
Bias Current vs. Common-Mode Voltage. Notice that the bias
current switches direction at approximately 1.2 V to 1.3 V below
the positive rail. At voltages below this, the bias current flows
out of the OP291, indicating a PNP input stage. Above this
voltage, however, the bias current enters the device, revealing the
NPN stage. The actual mechanism within the amplifier for
switching between the input stages is comprised of the transistors
Q3, Q4, and Q7. As the input common-mode voltage increases,
the emitters of Q1 and Q2 follow that voltage plus a diode drop.
Eventually the emitters of Q1 and Q2 are high enough to turn
Q3 on. This diverts the 8 µA of tail current away from the PNP
input stage, turning it off. Instead, the current is mirrored through
Q4 and Q7 to activate the NPN input stage.
Notice that the input stage includes 5 kΩ series resistors and
differential diodes, a common practice in bipolar amplifiers to
protect the input transistors from large differential voltages.
These diodes will turn on whenever the differential voltage
8␮A
–IN
5k⍀
Q3
5k⍀
+IN Q1 Q2 Q5 Q6
Q8 Q10 Q12
Q9 Q11 Q13
Q4 Q7
Figure 2. Simplified Schematic
–12–
exceeds approximately 0.6 V. In this condition, current will flow
between the input pins, limited only by the two 5 kΩ resistors.
Being aware of this characteristic is important in circuits where
the amplifier may be operated open-loop, such as a comparator.
Evaluate each circuit carefully to make sure that the increase in
current does not affect the performance.
The output stage of the OP191 family uses a PNP and an NPN
transistor as do most output stages; however, the output tran-
sistors, Q32 and Q33, are actually connected with their collec-
tors to the output pin to achieve the rail-to-rail output swing. As
the output voltage approaches either the positive or negative
rail, these transistors begin to saturate. Thus, the final limit on
output voltage is the saturation voltage of these transistors,
which is about 50 mV. The output stage does have inherent gain
arising from the collectors and any external load impedance.
Because of this, the open-loop gain of the amplifier is dependent
on the load resistance.
Input Overvoltage Protection
As with any semiconductor device, whenever the condition
exists for the input to exceed either supply voltage, attention
needs to be paid to the input overvoltage characteristic. When
an overvoltage occurs, the amplifier could be damaged depend-
ing on the voltage level and the magnitude of the fault current.
Figure 3 shows the characteristic for the OP191 family. This
graph was generated with the power supplies at ground and a
curve tracer connected to the input. As can be seen, when the
input voltage exceeds either supply by more than 0.6 V, internal
pn-junctions energize, allowing current to flow from the input to
the supplies. As described above, the OP291/OP491 does have
5 kΩ resistors in series with each input, which helps limit the
current. Calculating the slope of the current versus voltage in
the graph confirms the 5 kΩ resistor.
Q22 Q26
Q32
Q23 Q27
Q20
Q30
Q16
Q17 10pF
Q14
Q21 VOUT
Q31
Q15
Q24 Q28
Q18 Q19 Q25 Q29 Q33
REV. A

IIN
2mA
1mA
–10V –5V 5V 10V
VIN
–1mA
–2mA
Figure 3. Input Overvoltage Characteristics
This input current is not inherently damaging to the device as
long as it is limited to 5 mA or less. In the case shown, for an
input of 10 V over the supply, the current is limited to 1.8 mA.
If the voltage is large enough to cause more than 5 mA of current
to flow, then an external series resistor should be added. The size
of this resistor is calculated by dividing the maximum overvoltage
by 5mA and subtracting the internal 5 kΩ resister. For example,
if the input voltage could reach 100 V, the external resistor
should be (100 V/5 mA) –5 k = 15 kΩ. This resistance should
be placed in series with either or both inputs if they are subjected
to the overvoltages. For more information on general overvoltage
characteristics of amplifiers refer to the 1993 System Applications
Guide, available from the Analog Devices Literature Center.
OP191/OP291/OP491
ground and the cathode to the inputs, prevent input signal excur-
sions from exceeding the device’s negative supply (i.e., GND),
preventing a condition which could cause the output voltage to
change phase. JFET-input amplifiers may also exhibit phase
reversal, and, if so, a series input resistor is usually required to
prevent it.
The OP191 family is free from reasonable input voltage range
restrictions due to its novel input structure. In fact, the input
signal can exceed the supply voltage by a significant amount
without causing damage to the device. As illustrated in Figure 4,
the OP191 family can safely handle a 20 V p-p input signal on
± 5 V supplies without exhibiting any sign of output voltage
phase reversal or other anomalous behavior. Thus no external
clamping diodes are required.
Overdrive Recovery
The overdrive recovery time of an operational amplifier is the
time required for the output voltage to recover to its linear region
from a saturated condition. This recovery time is important in
applications where the amplifier must recover quickly after a
large transient event, such as a comparator. The circuit shown
in Figure 5 was used to evaluate the OP191 family’s overload
recovery time. The OP191 family takes approximately 8 µs to
recover from positive saturation and approximately 6.5 µs to
recover from negative saturation.
R1
9k⍀
3
VIN
1/2 VOUT
OP291 1
10V STEP
R2 2 R3
10k⍀ 10k⍀

Output Voltage Phase Reversal VS = ⴞ5V

Some operational amplifiers designed for single-supply opera-
tion exhibit an output voltage phase reversal when their inputs Figure 5. Overdrive Recovery Time Test Circuit
are driven beyond their useful common-mode range. Typically
for single-supply bipolar op amps, the negative supply deter-
mines the lower limit of their common-mode range. With these
devices, external clamping diodes, with the anode connected to

5␮s 5␮s
+5V 100 100
90 90

VIN 8
VIN – 2.5V/DIV

VOUT – 2V/DIV

3
20V p-p
1/2 1 VOUT
OP291
2
4
10 10
0% 0%
–5V

20mV 20mV

TIME – 200␮s/DIV TIME – 200␮s/DIV

Figure 4. Output Voltage Phase Reversal Behavior

REV. A –13–
OP191/OP291/OP491
APPLICATIONS Single-Supply RTD Amplifier
Single +3 V Supply, Instrumentation Amplifier The circuit in Figure 7 uses three op amps of the OP491 to
The OP291’s low supply current and low voltage operation make develop a bridge configuration for an RTD amplifier that oper-
it ideal for battery-powered applications such as the instrumen- ates from a single +5 V supply. The circuit takes advantage of
tation amplifier shown in Figure 6. The circuit utilizes the classic the OP491’s wide output swing range to generate a high bridge
two op amp instrumentation amplifier topology, with four resistors excitation voltage of 3.9 V. In fact, because of the rail-to-rail
to set the gain. The equation is simply that of a noninverting output swing, this circuit will work with supplies as low as 4.0 V.
amplifier as shown in the figure. The two resistors labeled R1 Amplifier A1 servos the bridge to create a constant excitation
should be closely matched to each other as well as both resistors current in conjunction with the AD589, a 1.235 V precision
labeled R2 to ensure good common-mode rejection performance. reference. The op amp maintains the reference voltage across
Resistor networks ensure the closest matching as well as matched the parallel combination of the 6.19 kΩ and 2.55 MΩ resistor,
drifts for good temperature stability. Capacitor C1 is included which generates a 200 µA current source. This current splits
to limit the bandwidth and, therefore, the noise in sensitive evenly and flows through both halves of the bridge. Thus, 100 µA
applications. The value of this capacitor should be adjusted flows through the RTD to generate an output voltage based on
depending on the desired closed-loop bandwidth of the instru- its resistance. A 3-wire RTD is used to balance the line resis-
mentation amplifier. The RC combination creates a pole at a tance in both 100 Ω legs of the bridge to improve accuracy.
frequency equal to 1/(2 π × R1C1). If AC-CMRR is critical,
than a matched capacitor to C1 should be included across the
second resistor labeled R1. 200⍀
GAIN = 274
10-TURNS +5V
+3V 26.7k⍀ 26.7k⍀
A3
1/4 VOUT
5 8 100⍀ A2 OP491
1/2 RTD
VIN 7 VOUT 1/4
OP291 2.55M⍀ 100⍀ OP491
6 4
3
1/2 365⍀ 365⍀ 100k⍀
OP291 1 6.19k⍀ A1
2
1/4 100k⍀
R1 R2 R2 R1
OP491
0.01pF
C1 ALL RESISTORS 1% OR BETTER
R1 AD589
VOUT = (1 + ––– ) VIN 37.4k⍀
R2 100pF

+5V
Figure 6. Single +3 V Supply Instrumentation Amplifier
Figure 7. Single-Supply RTD Amplifier
Because the OP291 accepts rail-to-rail inputs, the input common-
mode range includes both ground and the positive supply of 3 Amplifiers A2 and A3 are configured in the two op amp IA
V. Furthermore, the rail-to-rail output range ensures the widest discussed above. Their resistors are chosen to produce a gain of
signal range possible and maximizes the dynamic range of the 274, such that each 1°C increase in temperature results in a
system. Also, with its low supply current of 300 µA/device, this 10 mV change in the output voltage, for ease of measurement.
circuit consumes a quiescent current of only 600 µA, yet still A 0.01 µF capacitor is included in parallel with the 100 kΩ
exhibits a gain bandwidth of 3 MHz. resistor on amplifier A3 to filter out any unwanted noise from
this high gain circuit. This particular RC combination creates a
A question may arise about other instrumentation amplifier
pole at 1.6 kHz.
topologies for single-supply applications. For example, a variation
on this topology adds a fifth resistor between the two inverting
inputs of the op amps for gain setting. While that topology works
well in dual-supply applications, it is inherently not appropriate
for single-supply circuits. The same could be said for the tradi-
tional three op amp instrumentation amplifier. In both cases, the
circuits simply will not work in single-supply situations unless a
false ground between the supplies is created.

–14– REV. A
 OP191/OP291/OP491
A +2.5 V Reference from a +3 V Supply The OP291 serves two functions. First, it is required to buffer
In many single-supply applications, the need for a 2.5 V reference the high output impedance of the DAC’s VREF pin, which is on
often arises. Many commercially available monolithic 2.5 V the order of 10 kΩ. The op amp provides a low impedance output
references require at least a minimum operating supply voltage to drive any following circuitry. Secondly, the op amp amplifies
of 4 V. The problem is exacerbated when the minimum operating the output signal to provide a rail-to-rail output swing. In this
system supply voltage is +3 V. The circuit illustrated in Figure 8 particular case, the gain is set to 4.1 to generate a 5.0 V output
is an example of a +2.5 V that operates from a single +3 V supply. when the DAC is at full scale. If other output voltage ranges are
The circuit takes advantage of the OP291’s rail-to-rail input and needed, such as 0 to 4.095, the gain can easily be adjusted by
output voltage ranges to amplify an AD589’s 1.235 V output to altering the value of the resistors.
+2.5 V. The OP291’s low TCVOS of 1 µV/°C helps maintain an A High-Side Current Monitor
output voltage temperature coefficient of less than 200 ppm/°C. In the design of power supply control circuits, a great deal of
The circuit’s overall temperature coefficient is dominated by R2 design effort is focused on ensuring a pass transistor’s long-term
and R3’s temperature coefficient. Lower tempco resistors are reliability over a wide range of load current conditions. As a
recommended. The entire circuit draws less than 420 µA from a result, monitoring and limiting device power dissipation is of prime
+3 V supply at 25°C. importance in these designs. The circuit illustrated in Figure 10
+3V
is an example of a +5 V, single-supply high-side current monitor
R1
that can be incorporated into the design of a voltage regulator
+3V
17.4k⍀ with fold-back current limiting or a high current power supply
3 8 with crowbar protection. This design uses an OP291’s rail-to-rail
AD589
1/2 1 +2.5VREF input voltage range to sense the voltage drop across a 0.1 Ω
OP291
2 4 current shunt. A p-channel MOSFET used as the feedback
RESISTORS = 1%, 100ppm/ⴗC element in the circuit converts the op amp’s differential input
POTENTIOMETER = 10 TURN, 100ppm/ⴗC
voltage into a current. This current is then applied to R2 to
R3 R2 R1 generate a voltage that is a linear representation of the load
100k⍀ 100k⍀ 5k⍀
current. The transfer equation for the current monitor is given by:
Figure 8. A +2.5 V Reference that Operates on a Single R 
+3 V Supply Monitor Output = R2 ×  SENSE  × I L
 R1 
+5 V Only, 12-Bit DAC Swings Rail-to-Rail
For the element values shown, the Monitor Output’s transfer
The OP191 family is ideal for use with a CMOS DAC to generate
characteristic is 2.5 V/A.
a digitally controlled voltage with a wide output range. Figure 9
shows the DAC8043 used in conjunction with the AD589 to RSENSE IL
generate a voltage output from 0 V to 1.23 V. The DAC is actu- 0.1⍀
+5V +5V
ally operated in “voltage switching” mode where the reference is +5V
connected to the current output, IOUT, and the output voltage is R1
100⍀ 3 8
taken from the VREF pin. This topology is inherently noninverting 1/2 1
as opposed to the classic current output mode, which is inverting OP291
2 4
and, therefore, unsuitable for single supply.
S
G
M1
+5V 3N163
MONITOR D
OUTPUT
8 R2
R1 2
VDD RFB 2.49k⍀
17.8k⍀
3 1
1.23V IOUT DAC8043 VREF
+5V
GND CLK SR1 LD Figure 10. A High-Side Load Current Monitor
AD589 4 7 6 5 3 8
1/2 D
1 VOUT = –––– (5V)
DIGITAL OP291 4096
CONTROL 2 4

R3 R2 R4
232⍀ 32.4k⍀ 100k⍀
1% 1% 1%

Figure 9. +5 V Only, 12-Bit DAC Swings Rail-to-Rail

REV. A –15–
OP191/OP291/OP491
A +3 V, Cold Junction Compensated Thermocouple Amplifier 390pF

The OP291’s low supply operation makes it ideal for +3 V battery-

37.4k⍀
powered applications such as the thermocouple amplifier shown
20k⍀, 1%
in Figure 11. The K-type thermocouple terminates in an iso- A1 13
0.1␮F
thermal block where the junctions’ ambient temperature is 1/4
RXA 14 OP491
continuously monitored using a simple 1N914 diode. The diode 12
corrects the thermal EMF generated in the junctions by feeding 0.0047␮F

a small voltage, scaled by the 1.5 MΩ and 475 Ω resistors, to 3.3k⍀ 20k⍀, 1%
the op amp.
10 A2
To calibrate this circuit, immerse the thermocouple measuring 1/4 475⍀, 1%
junction in a 0°C ice bath, and adjust the 500 Ω pot to zero volts OP491 8
out. Next, immerse the thermocouple in a 250°C temperature 9
37.4k⍀, 1% T1
bath or oven and adjust the Scale Adjust pot for an output
voltage of 2.50 V. Within this temperature range, the K-type 0.1␮F 20k⍀, 1% 750pF
TXA
thermocouple is accurate to within ± 3°C without linearization. 0.033␮F 1:1
20k⍀ 1%

1.235V 20k⍀ 1%

AD589 10k⍀ 5.1V TO 6.2V

3.0V ZENER 5
6 A3
ISOTHERMAL SCALE 1/4
BLOCK ADJUST 7
7.15k⍀ 24.3k⍀ OP491
1N914 1% 1% 1.33M⍀ 20k⍀ 5
+3V OR +5V
1.5M⍀ 24.9k⍀ 4.99k⍀
ALUMEL 1% 1% 1% 8
2
AL VOUT 4 2
COLD 1/4 100k⍀
500⍀ OP291 1
JUNCTIONS 1
10-TURN OP491
3 A4 11 3
CR 11.2mV ZERO 4 0V = 0ⴗC
CHROMEL ADJUST 3V = 300ⴗC 100k⍀ 10␮F 0.1␮F
475⍀ 2.1k⍀
K-TYPE 1% 1%
THERMOCOUPLE
40.7␮V/ⴗC

Figure 11. A 3 V, Cold Junction Compensated Thermo-
couple Amplifier
Single-Supply, Direct Access Arrangement for Modems
An important building block in modems is the telephone line
interface. In the circuit shown in Figure 12, a direct access
arrangement is utilized for transmitting and receiving data from
the telephone line. Amplifier A1 is the receiving amplifier, and
amplifiers A2 and A3 are the transmitters. The forth amplifier,
A4, generates a pseudo ground half-way between the supply
voltage and ground. This pseudo ground is needed for the ac
coupled bipolar input signals.
The transmit signal, TXA, is inverted by A2 and then reinverted
by A3 to provide a differential drive to the transformer, where
each amplifier supplies half the drive signal. This is needed
because of the smaller swings associated with a single supply as
opposed to a dual supply. Amplifier A1 provides some gain for
the received signal, and it also removes the transmit signal present
at the transformer from the receive signal. To do this, the drive
signal from A2 is also fed to the noninverting input of A1 to
cancel the transmit signal from the transformer.
Figure 12. Single-Supply Direct Access Arrangement for
Modems
The OP491’s bandwidth of 3 MHz and rail-to-rail output swings
ensures that it can provide the largest possible drive to the trans-
former at the frequency of transmission.
A +3 V, 50 Hz/60 Hz Active Notch Filter with False Ground
To process ac signals in a single-supply system, it is often best
to use a false-ground biasing scheme. A circuit that uses this
approach is illustrated in Figure 13. In this circuit, a false-ground
circuit biases an active notch filter used to reject 50 Hz/60 Hz
power line interference in portable patient monitoring equipment.
Notch filters are quite commonly used to reject power line
frequency interference which often obscures low frequency
physiological signals, such as heart rates, blood pressure readings,
EEGs, and EKGs. This notch filter effectively squelches 60 Hz
pickup at a filter Q of 0.75. Substituting 3.16 kΩ resistors for
the 2.67 kΩ resistors in the twin-T section (R1 through R5)
configures the active filter to reject 50 Hz interference.

–16– REV. A
 OP191/OP291/OP491
R2 Single-Supply Half-Wave and Full-Wave Rectifiers
2.67k⍀
An OP191 family configured as a voltage follower operating on
+3V R1 a single supply can be used as a simple half-wave rectifier in
2.67k⍀
low-frequency (<2 kHz) applications. A full-wave rectifier can
11 C1 C2
2 1␮F 1␮F be configured with a pair of OP291s as illustrated in Figure 14.
1/4 1 5 The circuit works in the following way: When the input signal is
VIN OP491 VOUT
R3 R4
2.67k⍀
1/4 7 above 0 V, the output of amplifier A1 follows the input signal.
3 4 A1 2.67k⍀ OP491
6
Since the noninverting input of amplifier A2 is connected to
A2
R6
C3 R5 A1’s output, op amp loop control forces the A2’s inverting input
2␮F 1.33k⍀
100k⍀ (1␮Fⴛ2) (2.67k⍀÷2) R7 to the same potential. The result is that both terminals of R1 are
R8
1k⍀ equipotential; i.e., no current flows. Since there is no current
1k⍀
R11 flow in R1, the same condition exists upon R2; thus, the output
100k⍀
of the circuit tracks the input signal. When the input signal is
C5
below 0 V, the output voltage of A1 is forced to 0 V. This con-
+3V
0.01␮F
dition now forces A2 to operate as an inverting voltage follower
R9 9 R12 because the noninverting terminal of A2 is at 0 V as well. The
1M⍀ 499⍀
1/4 8
output voltage at VOUTA is then a full-wave rectified version of
OP491 C6 the input signal. If needed, a buffered, half-wave rectified version
10 1.5V
C4 A3 1␮F of the input signal is available at VOUTB.
1␮F
R10
1M⍀
R1 R2
100k⍀ 100k⍀

+5V
Figure 13. A +3 V Single-Supply, 50 Hz/60 Hz Active Notch 6
VOUT A
1/2
Filter with False Ground VIN 3 8 OP291 7 FULL-WAVE
2V p-p RECTIFIED
1/2 1 5
Amplifier A3 is the heart of the false-ground bias circuit. It <2kHz OP291 A2 OUTPUT
4 A1
simply buffers the voltage developed by R9 and R10 and is the 2

reference for the active notch filter. Since the OP491 exhibits a VOUT B
HALF-WAVE
rail-to-rail input common-mode range, R9 and R10 are chosen RECTIFIED
to split the +3 V supply symmetrically. An in-the-loop compen- OUTPUT
1V 500mV
sation scheme is used around the OP491 that allows the op amp VIN
to drive C6, a 1 µF capacitor, without oscillation. C6 maintains (1V/DIV) 100
90
a low impedance ac ground over the operating frequency range
of the filter.
VOUT B
The filter section uses a pair of OP491s in a twin-T configura- (0.5V/DIV)

tion whose frequency selectivity is very sensitive to the relative

matching of the capacitors and resistors in the twin-T section. 10
0%
Mylar is the material of choice for the capacitors, and the rela- VOUT A
(0.5V/DIV) 500mV 200␮s
tive matching of the capacitors and resistors determines the
filter’s passband symmetry. Using 1% resistors and 5% capaci- TIME – 200␮s/DIV
tors produces satisfactory results.
Figure 14. Single-Supply Half-Wave and Full-Wave
Rectifiers Using an OP291

REV. A –17–
OP191/OP291/OP491
* OP491 SPICE Macro-model Rev. A, 5/94 *
* ARG/ADI * POLE AT 2.5 MHz
* *
* Copyright 1994 by Analog Devices, Inc. G3 98 18 (12,39) 1E-6
* R11 18 98 1E6
* Refer to “README.DOC” file for License Statement. Use of C4 18 98 63.662E-15
* this model indicates your acceptance of the terms and pro- *
* visions in the License Statement. * BIAS CURRENT-VS-COMMON-MODE VOLTAGE
* *
* Node assignments EP 97 0 (99,0) 1
* noninverting input VB 99 17 1.3
* inverting input RB 17 50 1E9
* positive supply E3 19 0 (15,17) 16
* negative supply D13 19 20 DX
* output R12 20 0 1E6
* G4 98 21 (20,0) 1E-3
.SUBCKT OP491 1 2 99 50 45 R13 21 98 5E3
* D14 21 22 DY
* INPUT STAGE E4 97 22 (POLY(1) (99,98) -0.765 1
* *
I1 99 7 8.06E-6 * POLE AT 100 MHz
Q1 6 4 7 QP *
Q2 5 3 7 QP G6 98 40 (18,39) 1E-6
D1 3 99 DX R20 40 98 1E6
D2 4 99 DX C10 40 98 1.592E-15
D3 3 4 DX *
D4 4 3 DX * OUTPUT STAGE
R1 3 8 5E3 *
R2 4 2 5E3 RS1 99 39 109.375E3
R3 5 50 6.4654E3 RS2 39 50 109.375E3
R4 6 50 6.4654E3 RO1 99 45 41.667
EOS 8 1 POLY(1) (16,39) –0.08E-3 1 RO2 45 50 41.667
IOS 3 4 50E-12 G7 45 99 (99,40) 24E-3
GB1 3 98 (21,98) 50E-9 G8 50 45 (40,50) 24E-3
GB2 4 98 (21,98) 50E-9 G9 98 60 (45,40) 24E-3
CIN 1 2 1E-12 D9 60 61 DX
* D10 62 60 DX
* 1ST GAIN STAGE V7 61 98 DC 0
* V8 98 62 DC 0
EREF 98 0 (39,0) 1 FSY 99 50 POLY(2) V7 V8 0.207E-3 1 1
G1 98 9 (6,5) 31.667E-6 D11 41 45 DZ
R7 9 98 1E6 D12 45 42 DZ
EC1 99 10 POLY(1) (99,39) –0.52 1 V5 40 41 0.131
EC2 11 50 POLY(1) (39,50) –0.52 1 V6 42 40 0.131
D5 9 10 DX .MODEL DX D()
D6 11 9 DX .MODEL DY D(IS=1E-9)
* .MODEL DZ D(IS=1E-6)
* 2ND GAIN STAGE AND DOMINANT POLE AT 1.25 Hz .MODEL QP PNP(BF=66.667)
* .ENDS
G2 98 12 (9,39) 8E-6
R8 12 98 276.311E6
C2 12 98 16E-12
D7 12 13 DX
D8 14 12 DX
V1 99 13 0.58
V2 14 50 0.58
*
* COMMON-MODE STAGE
*
ECM 15 98 POLY(2) (1,39) (2,39) 0 0.5 0.5
R9 15 16 1E6
R10 16 98 10

–18– REV. A
 OP191/OP291/OP491
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

8-Lead Plastic DIP 8-Lead Narrow-Body SO

(N-8) (SO-8)

0.430 (10.92) 0.1968 (5.00)

0.348 (8.84) 0.1890 (4.80)

8 5
8 5
0.280 (7.11) 0.1574 (4.00) 0.2440 (6.20)
0.240 (6.10) 0.1497 (3.80) 1 4 0.2284 (5.80)
1 4 0.325 (8.25)
0.300 (7.62)
PIN 1 0.060 (1.52)
0.015 (0.38) PIN 1 0.0688 (1.75) 0.0196 (0.50)
0.210 (5.33) 0.195 (4.95) x 45°
0.0098 (0.25) 0.0532 (1.35) 0.0099 (0.25)
MAX 0.115 (2.93)
0.130 0.0040 (0.10)
0.160 (4.06) (3.30)
0.115 (2.93) MIN
0.015 (0.381) 8°
0.022 (0.558) 0.100 0.070 (1.77) SEATING 0.0500 0.0192 (0.49) 0°
PLANE 0.008 (0.204) SEATING 0.0098 (0.25) 0.0500 (1.27)
(1.27) 0.0138 (0.35)
0.014 (0.356) (2.54) 0.045 (1.15) PLANE
BSC BSC 0.0075 (0.19) 0.0160 (0.41)

14-Lead Plastic DIP 14-Lead Narrow-Body SO

(N-14) (R-14)

0.795 (20.19) 0.3444 (8.75)

0.725 (18.42) 0.3367 (8.55)

14 8
0.280 (7.11) 14 8
0.240 (6.10) 0.1574 (4.00) 0.2440 (6.20)
1 7 0.325 (8.25) 0.1497 (3.80) 1 7 0.2284 (5.80)
0.300 (7.62) 0.195 (4.95)
PIN 1 0.060 (1.52) 0.115 (2.93)
0.015 (0.38)
0.210 (5.33) PIN 1 0.0688 (1.75) 0.0196 (0.50)
MAX x 45°
0.130 0.0098 (0.25) 0.0532 (1.35) 0.0099 (0.25)
0.160 (4.06) (3.30) 0.0040 (0.10)
0.115 (2.93) MIN
0.015 (0.381)
0.022 (0.558) 0.100 0.070 (1.77) SEATING 8°
0.008 (0.204)
(2.54) 0.045 (1.15) PLANE 0.0500 0.0192 (0.49) 0°
0.014 (0.356) SEATING 0.0099 (0.25) 0.0500 (1.27)
BSC (1.27) 0.0138 (0.35)
PLANE BSC 0.0160 (0.41)
0.0075 (0.19)

14-Lead TSSOP
(RU-14)

0.201 (5.10)
0.193 (4.90)

14 8

0.177 (4.50) 0.256 (6.50)

0.169 (4.30) 0.246 (6.25)

1
7

PIN 1
0.006 (0.15)
0.002 (0.05) 0.0433
(1.10)
MAX 0.028 (0.70)
8°
0.0256 0.0118 (0.30) 0° 0.020 (0.50)
SEATING (0.65) 0.0079 (0.20)
PLANE 0.0075 (0.19)
BSC 0.0035 (0.090)

REV. A –19–
OP191/OP291/OP491
Revision History
Location Page
Data Sheet changed from REV. 0 to REV. A.
Edits to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

C00294-0-2/02(A)
Edits to PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to ODERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Edits to DICE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

PRINTED IN U.S.A.

REV. A
–20–