Iem ch1

Digital to Analog Converter
Analog to Digital Converter Analog to Digital Converter

DAC - ADC DAC - ADC
EIM Chap 2 Digital to analog converter . Analog to digital converter
Digital to Analog Converter
Function: converts binary input number in analog output; Function: converts binary input number in analog output;
f
DAC
:NR
Parameters: Parameters:
Conversion type: unipolar, bipolar;
Binary code (offset binary, twos complement, etc.); Binary code (offset binary, twos complement, etc.);
Output type (U, I);
Output range
Resolution - output variation for LSB variation of input code
_ max _ min O O
U U U =
_ max _ min O O
I I I =
Resolution - output variation for LSB variation of input code
- number of bits used for binary cod (n)
/(2 1)
n
LSB
U U U = =
- number of bits used for binary cod (n)
Settling time - interval between an input command and the time
when the output reaches its final value;
2
EIM Chap 2 Digital to analog converter
Binary representation
of numbers (n
1
+n
2
+1 bits):
{ }
2
2 ; 0,1 ;
n
k
k k
k n
N b b
=
=
of numbers (n
1
+n
2
+1 bits):
Binary coding (sub-unitary, N<1)
Natural binary (unsigned)
1
k n =
Natural binary (unsigned)
1
2
n
k
k
k
N b

=
=
min
0 N =
max
1 2
n
N

=
2
n
N

=
Offset binary (signed)
1
2 2
n
k
k
N b

=
min
1
N =
max
1
2
n
N

=
2
n
N

=
Twos complement (signed)
1
2 2
k
k
N b
=
=
min
2
N =
max
2
2
N =
2
n
N

=
Twos complement (signed)
( )
1
1
2
2 2
n
k
k
k
N b b

=
= +
2
n
N

=
min
1
2
N =
max
1
2
2
n
N

=
3
2 k=
2 2
Binary coding (contd)
Sign Magnitude (signed)
( )
1
2
1 2
n
b
k
k
k
N b

=
=
1
min
2 2
n
N

= +
1
max
2 2
n
N
+
=
2
n
N

=
Binary coded decimal (BCD) 4 bits (nibble) used to
represent one digit ;
2 k=
represent one digit ;
Gray the difference between codes of two successive
number is 1 bit; number is 1 bit;
Ones complement (signed);
4
Unipolar Codes Unipolar Codes
N (natural) Fraction ( subunitar nr) NB BCD Gray
0 0 0000 0000 0000
1 1/16 0001 0001 0001 1 1/16 0001 0001 0001
2 2/16 0010 0010 0011
3 3/16 0011 0011 0010
4 4/16 0100 0100 0110 4 4/16 0100 0100 0110
5 5/16 0101 0101 0111
6 6/16 0110 0110 0101
7 7/16 0111 0111 0100
8 8/16 1000 1000 1100
9 9/16 1001 1001 1101
10 10/16 1010 - 1111
11 11/16 1011 - 1110
12 12/16 1100 - 1010 12 12/16 1100 - 1010
13 13/16 1101 - 1011
14 14/16 1110 - 1001
15 15/16 1111 - 1000
5
15 15/16 1111 - 1000
Bipolar Codes
N Fraction SM C1 C2 OB* OB
+3 +3/8 011 011 011 111 000
+2 +2/8 010 010 010 110 001 +2 +2/8 010 010 010 110 001
+1 +1/8 001 001 001 101 010
+0 +0 000 000 000 100 011 +0 +0 000 000 000 100 011
-0 -0 100 111 - - -
-1 -1/8 101 101 111 011 100 -1 -1/8 101 101 111 011 100
-2 -2/8 110 101 110 010 101
-3 -3/8 111 100 101 001 110
-4 -4/8 - - 100 000 111
6
Binary codes conversion
7
Binary codes conversion
8
Ideal characteristic for unipolar DAC :
( )
2
n
k
R k
U N U b

=
2
n
CS
U
U U

= =
b
1
b
n
V(N)
( )
1
2
R k
k
U N U b
=
=
( )
min
0..0h 0V U U N = = =
2
2 1
CS
R
n
U U = =
V
R
V(N)
Ideal characteristic for bipolar DAC
V(N)
V
V
CS
R
( )
( )
max
... h 1 2
n
R CS
U U N F F U U
= = = =
Ideal characteristic for bipolar DAC
(offset binary code)
V
MSB
n

0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
N
V
LSB
N
m
a
x
+
1
( )
1
1
2 2
n
k
R k
k
U N U b

=

=

=
( )
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
N
L
S
B
M
S
B
N
m
a
x
0 1/8 4/8 7/8
N
m
a
x
+
1
1
min
2
R
U U

=
( )
1
max
2 2
n
R
U U

=
2
n
R
U U

=
9
0 1/8 4/8 7/8
2
R
U U =
Non-ideality errors
Static errors
Offset error - analog output response to an input code Offset error - analog output response to an input code
corresponding to output zero;
Gain error difference between slope of actual and ideal Gain error difference between slope of actual and ideal
transfer function;
Full-Scale error - difference between the actual and the ideal
output maximum value (offset error + gain error) ; output maximum value (offset error + gain error) ;
Integrated nonlinearity error (INL) - deviation of an actual
transfer function from a straight line (after nullifying offset and transfer function from a straight line (after nullifying offset and
gain errors);
Differential nonlinearity error (DNL) - difference between the
ideal and the measured output responses for successive ideal and the measured output responses for successive
DAC codes;
Dynamic error: overshoot, undershoot (during settling time)
10
Offset error
Gain error
Factor scale error Factor scale error
U
O
U
O
(N)
Overshoot
2
V
+
U
O
(N)
Undershoot
2
V
INL error DNL error Settling time

t
t
s
t
settling
t
sw
11
INL error DNL error Settling time
D/A converter traditional data converter at Nyquist
rate (f
s
>2f
m
)
- LPF is antialiasing filter (for extinction of image signal on f
S
) ;
- Droop correction means inverse Sinc function ;
- The S/H is a deglitching circuit and could be eliminated for
small glitches;
12
small glitches;
EIM Course 3 Digital to analog converter
D/A converter D/A converter mathematical representation:
Pulse Amplitude Modulation

p(t)
( )
y t
( )
y t
( ) ( ) ( )
( )
sh S
n
y t y t t nT p t
+
=

=

p(t)
hold
( ) ( )
T S
t t nT
+
=
( )
y t
( )
sh
y t
|Y( f ) |
( ) ( )
T S
n
t t nT
=
=
( ) { } ( ) ( ) ( ) { }
sh S S
n
y t y nT t nT p t
+
=

=

F F F
( ) ( ) ( )
sinc
sh s k s
n
Y f w f w f Y f nf
=
=
-f
m
f
m
For w = T (practical DAC converter)
-f
m
f
m
|Y
sh
( f ) |
( ) ( )
sinc 2
2
s
sh k s
T
Y f f Y f nf

=

For w = T
S
(practical DAC converter)
f
m
-f
m
f
S
-f
S
1/w
( ) ( )
sinc 2
2
sh k s
n
Y f f Y f nf
=
=

13
f
S
-f
S
Types of DACs
Binary Weighted Resistor Network Binary Weighted Resistor Network
R-2R Ladder Network
Stochastic
Multiplying DAC
14
V
R
Binary-Weighted Resistor DAC
2 R
n
bn
1
( )
1 1
{0,1}
n n
i
b
V N V b

+ =

Using Tellegens theorem:
8R
b3
.....
0 ( )
1 1
1 1
{0,1}
2 2 2
i
g R i
i n i
i i
b
V N V b
R R R
= =

+ =

( )
2
n
i
g R i R
V N V b V N
= =
4R
2R
b2
1
1
0
R(N)
( )
1
2
g R i R
i
V N V b V N
=
= =
( )
_min
0...0h 0V
g g
V V = = ( )
R
0...1h 2 V
n
g g
V V

= =
b1
2R
RT=2 R
n
0
Vg(N)
After source passivization:
( )
( )
_max
... h 1 2
n
g g R
V V F F V

= =
After source passivization:
( )
( )
1
1 1 1 1
2 2
n
i n
i
R N R
R N R R R
=
= + = =
15
Steady state voltage command
Binary-Weighted Resistor DAC (contd)
( ) ( )
0 g
V N V N =
Dynamic regime (Laplace transform )
Steady state voltage command

voltage command
0
1 1 1 1
( ) ( ) ( )
1 1/
g g
p
V s V s V s
sRC s s s

= =

+ +
1
t

( )
( )
0
1
( ) 1 ,
t
g
p
V t V e t
R N C

= =

V

R(N)
V (t)
current command
( )
( )
1
0
1
( ) ln 2
2
n
R
s g s
g
V
V t V N V t
V N

V
g
(N) (t)
C
p
V
0
(t)
( )
( )
( ) ( )
0 g g
R
V N V N V N
R N
= =
Steady state current command
16
( )
R N
Disadvantages:
Binary-Weighted Resistor DAC (contd)
Resistance Values Require Great Accuracy:
e.g. Tolerance of R must be < 1/2
n
Disadvantages:
e.g. Tolerance of R must be < 1/2
n
Often limited to 4-Bit conversions because of the limited current
range possible with resistors; range possible with resistors;
Larger bit numbers difficult due desired current changes being
close in magnitude to noise amplitudes (for less significant bits); close in magnitude to noise amplitudes (for less significant bits);
Hardware difficult realization for large bits number (due the weight Hardware difficult realization for large bits number (due the weight
inaccuracy for the large range);
17
I
R
R R R I
t
R R R
R-2R ladder network DAC
b1 b2 bn-1 bn
I
R
2R 2R
I1
I2
2R
.....
2R RT=2R
R R R I
t
V
R
1
2
2 2
k k
R
k k R
V
R
I I I

= = =
+
b1 b2 bn-1 bn
R
r
V0(N)
0 1
[B]
1 0
1
2 2
2 2
k k R
I I I
R R R
= = =
+
( ) ( )
0 r
V N R I N =
V0(N)
Convertor I - U
( ) ( )
0 r
V N R I N =
( ) ( )
0
1 1 1
1
2 2
n n n
k k
r
k R k R k
k k k
R
I N I V b V N V b
R R

= = =
= = =

( )
0_max
0...0h 0V V N= =
( )
( )
0_min
... h 1 2
n
r
R
R
V N F F V
R
= =
1 1 1 k k k
R R
= = =
0_max
R
( )
0
0...1h 2
n
r
R
R
V V N V
R

= = =
18
R-2R ladder network resistor DAC (contd)
Maintains constant current through all branches = no voltage
transients;
Less hardware constrain (easy to find R-2R resistor pair
values);
Faster response time due to lack of voltage transients.
19
Stochastic DAC (without resistor network)
NUM
f
CK
n
NUM
SUM
Cy out
R
C
V(N)
out
( )
0
1
2
cos
y out k k
k
C t A A k t
T
=

= + +

n
n
N
Cy out
C
out
(nefolosit)
T =/2
n
unused
1 k
T
=

( )
2 1
n
CK
T T =
1 1
T=2 T
CK
n
t
T =/2
n
T = (2
n
-1)T
CK
( )
2
1 1
1 2
1
T
H f
j fRC
f
f
= =
+

+

1 1
2
T
f
RC T
= <<
T=2 T
CK
Cy out()
A
0
A
1
LPF
T = (2 -1)T
CK T
f

( )
1
0
1
2
2
2 1 2 1
n
n
k
R k
n n
k
N E
V N A E E N V b
T

=
= = = = =

A
0
2/
A
2
4/ 0
N sub-unitary number (N
1
supra-unitary )
Multiplying DAC
U
slow time varying external
( )
out
U t
Ref
U
slow time varying external
( )
Ref in
U U t =
t
( )
Ref in
( )
out
U t
( )
o
d
d 2
in
U t
U
t t
<<
t
conv
max
d 2 t t
<<
binary code on digital input command for controlled amplification /

attenuation; attenuation;
U
in
(t) must preserve DAC functionality;
DAC applications
Industrial Control Systems
e.g. motor speed & valves;
Digital Audio
e.g. CD player;
Digital Communications
e.g. digital telephone and video systems;
Waveform Function Generators
e.g. direct digital synthesizer (DDS);
Example 1: Digital to analog converter (8 bits) - DAC 08
I
k
= 2
-k
I
( ) ( )
0
' ' 1 2
n n
k
R
k k
V
I N I b
R
= =

( )
0
2
n n
k
R
k k
V
I N I b
R
= =

( ) ( )
0
1 1
' ' 1 2
k k
k k
ref
I N I b
R
= =
= =

( )
0
1 1
k k
k k
ref
R
= =

( )
0_min
' FFh 0 I N= = ( )
( )
8
0_max
' 00h 1 2
R
ref
V
I N
R
= =
8
0
' 2
R
ref
V
I
R

=
ref
R
ref
R
( )
0_min
00h 0 I N= = ( )
( )
8
0_max
FFh 1 2
R
ref
V
I N
R
= =
8
0
2
R
ref
V
I
R

=+
23
Example 2: Inversion amplifier with digital adjustment gain
R
( )
v RI N =
I
I
+
_
DAC - 08
u(t)
IN
Vout
( ) ( ) ( )
n
R
( )
out
v RI N =
I
N
u(t)
IN
Vout
( ) ( ) ( )
1
( ) 2
n
k
out in k u in
k
ref
R
v t u t b A N u t
R
=
= =
n
( )
1
2
n
k
u k
k
ref
R
A N b
R
=
=
24
EIM Chap 2 Analog to digital converter
{n} s(t)
Analog to Digital Converter
{n}
ADC
s(t)
Function: converts input analog signal into a digital signal; Function: converts input analog signal into a digital signal;
ADC conversion comprises :
Time sampling: samples are taken from the analog signal Time sampling: samples are taken from the analog signal
(sampling frequency) and its values are maintained for a certain
time interval;
Quantization : rounding off of the sampled value to the nearest of Quantization : rounding off of the sampled value to the nearest of
a limited number of digital values;
Binary coding: conversion of the quantized value into a binary
code; code;
Sampling and quantization operation may give rise to loss of information.
Under certain conditions ADC loss can be limited to an acceptable Under certain conditions ADC loss can be limited to an acceptable
minimum;
25
{n} s(t)
Analog to Digital Converter
{n}
ADC
s(t)
Mathematical representation of ADC Function: Mathematical representation of ADC Function:
f
ADC
:RN
Parameters: Parameters:
Conversion type: unipolar, bipolar;
Quantization type: truncate, round, round-ceiling;
Binary code (natural, offset, twos complement, etc.); Binary code (natural, offset, twos complement, etc.);
Input type (U, I);
Input range;
Resolution - the smallest change required in the ADC analog input to Resolution - the smallest change required in the ADC analog input to
change its output code by one level;
- number of bits used for binary cod (n);
Conversion time - required time before the converter can provide valid Conversion time - required time before the converter can provide valid
output data
Accuracy of conversion - the difference between the actual input voltage
and the full-scale weighted equivalent of the binary output code
26
and the full-scale weighted equivalent of the binary output code
Parameters (contd)
Converter Throughput Rate - the number of times the input signal can be Converter Throughput Rate - the number of times the input signal can be
sampled maintaining full accuracy
- Inverse of the total time required for one
successful conversion successful conversion
- Inverse of Conversion time if no S/H
(Sample and Hold) circuit is used
ADC Interface Signals : ADC Interface Signals :
Data: Digital I/O pins the ADC uses to supply data
Parallel output n+1 pins (fast transmission, short distances)
Serial output 2 pins (for long distances, need a internal shift-register)
Start: Pulse high to start conversion (input)
EOC (End of Conversion): Typically active low low level of pulse EOC (End of Conversion): Typically active low low level of pulse
indicate complete conversion (output value can be read);
Clock: Clock used for conversion (for synchronising ADC sub-blocks, for
internal FSM);
27
internal FSM);
A/D Converter traditional data converter at Nyquist rate
(f
s
>2f
m
)
s m
( )
SH
X f ( )
Q
X f
Successive operations for AD conversion process.
f f f f
Successive operations for AD conversion process.
ADC introduces a non-compensable quantization noise.
28
Sampling process (remember)
- continuous signal conversion into a discrete time samplers sequence
(ideal sampling, natural sampling, flat-top sampling); (ideal sampling, natural sampling, flat-top sampling);
Ideal sampling
( ) ( ) [ ] ( )
s s
x t x t x n x nT R = =
( ) ( ) ( ) ( ) ( )
x t x t t nT x t t
+
= =
( )
2
1
S
S
jn t
T
T
n
t e
T
+
=
=

( ) ( ) ( ) ( ) ( )
S
s S T
n
x t x t t nT x t t
=
= =
n
S
T
=
( ) ( ) ( )
{ }
( )
1
S
S T
n
S S
n
X f x t t X f f
T T

+
=

= =

F
f
m
-f
m
|X
S
( f )|
( )
1
n
S S
S S
n n
S S
T T
n
X f f X f n f
T T
=
+ +
= =

= =

f -f f -f
29
f
m
-f
m
f
S
-f
S
Sampling process (contd) Sampling process (contd)
Natural sampling
( ) ( ) ( )
( )
S
s T
x t x t x t p t =
2
( )
2
S
S
jn t
T
T n
n
p t P e
+
=
=
f -f
( )
2
2 /2
2
/2
1
d
S
S
S S
S
nT
n T
j j t
T T
n T
s T
P e p t e t
T
f
m
-f
m
( ) ( ) ( )
/2
sinc n 1 sinc n
S
s T
n
jn
T
e

= =
( ) ( ) ( )
{ }
S
S T n
n
S
n
X f x t p t P X f
T
+
=

= =

F
f
m
-f
m
f
S
-f
S
30
Sampling process (contd)
Flat-top sampling Flat-top sampling
( ) ( ) ( ) ( )
( )
s S
n
x t x t x t t nT p t
+
=

=

n=
( ) ( ) { } ( )
sinc
= =
S
j fT
S S
P f p t T e f T F
( ) ( )
sinc
S
j fT
S S
n
X f e f T X f
T
( ) ( ) { } ( )
S S
F
f
m
-f
m
( ) ( )
sinc
=
=

S S
n
S
X f e f T X f
T
f
m
-f
m
Sampling rate is given in Samples/s
(S/s, kS/s, MS/s, GS/s);
f
m
-f
m
f
S
-f
S
31
Quantizing process Quantizing process
- analog signal approximation to the nearest discrete value: - analog signal approximation to the nearest discrete value:
[ ]
[ ] , 1, ,
q k k M
x n x n q k k M q Q =
a
a
M
q
M
M
q
M
M
x
q
(t)
Quant.
Quantized
a
1
a
k-1
a
k
q
2
2
q
k
k
q
2
2
q
k
k
Quant.
thresholds
Quantized
values
a
0
a
1
1 2 2 k M
q
1
1
t
q
1
1
n
q
(t)
+/2
-/2
t
t
-/2
Quantization of non-sampled signal (continuous)
32
Sampling & quantizing process Sampling & quantizing process
T
s
a
a
k
a
k-1
q
k
k
q
k-1
k-1
Quantization
thresholds
Quantized
values
a
0
q
1
1
n
sq
(t)

a
1
a
2
q
2
2
Quantization

-
t
Analog signal
Sampled signal (sample & hold)
Quantization
noise
Sampled signal (sample & hold)
Quantized signal
Quantization uniform (constant step) linear ADC
non-uniform (variable step) nonlinear ADC
33
Quantization
Quantization
Truncating quantization
1 k k
q a

=
1 1
2 2
n n
i n i
qt ref i i t
i i
U U b U b N U

= =
= = =

Quantization noise
p(n )
Quantization noise
1
2
i
qt qt ref i
i n
n U U U b
= +
= =

+
n
q
p(n
q
)
0
1 i n = +
+
n
q
0
1
{ } ( )
2
qt qt qt qt qt qt
E n p n n dn n dn
= = =

Noise mean value
0
{ } ( )
2
qt qt qt qt qt qt
E n p n n dn n dn
= = =

Noise variance (power)
2 2
2 2 2 2
2
{ } [ { }]
12 12
n
qt qt qt ref
E n E n U
= = =
Ideal characteristic
34
Quantization (contd)
Rounding quantization
1
1
2
k k
k
a a
q
+
+
+
=
2
1 1
1
1 1
2 2
( ) , {0,1}
n
n i
qr n qt ref n i
i
t n r n
U U b U U b b
N b U N U b

+ +
=
+ +

= + = +

= + =
Quantization noise
( 1)
( 2 2 )
n
n i
n U U U b b
+
= = +
1 1
( ) , {0,1}
t n r n
N b U N U b
+ +
= + =
( 1)
1
2
( 2 2 )
n i
qt qt ref n i
i n
n U U U b b
+
+
= +
= = +
p(n
q
)
/ 2
1
{ } 0 E n n dn
+
= =
Noise mean value

+/2
n
q
-/2
/ 2
1
{ } 0
qr qr qr
E n n dn
= =

2 2
2 2 2 2
2
{ } [ { }]
12 12
n
qr qr qr ref
E n E n U
= = =
35
12 12
Round-ceiling quantization
k k
q a =
1
(2 2 )
( 1)

=
= + = +
= + =
n i
qm qt ref i
i
t m
U U U U b
N U N U
Quantization noise
( 2 2 )
n i
qm qm ref i
n U U U b

= = +
t m
1
( 2 2 )
qm qm ref i
i n
n U U U b
= +
= = +
0
1
= =
Noise mean value p(n

q
)
1
{ } d
2
qm qm qm
E n n n
= =

0
n
q
-
2 2
2 2 2 2
2
{ } [ { }]
12 12
n
qm qm qm ref
E n E n U
= = =
36
Noise value as: voltage (rms, p-p), LSB (rms, p-p), SNR;
Signal to quantization noise ratio (SNR)
Considering a periodic signal at input, with period T, having power:
( )
1
T
( )
2 2
_
0
1
d
T
x x ef
P x t t U
T
= =
( )
2 2 2
_ _ _
2
12 12
10 log 10 log 10 log 10 log 2
x ef x ef x ef
n x
U U U
P
SNR n

= = = =
( )
_ _ _
2
2 2 2
_
10 log 10 log 10 log 10 log 2
6, 02 10,8 20 log [dB]
q
x ef x ef x ef
n x
n q ref
x ef
P
SNR n
P U
U
n

= = = =

= + +

Total SNR after quantization process:
For analog noisy signal, the total noise power is
2 2 2
= +
6, 02 10,8 20 log [dB]
ref
n
U
= + +

For analog noisy signal, the total noise power is
effective bit number :
2 2 2
T a q
= +
2
2
_
4 4
2 2
log log 1
x ef
a
ef
T q
U
n n

= = +

37
T q

Example: a full range sine wave input ( ) ( )
sin
2
ref
U
x t A t A =
Signal power and rms value:
2
( )
2
2
2 2
_
0
1
d
2 8
T
ref
x x ef
U
A
P x t t U
T
= = = =
2

( )
( )
2
2 2
2 2 2 2
3
6
10 log 10 log 10 log 10 log
2 2 2
6.02 1.76 dB (for sinwave quantization)
q
ref
x
q
n
n q ref
U
P A A
SNR n
P U
SNR n n

= = = =

= +
( )
max
min
6.02 1.76 dB (for sinwave quantization)
Dynamic range: 20 lg 6, 02 1.76 dB=
q
q
SNR n n
S
DR n SNR
S
= +
= = +
min
S
( )
10 bit 62 dB
q
SNR =
Example:
( )
1, 76 dB / 6.02 ENOB DR =
( )
10 bit 62 dB
q
SNR =
Example:
total effective bit number:
2 2
4 4 4
2 2
1
log log log 1
3
a
ef
T q
A
n n

= + = +

38
3
T q

Non-ideality errors
Static errors
Offset error (linear error);
Gain error (linear error);
Full-Scale error (offset error + gain error) ;
Integrated nonlinearity error (INL);
Differential nonlinearity error (DNL); Differential nonlinearity error (DNL);
Dynamic error:
Aperture error (due to the delay between Aperture error (due to the delay between
the clock signal of S/H block and the effective holding time)
( ) ( )
sin x t A t = For sin wave input ( ) ( )
sin x t A t =
( )
d
1
d 2 2
A A A
n
x t
V
E T T
t f
= < =
For sin wave input
39
d 2 2 t f
Offset error
Gain error
Factor scale error Factor scale error
INL error DNL error
40
Effects of static errors and quantizing error (examples)
Effects of static errors and quantizing error (examples)
An ideal three-bit quantizer, with
a gain of 1.25 instead of 1.00
a gain of 1.25 instead of 1.00
+0.6 LSB offset error
..
An ideal three-bit quantizer, with INL
error caused by important DNL error
INL error and small DNL error
error caused by important DNL error
41
Improving A/D conversion techniques
Oversampling
Signal
spectrum
Antialiasing
filter Imagine
spectrum
Oversampling
OSR oversampling ratio
= =
S S
f f
OSR
spectrum
Quant.
noise
( ) ( )
6.02 1.76 10log SNR n n OSR = + +
min
2
= =
S S
S sig
f f
OSR
f f
Dithering adding a small amount
( ) ( )
6.02 1.76 10log
q
SNR n n OSR = + +
of random noise (maximum = 1/2U)
to the input before conversion (for constant
and slow varying analog signal).
Nyquist rate ADC Oversampling ADC
and slow varying analog signal).
LSB oscillates randomly between 0 and 1
in the presence of very low input levels.
42
Acronyms for A/D converter Acronyms for A/D converter
SNR - Signal to (quantization) Noise Ratio;
THD Total Harmonic Distortion (due nonzero INL) = the ratio of the THD Total Harmonic Distortion (due nonzero INL) = the ratio of the
rms value of the fundamental signal to the mean value of the root-sum-
square of its harmonics (usually the first five harmonics); Specified in
dBc (decibels below carrier);
SINAD (dBc) - Signal-to-Noise Plus Distortion ratio (same as SNDR) = SINAD (dBc) - Signal-to-Noise Plus Distortion ratio (same as SNDR) =
ratio of the rms value of the fundamental signal to the mean value of
the root-sum-square of its harmonics plus all noise components;
SNDR - Signal to Noise + Distortion Ratio; SNDR - Signal to Noise + Distortion Ratio;
SFDR - Spurious Free Dynamic Range = the ratio of the rms value of
the signal to the rms value of the worst spurious signal (that may be or
may not be an harmonic of the original signal ); may not be an harmonic of the original signal );
Specified in dBc or in dBFS;
ENOB - Effective Number of Bits:
_
[dB] - 10, 8 dB-20 log

6,02
x ef
ref
U
SNR
U
n
(
| |
( ]
]
(
\
=
( ENOB - Effective Number of Bits:
FOM ADC Figure of Merit : [ ]
ENOB
Power
Joule/level resolved
2
S
FOM
f
=

6,02
n =
(
(
(
(
43
ENOB
Joule/level resolved
2
S
FOM
f
Input Tone
input tone
harmonics
Quantization Noise
Other quantization impairments:
intermodulation products
Other quantization impairments:
SFDR
Harmonics Harmonics
intermodulation products
44
A/D converter structures A/D converter structures
Without integration
Without feedback Without feedback
Flash ADC (direct conversion)
Folding ADC (Two-step ADC)
Pipelined ADC (serial ADC)
speed accuracy
Pipelined ADC (serial ADC)
Time-interleaved ADC
Charged coupled device ADC (CCD-ADC)
Time-stretch ADC (optical ADC)
speed accuracy
Time-stretch ADC (optical ADC)
With feedback
Successive approximation ADC (SAR)
Ramp-compare ADC Ramp-compare ADC
Delta-encoded ADC
With integration
Sigma-delta ADC
ADC with intermediate FM stage
Integrating ADC (single-slope, dual-slope, multiple slope)
45
Flash ADC
bank of 2
n
-1 parallel comparators (high complexity); bank of 2 -1 parallel comparators (high complexity);
very fast - GHz sampling rates (limited only by
delays of comparators and logic network);
references resistor ladder references resistor ladder
few bits of resolution (4 8 bits, rarely 10 bits)
high input capacitance
expensive power / area (in IC)
D
i
g
i
t
a
l

b
a
c
k
e
n
d
Input
D
OUT
are prone to produce glitches (clock skew
comparators sample the inputs at different instants)
high cost
applications: video, wideband communications,
D
i
g
i
t
a
l

b
a
c
k
e
n
d
applications: video, wideband communications,
optical storage
clock
46
Flash ADC
Improving technique track / hold Improving technique track / hold
T/H for good dynamic performance
Offset correction in comparators
Input
Track / Hold
D
OUT
Example: AD9066 Dual 6 AD9066 Dual 6--bit, 60MSPS bit, 60MSPS
Flash ADC Flash ADC Flash ADC Flash ADC
Key specifications: Key specifications:
Input Range: 500mV p-p
Input Impedance: 50k || 10pF
Offset
correction
Input Impedance: 50k || 10pF
ENOB: 5.7 bits @15.5MHz Input
On-Chip Reference
Power Supply: Single +5V Power Supply: Single +5V
Package: 28-pin SOIC
Ideal for Quadrature Demodulation
47
Interpolating Flash ADC
reduces the number of comparator reduces the number of comparator
preamplifiers at the input of a Flash
converter by a factor of two;
substantially reduces the input substantially reduces the input
capacitance, power dissipation, area of
flash converters;
preserves the one-step nature of a Flash preserves the one-step nature of a Flash
architecture ( VLSI technology);
48
Time-interleaved ADC (TI-ADC)
uses M parallel flash ADCs; uses M parallel flash ADCs;
ADC sample data every M-th cycle of
the effective sample clock; the effective sample clock;
sample rate is increased M times;
complexity is increased M times;
requires correction of time-
interleaving mismatch errors;
applications: video, wideband applications: video, wideband
communications, optical storage;
49
Folded Flash ADC (two steps)
Folding = technique that reduces hardware
maintaining the fast nature of a full Flash
INPUT
FOLDING
CIRCUIT
FINE
ADC
N
F
maintaining the fast nature of a full Flash
ADC;
An analogue pre-processing circuit
generates a residue which is digitised to
COARSE
ADC
DIGITAL ADDER &
CORRECTION CIRCUIT
generates a residue which is digitised to
obtain the LSBs;
The MSBs are resolved using a coarse
ADC that operates in parallel with the folding
DIGITAL OUTPUT
WORD
N
C
ADC that operates in parallel with the folding
circuit;
increase latency;
Folding principle
Folded ADC reduces latches and logic:
N
C
+N
F
bits need 2
Nc
+2
Nf
-2 comparators;
First stage determine the output sign;
Folding principle
First stage determine the output sign;
At every stage (except the last) the LSB
is wasted;
1 bits
C
N + bits
C
N bits
F
N
50
Serial/Parallel ADC (pipelined)
uses more steps of sub-ranging (with same bits number N
C
); uses more steps of sub-ranging (with same bits number N
C
);
one stage
a coarse conversion is done
amplifies the difference of the input signal (determined with a DAC), then go
to next stage
fast conversion - GHz sampling rates;
data latency greater than flash, but less than SAR
high resolution with less complexity; high resolution with less complexity;
ADC overload in next stage need Digital Error Correction;
1 bits
C
N +
bits N bits
C
N 1 bits N +
STAGE 2 STAGE 1
1 bits
C
N +
bits
C
N bits
C
N 1 bits
C
N +
51
STAGE 2 STAGE 1
Serial/Parallel ADC (pipelined)
Example: AD 9220/9221/9223 12 bits pipelined ADC Example: AD 9220/9221/9223 12 bits pipelined ADC
- Latency is four cycles;
- 1 bit overlap between adjacent stages
- accuracy of ADC in stages 1-4 needs 4
bits; 5-th stage needs greater accuracy; bits; 5-th stage needs greater accuracy;
- entire ADC accuracy established by 5-th
stage
Family Members: Family Members:
AD9221 (1.25MSPS), AD9223 (3MSPS),
AD9220 (10MSPS)
Power Dissipation: 60, 100, 250mW,
Respectively Respectively
FPBW: 25, 40, 60MHz, Respectively
Effective Input Noise: 0.1 LSB RMS (Span =5V)
SINAD: 71 dB
SFDR: 88dBc SFDR: 88dBc
On-Chip Reference
Differential Non-Linearity: 0.3 LSB
Single +5V Supply
28-Pin SOIC Package
52
28-Pin SOIC Package
Serial ADC (1 bit per stage)
it uses the truncating it uses the truncating
quantization in intermediate
stages.
Example for bipolar case; Example for bipolar case;
Single stage ADC
Obs: dont confuse with serial
output ADC of other
technologies (flash, SAR, technologies (flash, SAR,
folded flash, etc )
53
Successive approximation register ADC (SAR)
SAR = Successive approximation register SAR = Successive approximation register
DAC = digital-to-analog converter
EOC = end of conversion
SAR = successive approximation register SAR = successive approximation register
S/H = sample and hold circuit
Vin = input voltage
Vref = reference voltage Vref = reference voltage
- use a binary search to converge on the
closest quantisation level
- Binary search:
V
AX
- Binary search:
- select middle element
- If too high select middle element of lower group
- If too low select middle element of upper group - If too low select middle element of upper group
- Repeat until 1 element remains
- Constant conversion time (n cycles)
54
Successive approximation algorithm
B
i
t

2

=

0
B
i
t

2

=

0
B
i
t

3

=

1
B
i
t

4

=

0
V
DAC
B
i
t

3

=

1
B
i
t

1

=

1
T nT =
conv CK
T nT =
4 Bit SAC
Slower than Flash, but far fewer comparators
allows for higher accuracy
55
allows for higher accuracy
Delta - encoded ADC (tracking ADC)
an up-down counter feeds the DAC;
_
CK
CMP R
sens
Num. rev.
Up/Dw
UP/DOWN
an up-down counter feeds the DAC;
CMP compares U
X
and DAC output;
CMP drives U/D counter sens ;
+
_
N
CK
CMP
U
x
n
n
n
[z]
R
I(N)
sens
UP/DOWN
Counter
use a feedback to adjust the counter;
very wide range and high resolution;
conversion time is dependent of the input signal level (has a guaranteed value
CNA
R I(N)
I
DAC
conversion time is dependent of the input signal level (has a guaranteed value
for the worst case);
introduces granular noise for constant and very low frequency signals; introduces granular noise for constant and very low frequency signals;
can expect overflow error for rapid variable signal;
Granular
noise
Overflow
56
Ramp Compare ADC
A comparison voltage V(N) is ramped up;
FC
CK
EOC
A comparison voltage V(N) is ramped up;
When the comparison voltage matches
the sampled voltage (VA) the comparator is
triggered the sampled voltage has been
+
_
N
SC
CMP
U
x
n
z
NUM
triggered the sampled voltage has been
determined;
Variable Conversion Time (depends when
ramp signal matches actual signal):
CNA
V(N) V
R
N
DAC
ramp signal matches actual signal):
- Best case = 1 cycle
- Worst case = 2
n
cycles
U
X
V(N)
- Worst case = 2
n
cycles
Slower than SAR, same accuracy;
57
Sigma-delta ADC
the output is in the form of a 1 bit serial the output is in the form of a 1 bit serial
bit stream;
analog input variation proportional to
the duty of the output digital signal;
Oversampling (sampling freq 16 512 Oversampling (sampling freq 16 512
times greater than Nyquist rate);
low complexity;
presents granular noise for constants
Sigma-delta ADC of the first order
presents granular noise for constants
and possible overflow error for fast
analog input;
applications: typical low bandwidth applications: typical low bandwidth
digital transmission 22KHz(voice in digital
telephone network); recently - ADSL
network access, 1-2MHz (multi-bit ADC
and multi-bit feedback DAC ); digital and multi-bit feedback DAC ); digital
audio equipment (16-24 bit resolution,
48kS/s);
Oversampling ADC (- ADC)
58
Oversampling ADC (- ADC)
Sigma-delta ADC
Quantization noise is Quantization noise is
pushed out of the signal
band;
digital filter eliminates digital filter eliminates
out of band noise ;
very high SNR
Signal Quant. Noise Signal
spectrum
Quant. Noise
spectrum
59
Sigma-delta ADC
better performances for high order better performances for high order
-ADC (second, third, etc.);
changing LPF (integrator) BPF we can changing LPF (integrator) BPF we can
reduce the noise mDSP (N
0
) in band of interest;
Spectral noise shaping SNR vs OSR (-)
Second order - ADC
mPSD
Spectral noise shaping SNR vs OSR (-)
60
Integrating ADC single slope
similar with ramp - compare ADC, but analog similar with ramp - compare ADC, but analog
devices
contain: voltage comparator, digital counter,
sawtooth wave generator
Sawtooth
Phases:
0. Reset counter and sawtooth wave generator
1. Start conversion (SC) start generator and
counter
Sawtooth
wave gen.
counter
2. Finish conversion (FC) When the comparison
voltage (analog input) matches the output
generator the conversion finish and stop the
U
X
generator the conversion finish and stop the
counter:
Variable Conversion Time (depends when ramp
X X
N k U =
Variable Conversion Time (depends when ramp
signal matches actual signal):
- Best case = 1 cycle
- Worst case = 2
n
cycles
61
- Worst case = 2 cycles
Integrating ADC dual slope
2 , ' = =
n
T T T N T
1 2
2 , ' = =
n
CK CK
T T T N T
( )
1 1
R
0
1 1
d = d
+

X
T T t
x
T
U t t V t
RC RC
1
0 T
RC RC
( )
( )
1
1
'
= = 2
2
=
= =
n
x i x
x R i R
n
i
R
U t
t
N
U t V b V N
V T
Absolute values of R and C dont affect operation
Conversion time is given by:
1
1
2
= i
R
V T
( )
+
Digital output word gives average value of U
X
during first integration phase
( )
1
2 ' 2
+
= +
n n
conv CK CK
T N T T
during first integration phase
Can be used to get resolutions exceeding 20 bits
but at lower conversion rates
62
Integrating ADC dual slope with auto-zero
Phase 1 auto zero
(K
1
=0, K
2
=0)
Phase:
Phase 2 unknown
voltage integrating (K
1
=1,
K
2
=1) K
2
=1)
Phase 3 - reference
voltage integrating (K1=2,
K2=2) K2=2)
63
U
Dual slope ADC application: digital voltmeter
U
X
64
U
Functioning principle ICL7106
U
X
Switches Phase 0 Phase 1 Phase 2 Switches Phase 0
(AZ)
Phase 1 Phase 2
INPUT open close open
+REF open open funct. of
V
in
sign
-REF open open funct. of
V
in
sign
AUTO-
ZERO
close open open
65
comprise
-U
GI
comprise
a voltage-to-frequency converter
a frequency counter to convert
frequency into a digital count frequency into a digital count
( )
0
1
d
P x
V V U t t
R C
=
( )
( )
2
1 1
0
1
0 p
2 1
d
1 1
V =V + d d
P x
T
GI x
T T
V V U t t
R C
U t U t t
R C R C
=

V
1 1
2 1
1
1
1 2 2
1
T T
x GI out
R C R C
R
U U T K f
T T R
= =
+
V
0
66
U
Example U-f converter LM331
Longer integration times allow
U
X
Longer integration times allow
higher resolutions;
the speed of the converter can be
improved by sacrificing resolution; improved by sacrificing resolution;
few analog devices high accuracy
are very popular for low frequency
application with remote analog application with remote analog
sensor;
1
V R
1
2.09V
in S
out
L t t
V R
f
R R C
=
67
Application. Remote analog voltage measurement with LM331
(National Semiconductor)
l inie lunga
(transmi sie la distanta)
Remote transmission
U
U
x
x U-f
f-U
Catre f-metru
Tx Tx
to f-metru
1
2.09V
in S
out
L t t
V R
f
R R C
= 2.09
L
out in t t
S
R
V f R C
R
=
68
Catre f-metru
Tx Tx
to f-metru
2.09V
L t t
R R C
S
R
Ultra-fast ADC
Pure electronic ADC: CCD-ADC;
CCDs - ADC
Optical ADC : Time-stretch ADC.
CCDs - ADC
Charged-Coupled device (CCD) - sampled analog clocked delay line that
memories the input voltage at the clock impulse (analogical memory);
Typically size 512 stages (samples) and 100MS/s;
An slower ADC quantizes these analogical values;
For greater effective sample rate (400MS/s) are necessary several CCDs
in parallel with staggered clock drive.
Application digital video signal capturing Application digital video signal capturing
69
CCD matrix scheme
Ultra-fast ADC
CCD matrix scheme
CCD output waveform
70
CCD - ADC
Ultra-fast ADC electronic ADC
CCD - ADC
Correlated double sampling (CDS) minimise
switching noise at output switching noise at output
71
Ultra-fast ADC optical ADC
Electronic (pure) real-time analog-to digital conversion is limited to onversion
rates of few GS/s;
Communication, image processing and radar applications require extremely
fast real time A/D conversion;
A way out of this conversion bottleneck may be the use of photonic concepts
for A/D conversion;
Concept for ADC optical conversion: Concept for ADC optical conversion:
Photonic time stretching converter;
Self-Electro-optic Effect Device based all-optical A/D conversion;
Optical folding-flash converter; Optical folding-flash converter;
Optoelectronic thyristor based photonic smart comparator;
72
Ultra-fast ADC optical ADC (contd)
Absolute analog to digital conversion rate limits for a required SNR
q
Absolute analog to digital conversion rate limits for a required SNR
q
73
Time-stretch ADC (TS-ADC) Digitizes a very wide bandwidth analog
Ultra-fast ADC optical ADC
Time-stretch ADC (TS-ADC)
signal by time-stretching the signal prior to digitization using a photonic
preprocessor.
Improvements:
Effective sampling rate increased by M ; Effective sampling rate increased by M ;
Effective Input bandwidth increased by M ;
Reduce jitter noise ; Reduce jitter noise ;
Eliminates the need for samples interleaving ;
Ideal for time-limited signals or fast time-varying signals ;
74
Schematic photonic preprocessor for time-stretching
Schematic photonic preprocessor for time-stretching
Each ADC see the slowed-down signal;
Full Nyquist sampling by each ADC;
By allowing for finite overlap between segments, mismatch error can be
estimated from the signal itself;
Digitizer
x 4
1
WDM
P

R

I

S

M

Digitizer
x 4
x 4
Digitizer
2
T
P

R

I

S

M

4
x 4
x 4
Digitizer
3
Time
Time/ wavelength
2
T
4T
Time Stretch
x 4
T
Digitizer
4
Flash ADCs
or TI-ADCs
75
T
4T
Time Stretch
or TI-ADCs
Photonic Time Stretch System Photonic Time Stretch System
W
a
v
e
l
e
n
g
t
h
Stretched Signal
Input RF
Signal
W
a
v
e
l
e
n
g
t
h
Time
BW
Chirp
Signal
Dispersion
PD
Modulator
Dispersion
SC
Chirped Optical Pulse
PD
Modulator
L1 L2
Source
SC Optical Pulse
Stretch Factor = 1 + L
2
/ L
1
Time Aperture = D x x L
1
Time Aperture = D x x L
1
Baseband BW* =
Time BW Product* =
RF op
f f 2 /
) 8 /( 1
1 2
L
76
Mismatches in TS Mismatches in TS--ADC Arrays ADC Arrays
Offset
Mismatch
T
seg
=
=
1
0
) (
2
) (
L
k
s
k
s
L
k
F
T
S

Analog Signal
Mismatch
Gain
=0 k
s
2
1
k
L

=
L
N k
j
L
k
L
kN
M
km
j b
L
F
M
m
m k
) 1 (
exp
sin
sin
)
2
exp(
1
1
0
Gain
Mismatch ) (
2
) (
1
0
L
k
F
T
S
s
o
L
k
k
s
=
Clock
Skew

=
=
k
s
k
s
L
k
F
T
S ) (
1
) (
0
=
L
N k
j
L
k
L
kN
M
km
j T r j
L
F
M
m
s m k
) 1 (
exp
sin
sin
)
2
exp( ) exp(
1
1
0
0
L=MxN: the period of distortion pattern

77
L=MxN: the period of distortion pattern
Mismatches in TS-ADC Arrays Spectrum
Offset Error
Spurs at harmonics of
f
signal
/(MxN)
Gain Error or Clock Skew
Sidebands at multiples of
f
signal
/(MxN) centered at f
signal
f
signal
/(MxN)
signal
spurs
f
signal
/(MxN) centered at f
signal
f
s
/(MxN)
signal
spurs
Freq.
0
f
signal
-f
signal
Freq
f
s
/(MxN)
-f
signal
f
signal
Overlap between segments Overlap between segments
Slight redundancy in sampling could
(time overlaping) significantly improve
Digitizer 1 (S1)
Digitizer 2 (S2)
(time overlaping) significantly improve
the ADC performance;
Overlap
Digitizer 2 (S2)
78
Overlap
ADC SFDR Improvements
RMSE
(before)
SFDR
(before)
RMSE
(after)
SFDR
(after) (before) (before) (after) (after)
Offset 4% -36dBc 0.3% -58dBc
Gain 4% -36dBc 0.35% -57dBc
Conclusions:
Clock
Skew
8% -26dBc 0.45% -51dBc
Conclusions:
Signal is reconstructed based on segments, instead of the individual
samples;
In each segment, the sampling is above the Nyquist sampling rate;
Subject to the similar mismatch as the sample-interleaved counterpart;
79
Bibliography
S. Ciochina, Masurari electrice si electronice, 1999 ;
ham.elcom.pub.ro/iem; ham.elcom.pub.ro/iem;
Application notes - National Instruments;
J.G. Webster, Electrical Measurement, Signal Processing and Displays, J.G. Webster, Electrical Measurement, Signal Processing and Displays,
2004;
80

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L=MxN: the period of distortion pattern

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