Interface Issues in Hardware-in-the-Loop Simulation

A. Monti, Senior Member, IEEE, H. Figueroa, S. Lentijo, X. Wu, Student Member, IEEE, and R. Dougal, Senior Member, IEEE
main topics: The signal interface for power electronics applications Algorithms for conservation of energy at the boundary Wide bandwidth hardware for the power interface. The paper illustrates significant results for each of these issues including experimental results for hardware in the loop obtained by using the Virtual Test Bed platform with real-time extension (VTB-RT). II.
THE HIL SIMULATION SYSTEM

AbstractThis paper discusses the interface issues in hardware-in-the-loop (HIL) simulations. Different interfacing schemes are introduced to extend the applicability of HIL to power electronics applications that contains switching events and power hardware testing. Application examples are used to demonstrate the effectiveness of these interfaces, and HIL simulation results are presented. Index Termshardware-in-the-loop, interface, simulation

I. INTRODUCTION

ndustrial designers are increasingly interested in incremental prototyping of systems, a process in which Hardware-In-the-Loop (HIL) simulation plays a significant role. HIL simulation entails the interaction between real hardware components of a system and a real-time simulator that computes the performance of the rest of the system (ROS) for which real hardware does not yet exist. HIL is not a new concept and has been applied with success to many significant industrial processes [1]-[3]. So far, however, most of the tools and applications focus only on issues related to the design of system controls. In these cases, the plant running concurrently with the real control hardware in an HIL experiment. Our work attempts to extend this concept, allowing system designers to use the HIL methodology to test any kind of equipment, not just the control hardware. Furthermore, we address the specific issues that arise when the embedded control generates Pulse Width Modulation (PWM) signals in power electronics applications [8]. The goal of the research summarized in this paper is to provide designers with tools that will allow HIL testing of virtually any equipment before the insertion of that equipment into the ship. This technology is extremely significant for future All Electric Ships where one can envision many instances of late insertion of new technologies. The work described in this paper can be split into three

HIL simulation replaces the emulated hardware under test (HUT), or, control logic in the simulation model, with real hardware that interacts with the computer models. This increases the realism of the simulation and provides access to hardware features currently not available in software-only simulation models [6][7]. The structure of the HIL simulation system is shown in Fig. 1.

Fig. 1. The HIL platform with the VTB-RT and the signal interface

A. Monti is with the Department of Electrical Engineering , University of South Carolina, SC 29208 USA (e-mail: monti@engr.sc.edu). H. Figueroa is with the Department of Electrical Engineering , University of South Carolina, SC 29208 USA (e-mail: figueroh@engr.sc.edu). S. Lentijo is with the Department of Electrical Engineering , University of South Carolina, SC 29208 USA (e-mail: lentijo@engr.sc.edu). X. Wu is with the Department of Electrical Engineering , University of South Carolina, SC 29208 USA (e-mail: wu6@engr.sc.edu). R. Dougal is with the Department of Electrical Engineering , University of South Carolina, SC 29208 USA (e-mail: dougal@engr.sc.edu).

To perform HIL simulation, the original system is divided into two subsystems: the HUT and ROS. The HUT is constituted by the actual equipment and the ROS is presented by real-time models. These two subsystems exchange information through the simulation/hardware interface, as illustrated in Fig. 1. Most of the HIL applications involve only signal coupling between the simulation software and the actual hardware in HIL experiments. The following sections introduce different interfacing schemes to extend the applicability of the HIL methodology to the scenarios where switching events occur and/or the energy conservation at the coupling point is involved.

III. THE SIGNAL INTERFACE FOR POWER ELECTRONICS

APPLICATIONS

A. Issues in HIL Simulations that involve Switching Events One of the most frequent applications of the HIL technology is the prototyping of power electronic systems. This application field poses two main challenges to real-time simulation. First, power electronic systems usually include switched circuitse.g., power converters containing MOSFET switches that require digital switching firing signals that are normally provided by a digital controller. The switching events of the controllers firing signal are not necessarily synchronized with the real-time simulation time step; therefore, the simulation receives a delayed firing signal that leads to inaccurate results. Second, power electronics systems are characterized by a combination of subsystems working at different time scales; thus, when these subsystems are simulated, they have different needs in terms of time resolution. In a conventional simulation scheme, the time resolution of the simulation becomes the simulation time step. Among power electronics subsystems, switched circuits are the fastest and therefore require the highest time resolution for accurate simulation. Their requirements in terms of time resolution depend on the switching frequency of the firing signal, which is usually a pulse width modulation signal (PWM). Table 1 shows how the different time resolutions affect the accuracy of the acquisition of the firing signal duty coming from the digital controller.
TABLE I ACCURACY OF THE CONTROL FIRING SIGNAL DUTY VALUE MEASUREMENT IN A CONVENTIONAL REAL-TIME SIMULATION

simulation period h. Fig. 2 illustrates how a switching function is converted into an effective duty ratio averaged over one simulation time step. The duty ratio is mathematically expressed as
Averaged ( kh) = 1 kh (t ) dt h ( k 1) h
(1)

The FSA method assumes that the simulation time step for real-time simulators is much smaller than the controllers switching period, which is normally the case.

Fig. 2. Firing signal averaging over one simulation period

Switchin g frequency 1 kHz 2 kHz 2 kHz

Time Resolutio n 50 s 50 s 0.5 s

Simulation time step 50 s 50 s 0.5 s

Accurac y 5 % 10 % 0.1 %

B. Firing Signal Averaging (FSA) Method Lack of synchronization between the simulation time step and the controllers firing signal, and the high time resolution required to pinpoint the signal switching event, leads to the development of new techniques to separate software simulation requirements (50 s time step) from hardware requirements (less than 1us for sampling digital switching signals). This separation can be obtained by introducing a suitable hardware interface capable of sensing the commutation event of the switching signal and accurately measure the controllers firing signal duty. Here, the FSA method is adopted to increase the accuracy of the HIL simulation in case of switching events. The FSA method accounts for the harmonics terms introduced by the controllers firing signal (the switching function containing duty cycle information) by computing its average over one

In this study, the firing signal averaging method (FSA) is implemented in a field programmable array (FPGA) device that can be inserted in the HIL platform of choice, i.e., VTBRT. This interface permits direct connection of a real hardware controller to a real-time simulation of a power electronic system. In this scenario, the controller is tested under realistic conditions, sending the real actuating signal to the simulated plant. The FPGA-based interface offers high time resolution and provides 0.002% accuracynot possible to obtain with a software-only approachof the switch duty for a 2 kHz switching frequency (500us switching period), even when the simulation model executes in 50 or 100 s time steps. Moreover, the effect of the interface is to separate the simulation time step from the real-time platform time resolution as indicated in Table 2. Also, the use of the interface reduces the calculation load in the simulation platform, thereby increasing the efficiency of the simulation process without losing accuracy.
TABLE 2 ACCURACY OF THE CONTROL FIRING SIGNAL DUTY VALUE MEASUREMENT USING THE FPGA-BASED INTERFACE

Switchin g frequency 2 kHz 20 kHz

Time resolution 0.01 s 0.01 s

Simulation time step 50 or 100 s 50 or 100 s

Accuracy

0.002 % 0.02%

A schematic view of the insertion of the FPGA-based interface in a HIL experiment is reported in Fig. 3. Notice how the HW under test can be directly connected to the DAQ boards on one side and to the FPGA-system on the other. The simulation platform is a regular Personal Computer running

Linux Real Time.

Fig. 3. The HIL platform with the VTB-RT and the signal interface

C. Application Example--Testing of Digital Controller for a Buck Converter Here, the HIL testing of a digital controller for a buck converter is presented as an application example of the signal interface in the simulation of power electronics systems. The regulation problem in this application consists of making the output voltage error equal to zero, so that the output voltage follows the reference dc voltage. The buck converters switching circuit is averaged yielding a linear averaged model. The parameters of the buck converter used in this application example are specified in Table 3.
TABLE 3 BUCK CONVERTER PARAMETERS

Fig.4. Schematic for the HIL simulation of a FPGA controller for a buck converter

The transient response of the output voltage for a reference of 5V is shown in Fig. 5. The performance of the controller on both the real plant experiment and the HIL testing is observed. The HIL testing was performed for a simulation time step of 75 s. The expected delay due to the HIL approach is observed on the HIL transient (red curve); however, it can be observed that the HIL transient very closely matches the real plant transient. Moreover the high frequency content is preserved when using the HIL approach.

Parameter Symbol Value Input Voltage VDC 10 V Output Filter Inductance L 1.9 mH (r = 0.4 ) Output Filter Capacitance C 200 F Nominal Load R 10 A proportional-integral controller, with parameters Kp = 0.004 and Ki = 41.6, is chosen to provide the necessary firing signal to regulate the output voltage measured at the resistive load (vR(t) = vC(t)). HIL simulation is used to test the FPGA implementation of the PI controller for the buck converter. Figure 6.7 depicts the schematic of this application. In this schematic the plant is modeled in VTB-RT, and the controller is created using the Xilinx Simulink block set to be implemented on a Xilinx FPGA.

Fig.5. Buck converters output voltage in HIL simulation compared to real plant experimental results

Fig. 6 shows the output current transient for both the real plant experiment and the HIL testing. Even though a small attenuation effect can be observed, the switching content of the real plant current is very closely replicated by the VTB-RT HIL platform.

Fig.7. The simulation/hardware interface based on TFA for inductive/resistive HUT

In Fig. 7 Req(k) and Ieq(k) are equivalent resistance and voltage source, which approximate the time-variant HUT at time step k. Their values are updated at each time step using current and voltage values at the previous time steps as follows:
Fig.6. Buck converters output current in HIL simulation compared to real plant experimental results

Geq(k ) = I eq (k ) = i2 (k 1)
b Ts where = a Ts 1 2 as following:

(2)
a Ts 2 . They can be solved and = a Ts 1 2 1+
1

IV. ALGORITHMS FOR CONSERVATION OF ENERGY AT THE BOUNDARY The key element that enables natural coupling between the power hardware and the simulation model is the simulation/hardware interface. Several interfacing schemes are described in the literature, such as those based on the ideal transformer model (ITM) or the transmission line model (TLM). The ITM-based interface suffers from stability issues caused by the delay between simulation and the response of the actual hardware, while the TLM-based interface may cause undesired oscillation and steady state error when the inductor or the capacitor at the system partitioning point is not big enough to maintain a relatively smooth dynamic[5][6][9]. Instead, we describe a novel simulation/hardware interface that is based on approximation of the hardware under test as a linear, time-varying, first-order system. The approach compensates for delays caused by digital-to-analog (D/A) and analog-to-digital (A/D) conversion and by the computation time for executing the simulation time step. A. The Simulation/Hardware Interface based on TimeVariant First-Order Approximation (TFA) If the hardware under test (HUT) appears to be inductive or resistive at the main operation frequency, the dynamics of the real hardware system are approximated by the simulation/hardware interface as: di2 = a i2 + b v1 (1) dt Where i2 is the current going into the HUT and v1 the controlled voltage source applied across the HUT, whose value is determined by the output voltage of the ROS. Let us discretize (1) using the trapezoidal integration method: the equivalent schematic of the TFA-based simulation/hardware interface for inductive/resistive HUT is shown in Fig. 7.

v1 (k 1) i2 (k 1) i2 (k ) (3) = v (k 2) i (k 2) i (k 1) 2 1 2 The same estimation procedure can be applied to the case where the HUT appears to be capacitive or resistive at the main operation frequency. The dynamics of the real hardware system are approximated by the simulation/hardware interface as: dv2 (4) = a i1 + b v2 dt where v2 is the voltage across the HUT, and i1 the controlled current source going into the HUT, whose value is determined by the output current of the ROS. The schematic of the TFAbased simulation/hardware interface for inductive/resistive HUT is shown in Fig. 8.

Fig.8 The simulation/hardware interface based on TFA for capacitive/resistive HUT

In Fig. 8 Req(k) and Veq(k) are equivalent resistance and voltage source, which approximate the time-variant HUT at time step k. Their values are updated at each time step using current and voltage values at the previous time steps as follows: Req (k ) = (5) Veq (k ) = v2 (k 1)

a Ts where = b Ts 1 2 as follows:

b Ts 2 . They can be solved and = b Ts 1 2 1+

1

i1 (k 1) v2 (k 1) v2 (k ) = i (k 2) v (k 2) v (k 1) 2 1 2

(6)

More detailed information on the TFA-based information can be found in [6][7][9]. B. Decoupled Simulation of a DC Electrical Drive System The decoupled simulation of a DC electrical drive system is used to demonstrate the effectiveness of the TFA-based simulation/hardware interfacing scheme. Here, the HUT is comprised of a DC motor with an AC interface, while the ROS is comprised of a power supply and a transformer. The simulation/hardware interface is inserted between the transformer and the diode bridge, as shown in Fig. 9. The comparison of the simulation results between the original system and the decoupled system with the TFA-based interface is made in Fig. 10. The symbols used in the graphs are listed in Table 4. Fig. 10 shows the decoupled system with the TFA-based interface yields simulation results close to those from the original system.

(a) IHUT

(b) VHUT

Fig.9 VTB schematic of the decoupled DC electrical drive system TABLE 4 LIST OF SYMBOLS

(c) IR Fig.10 Comparison of the simulation results between the original system and the decoupled system with the TFA-based interface

V. HIGH BANDWIDTH HARDWARE FOR POWER INTERFACE In an HIL simulation, a hardware interface is required to achieve natural coupling between the actual power hardware and the simulated rest of the system. This interface must both deliver and absorb power so a key component of the hardware interface is a four-quadrant converter. The requirement that the interface seamlessly link the real and virtual worlds at the power interface introduces a set of problems related to sampling rate, delay, quantization and saturation. The unavoidable limitations of sampling rate and delay define the stability envelope of the hybrid system. In order to explore power system issues that are significant in the real world (e.g. stability, response to harmonics, or impact of active power quality controls), the power interface must have very high bandwidth. Obtaining such high bandwidth is straightforward with respect to sensing because very fast digitizers with low latency are readily available. However, it is generally very difficult to implement the power interface because of limits in the power converter bandwidth. The limitation in bandwidth

Symbol IHUT VHUT IR IHUT_org VHUT_tfa IR_org IR_tfa

Meaning Current going into the diode bridge Input voltage to the diode bridge Current through the resistor R Current going into the diode bridge in the original system Input voltage to the diode bridge in the decoupled system with the interface based on TFA Current through the resistor R in the original system Current through the resistor R in the decoupled system with the interface based on TFA

could be related to the control structure or to the switching frequency of the power components. Focusing on control issues, one option is the sliding mode control algorithm, which directly outputs the switching command, and then does not require a dedicated PWM unit. In terms of bandwidth, it is theoretically unlimited In this study, a prototype of the simulation/hardware interface is built and tested. This first prototype consists of a silicon H-Bridge inverter. In order to meet the bandwidth requirements, the platform is mostly digital and includes a minimal analog section composed of a fast A/D converter and a signal conditioning stage. The latter is based on high-speed operational amplifiers. Data acquisition and the fast control loop are implemented with a Memec Design Virtex II Pro FPGA Development Board with onboard 12-bit A/D channels. A discrete version of the sliding mode control is adopted as the control algorithm for the interface. This variable control structure is an adaptive controller that gives robust performance in the case of parameter variation and load disturbance. The control is nonlinear and the system is forced to slide along a predefined trajectory by a switching control algorithm. The controller detects the deviation of the actual trajectory from the reference trajectory and changes switching strategy to restore tracking [10]. Fig. 11 shows the general structure of the PHIL simulation platform. At each simulation step, the current in the HUT is sampled and sent to the VTB-RT through an A/D converter. Based on this current value, the VTB-RT approximates the dynamics of the HUT and solves the software model of the ROS. The simulation result is sent to the FPGA in digital form. The FPGA then controls the H-Bridge inverter using the simulation result from the VTB-RT as the reference. Finally, the output of the H-Bridge inverter is sent to the HUT.

TFA enables the natural coupling at the interfacing point; the high bandwidth hardware power interface realized the virtual power exchange between the HUT and the ROS. The output of this study greatly increases the applicability of the HIL methodology. VII. ACKNOWLEDGMENT This work was supported in part by the U.S. Office of Naval Research under Grant N00014-02-1-0623 and N0001403-1-0434. VIII. REFERENCES
M. Lansdaal, L. Lewis, "Boeing's 777 Systems Integration Lab," in IEEE Instrumentation & Measurement Magazine, pp:13-18, Sept., 2000. [2] P. Baracos, G. Murere, C.A.Rabbath, W. Jin, Enabling pc-based HIL simulation for automotive applications, in IEEE International Electric Machines and Drives Conference, pp: 721 729, 2001. [3] S. Abourida, C. Defour, J. Belanger, G. Murere, N. Lechevin, B. Yu, Real-time PC-based simulator of electric systems and drives, in IEEE APEC, pp. 433-438, 2002. [4] L. Bin, W. McKay, S. Lentijo, A. Monti, X. Wu, and R. Dougal, The Real Time extension of the Virtual Test Bed, presented at Huntsville Simulation Conference 2002, Oct. 2002, Huntsville, AL. [5] S.Y.R. Hui and C. Christopoulos. Numerical modeling of power circuits using transmission-line modeling, in Proc. IEEE on Power Electronics, vol. 6, No. 3, pp. 36-644, Oct. 1991. [6] X. Wu, S. Lentijo, A. Monti, A Novel Interface for Power-HardwareIn-the-Loop Simulation, presented at the Ninth IEEE Workshop on Computers in Power Electronics (COMPEL04), University of Illinois at Urbana-Champaign, Aug. 15-18, 2004, Urbana-Champaign. [7] X. Wu, S. Lentijo, A. Deshmuk, A. Monti, F. Ponci, Design and Implementation of a Power-Hardware in the Loop Interface: a NonLinear Load Case Study, presented at APEC 2005, Mar. 610, 2005, Austin, TX. [8] H. Figueroa, Novel Interface Based on the Firing Signal Averaging Method for Accurate Hardware-In-The-Loop Testing of Digital Controllers for Power Electronics Applications, Ph.D. dissertation, Dept. Electrical Engineering., Univ. of South Carolina, Columbia, 2005. [9] X. Wu, "Methods for partitioning the system and performance evaluation in power-hardware-in-the-loop simulations," Ph.D. dissertation, Dept. Electrical Engineering., Univ. of South Carolina, Columbia, 2005. [10] M. Carpita, M. Marchesoni, Experimental Study of a Power Conditioning System Using Sliding Mode Control, in IEEE Trans. Power Electronics, vol 11, no. 5, pp. 731-742, September 1996. [1]

IX. BIOGRAPHIES
Antonello Monti (SM2002) received his M.S. degree in Electrical Engineering from the "Politecnico di Milano" in 1989 and his Ph.D still from the "Politecnico di Milano" in 1994. From 1990 to 1994 he was with the research laboratory of Ansaldo Industria of Milan: he was responsible of the design of the digital control of a large power cycloconverter drive. In 1995 he joined the Department of Electrical Engineering of "Politecnico di Milano" as Assistant Professor. Starting from August 2000 he is Associate Professor at the Department of Electrical Engineering at the University of South Carolina. He is serving as chair of the IEEE Power Electronics Committee on Simulation, Modeling and Control and as Associate Editor of the IEEE Transaction on Automation Science and Engineering. He is author or co-author of more than 150 papers in the field of Power Electronics and Electrical Drives.

Fig.11 Structure of the HIL simulation system with natural coupling between the ROS and the HUT

VI. CONCLUSIONS This paper addresses the interface issues in HIL simulations from three different angles: the signal interface based on FSA method greatly improves the accuracy of the HIL simulations of fast-switching events without increasing the requirements on time step; the novel algorithm based on

Hernan Figueroa received the B.S.E.E. from the Universidad Nacional de Ingeniera, Lima, Per, in December 2000. He worked as a young design engineer in a major Peruvian telecommunications company. In 2001 joined the University of South Carolina and received his Ph.D degree in May, 2005. His research focuses on the realization of a novel and accurate hardware-in-the-loop platform for rapid prototyping and testing of digital controllers for power electronics systems. Santiago Lentijo received the B.S degree in Electronics Engineering from Javeriana University, Cali, Colombia in 1998 and the M.S in Electrical Engineering from the University of South Carolina in 2003, where currently he is a PhD candidate. His research area focuses on testing procedures for virtual prototyping including Processor-in-the-loop (PIL) and Power-Hardware-in-the-loop (PHIL). Xin Wu received her B.S degree in Electrical Engineering from Huazhong University of Science and Technology in August, 1999. She entered the Ph.D. program at the department of electrical engineering, University of South Carolina (USC), and worked as a research assistant for the Virtual Test Bed (VTB) project. She received her Ph.D degree from the University of South Carolina in May, 2005. Her interest of research is real-time hardware-in-the-loop and power-hardware-in-the-loop simulations. Roger Dougal joined the faculty at the University of South Carolina in 1983 immediately after earning the Ph.D. in electrical engineering at Texas Tech University. Dr. Dougal has received the Samuel Litman Distinguished Professor of Engineering award, has been honored as a Carolina Research Professor. Professor Dougal is Director of the Virtual Test Bed project, a multi-disciplinary, multiuniversity effort to develop a comprehensive simulation and virtual prototyping environment for advanced power sources and systems, integrating power electronics, electromechanics, electrochemistry, and controls into a common testbed. The VTB is unique in allowing the simulation of multi-disciplinary systems by importing models from discipline specific source languages to a common workspace. In addition to Modeling and Simulation, Prof. Dougals expertise includes power electronics, physical electronics, and electrochemical power sources.