Fully Integrated CMOS GPS Receiver for System-on-Chip Solutions

Christian Grewing, Bo Bokinge, Wenche Einerman, Anders Emericks, Detlev Theil, and Stefan van Waasen Infineon Technologies Sweden AB, Design Center Stockholm, 16481 Kista, Sweden
Abstract A CMOS receiver for the Global Positioning System (GPS) is presented. It is designed in a 0.13m standard CMOS process and is fully integrated for the needs of a System-on-Chip (SoC) solution for GPS and Assisted GPS (A-GPS). It provides the needed frequency conversion, gain and filtering for GPS signals without any other external components than those required for matching and decoupling. The receiver includes the local oscillator (LO) signal generation and all needed supply voltage regulators. The achieved noise figure (NF) of the receiver is 1.8dB, including losses of external filtering for blocking requirements. Index Terms Amplifier noise, analog systems, CMOS analog integrated circuits, global positioning system, receivers.

Special care must be taken to minimize coupling of digital noise into the receiver chain. In this paper a GPS analog receiver in a 0.13m standard CMOS is presented, which is designed for the use in a SoC GPS unit. After presenting a system overview, the different parts of the receiver are described in detail. The results of the performance measurements are presented before concluding the article. II. CIRCUIT ARCHITECTURE

I. INTRODUCTION In satellite navigation systems, such as the global positioning system (GPS), the signal strength at the antenna is below the thermal noise floor. Nevertheless, due to correlation techniques in the baseband section of the GPS unit and the use of auxiliary data in the Assisted GPS (A-GPS) system, very low signal levels can be used to achieve a position fix. Sensitivities of the system down to a signal power of -160dBm are sufficient even for locating in buildings and urban canyons [1] [2]. To achieve these sensitivity levels, the analog receiver chain needs to have a noise figure (NF) lower than 2dB. The A-GPS system is used in handhelds in which other communication systems, e.g. GSM or UMTS are located. For this reason the blocking requirements of the GPS receiver are a main challenge. Two external filters are required to avoid system degradation due to blocking, therefore special portioning of the receiver front-end is needed. The receiver has to be designed to serve both linearity and noise requirements. The development of handhelds with more and more integrated services and standards urges very small area use for the GPS unit. This is solved by utilizing a Systemon-Chip (SoC) practice. The SoC solution also reduces the current consumption, because a lower number of signal drivers are needed. The SoC integration of the baseband section with the receiver and all analog parts requires the development of all the receiver parts in standard CMOS.

Fi

lte

Analog Receiver

V Re olta gu ge la to r

1.8V Reg 1.5V Reg

f/2

Interfaces

Fig. 1. Block-diagram of the GPS receiver, showing the RF and analog parts of the SoC solution.

Fig. 1 shows an overview of the analog GPS receiver. It consists of a front-end that is designed for the use of two external filters, a down-conversion mixer to a low intermediate frequency (low-IF), and the IF bandpass filtering at 2MHz. An amplifier with automated gain control (AGC) provides the needed gain to achieve an

r Lo O cal s G cilla en to er r at io n
frac-N PLL w/ Loop Filter

iv i

de

IQ A M mpl i P xer ifier Fi olyp lte h r ase PG A ,A G C A D C

A/D

1s

tL

optimum amplitude for the digital to analog signal conversion in the ADC. All needed supply regulators for the use of variable power supply schemes are integrated. The receiver makes use of two voltage supply levels: the analog parts are supplied by 1.8V, the digital parts for the AGC and synthesizer are supplied by 1.5V. The complete receiver draws less than 50mA during operation. The synthesizer of the local oscillator (LO) for the mixer makes use of a sigma-delta fractional-N phase locked loop ( frac-N PLL) to serve all reference clocks between 10 and 40MHz. The voltage controlled oscillator (VCO) and the loop filter of the PLL are completely integrated. A chip photograph of the receiver is shown in Fig. 2, exhibiting two on chip coils for the LNA and the VCO.

driving stage is used for impedance transformation, the output is designed to be matched to the 50 input impedance of the second filter. The second filter provides a differential output with a matching network to the mixer input. Fig. 3 gives the details about this implementation.
Matching Network

LD L4 T2 50 L1 T1 L2 LS R1

Filter

L3

GPS - Receiver
Fig. 3. Simplified schematic of the LNA including matching elements.

B. Downconversion Mixer The mixer comes with an input amplifier, a double balanced I/Q phase Gilbert mixer and a post mixing amplifier. The differential input of the input amplifier is matched to the external filter output by means of the external matching circuitry. The input amplifier and all following circuitry in the receiver chain are differential for high robustness against noise and distortions both from digital and from analog parts. Especially for the mixer the differential design is necessary in order to minimize the LO feedthrough. The input amplifier is realized as a coilless amplifier with a resistive and capacitive feedback to set the input impedance for optimal performance. Post mixer amplifiers provide additional gain in order to drive the following integrated bandpass filter. The synthesizer consists of a VCO at two times of the LO frequency. The frequency is divided by a differential flip-flop in common source logic (SCL), which provides the I/Q LO signals with high accuracy in phase relation. C. Low Intermediate Frequency Signal Path The bandpass filter is realized as a three pole polyphase filter to suppress the noise contribution in the image frequency band. Additionally out of band noise of interferers inside the passband of the external filters would reduce the signal to noise ratio. The programmable gain amplifier (PGA) provides additional gain for an optimal amplitude for the 3-bit analog to digital converter (ADC) and is controlled by an on-chip AGC algorithm.

Fig. 2. Chip photograph of the analog GPS receiver in a 0.13m standard CMOS process.

A. Low Noise Amplifier The LNA needs to provide a noise figure and gain which are sufficiently low for the overall low noise figure of the receiver. High linearity is needed to avoid performance degradation in presence of a blocking signal. Two external filters are required to achieve the needed blocking performance for the receiver. The LNA is situated in between these external filters in order to avoid a too high overall noise figure due to the insertion loss of the second filter. Thus it is necessary that the input and output of the LNA is 50 matched. The LNA is designed single ended for low noise figure and low current consumption. A common source configuration with an inductive source degeneration is used. The inductance is provided by a bond wire to ground. A cascode transistor is used for decoupling, and an on-chip coil serves as the load of the stage. Since no output

III. PERFORMANCE The measured scattering matrix of the LNA including matching networks is presented in Fig. 4. The transmission coefficient S21 shows a maximum of 16.7dB at the GPS frequency. Whereas the input reflection coefficient S11 shows a low magnitude due to optimum noise match, the output reflection coefficient is sufficiently matched. Although the backwards transmission coefficient S12 is of high magnitude, the stability of the amplifier was analyzed in detail. Calculating from the scattering matrix the stability factors K (1) and (2) are shown in [3] [4], respectively.
K 1 S11 S 22 S12 S 21
2

maximum gain. The receiver NF degrades about NF = 0.3dB. This degradation is acceptable for the overall NF for a SoC solution. The NF for a GPS application can be assumed to be NF = 2dB taking losses from the first external filter into account and therefore suitable for the desired sensitivity level for an A-GPS system. These results are better compared to recently reported data for integrate CMOS GPS receivers [5] - [7].
S21
20 dB

Av

8 7 6 5 4 3 2 1 0

Transmission coefficient S21 Gain Av

2 S12 S 21
2

5 0 -5

1 S 22 S
* 11

S11

(2)
S12 S 21

-10 -15 -20

S11 S 22

S12 S 21

0.5

1.5

2.5

3.5

GHz

The frequency response of both stability factors is presented in Fig. 5 together with the transmission coefficient S21 and the voltage gain AV. It can be seen that the LNA is stable for the whole frequency range and provides a gain of 17dB at the desired frequency range.
S21 20 S11 S22 S12 0

Frequency f

Fig. 5. Measured S parameter S21, gain AV, and stability factors K, of the LNA, incl. input and output matching.

dB

dB

S-Parameter S11, S21

-20

-10

-30

S-Parameter S12, S22

The linearity of the receiver is limited by the LNA due to the external filter and can be depicted from Fig. 6 for the three frequencies fGPS = 1575MHz, fGSM = 1710MHz and fGSM = 915MHz. It can be seen that the 1dBcompression points are -14dBm and -5dBm, respectively, which is sufficient to avoid performance degradation from the blockers that pass the first external filter.
Receiver
6

Receiver incl. 1st LNA

-20

-40

dB
-30 0.5 0.6 0.7 0.8 0.9 1 2 3 GHz 5 -50

w/ digital noise

Frequency

Noise figure NF

w/o digital noise

3

Fig. 4. Measured scattering parameters of the LNA including input and output matching networks.

w/ digital noise
2

The noise figure of the LNA was measured to 1.35dB. In Fig. 6 the noise figure of the receiver from the mixer input and from the LNA including the second external filter are shown. The NF was calculated by the measured SNR at the ADC output with and without noise contribution of the baseband. The NF of the receiver from the input of the LNA is 1.5dB and degrades by NF = 0.2dB in the frequency band that provides the

w/o digital noise

1 1.4 1.45 1.5 GHz 1.6

Frequency

Fig.6. Measured NF of the receiver with and without the LNA, respectively, comparing the influence of the digital noise.

Stability K,

S11

S 22

10

(1)

1575 MHz
15

1710 MHz

915 MHz

Interpolation

IV. CONCLUSIONS A completely integrated GPS receiver was presented which is designed for a SoC solution. With the chosen 0.13m standard CMOS technology and its few needed external components it is designed for a complete GPS and A-GPS integration. It was proven that the performance degradation due to digital noise coupling and heating is well within the needed range to achieve state of the art system performance. With its low noise figure and image reject low-IF filtering it provides the needed SNR for the correlation in the baseband for best in class sensitivities. It comes with all needed voltage regulators to allow a variety of power supply concepts and achieves low power consumption due to optimized circuit design. The most standard reference clock frequencies are supported due to the used frac-N synthesizers. ACKNOWLEDGEMENT The authors wish to acknowledge the work of Andr Hanke as an early RF system architect, and Burkhard Khn and Emir Herenda for their work on early evaluation chips. Additionally the authors wish to thank Peter Thellenberg and Sven-Arne Gudmundson for performing the receiver measurements. REFERENCES

dBm

Output Power Pout

-5

-10 -25

-20

-15

-10

-5

dBm

Input Power Pin

Fig. 7. Measured 1dB compression point of the LNA, incl. input and output matching network.
Passband
5 dB

Stopband

Transferfunction A(f)/Amax

-5 -10

Image
-15 -20 -25 -30 -35

Rejection

0.5

1.5

2.5

3.5

MHz

Frequency f

Fig. 8. Measured frequency behavior of the Low-IF polyphase filter, showing the image rejection.

On addition to the gain reduction of the LNA, the out of band noise of the blocker signal causes additional performance penalties. The noise in the GPS band cannot be avoided, but in order to lower the noise contribution from the image band a polyphase filter is used implemented as an active filter structure. The bandwidth of the filter is automatically adjusted for technology variations. The frequency characteristics of the third order filter are shown in Fig. 8, the rejection of the image band rejection in the GPS signal bandwith is higher than 20dB. The PGA consists of operational amplifiers with switchable resistive feedback to provide a gain range of 32dB with a gain step of 1dB. With maximum gain in the PGA the receiver provides an overall gain of 117dB for an optimal use of the 3-bit ADC.

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