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Fault Simulation F lt Si l ti
Virendra Singh
Indian I tit t f S i I di Institute of Science Bangalore virendra@computer.org E0 286: Test & Verification of SoC Design Lecture - 7
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Fault Simulation
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Simulation Defined
Definition: Simulation refers to modeling of a design, its function and performance. A software simulator is a computer program; an emulator is a hardware simulator. Simulation is used for design verification:
Validate assumptions Verify logic Verify performance (timing) Logic or switch level Timing Circuit Fault
Types of simulation:
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Computed responses
True-value simulation
Input stimuli
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Modeling Levels
Modeling level Function, behavior, RTL Logic Circuit description Programming language-like HDL Connectivity of Boolean gates, flip-flops and transistors Transistor size and connectivity, node capacitances Signal values 0, 1 0, 1, 0 1 X and Z Timing Clock boundary Zero delay Zero-delay unit-delay, multipledelay Zero-delay Application Architectural and functional verification Logic verification and test Logic verification g Timing verification Digital timing and analog g circuit verification
5
Switch S it h
0, 0 1 and X
Timing Circuit
g gy Transistor technology Analog voltage data, connectivity, node capacitances Tech. Data, active/ passive component connectivity Analog voltage, voltage current
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Event-driven simulation
Compiled-Code Algorithm
Step 1: Levelize combinational logic and encode in a compilable programming language Step 2: Initialize internal state variables (flipp ( p flops) Step 3: For each input vector Set i S t primary i input variables t i bl Repeat (until steady-state or max. iterations)
Execute compiled code
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Event-Driven Algorithm
Scheduled events Activity list
a =1 c =1
0 2
e =1 g =1
T Time sta ack
t=0 1 2 3 4 5 6 7 8
c=0
d, e
d=0 b =1 g
0 4 8
d = 1, e = 0
f, g
f =0 0
g=0
f=1
Time, t
g=1
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Determine
Fault coverage - fraction (or percentage) of modeled faults detected by test vectors y Set of undetected faults
Motivation
Determine test quality and in turn product quality Find undetected fault targets to improve tests
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Low
Test generator
Add vectors
Adequate q Stop
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Timing
Zero-delay Zero delay for combinational and synchronous circuits Mostly unit-delay for circuits with feedback
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Serial Algorithm
Algorithm: Simulate fault-free circuit and save responses. responses Repeat following steps for each fault in the fault list:
Modify netlist by injecting one fault Simulate modified netlist, vector by vector, comparing responses with saved responses If response differs, report fault detection and suspend simulation of remaining vectors
Advantages:
Easy to implement; needs only a true-value simulator, less memory Most faults, including analog faults, can be simulated
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Serial Algorithm
Disadvantage: Much repeated computation; CPU time prohibitive for VLSI circuits Alternative: Simulate many faults together
Test vectors Fault-free circuit Circuit with fault f1 Comparator Circuit with fault f2 Comparator Circuit with fault fn fn detected? f2 detected? Comparator f1 detected?
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a b
c s-a-0 detected
1 0 1
e
0 0 0 s-a-1 0 0 1
s-a-0
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Set theoretic Set-theoretic rules difficult to derive for nonnon Boolean gates Gate delays are difficult to use
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a b
1 1 {b0}
c d
e f
{b0 , d0}
{b0 , d0 , f1}
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U U
a0
1 0
b0
0 1
c0
0
1 1
e0
0
a b
c d
1 1 0
e
0
1 0
0 0
a0
0 1 0
b 0 0
1 0 1 1 1
0 0 1
c0
0 1 1
0 0 1
e0
0
0 1
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b0
0 1
d0
1 1
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f1
g
0
f1
d0
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Thank You
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