Group 1: 2 Points; 1 out of 3

1. All of the following are RAM characteristics except: <C>Volatile memory. <C+>not erasable memory. <C>it is Read-Write Memory. <C>Write and Read are accomplished by electrical signal. <C> Random Access Memory. 2. All of the following are ROM characteristics except: <C>it is not erasable. <C>it is Read Only Memory. <C>it is a Random Access Memory. <C>it is non-volatile. <C+> it is Read-Write memory 3. All of the following are flash memory characteristics Except: <C>it is read mostly memory. <C>it is non-volatile. <C>Write and Read are accomplished by electrical signal. <C>it is random access memory. <C+> Not erasable memory

Group 2: 2 Points; 1 out of 3

1. All of the following are DRAM characteristics except: <C>Data is stored as charges on capacitor. <C>it is a volatile memory. <C+>DRAM cell requires at least 6 transistors. <C>Refreshing is required to hold the data on the cell <C> DRAM is slower than SRAM.

2. All of the following are DRAM characteristics except: <C>it is a volatile memory. <C>Memory cell requires one transistor. <C>Refreshing is required to hold the data on the cell. <C+>Data is stored in flip-flops <C> DRAM is slower than SRAM. 3. All of the following are SRAM characteristics Except: <C>Each memory cell requires at least 6 transistors. <C>No refreshing is required to hold the data on the cell. <C+>SRAM is slower than DRAM. <C>it is a volatile memory. <C>Each memory cell represents a flip-flop.

Group 3: 2 Point; 1 out of 3

1. To build a (16M x 16) RAM, by using (512K x 8) RAM, the required decoder, and number of RAM chips are: <C+>5 to 32 decoder and 64 RAMs. <C>6 to 64 decoder and 32 RAMs. <C>5 to 32 decoder and 32 RAMs. <C>6 to 64 decoder and 64 RAMs <C>4 to 16 decoder and 128 RAMs. <C>6 to 64 decoder and 128 RAMs 2. To build a 128M x 16, by using 4Mx8 RAM, the required decoder, and number of RAM chips are: <C>5 to 32 decoder and 128 RAMs. <C>6 to 64 decoder and 128 RAMs. <C>7 to 128 decoder and 64 RAMs. <C+>5 to 32 decoder and 64 RAMs. <C>6 to 64 decoder and 256 RAMs. <C>6 to 64 decoder and 32 RAMs. 3. To build a (64M x 16), by using (4Mx4) RAM, the required decoder, and number of RAM chips are: <C>5 to 32 decoder and 32 RAMs. <C+>4 to 16 decoder and 64 RAMs. <C>6 to 64 decoder and 32 RAMs. <C>4 to 16 decoder and 32 RAMs. <C>8 to 64 decoder and 64 RAMs. <C>2 to 4 decoder and 127 RAMs.

Group 4: 2 Point; 1 out of 3

1. How many address pins, Data pins respectively are required in a Multiplexed Pins DRAM of size (4Mx4): <C> 12 , 4 <C> 14 , 8 <C> 10 , 5 <C+> 11 , 4 <C> 9 , 4 <C> 8 , 2 2. How many address pins, Data pins respectively are required in a Multiplexed Pins DRAM of size (16Mx4): <C+> 12 , 4 <C> 14 , 8 <C> 10 , 5 <C> 11 , 4 <C> 9 , 4 <C> 8 , 2 3. How many address pins, Data pins respectively are required in a Multiplexed Pins DRAM of size (1Mx4): <C> 12 , 4 <C> 14 , 8 <C+> 10 , 4 <C> 11 , 4 <C> 9 , 4 <C> 8 , 2

Group 5: 2 Point; 1 out of 3

1. What is the DRAM size results from adding one address pin to 32M x 16 Multiplexed Pins DRAM chip: <C> 64M x 32 <C> 64M x 16 <C>32M x 32 <C+>128M x 16 <C> 64M x 64 <C> 32M x 64 2. What is the DRAM size results from adding one address pin to 16M x 4 Multiplexed Pins DRAM chip: <C+> 64M x 4 <C>64M x 16 <C>32M x 32 <C>128M x 16 <C> 64M x 64 <C> 64M x 8 3. What is the DRAM size results from adding one address pin to 4M x 8 Multiplexed Pins DRAM chip: <C> 64M x 4 <C> 32M x 16 <C> 32M x 32 <C+>16M x 8 <C> 64M x 64 <C> 16M x 16

Group 6: 2 Point; 1 out of 3

1. Which one of the following addressing modes is used in instruction fetching: <C+> Relative Addressing. <C> Indirect address mode. <C> Base - register addressing. <C>Indexing. <C> Register indirect addressing mode. <C> Memory indirect addressing mode. 2. Which one of the following addressing modes is most suitable for fetching contiguous memory allocation data such as arrays or Vectors: <C> Relative Addressing. <C> Indirect address mode. <C> Immediate addressing. <C+>Indexing. <C> Register indirect addressing mode. <C> M emory indirect addressing mode. 3. Which one of the following addressing modes is most suitable for fetching data stored by a pointer, like int *P = &X where X is integer variable: <C> Relative Addressing. <C> Auto-indexing with increment. <C> Base - register addressing. <C>Indexing. <C+> Register indirect addressing mode. <C> Auto-indexing with decrement.

Group 7: 3 Point (1point x 3); 1 out of 3

1. Suppose a processor is using one address instructions with an accumulator. If Accumulator is initially loaded by value AB00h, what will be the contents of Accumulator after executing the following instructions with the corresponding addressing mode. Some of memory locations contents are given below: Word address Word contents 2000H 2001H 2001H 5000H 2002H 2003H 2003H 2001H a. LOADI # 2002H; Immediate Addressing <C+>2002H <C>2003H <C>2000H <C>AB00H <C> 2001H <C> 5000H b. LOAD 2001H; Direct Addressing <C>2001H <C+>5000H <C>AB00H <C>2003H <C> 2002H <C> 200H c. LOAD (2002H); Indirect Addressing <C>2002H <C>2003H <C+>2001H <C>5000H <C> 2000H <C> AB00H

2. Suppose a processor is using one address instructions with an accumulator. If Accumulator is initially loaded by value AB00h, what will be the contents of Accumulator after executing the following instructions with the corresponding addressing modes. Some of memory locations contents are given below: Word address 3000h 3001h 3002h 3003h Word contents 3001h A000h 3003h 3001h

a. LOADI # 3002h; Immediate Addressing <C+>3002h <C>3003h <C>A000h <C>3001h <C> AB00h <C>3003H b. LOAD 3001h; Direct Addressing <C>3001h <C+>A000h <C>AB00h <C>3003h <C>3002h <C> 3000h c. LOAD (3002h); Indirect Addressing <C>3002h <C>3003h <C+>3001h <C>A000h <C> AB00h <C> 3000h

3. Suppose a processor is using one address instructions with an accumulator. If Accumulator is initailly loaded by value AB00h, what will be the contens of Accumulator after executing the following instructions with the corresponding addressing modes. Some of memory locations contents are given below: Word address 5000h 5001h 5002h 5003h Word contents 5001h B000h 5003h 5001h

a. LOADI # 5002h; Immediate Addressing <C+>5002h <C>5003h <C>AB00h <C>B000h <C> 5001h <C>5000h b. LOAD 5001h; Direct Addressing <C>5001h <C+>B000h <C>AB00h <C>5003h <C> 5002h <C> 5004h c. LOAD (5002h); Indirect Addressing <C>5002h <C>2003h <C+>5001h <C>B000h <C> 5000h <C>AB00h

Group 8: 3 Point (1point x 3); 1 out of 3

1. Consider a computer system with a 16 bit processor. The contents of some locations of the main memory is shown below, starting at location 200h: 200h 201h 202h Load to AC 0200h Next instruction

3FF 0FFFh h 400h 1000h 401h 1001h 402h 1002h The first part of the first word indicates that this instruction loads a value into an accumulator. In addition to the Accumulator, assume there is only one general purpose register R1 and its contents is 400h. There is also a base register contains the value 100h. The value 0200h in location 201h may be part of the instruction. a. What is the effective address if address mode is PC relative: <C>202h <C>1002h <C+>402h <C>499h <C> 100h <C>300h b. What is the effective address if address mode is Base: <C>202h <C>100h <C>200h <C+>300h <C> 402h <C>202h c. What value is loaded into Accumulator if the address mode is direct register: <C+>400h <C>200h <C>1000h <C>700h <C> 300h <C>202h

2. Consider a 16 bit processor in which the following appears in main memory, starting at location 200h: 200h Load to AC 201h 0300h 202h Next instruction 4FF 0FFFh h 500h 1000h 501h 1001h 502h 1002h The first part of the first word indicates that this instruction loads a value into an accumulator. In addition to the Accumulator, assume there is only one general purpose register R1 and its contents is 502h. There is also a base register contains the value 100h. The value 0300h in location 201h may be part of the instruction. a. What is the effective address if address mode is PC relative: <C>402h <C>1002h <C+>502h <C>499h <C> 1002h <C>501h b. What is the effective address if address mode is Base: <C>202h <C>100h <C>300h <C+>400h <C> 402h <C> 499h c. What value is loaded into Accumulator if the address mode is direct register: <C+>502h <C>200h <C>300h <C>700h <C> 400h <C>402h

3. Consider a 16 bit processor in which the following appears in main memory, starting at location 200: 200h Load to AC 201h 0100h 202h Next instruction 2FF h 300h 301h 302h 0FFFh 1000h 1001h 1002h

The first part of the first word indicates that this instruction loads a value into an accumulator. In addition to the Accumulator, assume there is only one general purpose register R1 and its contents is 302h. There is also a base register contains the value 300h. The value 0100h in location 201h may be part of the instruction. a. What is the effective address if address mode is PC relative: <C>202h <C>1002h <C+>302h <C>2FFh. <C> 1002h <C>100h b. What is the effective address if address mode is Base: <C>1002h <C>100h <C>300h <C+>400h <C> 202h <C> 2FFh c. What value is loaded into Accumulator if the address mode is direct register: <C+>302h <C>202h <C>1002h <C>700h <C> 1002h <C>100h

Group 9: 3 Point; 1 out of 3

1. Suppose you have a program consisting of 21 instructions. It is required to run this program on a CPU which includes an instruction pipeline of 8 segments. The program does not include any branch instruction. The no. of clock cycles required to finish executing this program is equal to: <C>20 <C>8 <C>27 <C+> 28 <C>29 <C>160 2. Suppose you have a program consisting of 18 instructions. It is required to run this program on a CPU which includes an instruction pipeline of 10 segments. The program does not include any branch instruction. The no. of clock cycles required to finish executing this program is equal to: <C> 15 <C> 10 <C> 28 <C> 25 <C+> 27 <C> 150 3. Suppose you have a program consisting of 25 instructions. It is required to run this program on a CPU which includes an instruction pipeline of 6 segments. The program does not include any branch instruction. The no. of clock cycles required to finish executing this program is equal to: <C>23 <C>6 <C+>30 <C>25 <C>24 <C>138

Group 10: 4 Point; 1 out of 3

1. Given the following program code: I1 I2 I3 I4 I5 I6 I7 I8 I9 CMP JZ AND OR ADD SHR MUL ADD DIV R1, R2 I8 R4, R5, R6 R7, R8, R9 R10, R5, R8 R11, R3, R6 R12, R5, R8 R8, R6, R9 R6, R4, R7

Where the instructions: I1 CMP R1, R2 I2 JZ I8 results in branching to instruction I8 if the contents of registers R1 & R2 are equal. Assume the above code will be executed in a pipeline with the following segments: FI: Fetch Instruction DI: Decode Instruction CO: Calculate Operand FO: Fetch Operand EI: Execute Instruction WO: Write Operand If the contents of registers R1 and R2 are equal then the contents of the six segments of the pipeline at the 8th clock cycle are: FI <C> I7 <C> I8 <C> I8 <C> I9 <C> I9 <C+> I9 DI I6 I6 I8 I8 CO I5 I5 FO I4 I4 EI I3 I3 WO I2 I2 I2 I2 -

2. Given the following program code: I1 I2 I3 I4 I5 I6 I7 I8 I9 SUB CMP JNZ OR ADD SHR MUL ADD DIV R1, R2, R3 R4, R5 I9 R7, R8, R9 R10, R2, R8 R11, R3, R6 R12, R3, R8 R1, R6, R9 R4, R4, R8

Where the instructions: I2 CMP R4, R5 I3 JNZ I9 results in branching to instruction I9 if the contents of registers R4 & R5 are not equal. Assume the above code will be executed in a pipeline with the following segments: FI: Fetch Instruction DI: Decode Instruction CO: Calculate Operand FO: Fetch Operand EI: Execute Instruction WO: Write Operand If the contents of registers R4 and R5 are not equal then the contents of the six segments of the pipeline at the 8th clock cycle are: <C> <C> <C+> <C> <C> <C> FI I7 I9 I9 I8 I9 I9 DI I6 I7 I8 I8 CO I5 I6 FO I4 I5 EI I3 I4 WO I2 I3 I3 I3 I3 -

3. Given the following program code: I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 CMP JE SUB AND OR ADD SHR MUL ADD DIV R7, R8 I7 R1, R2, R3 R4, R5, R6 R7, R8, R9 R10, R5, R8 R11, R3, R6 R12, R5, R8 R1, R6, R9 R4, R4, R8

Where the instructions: I0 CMP R7, R8 I1 JE I7 results in branching to instruction I7 if the contents of registers R7 & R8 are equal. Assume the above code will be executed in a pipeline with the following segments: FI: Fetch Instruction DI: Decode Instruction CO: Calculate Operand FO: Fetch Operand EI: Execute Instruction WO: Write Operand If there is no data hazards or data dependencies then the contents of the six segments of the pipeline at the 9th clock cycle are: <C> <C> <C> <C> <C+> <C> FI I6 I7 I7 I8 I9 I7 DI I5 I6 I7 I8 CO I4 I5 I7 FO I3 I4 EI I2 I3 WO I1 I2 I1 -