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to:cdsdisk Disk_28 auto:cdsdisk Disk_29 auto:cdsdisk Disk_30 auto:cdsdisk Disk_31 auto:cdsdisk Disk_32 auto:cdsdisk Disk_33 auto Disk_34 auto:cdsdisk

Disk_35 auto:cdsdisk Disk_36 auto:cdsdisk Disk_37 auto:cdsdisk Disk_38 auto:cdsdisk Disk_39 auto:cdsdisk Disk_40 auto:cdsdisk c0t0d0s2 auto:sliced rootdisk c0t1d0s2 auto:sliced rootmir root@rcisn022:/etc > root@rcisn022:/etc > vxdg list NAME STATE rootdg enabled root@rcisn022:/etc > root@rcisn022:/etc > df -h Filesystem size /dev/vx/dsk/bootdg/rootvol 1.9G /dev/vx/dsk/bootdg/usr 3.8G /proc 0K mnttab 0K fd 0K swap 21G /dev/vx/dsk/bootdg/homevol 941M /dev/vx/dsk/bootdg/var 3.8G root@rcisn022:/etc > root@rcisn022:/etc > mount /etc ID

online rootdg rootdg

online online online online online error online online online online online online online online online

1303487308.50.rcisn022

used avail capacity Mounted on 1.4G 3.2G 0K 0K 0K 0K 233M 1.2G 465M 660M 0K 0K 0K 21G 651M 2.6G 76% 84% 0% 0% 0% 0% 27% 31% / /usr /proc /etc/mnttab /dev/fd /tmp /export/home /var

mount: mount point cannot be determined root@rcisn022:/etc > root@rcisn022:/etc > cat /vfstab cat: cannot open /vfstab root@rcisn022:/etc > root@rcisn022:/etc > cat vfstab #device device #to mount to fsck # fd /dev/fd fd /proc /proc proc /dev/vx/dsk/bootdg/swapvol g mount point no no FS type swap fsck pass mount mount at boot options

no

nologgin

/dev/vx/dsk/bootdg/rootvol /dev/vx/rdsk/bootdg/rootvol / ufs 1 no nologging /dev/vx/dsk/bootdg/usr /dev/vx/rdsk/bootdg/usr /usr ufs 1 no nologging /dev/vx/dsk/bootdg/var /dev/vx/rdsk/bootdg/var /var ufs 1 no nologging #/dev/dsk/c0t0d0s5 /dev/rdsk/c0t0d0s5 /export/home ufs 2 yes /dev/vx/dsk/bootdg/homevol /dev/vx/rdsk/bootdg/homevol /export/home ufs 2 yes nologging /dev/vx/dsk/apps/staging /dev/vx/rdsk/apps/staging /staging vxfs 2 yes swap /tmp tmpfs yes #/dev/vx/dsk/oracle/oraclelv /dev/vx/rdsk/oracle/oraclelv /opt/oracle vxfs - yes suid #/dev/vx/dsk/oracle/dbf01 /dev/vx/rdsk/oracle/dbf01 /oradata/fidop/dbf01 vxfs yes suid #/dev/vx/dsk/oracle/dbf02 /dev/vx/rdsk/oracle/dbf02 /oradata/fidop/dbf02 vxfs yes suid #/dev/vx/dsk/oracle/dbf03 /dev/vx/rdsk/oracle/dbf03 /oradata/fidop/dbf03 vxfs yes suid #/dev/vx/dsk/oracle/dbf04 /dev/vx/rdsk/oracle/dbf04 /oradata/fidop/dbf04 vxfs yes suid #/dev/vx/dsk/oracle/dbf05 /dev/vx/rdsk/oracle/dbf05 /oradata/fidop/dbf05 vxfs yes suid #/dev/vx/dsk/oracle/dbf06 /dev/vx/rdsk/oracle/dbf06 /oradata/fidop/dbf06 vxfs yes suid #/dev/vx/dsk/oracle/dbf07 /dev/vx/rdsk/oracle/dbf07 /oradata/fidop/dbf07 vxfs yes suid #/dev/vx/dsk/oracle/arclog /dev/vx/rdsk/oracle/arclog /oradata/fidop/arch vxfs yes suid "vfstab" 28 lines, 1843 characters /rdsk/apps/removemelv /tempdb vxfs - yes suid /dev/vx/dsk/apps/rdmftplv /dev/vx/rdsk/apps/rdmftplv /rdmftp vxfs - yes suid #NOTE: volume rootvol () encapsulated partition c0t0d0s0 #NOTE: volume swapvol () encapsulated partition c0t0d0s1 #NOTE: volume usr () encapsulated partition c0t0d0s3 #NOTE: volume var () encapsulated partition c0t0d0s4 root@rcisn022:/etc > root@rcisn022:/etc > vi vfstab #device device mount FS fsck mount mount #to mount to fsck point type pass at boot options # fd /dev/fd fd no /proc /proc proc no /dev/vx/dsk/bootdg/swapvol swap no nologgin g /dev/vx/dsk/bootdg/rootvol /dev/vx/rdsk/bootdg/rootvol / ufs 1 no nologging /dev/vx/dsk/bootdg/usr /dev/vx/rdsk/bootdg/usr /usr ufs nologging /dev/vx/dsk/bootdg/var /dev/vx/rdsk/bootdg/var /var ufs nologging #/dev/dsk/c0t0d0s5 /dev/rdsk/c0t0d0s5 /export/home yes #/dev/vx/dsk/bootdg/homevol /dev/vx/rdsk/bootdg/homevol ufs 2 yes nologging #/dev/vx/dsk/apps/staging /dev/vx/rdsk/apps/staging 1 1 ufs no no 2

/export/home /staging

vxfs 2 yes swap /tmp tmpfs yes #/dev/vx/dsk/oracle/oraclelv /dev/vx/rdsk/oracle/oraclelv /opt/oracle vxfs - yes suid #/dev/vx/dsk/oracle/dbf01 /dev/vx/rdsk/oracle/dbf01 /oradata/fidop/dbf01 vxfs yes suid #/dev/vx/dsk/oracle/dbf02 /dev/vx/rdsk/oracle/dbf02 /oradata/fidop/dbf02 vxfs yes suid #/dev/vx/dsk/oracle/dbf03 /dev/vx/rdsk/oracle/dbf03 /oradata/fidop/dbf03 vxfs yes suid #/dev/vx/dsk/oracle/dbf04 /dev/vx/rdsk/oracle/dbf04 /oradata/fidop/dbf04 vxfs yes suid #/dev/vx/dsk/oracle/dbf05 /dev/vx/rdsk/oracle/dbf05 /oradata/fidop/dbf05 vxfs yes suid @ "vfstab" 28 lines, 1845 characters root@rcisn022:/etc > root@rcisn022:/etc > who -r . run-level 3 Nov 11 06:57 root@rcisn022:/etc > root@rcisn022:/etc > init 6 root@rcisn022:/etc > root@rcisn022:/etc > fsck -y /dev/vx/dsk/bootdg/rootvol IS CURRENTLY MOUNTED READ/WRITE. CONTINUE? yes ** /dev/vx/dsk/bootdg/rootvol ** Currently Mounted on / ** Phase 1 - Check Blocks and Sizes ** Phase 2 - Check Pathnames ** Phase 3a - Check Connectivity ** Phase 3b - Verify Shadows/ACLs ** Phase 4 - Check Reference Counts ** Phase 5 - Check Cylinder Groups FILESYSTEM MAY STILL BE INCONSISTENT. 20924 files, 1449248 used, 535795 free (14867 frags, 65116 blocks, 0.7% fragment ation) ***** PLEASE RERUN FSCK ON UNMOUNTED FILE SYSTEM ***** /dev/vx/dsk/bootdg/usr IS CURRENTLY MOUNTED READ/WRITE. CONTINUE? yes ** /dev/vx/dsk/bootdg/usr ** Currently Mounted on /usr ** Phase 1 - Check Blocks and Sizes ** Phase 2 - Check Pathnames ** Phase 3a - Check Connectivity ** Phase 3b - Verify Shadows/ACLs ** Phase 4 - Check Reference Counts ** Phase 5 - Check Cylinder Groups FILESYSTEM MAY STILL BE INCONSISTENT. 85030 files, 3316338 used, 715804 free (61636 frags, 81771 blocks, 1.5% fragment ation) 3 0 S

***** PLEASE RERUN FSCK ON UNMOUNTED FILE SYSTEM ***** /dev/vx/dsk/bootdg/var IS CURRENTLY MOUNTED READ/WRITE. CONTINUE? yes ** /dev/vx/dsk/bootdg/var ** Currently Mounted on /var ** Phase 1 - Check Blocks and Sizes ** Phase 2 - Check Pathnames ** Phase 3a - Check Connectivity ** Phase 3b - Verify Shadows/ACLs ** Phase 4 - Check Reference Counts ** Phase 5 - Check Cylinder Groups FILESYSTEM MAY STILL BE INCONSISTENT. 28788 files, 1217819 used, 2814323 free (12603 frags, 350215 blocks, 0.3% fragme ntation) ***** PLEASE RERUN FSCK ON UNMOUNTED FILE SYSTEM ***** root@rcisn022:/etc > root@rcisn022:/etc > exit resuming system initialization mount: /dev/vx/dsk/bootdg/var is already mounted, /var is busy, or the allowable number of mount points has been exceeded VxVM vxvm-startup2 INFO V-5-2-503 VxVM general startup... dumpadm: no swap devices could be configured as the dump device The system is coming up. Please wait. checking vxfs filesystems Running parallel replay fsck ... /dev/vx/rdsk/apps/rdmftplv:log replay in progress /dev/vx/rdsk/apps/removemelv:log replay in progress /dev/vx/rdsk/apps/rdmftplv:replay complete - marking super-block as CLEAN /dev/vx/rdsk/apps/removemelv:replay complete - marking super-block as CLEAN mount: /tmp is already mounted, swap is busy, or the allowable number of mount points has been exceeded panic[cpu8]/thread=300079a6320: alloccgblk: can't find blk in cyl, pos:0, i:284, fs:/var bno: 6e7 000002a1006d6fb0 ufs:ufs_fault_v+e0 (300079cfe18, 151b960, 2a1006d71a0, 2805ec0, b19c0, 0) %l0-3: 0000000000000000 000000000151b960 0000000001507e30 000002a1006d7aa8 %l4-7: 0000030008a0f350 0000030008a0f400 0000030007a3d430 0000030007a3d590 000002a1006d7060 ufs:ufs_fault+1c (300079cfe18, 151b960, 0, 11c, 3001242e0d4, 6e 7) %l0-3: 0000030005c878d8 00000300162c8620 00000000000b19c0 000001130001a1f9 %l4-7: 0000000000000000 0000030005c87908 00000300162c86d0 0000000000001000 000002a1006d7110 ufs:alloccgblk+4bc (6e7, 90000, 803, 11c, 11c, 3001242e560) %l0-3: 0000030008a0f350 000003001242e000 0000030012e9e568 0000030012e9e000 %l4-7: 00000300162c8620 0000030008a0f350 0000000000004000 0000000000000000 000002a1006d71c0 ufs:alloccg+158 (7, 70, 300162c8620, 30008a0f400, 2000, ff00) %l0-3: 0000030012e9e568 000000000005c948 000003001242e000 0000030012e9e000 %l4-7: 0000000000002000 0000030008a0f350 0000000000000007 0000030007a3d430 000002a1006d7270 ufs:hashalloc+2c (30007a3d430, 7, 5c948, 2000, 1196dac, 2a1006d 73d0) %l0-3: 0000000000000007 00000300162c8540 000003001242e000 0000000000002000 %l4-7: 0000000000000000 0000000001196dac 0000030007a3d430 0000000000001000 000002a1006d7320 ufs:alloc+154 (10, 0, 3001242e000, 2a1006d76e0, 30000dd7f28, 10

0314a40) %l0-3: 0000000000002000 000000000005c948 0000030008a0f350 0000030007a3d430 %l4-7: 000000000005c948 0000000000000000 0000000000000000 0000000000000000 000002a1006d73e0 ufs:bmap_write+c40 (45, 0, 0, 5c948, 2000, 0) %l0-3: 0000000000006000 0000030007a3d430 0000000000002000 000003001242e000 %l4-7: 0000000000000000 0000030008a0f350 0000000000000003 0000000000000051 000002a1006d76f0 ufs:wrip+428 (0, 0, 8, 30000dd7f28, 105d400, 0) %l0-3: 0000000000000005 0000030007a3d430 0000000000000005 000002a1006d7aa8 %l4-7: 0000030008a0f350 000002a7ca828000 0000030008a0f398 0000000000000001 000002a1006d7920 ufs:ufs_write+480 (30007a3d598, 30007a3d5e8, 151ac00, 151ac00, %l0-3: 0000030008a0f398 0000030008a0f350 0000000000000008 000002a1006d7aa8 %l4-7: 0000000000000000 0000030000dd7f28 0000030007a3d430 0000030007a3d590 000002a1006d79f0 genunix:write+26c (1, 1b, 1e9, 1, 9, 100345d60) %l0-3: 00000000011a6894 0000030007a3d4d0 00000000000001e9 0000000000000000 %l4-7: 0000000000000001 00000000000001e9 00000300071fb380 000000000000210b syncing file systems...Nov 11 07:37:04 sc6800 Domain-C.SC: Active - Panicking [1] 17 [1] 8 [1] 4 [1] 4 [1] 4 [1] 4 [1] 4 [1] 4 [1] 4 [1] 4 [1] 4 [1] 4 [1] 4 co mpleted) skipping system dump - no dump device configured rebooting... Resetting ... Nov 11 07:37:50 sc6800 Domain-C.SC: Active - Panicking Nov 11 07:37:51 sc6800 Domain-C.SC: POST after panic - using diag-level=quick. Powering boards off ... Powering boards on ... Testing CPU Boards ... cpuAB: All agents not usable {/N0/SB0/P2} Running CPU POR and Set Clocks {/N0/SB0/P3} Running CPU POR and Set Clocks {/N0/SB0/P2} @(#) lpost 5.20.5 2007/02/07 13:53 {/N0/SB0/P3} @(#) lpost 5.20.5 2007/02/07 13:53 {/N0/SB0/P2} Copyright 2007 Sun Microsystems, Inc. All rights reserved. {/N0/SB0/P3} Copyright 2007 Sun Microsystems, Inc. All rights reserved. {/N0/SB0/P2} Use is subject to license terms. {/N0/SB0/P3} Use is subject to license terms. {/N0/SB2/P0} Running CPU POR and Set Clocks {/N0/SB2/P2} Running CPU POR and Set Clocks {/N0/SB2/P3} Running CPU POR and Set Clocks {/N0/SB2/P1} Running CPU POR and Set Clocks {/N0/SB2/P0} @(#) lpost 5.14.6 2003/06/24 21:40 {/N0/SB2/P1} @(#) lpost 5.14.6 2003/06/24 21:40 {/N0/SB2/P0} Copyright 2001-2003 Sun Microsystems, Inc. All rights reserved. {/N0/SB2/P1} Copyright 2001-2003 Sun Microsystems, Inc. All rights reserved. {/N0/SB2/P2} @(#) lpost 5.14.6 2003/06/24 21:40 {/N0/SB2/P3} @(#) lpost 5.14.6 2003/06/24 21:40 {/N0/SB2/P2} Copyright 2001-2003 Sun Microsystems, Inc. All rights reserved. {/N0/SB2/P3} Copyright 2001-2003 Sun Microsystems, Inc. All rights reserved. {/N0/SB2/P2} Use is subject to license terms. {/N0/SB2/P3} Use is subject to license terms. {/N0/SB2/P0} Use is subject to license terms. {/N0/SB2/P1} Use is subject to license terms. {/N0/SB0/P2} Running Basic CPU {/N0/SB0/P3} Running Basic CPU {/N0/SB0/P2} Subtest: Setting Fireplane Config Registers for aid 0x2 {/N0/SB0/P3} Subtest: Setting Fireplane Config Registers for aid 0x3 {/N0/SB0/P2} Subtest: Display CPU Version, frequency {/N0/SB0/P3} Subtest: Display CPU Version, frequency {/N0/SB0/P2} Version register = 003e0015.23000507

{/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB0/P2} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB2/P2} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB0/P3} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB0/P2} {/N0/SB0/P3}

Version register = 003e0015.23000507 CPU features = 0000225f.004205ff CPU features = 0000225f.004205ff Ecache Control Register 00000000.07c35400 Ecache Control Register 00000000.07c35400 Cpu/System ratio = 7, cpu actual frequency = 1050 Cpu/System ratio = 7, cpu actual frequency = 1050 @(#) lpost 5.20.5 2007/02/07 13:53 @(#) lpost 5.20.5 2007/02/07 13:53 Copyright 2007 Sun Microsystems, Inc. All rights reserved. Copyright 2007 Sun Microsystems, Inc. All rights reserved. Use is subject to license terms. Use is subject to license terms. Subtest: I-Cache RAM Test Subtest: I-Cache RAM Test Subtest: I-Cache TAGS Test Subtest: I-Cache TAGS Test Subtest: I-Cache Valid/Predict TAGS Test Subtest: I-Cache Valid/Predict TAGS Test Subtest: I-Cache Snoop Tags Test Subtest: I-Cache Snoop Tags Test Running Basic CPU Running Basic CPU Subtest: Setting Fireplane Config Registers for aid 0xa Subtest: Setting Fireplane Config Registers for aid 0xb Subtest: Display CPU Version, frequency Subtest: Display CPU Version, frequency Version register = 003e0015.21000507 Version register = 003e0015.21000507 Running Basic CPU Running Basic CPU Subtest: Setting Fireplane Config Registers for aid 0x8 Subtest: Setting Fireplane Config Registers for aid 0x9 Subtest: Display CPU Version, frequency Subtest: Display CPU Version, frequency Cpu/System ratio = 6, cpu actual frequency = 900 Cpu/System ratio = 6, cpu actual frequency = 900 Version register = 003e0015.21000507 Version register = 003e0015.21000507 Subtest: I-Cache Branch Predict Array Test @(#) lpost 5.14.6 2003/06/24 21:40 @(#) lpost 5.14.6 2003/06/24 21:40 Cpu/System ratio = 6, cpu actual frequency = 900 Cpu/System ratio = 6, cpu actual frequency = 900 Subtest: I-Cache Branch Predict Array Test Running Test Large Tag Arrays and Enable MMU Running Test Large Tag Arrays and Enable MMU Subtest: I-Cache Initialization Subtest: I-Cache Initialization Subtest: D-Cache RAM Test Subtest: D-Cache RAM Test Subtest: D-Cache TAGS Test Copyright 2001-2003 Sun Microsystems, Inc. All rights reserved. @(#) lpost 5.14.6 2003/06/24 21:40 @(#) lpost 5.14.6 2003/06/24 21:40 Subtest: D-Cache TAGS Test Copyright 2001-2003 Sun Microsystems, Inc. All rights reserved. Copyright 2001-2003 Sun Microsystems, Inc. All rights reserved. Subtest: D-Cache MicroTags Test Subtest: D-Cache MicroTags Test

{/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P1} {/N0/SB0/P2} {/N0/SB2/P2} {/N0/SB0/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P0} {/N0/SB2/P2} {/N0/SB2/P1} {/N0/SB2/P3} {/N0/SB0/P2} {/N0/SB2/P0} {/N0/SB2/P2} {/N0/SB2/P1} {/N0/SB0/P3} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P1} {/N0/SB0/P2} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB0/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB0/P2} {/N0/SB2/P2} {/N0/SB0/P3} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB0/P2} {/N0/SB2/P2} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB0/P3} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2}

Use is subject to license terms. Use is subject to license terms. Copyright 2001-2003 Sun Microsystems, Inc. All rights reserved. Subtest: D-Cache SnoopTags Test Subtest: I-Cache RAM Test Subtest: D-Cache SnoopTags Test Use is subject to license terms. Use is subject to license terms. Subtest: I-Cache RAM Test Subtest: D-Cache Initialization Subtest: D-Cache Initialization Subtest: I-Cache RAM Test Subtest: I-Cache RAM Test Subtest: I-Cache TAGS Test Subtest: I-Cache TAGS Test Subtest: W-Cache RAM Test Subtest: W-Cache RAM Test Subtest: I-Cache TAGS Test Subtest: I-Cache Valid/Predict TAGS Test Subtest: I-Cache TAGS Test Subtest: I-Cache Valid/Predict TAGS Test Subtest: W-Cache TAGS Test Subtest: I-Cache Valid/Predict TAGS Test Subtest: I-Cache Snoop Tags Test Subtest: I-Cache Valid/Predict TAGS Test Subtest: W-Cache TAGS Test Subtest: I-Cache Snoop Tags Test Subtest: I-Cache Snoop Tags Test Subtest: W-Cache Valid bit Test Subtest: W-Cache Valid bit Test Subtest: I-Cache Branch Predict Array Test Subtest: I-Cache Branch Predict Array Test Subtest: I-Cache Snoop Tags Test Subtest: W-Cache Bank valid bit Test Subtest: I-Cache Branch Predict Array Test Subtest: I-Cache Branch Predict Array Test Subtest: W-Cache Bank valid bit Test Subtest: I-Cache Initialization Subtest: I-Cache Initialization Subtest: W-Cache SnoopTAGS Test Subtest: D-Cache RAM Test Subtest: W-Cache SnoopTAGS Test Subtest: D-Cache RAM Test Subtest: I-Cache Initialization Subtest: I-Cache Initialization Subtest: W-Cache Initialization Subtest: D-Cache TAGS Test Subtest: D-Cache RAM Test Subtest: D-Cache RAM Test Subtest: W-Cache Initialization Subtest: D-Cache TAGS Test Subtest: D-Cache TAGS Test Subtest: D-Cache TAGS Test Subtest: D-Cache MicroTags Test Subtest: D-Cache MicroTags Test Subtest: P-Cache RAM Test Subtest: P-Cache RAM Test Subtest: D-Cache MicroTags Test Subtest: D-Cache MicroTags Test Subtest: D-Cache SnoopTags Test

{/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB0/P2} {/N0/SB2/P2} {/N0/SB0/P3} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P1} {/N0/SB2/P0} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB0/P2} {/N0/SB2/P0} {/N0/SB2/P2} {/N0/SB2/P1} {/N0/SB2/P3} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P2} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB0/P2}

Subtest: D-Cache SnoopTags Test Subtest: D-Cache SnoopTags Test Subtest: D-Cache SnoopTags Test Subtest: P-Cache TAGS Test Subtest: D-Cache Initialization Subtest: P-Cache TAGS Test Subtest: D-Cache Initialization Subtest: D-Cache Initialization Subtest: D-Cache Initialization Subtest: P-Cache SnoopTags Test Subtest: P-Cache SnoopTags Test Running FPU Tests Running FPU Tests Subtest: P-Cache Status Data Test Subtest: W-Cache RAM Test Subtest: W-Cache RAM Test Subtest: W-Cache RAM Test Subtest: P-Cache Status Data Test Subtest: P-Cache Initialization Subtest: P-Cache Initialization Subtest: Branch Prediction Initialization Subtest: Branch Prediction Initialization Subtest: W-Cache RAM Test Subtest: W-Cache TAGS Test Subtest: W-Cache TAGS Test Subtest: W-Cache TAGS Test Subtest: IMMU Registers Access Subtest: IMMU Registers Access Subtest: W-Cache TAGS Test Subtest: W-Cache Valid bit Test Subtest: W-Cache Valid bit Test Subtest: DMMU Registers Access Subtest: W-Cache Valid bit Test Subtest: W-Cache Bank valid bit Test Subtest: W-Cache Valid bit Test Subtest: W-Cache Bank valid bit Test Subtest: DMMU Registers Access Running Basic Ecache Running Basic Ecache Subtest: 4M DTLB RAM Test Subtest: 4M DTLB RAM Test Subtest: 8K DTLB RAM Test Subtest: 8K DTLB RAM Test Subtest: 4M DTLB TAG Test Subtest: 4M DTLB TAG Test Subtest: W-Cache SnoopTAGS Test Subtest: W-Cache SnoopTAGS Test Subtest: W-Cache Bank valid bit Test Subtest: W-Cache Bank valid bit Test Subtest: 8K DTLB TAG Test Subtest: 8K DTLB TAG Test Subtest: W-Cache Initialization Subtest: W-Cache SnoopTAGS Test Subtest: W-Cache SnoopTAGS Test Subtest: W-Cache Initialization Subtest: 4M ITLB RAM Test Subtest: 4M ITLB RAM Test Subtest: W-Cache Initialization Subtest: W-Cache Initialization Subtest: 8K ITLB RAM Test

{/N0/SB0/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB0/P2} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB0/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P0} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB0/P2} {/N0/SB2/P2} {/N0/SB0/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P2} {/N0/SB2/P1} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P3} {/N0/SB2/P2}

Subtest: 8K ITLB RAM Test Subtest: P-Cache RAM Test Subtest: P-Cache RAM Test Subtest: P-Cache RAM Test Subtest: P-Cache RAM Test Subtest: P-Cache TAGS Test Subtest: 4M ITLB TAG Test Subtest: 4M ITLB TAG Test Subtest: P-Cache TAGS Test Subtest: 8K ITLB TAG Test Subtest: 8K ITLB TAG Test Subtest: P-Cache TAGS Test Subtest: P-Cache TAGS Test Subtest: P-Cache SnoopTags Test Subtest: P-Cache SnoopTags Test Subtest: P-Cache SnoopTags Test Subtest: P-Cache SnoopTags Test Subtest: E-Cache Global Variables Initialization Subtest: P-Cache Status Data Test Subtest: P-Cache Status Data Test Subtest: E-Cache Global Variables Initialization Subtest: P-Cache Status Data Test Subtest: P-Cache Status Data Test Subtest: E-Cache TAGS Test Subtest: E-Cache TAGS Test Running Enable MMU Running Enable MMU Running Enable MMU Subtest: P-Cache Initialization Subtest: P-Cache Initialization Subtest: Branch Prediction Initialization Subtest: Branch Prediction Initialization Running Enable MMU Subtest: IMMU Registers Access Subtest: IMMU Registers Access Subtest: P-Cache Initialization Subtest: P-Cache Initialization Subtest: Branch Prediction Initialization Subtest: Branch Prediction Initialization Subtest: IMMU Registers Access Subtest: IMMU Registers Access Subtest: Fast Init. Verification Test Running FPU Tests Subtest: Fast Init. Verification Test Running FPU Tests Running FPU Tests Subtest: DMMU Registers Access Subtest: DMMU Registers Access Subtest: 4M DTLB RAM Test Subtest: 4M DTLB RAM Test Subtest: E-Cache TAGS ECC Test Subtest: E-Cache TAGS ECC Test Running FPU Tests Subtest: 8K DTLB RAM Test Subtest: DMMU Registers Access Subtest: 8K DTLB RAM Test Subtest: IMMU Initialization Subtest: IMMU Initialization Subtest: DMMU Registers Access Subtest: 4M DTLB RAM Test

{/N0/SB2/P3} {/N0/SB0/P2} {/N0/SB2/P2} {/N0/SB0/P3} {/N0/SB2/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P1} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P0} {/N0/SB2/P2} {/N0/SB2/P1} {/N0/SB2/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P0} {/N0/SB2/P2} {/N0/SB2/P1} {/N0/SB2/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB0/P3} {/N0/SB2/P0} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB0/P2} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB0/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P2} {/N0/SB0/P2}

Subtest: 4M DTLB RAM Test Subtest: DMMU Initialization Subtest: 8K DTLB RAM Test Subtest: DMMU Initialization Subtest: 8K DTLB RAM Test Subtest: Map LPOST to local space Subtest: Map LPOST to local space Running Basic Ecache Running Basic Ecache Subtest: 4M DTLB TAG Test Subtest: 4M DTLB TAG Test Subtest: 8K DTLB TAG Test Subtest: 8K DTLB TAG Test Running Basic Ecache Subtest: 4M ITLB RAM Test Subtest: 4M ITLB RAM Test Running Basic Ecache Subtest: 4M DTLB TAG Test Subtest: 4M DTLB TAG Test Subtest: 8K DTLB TAG Test Subtest: 8K DTLB TAG Test Subtest: 4M ITLB RAM Test Subtest: 8K ITLB RAM Test Subtest: 4M ITLB RAM Test Subtest: 8K ITLB RAM Test Running Memory Registers Tests Running Memory Registers Tests Subtest: FPU Register Test Subtest: FPU Register Test Subtest: FSR Test Subtest: FSR Test Subtest: E-Cache Quick Verification Test Subtest: E-Cache Quick Verification Test Subtest: 8K ITLB RAM Test Subtest: 4M ITLB TAG Test Subtest: 8K ITLB RAM Test Subtest: 4M ITLB TAG Test Subtest: E-Cache RAM Test Part1 Subtest: E-Cache RAM Test Part1 Subtest: E-Cache RAM Test Part2 Subtest: 4M ITLB TAG Test Subtest: 4M ITLB TAG Test Subtest: 8K ITLB TAG Test Subtest: 8K ITLB TAG Test Subtest: E-Cache RAM Test Part2 Subtest: 8K ITLB TAG Test Subtest: E-Cache Global Variables Initialization Subtest: E-Cache Global Variables Initialization Subtest: 8K ITLB TAG Test Subtest: E-Cache TAGS Test Subtest: E-Cache TAGS Test Subtest: E-Cache Address Line Test Subtest: E-Cache Global Variables Initialization Subtest: E-Cache Global Variables Initialization Subtest: E-Cache Address Line Test Subtest: Fast Init. Verification Test Subtest: Fast Init. Verification Test Subtest: E-Cache TAGS Test Subtest: E-Cache TAGS ECC Test Subtest: E-Cache Initialization of first 1K

{/N0/SB0/P3} {/N0/SB2/P1} {/N0/SB2/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB0/P2} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB0/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2}

Subtest: E-Cache Initialization of first 1K Subtest: E-Cache TAGS Test Subtest: E-Cache TAGS ECC Test Subtest: E-Cache Initialization Subtest: E-Cache Initialization Subtest: Fast Init. Verification Test Subtest: Fast Init. Verification Test Subtest: Disable Memory Controllers Subtest: IMMU Initialization Subtest: IMMU Initialization Subtest: Disable Memory Controllers Subtest: DMMU Initialization Subtest: DMMU Initialization Subtest: E-Cache TAGS ECC Test Subtest: E-Cache TAGS ECC Test Subtest: Mem Addr Control Reg Test Subtest: Mem Addr Control Reg Test Subtest: IMMU Initialization Subtest: IMMU Initialization Subtest: Map LPOST to local space Subtest: Map LPOST to local space Subtest: DMMU Initialization Subtest: DMMU Initialization Subtest: FPU Register Test Subtest: FPU Register Test Subtest: Map LPOST to local space Subtest: Map LPOST to local space Subtest: FSR Test Subtest: FSR Test Subtest: FPU Register Test Subtest: FPU Register Test Subtest: E-Cache Quick Verification Test Subtest: E-Cache Quick Verification Test Subtest: FSR Test Subtest: FSR Test Subtest: E-Cache RAM Test Part1 Subtest: E-Cache RAM Test Part1 Subtest: E-Cache Quick Verification Test Subtest: E-Cache Quick Verification Test Subtest: E-Cache RAM Test Part1 Subtest: E-Cache RAM Test Part1 Subtest: Mem Addr Decoding Reg Test Subtest: Mem Addr Decoding Reg Test Subtest: E-Cache RAM Test Part2 Subtest: E-Cache RAM Test Part2 Subtest: E-Cache RAM Test Part2 Subtest: E-Cache RAM Test Part2 Running Memory Configuration Tests Running Memory Configuration Tests Subtest: Memory Controller Configuration Subtest: Memory Controller Configuration Subtest: Memory DIMMs Init Subtest: Memory DIMMs Init Subtest: UP Memory Clear Subtest: UP Memory Clear Subtest: E-Cache Address Line Test Subtest: E-Cache Address Line Test Subtest: E-Cache Address Line Test Subtest: E-Cache Address Line Test Subtest: E-Cache Initialization of first 1K

{/N0/SB2/P3} {/N0/SB2/P1} {/N0/SB0/P2} {/N0/SB2/P0} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P1} {/N0/SB0/P3} {/N0/SB2/P0} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P2} {/N0/SB2/P0} {/N0/SB2/P3} {/N0/SB2/P1} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB2/P2} {/N0/SB2/P0} {/N0/SB2/P3} {/N0/SB2/P1} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P0} {/N0/SB0/P1} {/N0/SB0/P2}

Subtest: E-Cache Initialization of first 1K Subtest: E-Cache Initialization of first 1K Running Memory Tests Subtest: E-Cache Initialization of first 1K Subtest: E-Cache Initialization Subtest: E-Cache Initialization Running Memory Tests Subtest: Memory Addressing Subtest: Memory Addressing Subtest: E-Cache Initialization Subtest: Memory DIMM Access Subtest: E-Cache Initialization Subtest: Memory DIMM Access Subtest: Memory MATS+ Subtest: Memory MATS+ Subtest: Memory MARCH CSubtest: Memory MARCH CSubtest: Memory Alternating Multiple Access Selection Subtest: Memory Alternating Multiple Access Selection Subtest: Enable Correctable Error Traps Running Memory Registers Tests Running Memory Registers Tests Running Memory Registers Tests Running Memory Registers Tests Subtest: Disable Memory Controllers Subtest: Disable Memory Controllers Subtest: Mem Addr Control Reg Test Subtest: Mem Addr Control Reg Test Subtest: Disable Memory Controllers Subtest: Disable Memory Controllers Subtest: Mem Addr Control Reg Test Subtest: Mem Addr Control Reg Test Running Ecache Functional Running Ecache Functional Subtest: Enable Correctable Error Traps Subtest: E-Cache Stress Subtest: E-Cache Stress Subtest: Mem Addr Decoding Reg Test Subtest: Mem Addr Decoding Reg Test Subtest: Mem Addr Decoding Reg Test Subtest: Mem Addr Decoding Reg Test Running CPU Functional Running CPU Functional Running Advanced CPU Tests Running Advanced CPU Tests Running CPU ECC Tests Running CPU ECC Tests Running System Level Tests Running System Level Tests Subtest: MP Memory Access Test Subtest: MP Memory Access Test Subtest: Invalidate Caches Subtest: Invalidate Caches Running Board Memory Interleave Running Board Memory Interleave Subtest: Board Memory Interleave Configuration Subtest: Board Memory Interleave Configuration Unpopulated Unpopulated Passed

{/N0/SB0/P3} {/N0/SB2/P0} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P0} {/N0/SB2/P3} {/N0/SB2/P1} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P1} {/N0/SB2/P0} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P0} {/N0/SB2/P3} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P0} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P1} {/N0/SB2/P0} {/N0/SB2/P2} {/N0/SB2/P1} {/N0/SB2/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P0}

Passed Running Memory Configuration Tests Running Memory Configuration Tests Running Memory Configuration Tests Running Memory Configuration Tests Subtest: Memory Controller Configuration Subtest: Memory Controller Configuration Subtest: Memory Controller Configuration Subtest: Memory Controller Configuration Subtest: UP Memory Clear Subtest: UP Memory Clear Subtest: UP Memory Clear Subtest: UP Memory Clear Running Memory Tests Running Memory Tests Running Memory Tests Running Memory Tests Subtest: Memory Addressing Subtest: Memory Addressing Subtest: Memory Addressing Subtest: Memory Addressing Subtest: Memory DIMM Access Subtest: Memory DIMM Access Subtest: Memory DIMM Access Subtest: Memory DIMM Access Subtest: Memory MATS+ Subtest: Memory MATS+ Subtest: Memory MATS+ Subtest: Memory MATS+ Subtest: Memory MARCH CSubtest: Memory MARCH CSubtest: Memory MARCH CSubtest: Memory MARCH CSubtest: Memory Alternating Multiple Access Subtest: Memory Alternating Multiple Access Subtest: Memory Alternating Multiple Access Subtest: Memory Alternating Multiple Access Running Ecache Functional Running Ecache Functional Subtest: E-Cache Stress Running Ecache Functional Running Ecache Functional Subtest: E-Cache Stress Subtest: E-Cache Stress Subtest: E-Cache Stress Running CPU Functional Running CPU Functional Running CPU Functional Running CPU Functional Running Advanced CPU Tests Running Advanced CPU Tests Running Advanced CPU Tests Running Advanced CPU Tests Running CPU ECC Tests Running CPU ECC Tests Running CPU ECC Tests Running CPU ECC Tests Running System Level Tests Running System Level Tests Subtest: MP Memory Access Test

Selection Selection Selection Selection

{/N0/SB2/P1} Subtest: MP Memory Access Test {/N0/SB2/P2} Running System Level Tests {/N0/SB2/P3} Running System Level Tests {/N0/SB2/P2} Subtest: MP Memory Access Test {/N0/SB2/P3} Subtest: MP Memory Access Test {/N0/SB2/P2} Running Board Memory Interleave {/N0/SB2/P3} Running Board Memory Interleave {/N0/SB2/P2} Subtest: Board Memory Interleave Configuration {/N0/SB2/P3} Subtest: Board Memory Interleave Configuration {/N0/SB2/P0} Running Board Memory Interleave {/N0/SB2/P1} Running Board Memory Interleave {/N0/SB2/P0} Subtest: Board Memory Interleave Configuration {/N0/SB2/P1} Subtest: Board Memory Interleave Configuration {/N0/SB2/P0} Passed {/N0/SB2/P1} Passed {/N0/SB2/P2} Passed {/N0/SB2/P3} Passed Testing IO Boards ... Copying IO PROM to CPU DRAM ............................................ {/N0/SB0/P2} Jumping to memory 00000000.00000020 [00000010] {/N0/SB0/P2} Running PCI IO Controller Basic Tests {/N0/SB0/P2} System PCI IO post code running from memory {/N0/SB0/P2} @(#) lpost 5.20.5 2007/02/07 13:57 {/N0/SB0/P2} Copyright 2007 Sun Microsystems, Inc. All rights reserved. {/N0/SB0/P2} Running PCI IO Controller Functional Tests {/N0/SB0/P2} Use is subject to license terms. {/N0/SB0/P2} Subtest: PCI IO Controller Register Initialization for aid 0x1c {/N0/SB0/P2} Subtest: PCI IO Controller IOMMU TLB Compare Tests for aid 0x1c {/N0/SB0/P2} Subtest: PCI IO Controller IOMMU TLB Flush Tests for aid 0x1c {/N0/SB0/P2} Subtest: PCI IO Controller DMA loopback Tests for aid 0x1c {/N0/SB0/P2} Subtest: PCI IO Controller block DMA loopback Tests for aid 0x1c {/N0/SB0/P2} Subtest: PCI IO Controller Interrupt Tests for aid 0x1c {/N0/SB0/P2} Running PCI IO Controller Ecc Tests {/N0/SB0/P2} Subtest: PCI IO Controller MergeBuffer Tests for aid 0x1c {/N0/SB0/P2} Subtest: PCI IO Controller StreamCache Tests for aid 0x1c {/N0/SB0/P2} Subtest: Schizo clean up for aid 0x1c {/N0/SB0/P2} Running SBBC Basic Tests {/N0/SB0/P2} Subtest: SBBC PCI Reg Initialization for aid 0x1c {/N0/SB0/P2} Running Probe io Devices {/N0/SB0/P2} Running PCI IO Controller Basic Tests {/N0/SB0/P2} Subtest: PCI IO Controller Register Initialization for aid 0x1d {/N0/SB0/P2} Running PCI IO Controller Functional Tests {/N0/SB0/P2} Subtest: PCI IO Controller IOMMU TLB Compare Tests for aid 0x1d {/N0/SB0/P2} Subtest: PCI IO Controller IOMMU TLB Flush Tests for aid 0x1d {/N0/SB0/P2} Subtest: PCI IO Controller DMA loopback Tests for aid 0x1d {/N0/SB0/P2} Subtest: PCI IO Controller block DMA loopback Tests for aid 0x1d {/N0/SB0/P2} Subtest: PCI IO Controller Interrupt Tests for aid 0x1d {/N0/SB0/P2} Subtest: PCI IO Controller MergeBuffer Tests for aid 0x1d {/N0/SB0/P2} Subtest: PCI IO Controller StreamCache Tests for aid 0x1d {/N0/SB0/P2} Running PCI IO Controller Ecc Tests {/N0/SB0/P2} Subtest: Schizo clean up for aid 0x1d {/N0/SB0/P2} Running Probe io Devices {/N0/SB0/P2} @(#) lpost 5.20.5 2007/02/07 13:53 {/N0/SB0/P2} Copyright 2007 Sun Microsystems, Inc. All rights reserved. {/N0/SB0/P2} Use is subject to license terms. {/N0/IB8/P0} Passed {/N0/IB8/P1} Passed Testing domain ... {/N0/SB0/P2} Running Domain Level Tests

{/N0/SB0/P2} {/N0/SB0/P2} {/N0/SB0/P2} {/N0/SB0/P2} {/N0/SB0/P2} {/N0/SB0/P2} {/N0/SB0/P2} {/N0/SB0/P2} {/N0/SB0/P2} {/N0/SB0/P2} {/N0/SB0/P2} {/N0/SB0/P2} {/N0/SB0/P2} {/N0/SB0/P2} {/N0/SB0/P2} {/N0/SB0/P2} {/N0/SB0/P2} {/N0/SB0/P2} {/N0/SB0/P2} {/N0/SB0/P2} {/N0/SB0/P2} {/N0/SB0/P2} {/N0/SB0/P2} {/N0/SB0/P2} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3}

Subtest: Mapping IO SRAM Subtest: Memory interleaving config Running Domain Basic Tests Subtest: Cross Call Test Running Domain Advanced Tests Subtest: MP Memory Clear Test CORE 3 clearing 00000000.00000000 to 00000000.2aaaaa80 CORE 8 clearing 00000000.2aaaaa80 to 00000000.55555500 CORE 9 clearing 00000000.55555500 to 00000000.7fffff80 CORE 10 clearing 00000000.7fffff80 to 00000000.aaaaaa00 CORE 11 clearing 00000000.aaaaaa00 to 00000000.d5555480 CORE 2 clearing 00000000.d5555480 to 00000001.00000000 CORE 3 clearing 00000020.00000000 to 00000020.aaaaaa80 CORE 8 clearing 00000020.aaaaaa80 to 00000021.55555500 CORE 9 clearing 00000021.55555500 to 00000021.ffffff80 CORE 10 clearing 00000021.ffffff80 to 00000022.aaaaaa00 CORE 11 clearing 00000022.aaaaaa00 to 00000023.55555480 CORE 2 clearing 00000023.55555480 to 00000024.00000000 Running Domain Stick Sync Tests Subtest: Sync. Stick Registers Test Running Domain Verify Stick Sync Tests Subtest: Verify Sync. Stick Registers Test DCB_DECOMP_OBP command succeeded Decompress OBP done DCB_ENTER_OBP command succeeded DCB_ENTER_OBP command succeeded DCB_ENTER_OBP command succeeded DCB_ENTER_OBP command succeeded DCB_ENTER_OBP command succeeded DCB_ENTER_OBP command succeeded

Entering OBP ... ChassisSerialNumber 150H263F Sun Fire 6800 OpenFirmware version 5.20.5 (02/07/07 13:51) Copyright 2007 Sun Microsystems, Inc. All rights reserved. Use is subject to license terms. SmartFirmware, Copyright (C) 1996-2001. All rights reserved. 20480 MB memory installed, Serial #50806996. Ethernet address 0:3:ba:7:40:d4, Host ID: 830740d4. Rebooting with command: boot SunOS Release 5.9 Version Generic_122300-11 64-bit Copyright 1983-2003 Sun Microsystems, Inc. All rights reserved. Use is subject to license terms. WARNING: /ssm@0,0/pci@1c,600000/SUNW,qlc@1/fp@0,0/ssd@w50060482cafe6723,0 (ssd9) : Corrupt label; wrong magic number WARNING: /ssm@0,0/pci@1d,600000/SUNW,qlc@1/fp@0,0/ssd@w50060482cafe672c,0 (ssd19 ): Corrupt label; wrong magic number Hardware watchdog enabled VxVM sysboot INFO V-5-2-3390 Starting restore daemon... VxVM sysboot INFO V-5-2-3409 starting in boot mode... NOTICE: VxVM vxdmp V-5-0-34 added disk array DISKS, datype = Disk

WARNING: /ssm@0,0/pci@1c,600000/SUNW,qlc@1/fp@0,0/ssd@w50060482cafe6723,0 (ssd9) : Corrupt label; wrong magic number WARNING: /ssm@0,0/pci@1c,600000/SUNW,qlc@1/fp@0,0/ssd@w50060482cafe6723,0 (ssd9) : Corrupt label; wrong magic number NOTICE: VxVM vxdmp V-5-0-112 disabled path 118/0x48 belonging to the dmpnode 274 /0x20 WARNING: /ssm@0,0/pci@1d,600000/SUNW,qlc@1/fp@0,0/ssd@w50060482cafe672c,0 (ssd19 ): Corrupt label; wrong magic number WARNING: /ssm@0,0/pci@1d,600000/SUNW,qlc@1/fp@0,0/ssd@w50060482cafe672c,0 (ssd19 ): Corrupt label; wrong magic number NOTICE: VxVM vxdmp V-5-0-112 disabled path 118/0x98 belonging to the dmpnode 274 /0x20 NOTICE: VxVM vxdmp V-5-0-111 disabled dmpnode 274/0x20 configuring IPv4 interfaces: ce0 hme0. Hostname: rcisn022 VxVM INFO V-5-2-3247 starting special volumes ( swapvol rootvol usr var )... The / file system (/dev/vx/rdsk/bootdg/rootvol) is being checked. /dev/vx/rdsk/bootdg/rootvol: 20924 files, 1449248 used, 535795 free (14867 frags , 65116 blocks, 0.7% fragmentation) The /usr file system (/dev/vx/rdsk/bootdg/usr) is being checked. /dev/vx/dsk/bootdg/usr: 85030 files, 3316338 used, 715804 free (61636 frags, 817 71 blocks, 1.5% fragmentation) The /var file system (/dev/vx/rdsk/bootdg/var) is being checked. /dev/vx/rdsk/bootdg/var: PARTIALLY TRUNCATED INODE I=31259 /dev/vx/rdsk/bootdg/var: UNEXPECTED INCONSISTENCY; RUN fsck MANUALLY. WARNING - Unable to repair the /var filesystem. Run fsck manually (fsck -F ufs /dev/vx/rdsk/bootdg/var). Exit the shell when done to continue the boot process. Type control-d to proceed with normal startup, (or give root password for system maintenance): single-user privilege assigned to /dev/console. Entering System Maintenance Mode Nov 11 07:54:41 su: 'su root' succeeded for root on /dev/console WARNING: By using this system, you agree to comply with RCI corporate policies governing accessing and using the companys IT systems and data. To protect this system from unauthorized use and to ensure that the system is functioning properly, activities on this system are monitored and recorded and are subject to audit. Unauthorized access use of this system is prohibited and could be subject to disciplinary actions as well criminal and/or civil penalties. root@rcisn022:/ > root@rcisn022:/

> fsck -F ufs /dev/vx/rdsk/bootdg/var ** /dev/vx/rdsk/bootdg/var ** Last Mounted on /var ** Phase 1 - Check Blocks and Sizes PARTIALLY TRUNCATED INODE I=31259 SALVAGE? yyyyyPARTIALLY TRUNCATED INODE I=32038 SALVAGE? y y y y ** Phase 2 - Check Pathnames ** Phase 3a - Check Connectivity ** Phase 3b - Verify Shadows/ACLs ** Phase 4 - Check Reference Counts ** Phase 5 - Check Cylinder Groups FRAG BITMAP WRONG FIX? FRAG BITMAP WRONG FIX? CORRECT GLOBAL SUMMARY SALVAGE? FILESYSTEM MAY STILL BE INCONSISTENT. 28788 files, 1217835 used, 2814231 free (12607 frags, 350203 blocks, 0.3% fragme ntation) ***** FILE SYSTEM WAS MODIFIED ***** ***** FILE SYSTEM IS BAD ***** ***** PLEASE RERUN FSCK ***** root@rcisn022:/ > y ksh: y: not found root@rcisn022:/ > root@rcisn022:/ > y ksh: y: not found root@rcisn022:/ > root@rcisn022:/ > y ksh: y: not found root@rcisn022:/ > root@rcisn022:/ > fsck -y /dev/vx/dsk/bootdg/rootvol IS CURRENTLY MOUNTED READ/WRITE. CONTINUE? yes ** ** ** ** /dev/vx/dsk/bootdg/rootvol Currently Mounted on / Phase 1 - Check Blocks and Sizes Phase 2 - Check Pathnames

** Phase 3a - Check Connectivity ** Phase 3b - Verify Shadows/ACLs ** Phase 4 - Check Reference Counts ** Phase 5 - Check Cylinder Groups FILESYSTEM MAY STILL BE INCONSISTENT. 20924 files, 1449248 used, 535795 free (14867 frags, 65116 blocks, 0.7% fragment ation) ***** PLEASE RERUN FSCK ON UNMOUNTED FILE SYSTEM ***** /dev/vx/dsk/bootdg/usr IS CURRENTLY MOUNTED READ/WRITE. CONTINUE? yes ** /dev/vx/dsk/bootdg/usr ** Currently Mounted on /usr ** Phase 1 - Check Blocks and Sizes ** Phase 2 - Check Pathnames ** Phase 3a - Check Connectivity ** Phase 3b - Verify Shadows/ACLs ** Phase 4 - Check Reference Counts ** Phase 5 - Check Cylinder Groups FILESYSTEM MAY STILL BE INCONSISTENT. 85030 files, 3316338 used, 715804 free (61636 frags, 81771 blocks, 1.5% fragment ation) ***** PLEASE RERUN FSCK ON UNMOUNTED FILE SYSTEM ***** ** /dev/vx/rdsk/bootdg/var ** Last Mounted on /var ** Phase 1 - Check Blocks and Sizes PARTIALLY TRUNCATED INODE I=31259 SALVAGE? yes ** Phase 2 - Check Pathnames ** Phase 3a - Check Connectivity ** Phase 3b - Verify Shadows/ACLs ** Phase 4 - Check Reference Counts ** Phase 5 - Check Cylinder Groups FRAG BITMAP WRONG FIX? yes CORRECT GLOBAL SUMMARY SALVAGE? yes 28788 files, 1217835 used, 2814307 free (12603 frags, 350213 blocks, 0.3% fragme ntation) ***** FILE SYSTEM WAS MODIFIED ***** root@rcisn022:/ > root@rcisn022:/ > exit resuming system initialization VxVM vxvm-startup2 INFO V-5-2-503 VxVM general startup... dumpadm: no swap devices could be configured as the dump device The system is coming up. Please wait. checking vxfs filesystems Running parallel replay fsck ... /dev/vx/rdsk/apps/removemelv:log replay in progress /dev/vx/rdsk/apps/rdmftplv:log replay in progress /dev/vx/rdsk/apps/rdmftplv:replay complete - marking super-block as CLEAN /dev/vx/rdsk/apps/removemelv:replay complete - marking super-block as CLEAN

panic[cpu2]/thread=30007906360: alloccgblk: can't find blk in cyl, pos:0, i:284, fs:/var bno: 6e7 000002a10071efb0 ufs:ufs_fault_v+e0 (3000895ca38, 151b960, 2a10071f1a0, 2805ec0, b19c0, 0) %l0-3: 0000000000000000 000000000151b960 0000000001507750 000002a10071faa8 %l4-7: 0000030000a47a48 0000030000a47af8 0000030007852e90 0000030007852ff0 000002a10071f060 ufs:ufs_fault+1c (3000895ca38, 151b960, 0, 11c, 300093a40d4, 6e 7) %l0-3: 0000030005c878d8 0000030009898a60 00000000000b19c0 000001130001a1f9 %l4-7: 0000000000000000 0000030005c87908 0000030009898b10 0000000000001000 000002a10071f110 ufs:alloccgblk+4bc (6e7, 90000, 803, 11c, 11c, 300093a4560) %l0-3: 0000030000a47a48 00000300093a4000 0000030009e28568 0000030009e28000 %l4-7: 0000030009898a60 0000030000a47a48 0000000000004000 0000000000000000 000002a10071f1c0 ufs:alloccg+158 (7, 70, 30009898a60, 30000a47af8, 2000, ff00) %l0-3: 0000030009e28568 000000000005c948 00000300093a4000 0000030009e28000 %l4-7: 0000000000002000 0000030000a47a48 0000000000000007 0000030007852e90 000002a10071f270 ufs:hashalloc+2c (30007852e90, 7, 5c948, 2000, 1196dac, 2a10071 f3d0) %l0-3: 0000000000000007 0000030009898980 00000300093a4000 0000000000002000 %l4-7: 0000000000000000 0000000001196dac 0000030007852e90 0000000000001000 000002a10071f320 ufs:alloc+154 (10, 0, 300093a4000, 2a10071f6e0, 30000dd7f28, 10 0314a40) %l0-3: 0000000000002000 000000000005c948 0000030000a47a48 0000030007852e90 %l4-7: 000000000005c948 0000000000000000 0000000000000000 0000000000000000 000002a10071f3e0 ufs:bmap_write+c40 (45, 0, 0, 5c948, 2000, 0) %l0-3: 0000000000006000 0000030007852e90 0000000000002000 00000300093a4000 %l4-7: 0000000000000000 0000030000a47a48 0000000000000003 0000000000000051 000002a10071f6f0 ufs:wrip+428 (0, 0, 8, 30000dd7f28, 105d400, 0) %l0-3: 0000000000000005 0000030007852e90 0000000000000005 000002a10071faa8 %l4-7: 0000030000a47a48 000002a7d4184000 0000030000a47a90 0000000000000001 000002a10071f920 ufs:ufs_write+480 (30007852ff8, 30007853048, 151ac00, 151ac00, 100345f49, 0) %l0-3: 0000030000a47a90 0000030000a47a48 0000000000000008 000002a10071faa8 %l4-7: 0000000000000000 0000030000dd7f28 0000030007852e90 0000030007852ff0 000002a10071f9f0 genunix:write+26c (1, 1b, 1e9, 1, 9, 100345d60) %l0-3: 00000000011a6894 0000030007852f30 00000000000001e9 0000000000000000 %l4-7: 0000000000000001 00000000000001e9 00000300071fbc78 000000000000210b syncing file systems...Nov 11 08:02:26 sc6800 Domain-C.SC: Active - Panicking [1] 18 [1] 12 [1] 5 [1] 5 [1] 5 [1] 5 [1] 5 [1] 5 [1] 5 [1] 5 [1] 5 [1] 5 [1] 5 [1] 5 [1] 5 [1] 5 [1] 5 [1] 5 [1] 5 [1] 5 [1] 5 [1] 5 [1] 5 done (not all i/o c ompleted) skipping system dump - no dump device configured rebooting... Resetting ... Nov 11 08:03:08 sc6800 Domain-C.SC: Active - Panicking Nov 11 08:03:09 sc6800 Domain-C.SC: POST after panic - using diag-level=min. Powering boards off ... Powering boards on ... Testing CPU Boards ... cpuAB: All agents not usable {/N0/SB2/P0} Running CPU POR and Set Clocks {/N0/SB2/P1} Running CPU POR and Set Clocks {/N0/SB2/P0} @(#) lpost 5.14.6 2003/06/24 21:40 {/N0/SB2/P1} @(#) lpost 5.14.6 2003/06/24 21:40 {/N0/SB2/P0} Copyright 2001-2003 Sun Microsystems, Inc. All rights reserved. {/N0/SB2/P1} Copyright 2001-2003 Sun Microsystems, Inc. All rights reserved.

{/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P0} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P0} {/N0/SB2/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P2} {/N0/SB2/P1} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P2} {/N0/SB2/P0} {/N0/SB2/P3} {/N0/SB2/P1} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P0} {/N0/SB2/P2} {/N0/SB0/P2} {/N0/SB0/P3}

Use is subject to license terms. Use is subject to license terms. Running CPU POR and Set Clocks Running CPU POR and Set Clocks @(#) lpost 5.14.6 2003/06/24 21:40 @(#) lpost 5.14.6 2003/06/24 21:40 Copyright 2001-2003 Sun Microsystems, Inc. All rights reserved. Copyright 2001-2003 Sun Microsystems, Inc. All rights reserved. Use is subject to license terms. Use is subject to license terms. Running CPU POR and Set Clocks Running CPU POR and Set Clocks @(#) lpost 5.20.5 2007/02/07 13:53 @(#) lpost 5.20.5 2007/02/07 13:53 Copyright 2007 Sun Microsystems, Inc. All rights reserved. Copyright 2007 Sun Microsystems, Inc. All rights reserved. Use is subject to license terms. Use is subject to license terms. Running Basic CPU Running Basic CPU Running Basic CPU Running Basic CPU Subtest: Setting Fireplane Config Registers for aid 0xa Subtest: Setting Fireplane Config Registers for aid 0x8 Subtest: Setting Fireplane Config Registers for aid 0xb Subtest: Display CPU Version, frequency Subtest: Display CPU Version, frequency Version register = 003e0015.21000507 Subtest: Setting Fireplane Config Registers for aid 0x9 Version register = 003e0015.21000507 Subtest: Display CPU Version, frequency Subtest: Display CPU Version, frequency Version register = 003e0015.21000507 Version register = 003e0015.21000507 Cpu/System ratio = 6, cpu actual frequency = 900 Cpu/System ratio = 6, cpu actual frequency = 900 Cpu/System ratio = 6, cpu actual frequency = 900 Cpu/System ratio = 6, cpu actual frequency = 900 @(#) lpost 5.14.6 2003/06/24 21:40 @(#) lpost 5.14.6 2003/06/24 21:40 @(#) lpost 5.14.6 2003/06/24 21:40 @(#) lpost 5.14.6 2003/06/24 21:40 Copyright 2001-2003 Sun Microsystems, Inc. All rights reserved. Copyright 2001-2003 Sun Microsystems, Inc. All rights reserved. Use is subject to license terms. Copyright 2001-2003 Sun Microsystems, Inc. All rights reserved. Use is subject to license terms. Copyright 2001-2003 Sun Microsystems, Inc. All rights reserved. Running Basic CPU Running Basic CPU Subtest: Setting Fireplane Config Registers for aid 0x2 Subtest: Setting Fireplane Config Registers for aid 0x3 Subtest: Display CPU Version, frequency Subtest: Display CPU Version, frequency Version register = 003e0015.23000507 Version register = 003e0015.23000507 Use is subject to license terms. Subtest: I-Cache RAM Test CPU features = 0000225f.004205ff CPU features = 0000225f.004205ff

{/N0/SB2/P1} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB0/P2} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB0/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P0} {/N0/SB2/P2} {/N0/SB2/P1} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P0} {/N0/SB2/P2} {/N0/SB2/P1} {/N0/SB2/P3}

Use is subject to license terms. Ecache Control Register 00000000.07c35400 Ecache Control Register 00000000.07c35400 Subtest: I-Cache RAM Test Subtest: I-Cache RAM Test Subtest: I-Cache RAM Test Cpu/System ratio = 7, cpu actual frequency = 1050 Cpu/System ratio = 7, cpu actual frequency = 1050 @(#) lpost 5.20.5 2007/02/07 13:53 @(#) lpost 5.20.5 2007/02/07 13:53 Subtest: I-Cache TAGS Test Subtest: I-Cache TAGS Test Subtest: I-Cache TAGS Test Subtest: I-Cache TAGS Test Copyright 2007 Sun Microsystems, Inc. All rights reserved. Subtest: I-Cache Valid/Predict TAGS Test Subtest: I-Cache Valid/Predict TAGS Test Subtest: I-Cache Valid/Predict TAGS Test Subtest: I-Cache Valid/Predict TAGS Test Copyright 2007 Sun Microsystems, Inc. All rights reserved. Subtest: I-Cache Snoop Tags Test Subtest: I-Cache Snoop Tags Test Use is subject to license terms. Use is subject to license terms. Subtest: I-Cache Snoop Tags Test Subtest: I-Cache Snoop Tags Test Subtest: I-Cache Branch Predict Array Test Subtest: I-Cache Branch Predict Array Test Subtest: I-Cache RAM Test Subtest: I-Cache RAM Test Subtest: I-Cache Branch Predict Array Test Subtest: I-Cache Branch Predict Array Test Subtest: I-Cache TAGS Test Subtest: I-Cache TAGS Test Subtest: I-Cache Initialization Subtest: I-Cache Initialization Subtest: I-Cache Initialization Subtest: I-Cache Initialization Subtest: D-Cache RAM Test Subtest: D-Cache RAM Test Subtest: D-Cache RAM Test Subtest: D-Cache RAM Test Subtest: I-Cache Valid/Predict TAGS Test Subtest: I-Cache Valid/Predict TAGS Test Subtest: I-Cache Snoop Tags Test Subtest: I-Cache Snoop Tags Test Subtest: I-Cache Branch Predict Array Test Subtest: I-Cache Branch Predict Array Test Subtest: D-Cache TAGS Test Subtest: D-Cache TAGS Test Subtest: D-Cache TAGS Test Subtest: D-Cache TAGS Test Subtest: D-Cache MicroTags Test Subtest: D-Cache MicroTags Test Subtest: D-Cache MicroTags Test Subtest: D-Cache MicroTags Test Subtest: D-Cache SnoopTags Test Subtest: D-Cache SnoopTags Test Subtest: D-Cache SnoopTags Test Subtest: D-Cache SnoopTags Test

{/N0/SB2/P0} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB0/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB0/P3} {/N0/SB2/P0} {/N0/SB2/P2} {/N0/SB2/P1} {/N0/SB2/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P2} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P2} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3}

Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest: Subtest:

D-Cache Initialization I-Cache Initialization I-Cache Initialization D-Cache Initialization D-Cache Initialization D-Cache RAM Test D-Cache Initialization W-Cache RAM Test W-Cache RAM Test D-Cache RAM Test W-Cache TAGS Test W-Cache RAM Test W-Cache TAGS Test W-Cache RAM Test W-Cache TAGS Test W-Cache TAGS Test W-Cache Valid bit Test W-Cache Valid bit Test W-Cache Valid bit Test W-Cache Valid bit Test W-Cache Bank valid bit Test W-Cache Bank valid bit Test W-Cache Bank valid bit Test W-Cache SnoopTAGS Test W-Cache SnoopTAGS Test W-Cache Bank valid bit Test W-Cache Initialization W-Cache Initialization W-Cache SnoopTAGS Test W-Cache SnoopTAGS Test P-Cache RAM Test P-Cache RAM Test D-Cache TAGS Test D-Cache TAGS Test W-Cache Initialization W-Cache Initialization P-Cache TAGS Test P-Cache TAGS Test P-Cache RAM Test P-Cache RAM Test P-Cache SnoopTags Test P-Cache SnoopTags Test P-Cache TAGS Test P-Cache TAGS Test D-Cache MicroTags Test D-Cache MicroTags Test P-Cache SnoopTags Test P-Cache Status Data Test P-Cache Status Data Test P-Cache SnoopTags Test D-Cache SnoopTags Test D-Cache SnoopTags Test P-Cache Status Data Test P-Cache Initialization P-Cache Initialization P-Cache Status Data Test Branch Prediction Initialization Branch Prediction Initialization P-Cache Initialization P-Cache Initialization

{/N0/SB0/P2} {/N0/SB2/P0} {/N0/SB2/P2} {/N0/SB0/P3} {/N0/SB2/P1} {/N0/SB2/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P0} {/N0/SB2/P2} {/N0/SB2/P1} {/N0/SB2/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB0/P2} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB0/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB0/P2} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB0/P2} {/N0/SB2/P0} {/N0/SB2/P3} {/N0/SB0/P3} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB0/P2} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0}

Subtest: D-Cache Initialization Subtest: IMMU Registers Access Subtest: Branch Prediction Initialization Subtest: D-Cache Initialization Subtest: IMMU Registers Access Subtest: Branch Prediction Initialization Subtest: W-Cache RAM Test Subtest: W-Cache RAM Test Subtest: DMMU Registers Access Subtest: IMMU Registers Access Subtest: DMMU Registers Access Subtest: IMMU Registers Access Subtest: W-Cache TAGS Test Subtest: W-Cache TAGS Test Subtest: DMMU Registers Access Subtest: DMMU Registers Access Subtest: 4M DTLB RAM Test Subtest: 4M DTLB RAM Test Subtest: W-Cache Valid bit Test Subtest: 4M DTLB RAM Test Subtest: 4M DTLB RAM Test Subtest: W-Cache Valid bit Test Subtest: 8K DTLB RAM Test Subtest: 8K DTLB RAM Test Subtest: 8K DTLB RAM Test Subtest: 8K DTLB RAM Test Subtest: 4M DTLB TAG Test Subtest: 4M DTLB TAG Test Subtest: W-Cache Bank valid bit Test Subtest: 4M DTLB TAG Test Subtest: 4M DTLB TAG Test Subtest: W-Cache Bank valid bit Test Running Test Large Tag Arrays and Enable MMU Running Test Large Tag Arrays and Enable MMU Subtest: W-Cache SnoopTAGS Test Subtest: W-Cache SnoopTAGS Test Subtest: W-Cache Initialization Subtest: W-Cache Initialization Subtest: 8K DTLB TAG Test Subtest: 8K DTLB TAG Test Subtest: 8K DTLB TAG Test Subtest: 8K DTLB TAG Test Subtest: P-Cache RAM Test Subtest: P-Cache RAM Test Subtest: 4M ITLB RAM Test Subtest: 4M ITLB RAM Test Subtest: 4M ITLB RAM Test Subtest: P-Cache TAGS Test Subtest: 8K ITLB RAM Test Subtest: 4M ITLB RAM Test Subtest: P-Cache TAGS Test Subtest: 8K ITLB RAM Test Subtest: 8K ITLB RAM Test Subtest: 8K ITLB RAM Test Subtest: 4M ITLB TAG Test Subtest: 4M ITLB TAG Test Subtest: P-Cache SnoopTags Test Subtest: 4M ITLB TAG Test Subtest: 4M ITLB TAG Test Subtest: 8K ITLB TAG Test

{/N0/SB2/P1} {/N0/SB0/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB0/P2} {/N0/SB2/P0} {/N0/SB2/P2} {/N0/SB0/P3} {/N0/SB2/P3} {/N0/SB2/P1} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P2} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P0} {/N0/SB2/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P1} {/N0/SB2/P0} {/N0/SB2/P2} {/N0/SB2/P1} {/N0/SB0/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P0}

Subtest: 8K ITLB TAG Test Subtest: P-Cache SnoopTags Test Subtest: 8K ITLB TAG Test Subtest: 8K ITLB TAG Test Subtest: E-Cache Global Variables Initialization Subtest: E-Cache Global Variables Initialization Subtest: P-Cache Status Data Test Subtest: P-Cache Status Data Test Subtest: E-Cache Global Variables Initialization Subtest: E-Cache Global Variables Initialization Subtest: E-Cache TAGS Test Subtest: E-Cache TAGS Test Subtest: E-Cache TAGS Test Subtest: E-Cache TAGS Test Subtest: P-Cache Initialization Subtest: P-Cache Initialization Subtest: Fast Init. Verification Test Subtest: Fast Init. Verification Test Subtest: Fast Init. Verification Test Subtest: Fast Init. Verification Test Subtest: Branch Prediction Initialization Subtest: E-Cache TAGS ECC Test Subtest: E-Cache TAGS ECC Test Subtest: Branch Prediction Initialization Subtest: E-Cache TAGS ECC Test Subtest: E-Cache TAGS ECC Test Subtest: IMMU Registers Access Subtest: IMMU Registers Access Subtest: DMMU Registers Access Subtest: DMMU Registers Access Subtest: 4M DTLB RAM Test Subtest: 4M DTLB RAM Test Subtest: 8K DTLB RAM Test Subtest: 8K DTLB RAM Test Subtest: 4M DTLB TAG Test Subtest: 4M DTLB TAG Test Subtest: 8K DTLB TAG Test Subtest: 8K DTLB TAG Test Subtest: 4M ITLB RAM Test Subtest: 4M ITLB RAM Test Subtest: 8K ITLB RAM Test Subtest: 8K ITLB RAM Test Subtest: 4M ITLB TAG Test Subtest: 4M ITLB TAG Test Running Enable MMU Subtest: 8K ITLB TAG Test Subtest: 8K ITLB TAG Test Running Enable MMU Running Enable MMU Subtest: E-Cache Global Variables Initialization Subtest: E-Cache Global Variables Initialization Running Enable MMU Subtest: IMMU Initialization Subtest: IMMU Initialization Subtest: IMMU Initialization Subtest: E-Cache TAGS Test Subtest: IMMU Initialization Subtest: DMMU Initialization Subtest: DMMU Initialization Subtest: Map LPOST to local space

{/N0/SB2/P1} {/N0/SB0/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P2} {/N0/SB0/P2} {/N0/SB2/P3} {/N0/SB0/P3} {/N0/SB2/P0} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P1} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P1} {/N0/SB2/P0} {/N0/SB2/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB0/P2} {/N0/SB2/P1} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB0/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3}

Subtest: Map LPOST to local space Subtest: E-Cache TAGS Test Subtest: DMMU Initialization Subtest: DMMU Initialization Subtest: Map LPOST to local space Subtest: Map LPOST to local space Running FPU Tests Subtest: Fast Init. Verification Test Running FPU Tests Subtest: Fast Init. Verification Test Running FPU Tests Subtest: FPU Register Test Subtest: FPU Register Test Running FPU Tests Subtest: FPU Register Test Subtest: FPU Register Test Subtest: FSR Test Subtest: FSR Test Subtest: FSR Test Subtest: FSR Test Running Basic Ecache Running Basic Ecache Subtest: E-Cache Quick Verification Test Subtest: E-Cache Quick Verification Test Running Basic Ecache Subtest: E-Cache TAGS ECC Test Running Basic Ecache Subtest: E-Cache Quick Verification Test Subtest: E-Cache Quick Verification Test Subtest: E-Cache TAGS ECC Test Subtest: E-Cache RAM Test Part1 Subtest: E-Cache RAM Test Part1 Subtest: E-Cache RAM Test Part1 Subtest: E-Cache RAM Test Part1 Subtest: IMMU Initialization Subtest: IMMU Initialization Subtest: DMMU Initialization Running FPU Tests Running FPU Tests Subtest: DMMU Initialization Subtest: Map LPOST to local space Subtest: Map LPOST to local space Subtest: FPU Register Test Subtest: FPU Register Test Subtest: FSR Test Running Basic Ecache Running Basic Ecache Subtest: FSR Test Subtest: E-Cache Quick Verification Test Subtest: E-Cache Quick Verification Test Subtest: E-Cache RAM Test Part1 Subtest: E-Cache RAM Test Part1 Subtest: E-Cache RAM Test Part2 Subtest: E-Cache RAM Test Part2 Subtest: E-Cache Address Line Test Subtest: E-Cache Address Line Test Subtest: E-Cache Initialization of first 1K Subtest: E-Cache Initialization of first 1K Subtest: E-Cache Initialization Subtest: E-Cache Initialization

{/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P3} {/N0/SB2/P2} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P2} {/N0/SB2/P0} {/N0/SB2/P3} {/N0/SB2/P1} {/N0/SB2/P1} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P1} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P2} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P2} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P0}

Running Memory Registers Tests Running Memory Registers Tests Subtest: Disable Memory Controllers Subtest: Disable Memory Controllers Subtest: Mem Addr Control Reg Test Subtest: Mem Addr Control Reg Test Subtest: E-Cache RAM Test Part2 Subtest: E-Cache RAM Test Part2 Subtest: E-Cache RAM Test Part2 Subtest: E-Cache RAM Test Part2 Subtest: Mem Addr Decoding Reg Test Subtest: Mem Addr Decoding Reg Test Subtest: E-Cache Address Line Test Subtest: E-Cache Address Line Test Subtest: E-Cache Address Line Test Subtest: E-Cache Address Line Test Subtest: E-Cache Initialization of first Subtest: E-Cache Initialization of first Subtest: E-Cache Initialization of first Subtest: E-Cache Initialization Subtest: E-Cache Initialization Subtest: E-Cache Initialization Subtest: E-Cache Initialization of first Subtest: E-Cache Initialization Running Memory Registers Tests Running Memory Registers Tests Subtest: Disable Memory Controllers Subtest: Disable Memory Controllers Running Memory Registers Tests Running Memory Registers Tests Subtest: Mem Addr Control Reg Test Subtest: Mem Addr Control Reg Test Subtest: Disable Memory Controllers Subtest: Disable Memory Controllers Subtest: Mem Addr Control Reg Test Subtest: Mem Addr Control Reg Test Running Memory Configuration Tests Running Memory Configuration Tests Subtest: Memory Controller Configuration Subtest: Memory Controller Configuration Subtest: Memory DIMMs Init Subtest: Memory DIMMs Init Subtest: UP Memory Clear Subtest: UP Memory Clear Subtest: Mem Addr Decoding Reg Test Subtest: Mem Addr Decoding Reg Test Subtest: Mem Addr Decoding Reg Test Subtest: Mem Addr Decoding Reg Test Running Memory Tests Running Memory Tests Subtest: Memory Addressing Subtest: Memory Addressing Subtest: Memory DIMM Access Subtest: Memory DIMM Access Subtest: Memory MATS+ Subtest: Memory MATS+ Running Memory Configuration Tests Running Memory Configuration Tests Running Memory Configuration Tests Subtest: Memory Controller Configuration

1K 1K 1K

1K

{/N0/SB2/P1} {/N0/SB2/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P2} {/N0/SB2/P0} {/N0/SB2/P3} {/N0/SB2/P1} {/N0/SB2/P0} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P0} {/N0/SB2/P3} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB0/P0} {/N0/SB0/P1} {/N0/SB0/P2} {/N0/SB0/P3}

Subtest: Memory Controller Configuration Running Memory Configuration Tests Subtest: Memory Controller Configuration Subtest: Memory Controller Configuration Subtest: UP Memory Clear Subtest: UP Memory Clear Subtest: UP Memory Clear Subtest: UP Memory Clear Running Memory Tests Running Memory Tests Running Memory Tests Running Memory Tests Subtest: Memory Addressing Subtest: Memory Addressing Subtest: Memory Addressing Subtest: Memory Addressing Subtest: Memory DIMM Access Subtest: Memory DIMM Access Subtest: Memory DIMM Access Subtest: Memory DIMM Access Subtest: Memory MATS+ Subtest: Memory MATS+ Subtest: Memory MATS+ Subtest: Memory MATS+ Subtest: Memory MARCH CSubtest: Memory MARCH CSubtest: Memory Alternating Multiple Access Selection Subtest: Memory Alternating Multiple Access Selection Subtest: Enable Correctable Error Traps Subtest: Enable Correctable Error Traps Running Ecache Functional Running Ecache Functional Subtest: E-Cache Stress Subtest: E-Cache Stress Running CPU Functional Running CPU Functional Running Advanced CPU Tests Running Advanced CPU Tests Subtest: CPU Tick and Tick Compare Registers Test Subtest: CPU Tick and Tick Compare Registers Test Subtest: CPU Stick and Stick Compare Registers Test Subtest: CPU Stick and Stick Compare Registers Test Subtest: Branch Memory Test Subtest: Branch Memory Test Running CPU ECC Tests Running CPU ECC Tests Running System Level Tests Running System Level Tests Subtest: MP Memory Access Test Subtest: MP Memory Access Test Subtest: Invalidate Caches Subtest: Invalidate Caches Running Board Memory Interleave Running Board Memory Interleave Subtest: Board Memory Interleave Configuration Subtest: Board Memory Interleave Configuration Unpopulated Unpopulated Passed Passed

{/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P0} {/N0/SB2/P2} {/N0/SB2/P1} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P2} {/N0/SB2/P1} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P2} {/N0/SB2/P1} {/N0/SB2/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P2} {/N0/SB2/P0} {/N0/SB2/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P1} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P0} {/N0/SB2/P2} {/N0/SB2/P1} {/N0/SB2/P0} {/N0/SB2/P3} {/N0/SB2/P2} {/N0/SB2/P3} {/N0/SB2/P1} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3}

Subtest: Memory MARCH CSubtest: Memory MARCH CSubtest: Memory MARCH CSubtest: Memory MARCH CSubtest: Memory Alternating Multiple Access Selection Subtest: Memory Alternating Multiple Access Selection Subtest: Memory Alternating Multiple Access Selection Subtest: Memory Alternating Multiple Access Selection Running Ecache Functional Running Ecache Functional Running Ecache Functional Running Ecache Functional Subtest: E-Cache Stress Subtest: E-Cache Stress Subtest: E-Cache Stress Subtest: E-Cache Stress Running CPU Functional Running CPU Functional Running CPU Functional Running CPU Functional Running Advanced CPU Tests Running Advanced CPU Tests Subtest: CPU Tick and Tick Compare Registers Test Subtest: CPU Tick and Tick Compare Registers Test Subtest: CPU Stick and Stick Compare Registers Test Running Advanced CPU Tests Subtest: CPU Stick and Stick Compare Registers Test Subtest: Branch Memory Test Subtest: Branch Memory Test Running Advanced CPU Tests Subtest: CPU Tick and Tick Compare Registers Test Subtest: CPU Tick and Tick Compare Registers Test Subtest: CPU Stick and Stick Compare Registers Test Subtest: CPU Stick and Stick Compare Registers Test Subtest: Branch Memory Test Subtest: Branch Memory Test Running CPU ECC Tests Running CPU ECC Tests Running CPU ECC Tests Running CPU ECC Tests Running System Level Tests Running System Level Tests Subtest: MP Memory Access Test Subtest: MP Memory Access Test Running System Level Tests Running System Level Tests Subtest: MP Memory Access Test Subtest: MP Memory Access Test Running Board Memory Interleave Running Board Memory Interleave Running Board Memory Interleave Subtest: Board Memory Interleave Configuration Running Board Memory Interleave Subtest: Board Memory Interleave Configuration Subtest: Board Memory Interleave Configuration Subtest: Board Memory Interleave Configuration Passed Passed Passed Passed

Testing IO Boards ... Copying IO PROM to CPU DRAM ............................................ {/N0/SB0/P2} Running PCI IO Controller Basic Tests {/N0/SB0/P2} Jumping to memory 00000000.00000020 [00000010] {/N0/SB0/P2} System PCI IO post code running from memory {/N0/SB0/P2} @(#) lpost 5.20.5 2007/02/07 13:57 {/N0/SB0/P2} Running PCI IO Controller Functional Tests {/N0/SB0/P2} Copyright 2007 Sun Microsystems, Inc. All rights reserved. {/N0/SB0/P2} Use is subject to license terms. {/N0/SB0/P2} Subtest: PCI IO Controller Register Initialization for aid 0x1c {/N0/SB0/P2} Subtest: PCI IO Controller IOMMU TLB Compare Tests for aid 0x1c {/N0/SB0/P2} Subtest: PCI IO Controller IOMMU TLB Flush Tests for aid 0x1c {/N0/SB0/P2} Subtest: PCI IO Controller DMA loopback Tests for aid 0x1c {/N0/SB0/P2} Subtest: PCI IO Controller block DMA loopback Tests for aid 0x1c {/N0/SB0/P2} Subtest: PCI IO Controller Interrupt Tests for aid 0x1c {/N0/SB0/P2} Subtest: PCI IO Controller MergeBuffer Tests for aid 0x1c {/N0/SB0/P2} Subtest: PCI IO Controller StreamCache Tests for aid 0x1c {/N0/SB0/P2} Running PCI IO Controller Ecc Tests {/N0/SB0/P2} Subtest: Schizo clean up for aid 0x1c {/N0/SB0/P2} Running SBBC Basic Tests {/N0/SB0/P2} Subtest: SBBC PCI Reg Initialization for aid 0x1c {/N0/SB0/P2} Running Probe io Devices {/N0/SB0/P2} Running PCI IO Controller Basic Tests {/N0/SB0/P2} Subtest: PCI IO Controller Register Initialization for aid 0x1d {/N0/SB0/P2} Running PCI IO Controller Functional Tests {/N0/SB0/P2} Subtest: PCI IO Controller IOMMU TLB Compare Tests for aid 0x1d {/N0/SB0/P2} Subtest: PCI IO Controller IOMMU TLB Flush Tests for aid 0x1d {/N0/SB0/P2} Subtest: PCI IO Controller DMA loopback Tests for aid 0x1d {/N0/SB0/P2} Subtest: PCI IO Controller block DMA loopback Tests for aid 0x1d {/N0/SB0/P2} Subtest: PCI IO Controller Interrupt Tests for aid 0x1d {/N0/SB0/P2} Subtest: PCI IO Controller MergeBuffer Tests for aid 0x1d {/N0/SB0/P2} Running PCI IO Controller Ecc Tests {/N0/SB0/P2} Subtest: PCI IO Controller StreamCache Tests for aid 0x1d {/N0/SB0/P2} Subtest: Schizo clean up for aid 0x1d {/N0/SB0/P2} Running Probe io Devices {/N0/SB0/P2} @(#) lpost 5.20.5 2007/02/07 13:53 {/N0/SB0/P2} Copyright 2007 Sun Microsystems, Inc. All rights reserved. {/N0/SB0/P2} Use is subject to license terms. {/N0/IB8/P0} Passed {/N0/IB8/P1} Passed Testing domain ... {/N0/SB0/P2} Running Domain Level Tests {/N0/SB0/P2} Subtest: Mapping IO SRAM {/N0/SB0/P2} Subtest: Memory interleaving config {/N0/SB0/P2} Running Domain Basic Tests {/N0/SB0/P2} Subtest: Cross Call Test {/N0/SB0/P2} Running Domain Advanced Tests {/N0/SB0/P2} Subtest: MP Memory Clear Test {/N0/SB0/P2} CORE 3 clearing 00000000.00000000 to 00000000.2aaaaa80 {/N0/SB0/P2} CORE 8 clearing 00000000.2aaaaa80 to 00000000.55555500 {/N0/SB0/P2} CORE 9 clearing 00000000.55555500 to 00000000.7fffff80 {/N0/SB0/P2} CORE 10 clearing 00000000.7fffff80 to 00000000.aaaaaa00 {/N0/SB0/P2} CORE 11 clearing 00000000.aaaaaa00 to 00000000.d5555480 {/N0/SB0/P2} CORE 2 clearing 00000000.d5555480 to 00000001.00000000 {/N0/SB0/P2} CORE 3 clearing 00000020.00000000 to 00000020.aaaaaa80 {/N0/SB0/P2} CORE 8 clearing 00000020.aaaaaa80 to 00000021.55555500 {/N0/SB0/P2} CORE 9 clearing 00000021.55555500 to 00000021.ffffff80 {/N0/SB0/P2} CORE 10 clearing 00000021.ffffff80 to 00000022.aaaaaa00 {/N0/SB0/P2} CORE 11 clearing 00000022.aaaaaa00 to 00000023.55555480

{/N0/SB0/P2} {/N0/SB0/P2} {/N0/SB0/P2} {/N0/SB0/P2} {/N0/SB0/P2} {/N0/SB0/P2} {/N0/SB0/P2} {/N0/SB0/P2} {/N0/SB0/P3} {/N0/SB2/P0} {/N0/SB2/P1} {/N0/SB2/P2} {/N0/SB2/P3} Entering OBP

CORE 2 clearing 00000023.55555480 to 00000024.00000000 Running Domain Stick Sync Tests Subtest: Sync. Stick Registers Test Running Domain Verify Stick Sync Tests Subtest: Verify Sync. Stick Registers Test DCB_DECOMP_OBP command succeeded Decompress OBP done DCB_ENTER_OBP command succeeded DCB_ENTER_OBP command succeeded DCB_ENTER_OBP command succeeded DCB_ENTER_OBP command succeeded DCB_ENTER_OBP command succeeded DCB_ENTER_OBP command succeeded ...

ChassisSerialNumber 150H263F Sun Fire 6800 OpenFirmware version 5.20.5 (02/07/07 13:51) Copyright 2007 Sun Microsystems, Inc. All rights reserved. Use is subject to license terms. SmartFirmware, Copyright (C) 1996-2001. All rights reserved. 20480 MB memory installed, Serial #50806996. Ethernet address 0:3:ba:7:40:d4, Host ID: 830740d4. Rebooting with command: boot SunOS Release 5.9 Version Generic_122300-11 64-bit Copyright 1983-2003 Sun Microsystems, Inc. All rights reserved. Use is subject to license terms. WARNING: /ssm@0,0/pci@1c,600000/SUNW,qlc@1/fp@0,0/ssd@w50060482cafe6723,0 (ssd9) : Corrupt label; wrong magic number WARNING: /ssm@0,0/pci@1d,600000/SUNW,qlc@1/fp@0,0/ssd@w50060482cafe672c,0 (ssd19 ): Corrupt label; wrong magic number Hardware watchdog enabled VxVM sysboot INFO V-5-2-3390 Starting restore daemon... VxVM sysboot INFO V-5-2-3409 starting in boot mode... NOTICE: VxVM vxdmp V-5-0-34 added disk array DISKS, datype = Disk WARNING: /ssm@0,0/pci@1c,600000/SUNW,qlc@1/fp@0,0/ssd@w50060482cafe6723,0 (ssd9) : Corrupt label; wrong magic number WARNING: /ssm@0,0/pci@1c,600000/SUNW,qlc@1/fp@0,0/ssd@w50060482cafe6723,0 (ssd9) : Corrupt label; wrong magic number NOTICE: VxVM vxdmp V-5-0-112 disabled path 118/0x48 belonging to the dmpnode 274 /0xe8 WARNING: /ssm@0,0/pci@1d,600000/SUNW,qlc@1/fp@0,0/ssd@w50060482cafe672c,0 (ssd19 ): Corrupt label; wrong magic number WARNING: /ssm@0,0/pci@1d,600000/SUNW,qlc@1/fp@0,0/ssd@w50060482cafe672c,0 (ssd19 ):

Corrupt label; wrong magic number NOTICE: VxVM vxdmp V-5-0-112 disabled path 118/0x98 belonging to the dmpnode 274 /0xe8 NOTICE: VxVM vxdmp V-5-0-111 disabled dmpnode 274/0xe8 configuring IPv4 interfaces: ce0 hme0. Hostname: rcisn022 VxVM INFO V-5-2-3247 starting special volumes ( swapvol rootvol usr var )... The / file system (/dev/vx/rdsk/bootdg/rootvol) is being checked. /dev/vx/rdsk/bootdg/rootvol: 20924 files, 1449248 used, 535795 free (14867 frags , 65116 blocks, 0.7% fragmentation) The /usr file system (/dev/vx/rdsk/bootdg/usr) is being checked. /dev/vx/dsk/bootdg/usr: 85030 files, 3316338 used, 715804 free (61636 frags, 817 71 blocks, 1.5% fragmentation) The /var file system (/dev/vx/rdsk/bootdg/var) is being checked. /dev/vx/rdsk/bootdg/var: INCORRECT DISK BLOCK COUNT I=106 (4 should be 0) (CORRE CTED) /dev/vx/rdsk/bootdg/var: PARTIALLY TRUNCATED INODE I=9503 /dev/vx/rdsk/bootdg/var: UNEXPECTED INCONSISTENCY; RUN fsck MANUALLY. WARNING - Unable to repair the /var filesystem. Run fsck manually (fsck -F ufs /dev/vx/rdsk/bootdg/var). Exit the shell when done to continue the boot process. Type control-d to proceed with normal startup, (or give root password for system maintenance): Login incorrect Type control-d to proceed with normal startup, (or give root password for system maintenance): Login incorrect Type control-d to proceed with normal startup, (or give root password for system maintenance): Login incorrect Type control-d to proceed with normal startup, (or give root password for system maintenance): single-user privilege assigned to /dev/console. Entering System Maintenance Mode Nov 11 08:22:01 su: 'su root' succeeded for root on /dev/console WARNING: By using this system, you agree to comply with RCI corporate policies governing accessing and using the companys IT systems and data. To protect this system from unauthorized use and to ensure that the system is functioning properly, activities on this system are monitored and recorded and are subject to audit. Unauthorized access use of this system is prohibited and could be subject to disciplinary actions as well criminal and/or civil penalties. root@rcisn022:/ > root@rcisn022:/ > mount /var mount: the state of /dev/vx/dsk/bootdg/var is not okay

and it was attempted to be mounted read/write mount: Please run fsck and try again root@rcisn022:/ > root@rcisn022:/ > fsck -F -y ufs /dev/vx/rdsk/bootdg/var fsck: operation not applicable to FSType -y fsck: operation not applicable to FSType -y root@rcisn022:/ > root@rcisn022:/ > fsck -F ufs -y /dev/vx/rdsk/bootdg/var ** /dev/vx/rdsk/bootdg/var ** Last Mounted on /var ** Phase 1 - Check Blocks and Sizes INCORRECT DISK BLOCK COUNT I=106 (4 should be 0) CORRECT? yes PARTIALLY TRUNCATED INODE I=9503 SALVAGE? yes PARTIALLY TRUNCATED INODE I=31259 SALVAGE? yes PARTIALLY TRUNCATED INODE I=32038 SALVAGE? yes ** Phase 2 - Check Pathnames

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